© 2008 Microchip Technology Inc. DS80374B-page 1
PIC18F6585/8585/6680/8680
Clarifications/Corrections to the Data
Sheet:
In the Device Data Sheet (DS30491C), the following
clarific at ions and correcti on s sho ul d be not ed. Any sil i-
con issu es related to the PIC18F65 85/8585/6680 /8680
will be reported in a separate silicon errata. Please
check the Microchip web site for any existing issues.
1. Module: Device Overview (Pinout
Descriptions)
The last page of Table 1-2 changes the pin count
for the TQFP package, for the pins indicated in
bold text.
TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type Buffer
Type DescriptionPIC18F6X8X PIC18F8X8X
TQFP PLCC TQFP
RJ5/CE
CE — — 40 I/O
OST
TTL Digital I/O
External memory chip enable.
RJ6/LB
RJ6
LB
—— 41 I/O
OST
TTL Digital I/O.
External memory low byte select.
RJ7/UB
RJ7
UB
—— 42 I/O
OST
TTL Digital I/O.
External memory high byte select.
VSS 9, 25,
41, 56 19, 36,
53, 68 11, 31,
51, 70 P — Ground reference for logic and I/O pins.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for CCP2 in all op erating modes excep t Microco ntroller – applies to PIC18F8X8X only.
2: Default assignment when CCP2MX is set.
3: External memory interface functions are only available on PIC18F8X8X devices.
4: CCP2 is multiplexed with this pin by default when configured in Microcontroller mode; otherwise, it is
multiplexed with either RB3 or RC1.
5: PORTH and PORTJ are only available on PIC18F6585 (80-pin) devices.
6: PSP is available in Microcontroller mode only.
7: On PIC18F8X8X devices, these pins can be multiplexed with RH7/RH6 by changing the ECCPMX
configuration bit.
PIC18F6585/8585/6680/8680 Data Sheet Errata
PIC18F6585/8585/6680/8680
DS80374B-page 2 © 2008 Microchip Technology Inc.
2. Module: Master Synchronous Serial Port
Module (SPI Slave Mode)
The pin number of the Serial Pin Select (SPI)
mode’s slave select signal (SS) is changed to the
following:
• PIC18F6X8X, TQFP package – Pin 27
• PIC18F6X8X, PLCC package – Pin 38
• PIC18F8X8X, TQFP package – Pin 33
The SS sig nal i s on the s ame pin a s the R A5/AN 4/
LVDIN signals, not on the pin with the RF7 signal.
This change is made in the following locations,
each indicated by bold text:
• Pin Diagram, PIC18F6X8X, 64-Pin TQFP
package – Page 3
• Pin Diagram, PIC18F6X8X, 68-Pin PLCC
package – Page 4
• Pin Diagram, PIC18F8X8X, 80-Pin TQFP
package – Page 5
• Block diagram, PIC18F6X8X – Page 6
• Block diagram, PIC18F8X8X – Page 7
• Table 1-2, PIC18F6585/8585/6680/8680 Pinout
I/O Descriptions – Page 8
• Figure 10-2, Block Diagram of RA3:RA0 and
RA5/SS Pins – Page 9
• Figure 10-15, RF7 Pin Block Diagram – Page 9
• Table 10-11, PORTF Functions – Page 9
•Section 17.3 “SPI Mode” – Page 10
• Figure 17-1, MSSP Block Diagram (SPI Mode) –
Page 10
© 2008 Microchip Technology Inc. DS80374B-page 3
PIC18F6585/8585/6680/8680
Pin Diagrams
PIC18F6X8X
1
2
3
4
5
6
7
8
9
10
11
12
13
14
38
37
36
35
34
33
50 49
17 18 19 20 21 22 23 24 25 26
RE2/CS
RE3
RE4
RE5/P1C
RE6/P1B
RE7/CCP2(1)
RD0/PSP0
VDD
VSS
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE1/WR
RE0/RD
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/VPP
RG4/P1D
VSS
VDD
RF7
RF6/AN11/C1IN-
RF5/AN10/C1IN+/CVREF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RF0/AN5
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4/LVDIN/SS
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
15
16
31
40
39
27 28 29 30 32
48
47
46
45
44
43
42
41
54 53 52 5158 57 56 5560 59
64 63 62 61
64-Pin TQFP
Note 1: CCP2 pin placement depends on CCP2MX setting.
PIC18F6585/8585/6680/8680
DS80374B-page 4 © 2008 Microchip Technology Inc.
Pin Diagrams (Continued)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 6867666564636261
2728 2930 3132 33 34 35 36 37 38 39 40 41 42 43
Top V ie w
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RE1/WR
RE0/RD
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/VPP
RG4/P1D
VSS
VDD
RF7
RF6/AN11/C1IN-
RF5/AN10/C1IN+/CVREF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
RE2/CS
RE3
RE4
RE5/P1C
RE6/P1B
RE7/CCP2(1)
RD0/PSP0
VDD
VSS
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RF1/AN6/C2OUT
RF0/AN5
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
VDD
RA4/T0CKI
RA5/AN4/LVDIN/SS
RC1/T1OSI/CCP2(1)
RC0/T1OSO/T13CKI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
N/C
N/C
N/C
N/C
VSS
PIC18F6X8X
68-Pin PLCC
Note 1: CCP2 pin placement depends on CCP2MX setting.
© 2008 Microchip Technology Inc. DS80374B-page 5
PIC18F6585/8585/6680/8680
Pin Diagrams (Continued)
PIC18F8X8X
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32
RE2/CS/AD10
RE3/AD11
RE4/AD12
RE5/AD13/P1C(3)
RE6/AD14/P1B(3)
RE7/CCP2(2)/AD15
RD0/PSP0(1)/AD0
VDD
VSS
RD1/PSP1(1)/AD1
RD2/PSP2(1)/AD2
RD3/PSP3(1)/AD3
RD4/PSP4(1)/AD4
RD5/PSP5(1)/AD5
RD6/PSP6(1)/AD6
RD7/PSP7(1)/AD7
RE1/WR/AD9
RE0/RD/AD8
RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG5/MCLR/VPP
RG4/P1D
VSS
VDD
RF7
RB0/INT0
RB1/INT1
RB2/INT2
RB3/INT3/CCP2(2)
RB4/KBI0
RB5/KBI1/PGM
RB6/KBI2/PGC
VSS
OSC2/CLKO/RA6
OSC1/CLKI
VDD
RB7/KBI3/PGD
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1/P1A
RF0/AN5
RF1/AN6/C2OUT
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
VSS
VDD
RA4/T0CKI
RA5/AN4/LVDIN/SS
RC1/T1OSI/CCP2(2)
RC0/T1OSO/T13CKI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RJ0/ALE
RJ1/OE
RH1/A17
RH0/A16
1
2
RH2/A18
RH3/A19
17
18
RH7/AN15/P1B(3)
RH6/AN14/P1C(3)
RH5/AN13
RH4/AN12
RJ5/CE
RJ4/BA0
37
RJ7/UB
RJ6/LB
50
49
RJ2/WRL
RJ3/WRH
19
20
33 34 35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 73
78 77 76 75
79
80
80-Pin TQFP
Note 1: PSP is available only in Microcontroller mode.
2: CCP2 pin placement depends on CCP2MX and Processor mode settings.
3: P1B and P1C pin placement depends on ECCPMX setting.
RF5/AN10/C1IN+/CVREF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
RF6/AN11/C1IN-
PIC18F6585/8585/6680/8680
DS80374B-page 6 © 2008 Microchip Technology Inc.
FIGURE 1-1: PIC18F6X 8X BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO/RA6
RG5/ VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/LVDIN/SS
RB2/INT2:RB0/INT0
RB6/KBI2/PGC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
AUSARTComparator Synchronous
BOR Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
ECAN Module
Timing
Generation
10-Bit
ADC
RB3/INT3
Data Latch
Data RAM
(3328 bytes)
Address Latch
Address<12>
12
Bank0, F
BSR FSR0
FSR1
FSR2
inc/dec
logic
Decode
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
W
8
BITOP 8
8
ALU<8>
8
Test Mode
Select
Address Latch
Program Memory
(48 Kbytes)
Data Latch
21
21
16
8
8
8
Table Pointer<21>
inc/dec logic
21 8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Lat ch
Timer3
PORTD
RD7/PSP7
CCP2
RB4/KBI0
RB5/KBI1/PGM
PCLATU
PCU
Precision
Reference
Band Gap
PORTE
PORTG RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG4/P1D
Timer0
RE6/P1B
RE7/CCP2(1)
RE5/P1C
RE4
RE3
RE2/CS
RE0/RD
RE1/WR
LVD
ECCP1
RB7/KBI3/PGD
:RD0/PSP0
RF6/AN11/C1IN-
RF7
RF5/AN10/C1IN+/CVREF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
RF0/AN5
RF1/AN6/C2OUT
PORTF
RG5/MCLR/VPP
MCLR
OSC2/CLKO/RA6
Data EEPROM
Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.
© 2008 Microchip Technology Inc. DS80374B-page 7
PIC18F6585/8585/6680/8680
FIGURE 1-2: PIC18F8X 8X BLOCK DIAGRAM
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO/RA6
RG5/ VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/LVDIN/SS
RB2/INT2:RB0/INT0
RB6/KBI2/PGC
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2(1)
RC2/CCP1/P1A
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
Brown-out
Reset
AUSARTComparator Synchronous
BOR Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
ECAN Module
Timing
Generation
10-Bit
ADC
RB3/INT3/CCP2(1)
Data Latch
Data RAM
(3328 bytes)
Address Latch
Address<12>
12
Bank0, F
BSR FSR0
FSR1
FSR2
inc/dec
logic
Decode
412 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
W
8
BITOP 8
8
ALU<8>
8
Test Mode
Select
Address Latch
Program Memory
(64 Kbytes)
Data Latch
21
21
16
8
8
8
Table Pointe r<21>
inc/dec logic
21 8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
Timer3
PORTD
RD7/PSP7
CCP2
RB4/KBI0
RB5/KBI1/PGM
PCLATU
PCU
Precision
Reference
Band Gap
PORTE
PORTG RG0/CANTX1
RG1/CANTX2
RG2/CANRX
RG3
RG4/P1D
Timer0
RE6/AD14/P1B(2)
RE7/CCP2(1)/AD15
RE5/AD13/P1C(2)
RE4/AD12
RE3/AD11
RE2/CS/AD10
RE0/RD/AD8
RE1/WR/AD9
LVD
ECCP1
RB7/KBI3/PGD
/AD7:
RF6/AN11/C1IN-
RF7
RF5/AN10/C1IN+/CVREF
RF4/AN9/C2IN-
RF3/AN8/C2IN+
RF2/AN7/C1OUT
RF0/AN5
RF1/AN6/C2OUT
PORTF
PORTJ
RJ6/LB
RJ7/UB
RJ5/CE
RJ4/BA0
RJ3/WRH
RJ2/WRL
RJ0/ALE
RJ1/OE
RG5/MCLR/VPP
MCLR
OSC2/CLKO/RA6
RD0/PSP0/AD0
AD7:AD0
A16, AD15:AD8
System Bus Interface
Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings.
2: P1B and P1C pin placement depends on the ECCPMX setting.
PORTH
RH3/A19:RH0/A16
RH7/AN15/P1B(2)
RH6/AN14/P1C(2)
RH5/AN13
RH4/AN12
PIC18F6585/8585/6680/8680
DS80374B-page 8 © 2008 Microchip Technology Inc.
Note: The SS s ignal is remov ed from the PO RT F portion of the same t able, whe re it had been associa ted with the
RF7 signal.
TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number Pin
Type Buffer
Type DescriptionPIC18F6X8X PIC18F8X8X
TQFP PLCC TQFP
PORTA is a bidirectional I/O port.
RA0/AN0
RA0
AN0
24 34 30 I/O
ITTL
Analog Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
23 33 29 I/O
ITTL
Analog Digital I/O.
Analog input 1.
RA2/AN2/VREF-
RA2
AN2
VREF-
22 32 28 I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (Low) input.
RA3/AN3/VREF+
RA3
AN3
VREF+
21 31 27 I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
RA4/T0CKI
RA4
T0CKI
28 39 34 I/O
I
ST/OD
ST
Digital I/O – Open-drain when
configured as output.
Timer0 external clock input.
RA5/AN4/LVDIN/SS
RA5
AN4
LVDIN
SS
27 38 33 I/O
I
I
I
TTL
Analog
Analog
TTL
Digital I/O.
Analog input 4.
Low-voltage detect input.
SPI slave select input.
RA6 See the OSC2/C LKO/RA6 pin.
© 2008 Microchip Technology Inc. DS80374B-page 9
PIC18F6585/8585/6680/8680
FIGURE 10-2: BLOCK DIAGRAM OF
RA3:RA0 AND RA5/SS
PINS
FIGURE 10-15: RF7 PIN BLOCK
DIAGRAM
Note: The SS signal was removed from this
diagram.
TABLE 10-11: PORTF FUNCTIONS
Data
Bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR LATA
WR TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
VDD
I/O pin(1)
Note 1: I/O pins have protection diodes to VDD and VSS.
Analog
Input
Mode
TTL
Input
Buffer
To A/D Converter and LVD Modules
RD LATA
or
PORTA
TTL
Input
Buffer
SS Input
Data
Bus
WR LATF
WR TRISF
RD PORTF
Data Latch
TRIS Latch
RD TRISF
Schmitt
Trigger
Input
Buffer
I/O pin
QD
CK
QD
CK
EN
QD
EN
RD LATF
or
WR PORTF
Note: I/O pins have diode protection to VDD and VSS.
Name Bit# Buffer Type Function
RF0/AN5 bit 0 ST Input/output port pin or analog input.
RF1/AN6/C2OUT bit 1 ST Input/output port pin, analog input or comparator 2 output.
RF2/AN7/C1OUT bit 2 ST Input/output port pin, analog input or comparator 1 output.
RF3/AN8/C2IN+ bit 3 ST Input/output port pin, analog input or comparator 2 input (+).
RF4/AN9/C2IN- bit 4 ST Input/output port pin, analog input or comparator 2 input (-).
RF5/AN10/
C1IN+/CVREF bit 5 ST Input/output port pin, analog input, comparator 1 input (+) or
comparator reference output.
RF6/AN11/C1IN- bit 6 ST Input/output port pin, analog input or comparator 1 input (-).
RF7 bit 7 ST/TTL Input/output port pin or slave select pin for synchronous serial port.
Legend: ST = Schmitt Trigger input, TTL = TTL input
Note: The SS signal was removed from this table’s bottom row.
PIC18F6585/8585/6680/8680
DS80374B-page 10 © 2008 Microchip Technology Inc.
17.3 SPI Mode
The SPI mode allows eight bits of data to be synchro-
nously transmitted and received simultaneously. All
four modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDO) – RC5/SDO
• Serial Data In (SDI) – RC4/SDI/SDA
• Serial Clock (SCK) – RC3/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS) – RA5/AN4/LVDIN/SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR Reg
SSPM3:SSPM0
bit0 Shift
Clock
SS Control
Enable
Edge
Select
Clock Select
TMR2 Output
TOSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPS R
TRIS bit
2
SMP:CKE
RC5/SDO
SSPBUF Reg
RC4/SDI/SDA
RC3/SCK/
SCL
RA5/AN4/
LVDIN/SS
© 2008 Microchip Technology Inc. DS80374B-page 11
PIC18F6585/8585/6680/8680
REVISION HISTORY
Rev A Document (3/2008)
Original release of this errata. Data Sheet Clarification
1 (Device Overview – Pinout Descriptions).
Rev B Document (8/2008)
Added D ata She et Clarific ation 2 (Mast er Synchro nous
Serial Port Module, SPI Slave Mode).
PIC18F6585/8585/6680/8680
DS80374B-page 12 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS80374B-page 13
Information contained in this publication regarding device
applications a nd the lik e is provided only f or your convenience
and may be supers ed ed by u pda t es . I t is y o u r r es ponsibil it y to
ensure that your application meets with your specifications.
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U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its f amily of products is one of t he most secure famili es of its kind on the market t oday, when used i n the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS80374B-page 14 © 2008 Microchip Technology Inc.
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