SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B - DECEMBER 1982 - REVISED MAY 1997 D D D D Contain Eight Flip-Flops With Single-Rail Outputs Direct Clear Input Individual Data Input to Each Flip-Flop Applications Include: - Buffer/Storage Registers - Shift Registers - Pattern Generators Package Options Include Plastic Small-Outline (DW), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54HC273 . . . J OR W PACKAGE SN74HC273 . . . DW, N, OR PW PACKAGE (TOP VIEW) CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK SN54HC273 . . . FK PACKAGE (TOP VIEW) description 1D 1Q CLR VCC These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D 2D 2Q 3Q 3D 4D 8Q D The SN54HC273 is characterized for operation over the full military temperature range of -55C to 125C. The SN74HC273 is characterized for operation from -40C to 85 C. FUNCTION TABLE (each flip-flop) INPUTS CLR CLK D OUTPUT Q L X X L H H H H L L H L X Q0 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B - DECEMBER 1982 - REVISED MAY 1997 logic symbol 1 CLR R 11 CLK C1 3 1D 2D 3D 4D 5D 6D 7D 8D 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1D CLK 2D 3 11 3D 4 1D 7 1D C1 5D 8 1D C1 R CLR 4D 13 1D C1 R 6D R 14 1D C1 7D 17 1D C1 R 8D 1D C1 R 18 1D C1 R C1 R R 1 2 1Q 5 6 2Q 3Q 9 12 4Q 15 5Q 6Q 16 7Q 19 8Q logic diagram, each flip-flop (positive logic) D C C TG TG Q C C C C TG CLK(I) TG C C C C R 2 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B - DECEMBER 1982 - REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, JA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54HC273 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage tt Input transition (rise and fall) time TA SN74HC273 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC VCC = 2 V VCC = 4.5 V 0 1000 0 1000 0 500 0 500 VCC = 6 V 0 400 0 400 -55 125 -40 85 Operating free-air temperature POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 V V 0 VCC = 4.5 V VCC = 6 V UNIT V V V ns C 3 SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B - DECEMBER 1982 - REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = -20 A VOH VI = VIH or VIL IOH = -4 mA IOH = -5.2 mA IOL = 20 A VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC VI = VCC or 0 VI = VCC or 0, IO = 0 MIN TA = 25C TYP MAX MIN MAX SN74HC273 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V 0.1 100 1000 1000 nA 8 160 80 A 3 10 10 10 pF 6V Ci SN54HC273 2 V to 6 V V timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLR low tw Pulse duration CLK high or low Data tsu Setup time before CLK CLR inactive th 4 Hold time, data after CLK POST OFFICE BOX 655303 TA = 25C MIN MAX SN54HC273 MIN SN74HC273 MAX MIN MAX 2V 0 5 0 4 0 4 4.5 V 0 27 0 18 0 21 6V 0 32 0 21 0 25 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 * DALLAS, TEXAS 75265 UNIT MHz ns ns ns SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B - DECEMBER 1982 - REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPHL tpd tt CLR CLK Any Any Any VCC MIN TA = 25C TYP MAX SN54HC273 MIN MAX SN74HC273 MIN 2V 5 11 4 4 4.5 V 27 50 18 21 6V 32 60 21 25 MAX UNIT MHz 2V 55 160 240 200 4.5 V 15 32 48 40 6V 12 27 41 34 2V 56 160 240 200 4.5 V 15 32 48 40 6V 13 27 41 34 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns ns operating characteristics, TA = 25C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance per flip-flop POST OFFICE BOX 655303 No load * DALLAS, TEXAS 75265 TYP 35 UNIT pF 5 SN54HC273, SN74HC273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS136B - DECEMBER 1982 - REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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