- 1 -
June24,2014 |DATASHEET|Rev3.6
1
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
73
75
77
79
81
83
85
87
89
91
93
95
97
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Load Current (A)
Efficiency (%)
1.2Vout 3.3Vout
12Vin,Internal bias,Frequency 600KHz
FEATURES
Single5Vto21Vapplication
WideInputVoltageRangefrom1.0Vto21Vwith
externalVcc
OutputVoltageRange:0.5Vto0.86×Vin
EnhancedLine/LoadRegulationwithFeed‐Forward
ProgrammableSwitchingFrequencyupto1.5MHz
InternalDigitalSoft‐Start/Soft‐Stop
EnableinputwithVoltageMonitoringCapability
ThermallyCompensatedCurrentLimitwithrobust
hiccupmodeovercurrentprotection
SmartInternalLDOtoimprovelightloadandfullload
efficiency
ExternalSynchronizationwithSmoothClocking
EnhancedPre‐BiasStart‐Up
PrecisionReferenceVoltage(0.5V+/‐0.5%)with
marginingcapability
VpforTrackingApplications(Source/SinkCapability
+/‐4A)
IntegratedMOSFETdriversandBootstrapDiode
ThermalShutDown
ProgrammablePowerGoodOutputwithtracking
capability
MonotonicStart‐Up
Operatingtemp:‐40oC<Tj<125oC
SmallSize:4mmx5mmPQFN
Lead‐free,Halogen‐freeandRoHSCompliant
BASICAPPLICATION
Figure1:IR3897BasicApplicationCircuit
DESCRIPTION
TheIR3897SupIRBuckTMisaneasy‐to‐use,fully
integratedandhighlyefficientDC/DCregulator.
TheonboardPWMcontrollerandMOSFETsmake
IR3897aspace‐efficientsolution,providingaccurate
powerdelivery.
IR3897isaversatileregulatorwhichoffers
programmabilityofswitchingfrequencyandinternal
currentlimitwhileoperatesinwideinputandoutput
voltagerange.
Theswitchingfrequencyisprogrammablefrom300kHz
to1.5MHzforanoptimumsolution.
Italsofeaturesimportantprotectionfunctions,suchas
Pre‐Biasstartup,thermallycompensatedcurrentlimit,
overvoltageprotectionandthermalshutdowntogive
requiredsystemlevelsecurityintheeventoffault
conditions.
APPLICATIONS
NetcomApplications
EmbeddedTelecomSystems
ServerApplications
StorageApplications
DistributedPointofLoadPowerArchitectures
Figure2:IR3897Efficiency
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June24,2014 |DATASHEET|Rev3.6
2
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
ORDERINGINFORMATION
IR3897―
Package Tape&ReelQtyPartNumber
M750IR3897MTR1PBF
M4000IR3897MTRPBF
PINDIAGRAM
4mmx5mmPOWERQFN
TOPVIEW
PBF–LeadFree
TR/TR1–TapeandReel
M–PackageType
-
32 /
2/
o
JA
o
JPCB
CW
CW
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June24,2014 |DATASHEET|Rev3.6
3
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
BLOCKDIAGRAM
Figure3:IR3897SimplifiedBlockDiagram
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
PINDESCRIPTIONS
PIN # PIN NAME PIN DESCRIPTION
1Fb
Invertinginputtotheerroramplifier.Thispinisconnecteddirectlytotheoutput
oftheregulatorviaresistordividertosettheoutputvoltageandprovide
feedbacktotheerroramplifier.
2Vref
Internalreferencevoltage,itcanbeusedformarginingoperationalso.In
normalandsequencingmodeoperation,a100pFceramiccapacitoris
recommendedbetweenthispinandGnd.Intrackingmodeoperation,Vref
shouldbetiedtoGnd.
3CompOutputoferroramplifier.Anexternalresistorandcapacitornetworkistypically
connectedfromthispintoFbtoprovideloopcompensation.
4GndSignalgroundforinternalreferenceandcontrolcircuitry.
5Rt/Sync
Multi‐functionpintosetswitchingfrequency.Useanexternalresistorfromthis
pintoGndtosetthefree‐runningswitchingfrequency.Oruseanexternalclock
signaltoconnecttothispinthroughadiode,thedevice’sswitchingfrequencyis
synchronizedwiththeexternalclock.
6S_Ctrl
Softstart/stopcontrol.Ahighlogicinputenablesthedevicetogointothe
internalsoftstart;alowlogicinputenablestheoutputsoftdischarged.Pullthis
pinhighifthisfunctionisnotused.
7PGoodPowerGoodstatuspin.Outputisopendrain.Connectapullupresistor(49.9k)
fromthispintothevoltagelowerthanorequaltotheVcc.
8VsnsSensepinforover‐voltageprotectionandPGood.Itisoptionaltotiethispinto
FBpindirectlyinsteadofusingaresistordividerfromVout.
9Vin
InputvoltageforInternalLDO.A1.0µFcapacitorshouldbeconnectedbetween
thispinandPGnd.IfexternalsupplyisconnectedtoVcc/LDO_outpin,thispin
shouldbeshortedtoVcc/LDO_outpin.
10Vcc/LDO_OutInputBiasforexternalVccVoltage/outputofinternalLDO.Placeaminimum
2.2µFcapfromthispintoPGnd.
11PGndPowerGround.ThispinservesasaseparatedgroundfortheMOSFETdrivers
andshouldbeconnectedtothesystem’spowergroundplane.
12SWSwitchnode.Thispinisconnectedtotheoutputinductor.
13PVinInputvoltageforpowerstage.
14BootSupplyvoltageforhighsidedriver,a100nFcapacitorshouldbeconnected
betweenthispinandSWpin.
15EnableEnablepintoturnonandoffthedevice,ifthispinisconnectedtoPVinpin
througharesistordivider,inputvoltageUVLOcanbeimplemented.
16Vp
Inputtoerroramplifierfortrackingpurposes.Inthenormaloperation,itisleft
floatingandnoexternalcapacitorisrequired.Inthesequencingorthetracking
modeoperation,anexternalsignalcanbeappliedasthereference.
17GndSignalgroundforinternalreferenceandcontrolcircuitry.
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
ABSOLUTEMAXIMUMRATINGS
Stressesbeyondthoselistedunder“AbsoluteMaximumRatings”maycausepermanentdamagetothedevice.Theseare
stressratingsonlyandfunctionaloperationofthedeviceattheseoranyotherconditionsbeyondthoseindicatedinthe
operationalsectionsofthespecificationsarenotimplied.
PVin,Vin ‐0.3Vto25V
Vcc/LDO_Out‐0.3Vto8V(Note2)
Boot ‐0.3Vto33V
SW‐0.3Vto25V(DC),‐4Vto25V(AC,100ns)
BoottoSW ‐0.3VtoVCC+0.3V(Note1)
S_Ctrl,PGood‐0.3VtoVCC+0.3V(Note1)
OtherInput/OutputPins ‐0.3Vto+3.9V
PGndtoGnd‐0.3Vto+0.3V
StorageTemperatureRange ‐55°Cto150°C
JunctionTemperatureRange‐40°Cto150°C(Note2)
ESDClassification(HBMJESD22‐A114)2kV
MoistureSensitivityLevelJEDECLevel2@260°C
Note1:Mustnotexceed8V
Note2:Vccmustnotexceed7.5VforJunctionTemperaturebetween‐10°Cand‐40°C
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
ELECTRICALSPECIFICATIONS
RECOMMENDEDOPERATINGCONDITIONSFORRELIABLEOPERATIONWITHMARGIN
SYMBOLMINMAXUNITS
InputVoltageRange*PVin1.021
V
InputVoltageRange**Vin521
SupplyVoltageRange***VCC4.57.5
SupplyVoltageRangeBoottoSW4.57.5
OutputVoltageRangeVO0.50.86xVin
OutputCurrentRangeIO0±4A
SwitchingFrequencyFS3001500kHz
OperatingJunctionTemperatureTJ‐40125°C
*MaximumSWvoltageshouldnotexceed25V.
**Forinternallybiasedsinglerailoperation.WhenVindropsbelow6.8V,theinternalLDOentersdropout.PleaserefertoSmartLDO
sectionandOverCurrentProtectionfordetailedapplicationinformation.
***Vcc/LDO_Outcanbeconnectedtoanexternalregulatedsupply.Ifso,theVininputshouldbeconnectedtoVcc/LDO_Outpin.
ELECTRICALCHARACTERISTICS
Unlessotherwisespecified,thesespecificationsapplyover,6.8V<Vin=PVin<21V,Vref=0.5Vin0°C<TJ<125°C.
TypicalvaluesarespecifiedatTa=25°C.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNIT
PowerStage
PowerLossesPLOSSVin=12V,VO=1.2V,IO=4A,
Fs=600kHz,L=1.5uH,
Vcc=6.4V,Note4
0.5 W
TopSwitchRds(on)_TopVBoot‐Vsw=6.4V,IO=4A,Tj=25°C17.522.5mΩ
BottomSwitchRds(on)_BotVcc=6.4V,IO=4A,Tj=25°C17.923.3
BootstrapDiodeForwardVoltage I(Boot)=10mA180 260470mV
SWLeakageCurrentISWSW=0V,Enable=0V
1µA
SW=0V,Enable=high,
Vp=0V
DeadBandTimeTdbNote451030ns
SupplyCurrent
VINSupplyCurrent(standby)Iin(Standby)EN=Low,NoSwitching100µA
VINSupplyCurrent(dynamic)Iin(Dyn)EN=High,Fs=600kHz,
Vin=PVin=21V
9.512.5mA
Vcc/LDO_Out
OutputVoltageVccVin(min)=6.8V,Icc=0‐30mA,
Cload=2.2uF,DCM=06.06.46.7
V
Vin(min)=6.8V,Icc=0‐30mA,
Cload=2.2uF,DCM=14.04.44.8
LDODropoutVoltageVcc_dropIcc=30mA,Cload=2.2uF0.7V
ShortCircuitCurrentIshort 70mA
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNIT
Zero‐crossingComparatorDelayTdly_zcNote4256/Fs s
Zero‐crossingComparatorOffsetVos_zcNote4‐404mV
Oscillator
RtVoltageVrt 1.0 V
FrequencyRangeFsRt=80.6K270300330
kHz
Rt=39.2K540600660
Rt=15.0K135015001650
RampAmplitudeVrampVin=7.0V,Vinslewratemax=
1V/µs,Note4
1.05
Vp‐p
Vin=12V,Vinslewratemax=
1V/µs,Note4
1.80
Vin=21V,Vinslewratemax=
1V/µs,Note4
3.15
Vin=Vcc=5V,ForexternalVcc
operation,Note4
0.75
RampOffsetRamp(os)Note40.16 V
MinPulseWidthTmin(ctrl)Note460ns
MaxDutyCycleDmaxFs=300kHz,PVin=Vin=12V86 %
FixedOffTimeToffNote4200250ns
SyncFrequencyRangeFsync 2701650kHz
SyncPulseDurationTsync 100200 ns
SyncLevelThresholdHigh 3
V
Low 0.6
ErrorAmplifier
InputOffsetVoltageVos_VrefVFb–Vref,Vref=0.5V‐1.5+1.5
%
Vos_VpVFb–Vp,Vp=0.5V‐1.5 +1.5
InputBiasCurrentIFb(E/A) ‐1 +1
µA
InputBiasCurrentIVp(E/A) 0+4
SinkCurrentIsink(E/A) 0.40.851.2mA
SourceCurrentIsource(E/A) 47.511mA
SlewRateSRNote471220V/µs
Gain‐BandwidthProductGBWPNote4203040MHz
DCGainGainNote4100110120dB
MaximumoutputVoltageVmax(E/A) 1.72.02.3V
MinimumoutputVoltageVmin(E/A) 100mV
CommonModeinputVoltage01.2V
ReferenceVoltage
FeedbackVoltageVfbVrefandVppinfloating0.5 V
Accuracy0°C<Tj<+70°C‐0.5 +0.5%
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNIT
‐40°C<Tj<+125°C,Note3‐1.0 +1.0
VrefMarginingVoltage
Vref_marg 0.41.2V
SinkCurrentIsink_VrefVref=0.6V12.716.019.3
µA
SourceCurrentIsrc_VrefVref=0.4V12.716.019.3
VrefComparatorThresholdVref_disableVrefpinconnectedexternally0.15
V
Vref_enable0.4
SoftStart/Stop
SoftStartRampRateRamp(SS_start) 0.160.20.24
mV/µs
SoftStopRampRateRamp(SS_stop) ‐0.24‐0.2‐0.16
S_CtrlThresholdHigh 2.4
V
Low 0.6
PowerGood
PGoodTurnonThresholdVPG(on)VsnsRising,0.4V<Vref<1.2V859095 %Vref
VsnsRising,Vref<0.1V859095%Vp
PGoodLowerTurnoffThresholdVPG(lower)VsnsFalling,0.4V<Vref<1.2V808590%Vref
VsnsFalling,Vref<0.1V808590%Vp
PGoodTurnonDelayVPG(on)_DlyVsnsRising,seeVPG(on)1.28 ms
PGoodUpperTurnoffThresholdVPG(upper)VsnsRising,0.4V<Vref<1.2V115 120125 %Vref
VsnsRising,Vref<0.1V115120125%Vp
PGoodComparatorDelayVPG(comp)_
Dly
Vsns<VPG(lower)or
Vsns>VPG(upper)
123.5µs
PGoodVoltageLowPG(voltage)IPgood=‐5mA0.5 V
TrackerComparatorUpper
Threshold
VPG(tracker_
upper)
VpRising,Vref<0.1V0.4
V
TrackerComparatorLower
Threshold
VPG(tracker_
lower)
VpFalling,Vref<0.1V0.3
TrackerComparatorDelayTdelay(tracker)VpRising,Vref<0.1V,see
VPG(tracker_upper)
1.28 ms
Under‐VoltageLockout
Vcc‐StartThresholdVCC_UVLO_StartVccRisingTripLevel4.04.24.4
V
Vcc‐StopThresholdVCC_UVLO_StopVccFallingTripLevel3.73.94.1
Enable‐Start‐ThresholdEnable_UVLO_StartSupplyrampingup1.141.21.26
V
Enable‐Stop‐ThresholdEnable_UVLO_StopSupplyrampingdown0.9511.05
EnableLeakageCurrentIenEnable=3.3V1µA
Over‐VoltageProtection
OVPTripThresholdOVP_VthVsnsRising,0.45V<Vref<1.2V115120125%Vref
VsnsRising,Vref<0.1V115120125%Vp
OVPComparatorDelyOVP_Tdly 123.5µs
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNIT
Over‐CurrentProtection
CurrentLimitILIMITTj=25°C,Vcc=6.4V5.87.08.2A
HiccupBlankingTimeTblk_HiccupNote420.48 ms
Over‐TemperatureProtection
ThermalShutdownThresholdTtsdNote4145
°C
HysteresisTtsd_hysNote420
Note3:Coldtemperatureperformanceisguaranteedviacorrelationusingstatisticalqualitycontrol.Nottestedinproduction.
Note4:Guaranteedbydesignbutnottestedinproduction.
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June24,2014 |DATASHEET|Rev3.6
10
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
71
73
75
77
79
81
83
85
87
89
91
93
95
97
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Load Current (A)
Efficiency (%)
1.0V 1.2V 1.8V 3.3V 5.0V
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Load Current (A)
Power Dissipation(W)
1.0V 1.2V 1.8V 3.3V 5.0V
TYPICALEFFICIENCYANDPOWERLOSSCURVES
PVin=12V,Vcc=InternalLDO(4.4V/6.4V),Io=0A‐4A,Fs=600KHz,RoomTemperature,NoAirFlow.Notethatthe
efficiencyandpowerlosscurvesincludethelossesofIR3897,theinductorlossesandthelossesoftheinputandoutput
capacitors.Thetablebelowshowstheinductorsusedforeachoftheoutputvoltagesintheefficiencymeasurement.
VOUT(V)LOUT(µH) P/N DCR(mΩ)
1.01.5 PCMB065T-1R5MS(Cyntec) 6.7
1.21.5 PCMB065T-1R5MS(Cyntec) 6.7
1.82.2 7443340220(Wurth Elektronik) 4.4
3.33.3 7443340330(Wurth Elektronik) 6.5
53.3 7443340330(Wurth Elektronik) 6.5
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June24,2014 |DATASHEET|Rev3.6
11
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
80
82
84
86
88
90
92
94
96
98
0.40.81.21.6 2 2.42.83.23.6 4
Load Current (A)
Efficiency (%)
1.0V 1.2V 1.8V 3.3V 5.0V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Load Current (A)
Power Dissiation(W)
1.0V 1.2V 1.8V 3.3V 5.0V
TYPICALEFFICIENCYANDPOWERLOSSCURVES
PVin=12V,Vcc=External5V,Io=0A‐4A,Fs=600KHz,RoomTemperature,NoAirFlow.Notethattheefficiencyandpower
losscurvesincludethelossesofIR3897,theinductorlossesandthelossesoftheinputandoutputcapacitors.Thetable
belowshowstheinductorsusedforeachoftheoutputvoltagesintheefficiencymeasurement.
VOUT(V)LOUT(µH) P/N DCR(mΩ)
1.01.5 PCMB065T-1R5MS (Cyntec) 6.7
1.21.5 PCMB065T-1R5MS (Cyntec) 6.7
1.82.2 7443340220 (Wurth Elektronik) 4.4
3.33.3 7443340330 (Wurth Elektronik) 6.5
53.3 7443340330 (Wurth Elektronik) 6.5
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June24,2014 |DATASHEET|Rev3.6
12
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
83
85
87
89
91
93
95
97
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Load Current (A)
Efficiency (%)
1.0V 1.2V 1.8V 3.3V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
Load Current (A)
Power Dissipation(W)
1.0V 1.2V 1.8V 3.3V
TYPICALEFFICIENCYANDPOWERLOSSCURVES
PVin=5.0V,Vcc=5.0V,Io=0A‐4A,Fs=600KHz,RoomTemperature,NoAirFlow.Notethattheefficiencyandpowerloss
curvesincludethelossesofIR3897,theinductorlossesandthelossesoftheinputandoutputcapacitors.Thetablebelow
showstheinductorsusedforeachoftheoutputvoltagesintheefficiencymeasurement.
VOUT(V)LOUT(µH) P/N DCR(mΩ)
1.01 SPM6550T-1R0M (TDK) 4.7
1.21 SPM6550T-1R0M (TDK) 4.7
1.81.5 PCMB065T-1R5MS (Cyntec) 6.7
3.31.5 PCMB065T-1R5MS (Cyntec) 6.7
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
4.4
4.6
4.8
5
5.2
5.4
5.6
25 30 35 40 45 50 55 60 65 70 75 80 85
TAmb
Iout(A)
0 LFM
Lout-3.3uH,6.5mΩ(Wurth Elektronik 7443340330)
4.4
4.6
4.8
5
5.2
5.4
5.6
25 30 35 40 45 50 55 60 65 70 75 80 85
TAmb
Iout(A)
0 LFM
Lout-1.5uH,6.7mΩ(Cyntec PCMB065T-1R5MS)
THERMALDERATINGCURVES
MeasurementdoneonEvaluationboardofIRDC3897.PCBis4layerboardwith2ozCopper,FR4material,size2.23"x2"
PVin=12V,Vout=1.2V,Vcc=InternalLDO(6.4V),Fs=600kHz
PVin=12V,Vout=3.3V,Vcc=InternalLDO(6.4V),Fs=600kHz
Note: International Rectifier Corporation specifies current rating of SupIRBuck devices conservatively. The continuous current
load capability might be higher than the rating of the device if input voltage is 12V typical and switching frequency is below
750 kHz.The above derating curves are generated at 12V input ,600kHz with 0-200LFM air flow and ambient temperature up
to 85°C.Detailed thermal derating information can be found in the Application Note AN-1174 “Thermal Derating of DC DC
Convertors using IR3899/98/97”. However, the maximum current is limited by the internal current limit and designers need to
consider enough guard bands between load current and minimum current limit to guarantee that the device does not trip at
steady state condition.
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
RDSONOFMOSFETSOVERTEMPERATUREATVcc=6.4V
RDSONOFMOSFETSOVERTEMPERATUREATVcc=5.0V
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
TYPICALOPERATINGCHARACTERISTICS(‐40°Cto+125°C)
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
TYPICALOPERATINGCHARACTERISTICS(‐40°Cto+125°C)
InternalLDOisinregulation InternalLDOisindropoutmode
WithanExternal5VVccVoltage
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
TYPICALOPERATINGCHARACTERISTICS(‐40°Cto+125°C)
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
THEORYOFOPERATION
DESCRIPTION
TheIR3897usesaPWMvoltagemodecontrolschemewith
externalcompensationtoprovidegoodnoiseimmunity
andmaximumflexibilityinselectinginductorvaluesand
capacitortypes.
Theswitchingfrequencyisprogrammablefrom300kHz
to1.5MHzandprovidesthecapabilityofoptimizingthe
designintermsofsizeandperformance.
IR3897providespreciselyregulatedoutputvoltage
programmedviatwoexternalresistorsfrom0.5Vto
0.86*Vin.
TheIR3897operateswithaninternalbiassupply(LDO)
whichisconnectedtotheVcc/LDO_outpin.Thisallows
operationwithsinglesupply.Thebiasvoltageisvariable
accordingtoloadcondition.Iftheoutputloadcurrentis
lessthanhalfofthepeak‐to‐peakinductorcurrent,alower
biasvoltage,4.4V,isusedastheinternalgatedrive
voltage;otherwise,ahighervoltage,6.4V,isused.
Thisfeaturehelpstheconvertertoreducepowerlosses.
Thedevicecanalsobeoperatedwithanexternalsupply
from4.5to7.5V,allowinganextendedoperatinginput
voltage(PVin)rangefrom1.0Vto16V.Forusingthe
internalLDOsupply,theVinpinshouldbeconnectedto
PVinpin.Ifanexternalsupplyisused,itshouldbe
connectedtoVcc/LDO_OutpinandtheVinpinshouldbe
shortedtoVcc/LDO_Outpin.
Thedeviceutilizestheon‐resistanceofthelowside
MOSFET(synchronousMosfet)fortheovercurrent
protection.Thismethodenhancestheconverter’s
efficiencyandreducescostbyeliminatingtheneedfor
externalcurrentsenseresistor.
IR3897includestwolowRds(on)MOSFETsusingIR’sHEXFET
technology.Thesearespecificallydesignedforhigh
efficiencyapplications.
UNDER‐VOLTAGELOCKOUTANDPOR
Theunder‐voltagelockoutcircuitmonitorsthevoltageof
Vcc/LDO_OutpinandtheEnableinput.Itassuresthatthe
MOSFETdriveroutputsremainintheoffstatewhenever
eitherofthesetwosignalsdropbelowthesetthresholds.
NormaloperationresumesonceVcc/LDO_OutandEnable
riseabovetheirthresholds.
ThePOR(PowerOnReady)signalisgeneratedwhenall
thesesignalsreachthevalidlogiclevel(seesystemblock
diagram).WhenthePORisassertedthesoftstart
sequencestarts(seesoftstartsection).
ENABLE
TheEnablefeaturesanotherlevelofflexibilityforstartup.
TheEnablehasprecisethresholdwhichisinternally
monitoredbyUnder‐VoltageLockout(UVLO)circuit.
Therefore,theIR3897willturnononlywhenthevoltage
attheEnablepinexceedsthisthreshold,typically,1.2V.
IftheinputtotheEnablepinisderivedfromthebus
voltagebyasuitablyprogrammedresistivedivider,itcan
beensuredthattheIR3897doesnotturnonuntilthebus
voltagereachesthedesiredlevel(Fig.4).Onlyafterthebus
voltagereachesorexceedsthislevelandvoltageatthe
Enablepinexceedsitsthreshold,IR3897willbeenabled.
Therefore,inadditiontobeingalogicinputpintoenable
theIR3897,theEnablefeature,withitsprecisethreshold,
alsoallowstheusertoimplementanUnder‐Voltage
Lockoutforthebusvoltage(PVin).Thisisdesirable
particularlyforhighoutputvoltageapplications,wherewe
mightwanttheIR3897tobedisabledatleastuntilPVIN
exceedsthedesiredoutputvoltagelevel.
Pvin (12V)
Vcc
Enable
Intl_SS
10. 2 V
Enable Threshold = 1.2V
Figure4:NormalStartup,deviceturnson
whenthebusvoltagereaches10.2V
AresistordividerisusedatENpinfromPVintoturnonthe
deviceat10.2V.
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June24,2014 |DATASHEET|Rev3.6
19
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
Pvin(12V)
Vcc
Intl_SS
Enable >1.2V
Vp>1V
Figure5a:RecommendedstartupforNormaloperation
Pvin (12V)
Vcc
Enable > 1. 2 V
Intl_SS
Vp
Figure5b:Recommendedstartupforsequencingoperation
(ratiometricorsimultaneous)
Figure5c:Recommendedstartupfor
memorytrackingoperation(VTT‐DDR4)
Figure5ashowstherecommendedstart‐upsequencefor
thenormal(non‐tracking,non‐sequencing)operationof
IR3897,whenEnableisusedasalogicinput.Figure5b
showstherecommendedstartupsequenceforsequenced
operationofIR3897withEnableusedaslogicinput.Figure
5cshowstherecommendedstartupsequencefortracking
operationofIR3897withEnableusedaslogicinput.
Innormalandsequencingmodeoperation,Vrefisleft
floating.A100pFceramiccapacitorisrecommended
betweenthispinandGnd.Intrackingmodeoperation,
VrefshouldbetiedtoGnd.
ItisrecommendedtoapplytheEnablesignalaftertheVCC
voltagehasbeenestablished.IftheEnablesignalispresent
beforeVCC,a50kΩresistorcanbeusedinserieswiththe
EnablepintolimitthecurrentflowingintotheEnablepin.
PRE‐BIASSTARTUP
IR3897isabletostartupintopre‐chargedoutput,which
preventsoscillationanddisturbancesoftheoutput
voltage.
Theoutputstartsinasynchronousfashionandkeepsthe
synchronousMOSFET(SyncFET)offuntilthefirstgate
signalforcontrolMOSFET(CtrlFET)isgenerated.Figure6a
showsatypicalPre‐Biasconditionatstartup.ThesyncFET
alwaysstartswithanarrowpulsewidth(12.5%ofa
switchingperiod)andgraduallyincreasesitsdutycycle
withastepof12.5%untilitreachesthesteadystatevalue.
Thenumberofthesestartuppulsesforeachstepis16and
it’sinternallyprogrammed.Figure6bshowstheseriesof
16x8startuppulses.
Vo
[V]
[Time]
Pre-Bias
Voltage
Figure6a:Pre‐Biasstartup
... ... ...
HDRv
... ... ...
16 End of
PB
LDRv
12.5% 25% 87.5%
16 ...
...
...
...
Figure6b:Pre‐Biasstartuppulses
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June24,2014 |DATASHEET|Rev3.6
20
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
SOFT‐START
IR3897hasaninternaldigitalsoft‐starttocontrolthe
outputvoltageriseandtolimitthecurrentsurgeatthe
start‐up.Toensurecorrectstart‐up,thesoft‐start
sequenceinitiateswhentheEnableandVccriseabove
theirUVLOthresholdsandgeneratethePowerOnReady
(POR)signal.Theinternalsoft‐start(Intl_SS)signallinearly
riseswiththerateof0.2mV/µsfrom0Vto1.5V.Figure7
showsthewaveformsduringsoftstart(alsorefertoFig.
20).ThenormalVoutstart‐uptimeisfixed,andisequalto:
0.65V-0.15V 2.5ms (1)
0.2mV/ s
start
T
Duringthesoftstarttheover‐currentprotection(OCP)and
over‐voltageprotection(OVP)isenabledtoprotectthe
deviceforanyshortcircuitorovervoltagecondition.
POR
Intl_SS
Vout
0.15V
0.65V
t1t2t3
1.5V
3.0V
Figure7:Theoreticaloperationwaveformsduring
soft‐start(nontracking/nonsequencing)
OPERATINGFREQUENCY
Theswitchingfrequencycanbeprogrammedbetween
300kHz–1500kHzbyconnectinganexternalresistorfrom
RtpintoGnd.Table1tabulatestheoscillatorfrequency
versusRt.
SHUTDOWN
IR3897canbeshutdownbypullingtheEnablepinbelow
its1.0Vthreshold.Thiswilltri‐stateboththehighsideand
thelowsidedriver.
TABLE1:SWITCHINGFREQUENCY(FS)VS.EXTERNALRESISTOR(RT)
Rt(KΩ)Freq(KHz)
80.6 300
60.4 400
48.7 500
39.2 600
34 700
29.4 800
26.1 900
23.2 1000
21 1100
19.1 1200
17.4 1300
16.2 1400
15 1500
OVERCURRENTPROTECTION
Theovercurrent(OC)protectionisperformedbysensing
currentthroughtheRDS(on)oftheSynchronousMosfet.This
methodenhancestheconverter’sefficiency,reducescost
byeliminatingacurrentsenseresistorandanylayout
releatednoiseissues.Thecurrentlimitispre‐setinternally
andiscompensatedaccordingtotheICtemperature.Soat
differentambienttemperature,theover‐currenttrip
thresholdremainsalmostconstant.
NotethattheovercurrentlimitisafunctionoftheVcc
voltage.Refertothetypicalperformancecurvesofthe
OCPcurrentlimitwiththeinternalLDOandtheexternal
Vccvoltage.DetailedoperationofOCPisexplainedas
follows.
OverCurrentProtectioncircuitsensestheinductorcurrent
flowingthroughtheSynchronousMosfetclosertothe
valleypoint.OCPcircuitsamplesthiscurrentfor40nsec
typicallyaftertherisingedgeofthePWMsetpulsewhich
hasawidthof12.5%oftheswitchingperiod.ThePWM
pulsestartsatthefallingedgeofthePWMsetpulse.This
makesvalleycurrentsensemorerobustascurrentis
sensedclosetothebottomoftheinductordownward
slopewheretransientandswitchingnoisearelowerand
helpstopreventfalsetrippingduetonoiseandtransient.
AnOCconditionisdetectediftheloadcurrentexceedsthe
threshold,theconverterentersintohiccupmode.PGood
willgolowandtheinternalsoftstartsignalwillbepulled
low.Theconvertergoesintohiccupmodewitha20.48ms
(typ.)delayasshowninFigure8.Theconvertorstaysin
thismodeuntiltheoverloadorshortcircuitisremoved.
TheactualDCoutputcurrentlimitpointwillbegreater
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June24,2014 |DATASHEET|Rev3.6
21
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
thanthevalleypointbyanamountequaltoapproximately
halfofpeaktopeakinductorripplecurrent.Thecurrent
limitpointwillbeafunctionoftheinductorvalue,input,
outputvoltageandthefrequencyofoperation.
(2)
2
OCP LIMIT
i
II
IOCP=DCcurrentlimithiccuppoint
ILIMIT=CurrentlimitValleyPoint
Δi=Inductorripplecurrent
Figure8:TimingDiagramfor
CurrentLimitandHiccup
THERMALSHUTDOWN
TemperaturesensingisprovidedinsideIR3897.Thetrip
thresholdistypicallysetto145oC.Whentripthresholdis
exceeded,thermalshutdownturnsoffbothMOSFETsand
resetstheinternalsoftstart.
Automaticrestartisinitiatedwhenthesensed
temperaturedropswithintheoperatingrange.Thereis
a20oChysteresisinthethermalshutdownthreshold.
EXTERNALSYNCHRONIZATION
IR3897incorporatesaninternalphaselockloop(PLL)
circuitwhichenablessynchronizationoftheinternal
oscillatortoanexternalclock.Thisfunctionisimportantto
avoidsub‐harmonicoscillationsduetobeatfrequencyfor
embeddedsystemswhenmultiplepoint‐of‐load(POL)
regulatorsareused.Amulti‐functionpin,Rt/Sync,isused
toconnecttheexternalclock.Iftheexternalclockis
presentbeforetheconverterturnson,Rt/Syncpincanbe
connectedtotheexternalclocksignalsolelyandnoother
resistorisneeded.Iftheexternalclockisappliedafterthe
converterturnson,ortheconverterswitchingfrequency
needstotogglebetweentheexternalclockfrequencyand
theinternalfree‐runningfrequency,anexternalresistor
fromRt/SyncpintoGndisrequiredtosetthefree‐running
frequency.
WhenanexternalclockisappliedtoRt/Syncpinafterthe
converterrunsinsteadystatewithitsfree‐running
frequency,atransitionfromthefree‐runningfrequencyto
theexternalclockfrequencywillhappen.Thistransitionis
tograduallymaketheactualswitchingfrequencyequalto
theexternalclockfrequency,nomatterwhichoneis
higher.Onthecontrary,whentheexternalclocksignalis
removedfromRt/Syncpin,theswitchingfrequencyisalso
changedtofree‐runninggradually.Inordertominimize
theimpactfromthesetransitionstooutputvoltage,a
diodeisrecommendedtoaddbetweentheexternalclock
andRt/Syncpin,asshowninFigure9a.Figure9bshows
thetimingdiagramofhesetransitions.
IR3897
Rt/Sync
Gnd
Figure9a:ConfigurationofExternalSynchronization
Figure9:TimingDiagramforSynchronization
totheexternalclock(Fs1>Fs2orFs1<Fs2)
AninternalcircuitisusedtochangethePWMrampslope
accordingtotheclockfrequencyappliedonRt/Syncpin.
Eventhoughthefrequencyoftheexternalsynchronization
clockcanvaryinawiderange,thePLLcircuitwillmake
surethattherampamplitudeiskeptconstant,requiringno
adjustmentoftheloopcompensation.Vinvariationalso
affectstherampamplitude,whichwillbediscussed
separatelyinFeed‐Forwardsection.
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June24,2014 |DATASHEET|Rev3.6
22
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
FEED‐FORWARD
Feed‐Forward(F.F.)isanimportantfeature,becauseitcan
keeptheconverterstableandpreserveitsloadtransient
performancewhenVinvariesinalargerange.InIR3897,
F.F.functionisenabledwhenVinpinisconnectedtoPVin
pin.Inthiscase,theinternallowdropout(LDO)regulatoris
used.ThePWMrampamplitude(Vramp)isproportionally
changedwithVintomaintainVin/Vrampalmostconstant
throughoutVinvariationrange(asshowninFig.10).Thus,
thecontrolloopbandwidthandphasemargincanbe
maintainedconstant.Feed‐forwardfunctioncanalso
minimizeimpactonoutputvoltagefromfastVinchange.
ThemaximumVinslewrateiswithin1V/µs.
IfanexternalbiasvoltageisusedasVcc,Vinpinshouldbe
connectedtoVcc/LDO_OutpininsteadofPVinpin.Then
theF.F.functionisdisabled.Are‐calculationofcontrol
loopparametersisneededforre‐compensation.
Figure10:TimingDiagramforFeed‐Forward(F.F.)Function
SMARTLOWDROPOUTREGULATOR(LDO)
IR3897hasanintegratedlowdropout(LDO)regulator
whichcanprovidegatedrivevoltageforbothdrivers.
Inordertoimproveoverallefficiencyoverthewholeload
range,LDOvoltageissetto6.4V(typ.)atmid‐orheavy
loadconditiontoreduceRds(on)andthusMOSFET
conductionloss;anditisreducedto4.4(typ.)atlightload
conditiontoreducegatedriveloss.
ThesmartLDOcanselectitsoutputvoltageaccordingto
theloadconditionbysensingswitchnode(SW)voltage.At
lightloadconditionwhenpartoftheinductorcurrent
flowsinthereversedirection(DCM=1),VSW>0onLDrv
fallingedgeinaswitchingcycle.Ifthiscasehappensfor
consecutive256switchingcycles,thesmartLDOreduces
itsoutputto4.4.Ifinanyoneofthe256cycles,Vsw<0on
LDrvfallingedge,thecounterisresetandLDOvoltage
doesn’tchange.Ontheotherhand,ifVsw<0onLDrv
fallingedge(DCM=0),LDOoutputisincreasedto6.4V.A
hysteresisbandisaddedtoVswcomparisontoavoid
chattering.Figure11ashowsthetimingdiagram.
Wheneverdeviceturnson,LDOalwaysstartswith6.4V,
thengoesto4.4V/6.4Vdependingupontheload
condition.Forinternallybiasedsinglerailoperation,Vin
pinshouldbeconnectedtoPVinpin,asshowninFigure
11b.Ifexternalbiasvoltageisused,Vinpinshouldbe
connectedtoVcc/LDO_Outpin,asshowninFigure11c.
Vcc/
LDO
0
0
IL
256/Fs
... ...
...
6.4V 6.4V
4.4V
...
Figure11a:TimeDiagramforSmartLDO
IR3897
VCC/
LDO_OUT
PGnd
Vin
Vin PVin
Figure11b:InternallyBiasedSingleRailOperation
Figure11c:UseExternalBiasVoltage
WhentheVinvoltageisbelow6.8V,theinternalLDO
entersthedropoutmodeatmediumandheavyload.The
dropoutvoltageincreaseswiththeswitchingfrequency.
Figure11dshowstheLDOvoltagefor600kHzand1500
kHzswitchingfrequencyrespectively.
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June24,2014 |DATASHEET|Rev3.6
23
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
Figure11d:LDO_OutVoltageindropoutmode
OUTPUTVOLTAGETRACKINGANDSEQUENCING
IR3897canaccommodateuserprogrammabletracking
and/orsequencingoptionsusingVp,Vref,Enable,and
PowerGoodpins.Intheblockdiagrampresentedonpage
3,theerror‐amplifier(E/A)hasbeendepictedwiththree
positiveinputs.Ideally,theinputwiththelowestvoltage
isusedforregulatingtheoutputvoltageandtheother
twoinputsareignored.Inpracticethevoltageoftheother
twoinputsshouldbeabout200mVgreaterthanthe
low‐voltageinputsothattheireffectscancompletely
beignored.Vpisinternallybiasedto3.3Vviaahigh
impedancepath.Fornormaloperation,VpandVrefis
leftfloating(Vrefshouldhaveabypasscapacitor).
Therefore,innormaloperatingcondition,afterEnable
goeshigh,theinternalsoft‐start(Intl_SS)rampsupthe
outputvoltageuntilVfb(voltageoffeedback/Fbpin)
reachesabout0.5V.ThenVreftakesoverandtheoutput
voltageisregulated.
Tracking‐modeoperationisachievedbyconnectingVrefto
GND.Intracking‐mode,VfbalwaysfollowsVp,which
meansVoutisalwaysproportionaltoVpvoltage(typical
forDDR/VTTrailapplications).TheeffectiveVpvariation
rangeis0V~1.2V.Fig.5cillustratesthestart‐upofVTT
trackingforDDR4application.VpisproportionaltoVDDQ.
AfterVpisestablished,assertingEnableinitiatesthe
internalsoft‐start.VTT,whichistheoutputofPOL,starts
torampupandtracksVp.
Insequencingmodeofoperation(simultaneousor
ratiometric),VrefisleftfloatingandVpiskepttoground
leveluntilIntl_SSsignalreachesthefinalvalue.ThenVpis
rampedupandVfbfollowsVp.WhenVp>0.5Vtheerror‐
amplifierswitchestoVrefandtheoutputvoltageis
regulatedwithVref.ThefinalVpvoltageaftersequencing
startupshouldbetween0.7V~3.3V.
Boot
Vcc/LDO
Fb
Comp
Gnd PGnd
SW
Vo2
(Salve)
PGood
PGood
Rt/
Sync
PVin
Vp
Vo1
(master)
S_Ctrl Vin
Vref EN
RE
RF
RC
RD
5V < Vin<21V
Vsns
Figure12:ApplicationCircuitforSimultaneous
andRatiometricSequencing
Trackingandsequencingoperationscanbeimplemented
tobesimultaneousorratiometric(refertoFig.13and14).
Figure12showstypicalcircuitconfigurationforsequencing
operation.Withthispower‐upconfiguration,thevoltage
attheVppinoftheslavereaches0.5VbeforetheFbpinof
themaster.IfRE/RF=RC/RD,simultaneousstartupis
achieved.Thatis,theoutputvoltageoftheslavefollows
thatofthemasteruntilthevoltageattheVppinofthe
slavereaches0.5V.AfterthevoltageattheVppinofthe
slaveexceeds0.5V,theinternal0.5Vreferenceofthe
slavedictatesitsoutputvoltage.Inrealitytheregulation
graduallyshiftsfromVptointernalVref.Thecircuitshown
inFig.12canalsobeusedforsimultaneousorratiometric
trackingoperationifVrefoftheslaveisconnectedtoGND.
Table2summarizestherequiredconditionstoachieve
simultaneous/ratiometrictrackingorsequencing
operations.
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June24,2014 |DATASHEET|Rev3.6
24
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
Vcc
Vref=0.5V
1.2V Soft Start (slave)
Enable (slave)
Vo1 (master)
Vo2 (slave)
(a)
Vo1 (master)
Vo2 (slave)
(b)
Figure13:Typicalwaveformsforsequencingmodeofoperation:
(a)simultaneous,(b)ratiometric
Figure14:Typicalwaveformsintrackingmodeofoperation:
(a)simultaneous,(b)ratiometric
TABLE2:REQUIREDCONDITIONSFORSIMULTANEOUS/RATIOMETRIC
TRACKINGANDSEQUENCING(FIG.12)
Operating
Mode
Vref
(Slave)
VpRequired
Condition
Normal
(Non‐sequencing,
Non‐tracking)
0.5V
(Floating)Floating―
Simultaneous
Sequencing0.5VRampup
from0V
RA/RB>RE/
RF=RC/RD
Ratiometric
Sequencing0.5VRampup
from0V
RA/RB>RE/
RF>RC/RD
Simultaneous
Tracking0VRampup
beforeEn
RE/RF
=RC/RD
Ratiometric
Tracking0VRampup
beforeEn
RE/RF
>RC/RD
VREF
Thispinreflectstheinternalreferencevoltagewhichis
usedbytheerroramplifiertosettheoutputvoltage.In
mostoperatingconditionsthispinisonlyconnectedtoan
externalbypasscapacitoranditisleftfloating.A100pF
ceramiccapacitorisrecommendedforthebypass
capacitor.Tokeepstandbycurrenttominimum,Vrefis
notallowedtocomeupuntilENstartsgoinghigh.In
trackingmodethispinshouldbepulledtoGND.For
marginingapplications,anexternalvoltagesourceis
connectedtoVrefpinandoverridestheinternalreference
voltage.Theexternalvoltagesourceshouldhavealow
internalresistance(<100Ω)andbeabletosourceandsink
morethan25µA
POWERGOODOUTPUT(TRACKING,
SEQUENCING,VREFMARGINING)
IR3897continuallymonitorstheoutputvoltageviathe
sensepin(Vsns)voltage.TheVsnsvoltageisaninputto
thewindowcomparatorwithupperandlowerthresholdof
0.6Vand0.45Vrespectively.PGoodsignalishigh
wheneverVsnsvoltageiswithinthePGoodcomparator
windowthresholds.ThePGoodpinisopendrainandit
needstobeexternallypulledhigh.Highstateindicatesthat
outputisinregulation.
Thethresholdissetdifferentlyatdifferentoperating
modesandtheresultsofthecomparisonsetsthePGood
signal.Figures15,16,and17showthetimingdiagramof
thePGoodsignalatdifferentoperatingmodes.Vsnssignal
isalsousedbyOVPcomparatorfordetectingoutputover
voltagecondition.
0
0
0
Vref
PGood
Vsns
0.5 V
1.2*Vref
0.85*Vp
1.28ms 1.28ms
OVP
Latch
0.9*Vp
Figure15:Non‐sequence,Non‐trackingStartup
andVrefMargin(Vppinfloating)
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June24,2014 |DATASHEET|Rev3.6
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IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
0.3V
0
0
0
Vp
Vsns
0.4V
PGood
0.9*Vp
1.2*Vp
1.28ms
Figure16:VpTracking(Vref=0V)
Figure17:VpSequenceandVrefMargin
OVER‐VOLTAGEPROTECTION(OVP)
OVPisachievedbycomparingVsnsvoltagetoanOVP
thresholdvoltage.Innon‐trackingmode,OVPthreshold
voltageis1.2×Vref;intrackingmode,itissetat1.2×Vp.
WhenVsnsexceedstheOVPthreshold,anovervoltage
tripsignalassertsafter2us(typ.)delay.Thenthecontrol
FETislatchedoffimmediately,PGoodflagslow.Thesync
FETremainsontodischargetheoutputcapacitor.When
theVsnsvoltagedropsbelowthethreshold,thesyncFET
turnsofftopreventthecompletedepletionoftheoutput
capacitor.ThecontrolFETremainslatchedoffuntiluser
cycleeitherVccorEnable.
OVPcomparatorbecomesactiveonlywhenthedeviceis
enabled.Furthermore,forOVPtobeactiveVrefhasto
exceed0.2Vinnon‐trackingmode,orVphastoexceedthe
thresholdintracking‐mode,asillustratedinFig18aandFig
18b.Ifeitheroftheaboveconditionsisnotsatisfied,OVP
isdisabled.Vsnsvoltageissetbythevoltagedivider
connectedtotheoutputanditcanbeprogrammed
externally.Figure18cshowsthetimingdiagramforOVPin
non‐trackingmode.
Figure18a:ActivationofOVPinnon‐trackingmode
Figure18b:ActivationofOVPintrackingmode
0
0
0
1.2*Vref
0
1.15*Vref
Figure18c:TimingDiagramforOVPinnon‐trackingmode
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June24,2014 |DATASHEET|Rev3.6
26
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
SOFTSTART/SOFT‐STOP(S_CTRL)
Soft‐stopfunctioncanmakeoutputvoltagedischarge
gradually.Toenablethisfunction,S_Ctrliskeptlowfirst
whenENgoeshigh.ThenS_Ctrlispulledhightocrossthe
logiclevelthreshold(typ.2V),theinternalsoft‐startramp
isinitiated.SoVofollowsIntl_SStorampupuntilit
reachesitssteadystate.Insoft‐stopprocess,S_Ctrlneeds
tobepulledlowbeforeENgoeslow.AfterS_Ctrlgoes
belowitsthreshold,adecreasingrampisgeneratedat
Intl_SSwiththesameslopeasinsoft‐startramp.Vo
followsthisramptodischargesoftlyuntilshutdown
completely.Figure19showsthetimingdiagramofS_Ctrl
controlledsoft‐startandsoft‐stop.
IfthefallingedgeofEnablesignalassertsbeforeS_Ctrl
fallingedge,theconverterisstillturnedoffbyEnable.
BothgatedriversareturnedoffimmediatelyandVo
dischargestozero.Figure20showsthetimingdiagram
ofEnablecontrolledsoft‐startandsoft‐stop.Softstop
featureensuresthatVoutdischargesandalsoregulates
thecurrentpreciselytozerowithnoundershoot.
0
0
0
Intl
_SS
S_Ctrl
Vout
0
Enable
0.15V
0.65V
0.15V
0.65V
Figure19:TimingDiagramforS_Ctrlcontrolled
SoftStart/SoftStop
0
0
0
Intl
_SS
S_Ctrl
Vout
0.15V
0
Enable 1.2V 1.0V
0.65V
Figure20:TimingDiagramforEnablecontrolled
SoftStart/Shutdown
MINIMUMONTIMECONSIDERATIONS
TheminimumONtimeistheshortestamountoftimefor
CtrlFETtobereliablyturnedon.Thisisverycritical
parameterforlowdutycycle,highfrequencyapplications.
Conventionalapproachlimitsthepulsewidthtoprevent
noise,jitterandpulseskipping.Thisresultstolowerclosed
loopbandwidth.
IRhasdevelopedaproprietaryschemetoimproveand
enhanceminimumpulsewidthwhichutilizesthebenefits
ofvoltagemodecontrolschemewithhigherswitching
frequency,widerconversionratioandhigherclosedloop
bandwidth,thelatterresultsinreductionofoutput
capacitors.AnydesignorapplicationusingIR3897must
ensureoperationwithapulsewidththatishigherthanthis
minimumon‐timeandpreferablyhigherthan60ns.
Thisisnecessaryforthecircuittooperatewithoutjitter
andpulse‐skipping,whichcancausehighinductorcurrent
rippleandhighoutputvoltageripple.
in
(3)
V
out
on
ss
V
D
tFF
InanyapplicationthatusesIR3897,thefollowingcondition
mustbesatisfied:
(min)
(min)
(min)
(4)
(5)
(6)
on on
out
on
in s
out
in s
on
tt
V
tVF
V
VFt
Theminimumoutputvoltageislimitedbythereference
voltageandhenceVout(min)=0.5V.Therefore,for
Vout(min)=0.5V,
V/uS 33.8
ns 60
V 0.5
V
V
in
(min)
(min)
in
s
on
out
s
F
t
V
F
Therefore,atthemaximumrecommendedinputvoltage
21Vandminimumoutputvoltage,theconvertershouldbe
designedataswitchingfrequencythatdoesnotexceed
396kHz.Conversely,foroperationatthemaximum
recommendedoperatingfrequency(1.65MHz)and
minimumoutputvoltage(0.5V).Theinputvoltage(PVin)
shouldnotexceed5.05V,otherwisepulseskippingwill
happen.
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June24,2014 |DATASHEET|Rev3.6
27
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
MAXIMUMDUTYRATIO
Acertainoff‐timeisspecifiedforIR3897.Thisprovides
anupperlimitontheoperatingdutyratioatanygiven
switchingfrequency.Theoff‐timeremainsatarelatively
fixedratiotoswitchingperiodinlowandmidfrequency
range,whileinhighfrequencyrangethisratioincreases,
thusthelowerthemaximumdutyratioatwhichIR3897
canoperate.Figure21showsaplotofthemaximumduty
ratiovs.theswitchingfrequencywithbuiltininputvoltage
feedforwardmechanism.
Figure21:Maximumdutycyclevs.switchingfrequency.
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June24,2014 |DATASHEET|Rev3.6
28
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
DESIGNEXAMPLE
Thefollowingexampleisatypicalapplicationfor
IR3897.TheapplicationcircuitisshowninFig.28.
=12 V ( 10% )
=1 2 V
= 4 A
Ripple Voltage= 1% *
= 5% * 50%
=600 kHz
in
o
o
o
oo
s
V
V.
I
V
Δ
V V load transient
F
︵
for )
EnablingtheIR3897
Asexplainedearlier,theprecisethresholdoftheEnable
lendsitselfwelltoimplementationofaUVLOforthe
BusVoltageasshowninFig.22.
Figure22:UsingEnablepinforUVLOimplementation
ForatypicalEnablethresholdofVEN=1.2V
2
(min)
12
* 1.2 (7)
in EN
R
V V
RR
21
min
(8)
EN
in( ) EN
V
RR
VV
ForVin(min)=9.2V,R1=49.9KandR2=7.5Kohmisagood
choice.
Programmingthefrequency
ForFs=600kHz,selectRt=39.2KΩ,usingTable1.
OutputVoltageProgramming
Outputvoltageisprogrammedbyreferencevoltageand
externalvoltagedivider.TheFbpinistheinvertinginputof
theerroramplifier,whichisinternallyreferencedto0.5V.
Thedividerratioissettoprovide0.5VattheFbpinwhenthe
outputisatitsdesiredvalue.Theoutputvoltageisdefinedby
usingthefollowingequation:
5
6
1(9)
oref
R
VV R
Whenanexternalresistordividerisconnectedtotheoutput
asshowninFig.23.
65 (10)
ref
oref
V
RR
VV
ForthecalculatedvaluesofR5andR6,seefeedback
compensationsection.
Figure23:TypicalapplicationoftheIR3897
forprogrammingtheoutputvoltage
BootstrapCapacitorSelection
TodrivetheControlFET,itisnecessarytosupplyagate
voltageatleast4VgreaterthanthevoltageattheSWpin,
whichisconnectedtothesourceoftheControlFET.
Thisisachievedbyusingabootstrapconfiguration,which
comprisestheinternalbootstrapdiodeandanexternal
bootstrapcapacitor(C1).Theoperationofthecircuitisas
follows:WhenthesyncFETisturnedon,thecapacitornode
connectedtoSWispulleddowntoground.Thecapacitor
chargestowardsVccthroughtheinternalbootstrapdiode
(Fig.24),whichhasaforwardvoltagedropVD.ThevoltageVc
acrossthebootstrapcapacitorC1isapproximatelygivenas:
(11)
cccD
VVV
- 29 -
June24,2014 |DATASHEET|Rev3.6
29
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
WhenthecontrolFETturnsoninthenextcycle,the
capacitornodeconnectedtoSWrisestothebusvoltage
Vin.However,ifthevalueofC1isappropriatelychosen,
thevoltageVcacrossC1remainsapproximately
unchangedandthevoltageattheBootpinbecomes:
(12)
Boot in cc D
VVVV
Figure24:BootstrapcircuittogenerateVcvoltage
Abootstrapcapacitorofvalue0.1uFissuitableformost
applications.
InputCapacitorSelection
Theripplecurrentgeneratedduringtheontimeofthe
controlFETshouldbeprovidedbytheinputcapacitor.
TheRMSvalueofthisrippleisexpressedby:
(1 ) (13)
RMS o
IIDD
(14)
o
in
V
DV
Where:
DistheDutyCycle
IRMSistheRMSvalueoftheinputcapacitorcurrent.
Ioistheoutputcurrent.
ForIo=4AandD=0.1,theIRMS=1.8A.
Ceramiccapacitorsarerecommendedduetotheirpeak
currentcapabilities.TheyalsofeaturelowESRandESLat
higherfrequencywhichenablesbetterefficiency.
Forthisapplication,itisadvisabletohave3x10uF,25V
ceramiccapacitors,C3216X5R1E106MfromTDK.
Inadditiontothese,althoughnotmandatory,
a1x330uF,25VSMDcapacitorEEV‐FK1E331PfromPanasonic
mayalsobeusedasabulkcapacitorandisrecommendedif
theinputpowersupplyisnotlocatedclosetotheconverter.
InductorSelection
Theinductorisselectedbasedonoutputpower,operating
frequencyandefficiencyrequirements.Alowinductorvalue
causeslargeripplecurrent,resultinginthesmallersize,faster
responsetoaloadtransientbutpoorefficiencyandhigh
outputnoise.Generally,theselectionoftheinductorvalue
canbereducedtothedesiredmaximumripplecurrentinthe
inductor(Δi).Theoptimumpointisusuallyfoundbetween
20%and50%rippleoftheoutputcurrent.
Forthebuckconverter,theinductorvalueforthedesired
operatingripplecurrentcanbedeterminedusingthe
followingrelation:
1
;
(15)
*
in o
s
o
in o
in s
i
VVL tD
tF
V
LVV ViF
Where:
Vin=Maximuminputvoltage
V0=OutputVoltage
Δi=InductorPeak‐to‐PeakRippleCurrent
Fs=SwitchingFrequency
Δt=ONtime
D=DutyCycle
IfΔi≈30%*Io,thentheoutputinductoriscalculatedtobe
1.5μH.SelectL=1.5μH,PCMB065T‐1R5MS,fromCyntecwhich
providesacompact,lowprofileinductorsuitableforthis
application.
- 30 -
June24,2014 |DATASHEET|Rev3.6
30
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
OutputCapacitorSelection
Thevoltagerippleandtransientrequirements
determinetheoutputcapacitorstypeandvalues.
Thecriteriaisnormallybasedonthevalueofthe
EffectiveSeriesResistance(ESR).Howevertheactual
capacitancevalueandtheEquivalentSeriesInductance
(ESL)areothercontributingcomponents.
Thesecomponentscanbedescribedas:
() () ()
()
()
()
*
*
(16)
8* *
o o ESR o ESL o C
oESR L
in o
oESL
L
oC
os
VV V V
VIESR
VV
VESL
L
I
VCF
Where:
ΔV0=OutputVoltageRipple
ΔIL=InductorRippleCurrent
Sincetheoutputcapacitorhasamajorroleinthe
overallperformanceoftheconverteranddetermines
theresultoftransientresponse,selectionofthe
capacitoriscritical.TheIR3897canperformwellwith
alltypesofcapacitors.
Asarule,thecapacitormusthavelowenoughESRto
meetoutputrippleandloadtransientrequirements.
Thegoalforthisdesignistomeetthevoltageripple
requirementinthesmallestpossiblecapacitorsize.
Thereforeitisadvisabletoselectceramiccapacitors
duetotheirlowESRandESLandsmallsize.FourofTDK
C2012X5R0J226M(22uF/0805/X5R/6.3V)capacitorsis
agoodchoice.
Itisalsorecommendedtousea0.1µFceramiccapacitor
attheoutputforhighfrequencyfiltering.
FeedbackCompensation
TheIR3897isavoltagemodecontroller.Thecontrolloop
isasinglevoltagefeedbackpathincludinganerroramplifier
anderrorcomparator.Toachievefasttransientresponse
andaccurateoutputregulation,acompensationcircuitis
necessary.Thegoalofthecompensationnetworkistoclose
thecontrolloopathighcrossoverfrequencywithphase
margingreaterthan45o.
TheoutputLCfilterintroducesadoublepole,‐40dB/decade
gainslopeaboveitscornerresonantfrequency,andatotal
phaselagof180o.TheresonantfrequencyoftheLCfilteris
expressedasfollows:
1 (17)
2
LC
oo
FLC
Figure25showsgainandphaseoftheLCfilter.Sincewe
alreadyhave180ophaseshiftfromtheoutputfilteralone,
thesystemrunstheriskofbeingunstable.
Phase
00
FLC
0
Frequency
FLC Frequency
00
-180
0
0dB
-40dB/Decade
-90
Gain
Figure25:GainandPhaseofLCfilter
TheIR3897usesavoltage‐typeerroramplifierwithhigh‐gain
(110dB)andhigh‐bandwidth(30MHz).Theoutputofthe
amplifierisavailableforDCgaincontrolandACphase
compensation.
TheerroramplifiercanbecompensatedeitherintypeIIor
typeIIIcompensation.TypeIIcompensationisshowninFig.
26.Thismethodrequiresthattheoutputcapacitorshave
enoughESRtosatisfystabilityrequirements.Iftheoutput
capacitor’sESRgeneratesazeroat5kHzto50kHz,thezero
generatesacceptablephasemarginandtheTypeII
compensatorcanbeused.
- 31 -
June24,2014 |DATASHEET|Rev3.6
31
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
TheESRzerooftheoutputcapacitorisexpressedas
follows:
1(18)
2
ESR
o
Fπ*ESR*C
VOUT
VREF
R6
R5
CPOLE
C3
R3
Ve
FZFPOLE
E/A
Zf
Frequency
Gain(dB)
H(s) dB
Fb
Comp
ZIN
Figure26:TypeIIcompensationnetwork
anditsasymptoticgainplot
Thetransferfunction(Ve/Vout)isgivenby:
33
53
1
( ) (19)
f
e
out IN
Z
VsRC
Hs
VZsRC
The(s)indicatesthatthetransferfunctionvariesasa
functionoffrequency.Thisconfigurationintroducesa
gainandzero,expressedby:
3
5
33
(20)
1(21)
2* *
z
R
Hs R
FRC
Firstselectthedesiredzero‐crossoverfrequency(Fo):
o(22) and F 1/5~1/10 *
oESR s
FF F
UsethefollowingequationtocalculateR3:
5
32
** * (23)
*
osc o ESR
in LC
VFF R
RVF
Where:
Vin=MaximumInputVoltage
Vosc=AmplitudeoftheoscillatorRampVoltage
Fo=CrossoverFrequency
FESR=ZeroFrequencyoftheOutputCapacitor
FLC=ResonantFrequencyoftheOutputFilter
R5=FeedbackResistor
TocanceloneoftheLCfilterpoles,placethezerobeforethe
LCfilterresonantfrequencypole:
75 % *
1
0.75* (24)
2*
zLC
z
oo
FF
FLC
Useequations(20),(21)and(22)tocalculateC3.
OnemorecapacitorissometimesaddedinparallelwithC3
andR3.Thisintroducesonemorepolewhichismainlyused
tosuppresstheswitchingnoise.
Theadditionalpoleisgivenby:
3
3
3
1(25)
*
2* *
P
POLE
POLE
FCC
RCC
Thepolesetstoonehalfoftheswitchingfrequencywhich
resultsinthecapacitorCPOLE:
3
3
3
11
(26)
1
POLE
s
s
C*R *F
*R *F C
Forageneralsolutionforunconditionalstabilityforanytype
ofoutputcapacitors,andawiderangeofESRvalues,atypeIII
compensationnetworkcanbeused,asshowninFig.27.
- 32 -
June24,2014 |DATASHEET|Rev3.6
32
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
V
OUT
V
REF
R6
R5
R4
C4
C2
C3
R3
Ve
F
Z1F
Z2F
P2FP3
E/A
Zf
ZIN
Frequency
Gain (dB)
|H(s)| dB
Fb
Comp
Figure27:TypeIIICompensationnetwork
anditsasymptoticgainplot
Again,thetransferfunctionisgivenby:
IN
f
out
e
Z
Z
sH
V
V )(
ByreplacingZinandZf,accordingtoFig.27,thetransfer
functioncanbeexpressedas:
33 4 4 5
23
52 3 3 44
23
(1 ) 1
*
() ()1 (1 )
(27)
sR C sC R R
CC
Hs
s
RC C sR sRC
CC
Thecompensationnetworkhasthreepolesandtwo
zerosandtheyareexpressedasfollows:
1
2
44
3
32
23
3
23
0(28)
1(29)
2* *
11
(30)
2* *
*
2*
P
P
P
F
FRC
FRC
CC
RCC
1
33
2
445 45
1(31)
2* *
11
(32)
2* *( ) 2* *
Z
Z
FRC
FCRR CR
Crossoverfrequencyisexpressedas:
34
1
* * * (33)
2* *
in
o
osc o o
V
FRC
VLC
Basedonthefrequencyofthezerogeneratedbytheoutput
capacitoranditsESR,relativetocrossoverfrequency,the
compensationtypecanbedifferent.Table3showsthe
compensationtypesforrelativelocationsofthecrossover
frequency.
TABLE3:DIFFERENTTYPESOFCOMPENSATORS
Compensator
Type FESRvsFOTypicalOutput
Capacitor
TypeIIFLC<FESR<FO<FS/2Electrolytic
TypeIIIFLC<FO<FESRSPCap,Ceramic
Thehigherthecrossoverfrequencyis,thepotentiallyfaster
theloadtransientresponsewillbe.However,thecrossover
frequencyshouldbelowenoughtoallowattenuationof
switchingnoise.Typically,thecontrolloopbandwidthor
crossoverfrequency(Fo)isselectedsuchthat:
so F F * 1/10~1/5
TheDCgainshouldbelargeenoughtoprovidehigh
DC‐regulationaccuracy.Thephasemarginshouldbegreater
than45oforoverallstability.
Forthisdesignwehave:
Vin=12V
Vo=1.2V
Vosc=1.8V(ThisisafunctionofVin,pls.seefeedforward
section)
Vref=0.5V
Lo=1.5uH
Co=4x22uF,ESR≈3mΩeach
Itmustbenotedherethatthevalueofthecapacitanceused
inthecompensatordesignmustbethesmallsignalvalue.
Forinstance,thesmallsignalcapacitanceofthe22uF
capacitorusedinthisdesignis10uFat1.2VDCbiasand
600kHzfrequency.Itisthisvaluethatmustbeusedforall
- 33 -
June24,2014 |DATASHEET|Rev3.6
33
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
computationsrelatedtothecompensation.Thesmall
signalvaluemaybeobtainedfromthemanufacturer’s
datasheets,designtoolsorSPICEmodels.Alternatively,
theymayalsobeinferredfrommeasuringthepower
stagetransferfunctionoftheconverterandmeasuring
thedoublepolefrequencyFLCandusingequation(17)
tocomputethesmallsignalCo.
Theseresultto:
FLC=20.5kHz
FESR=5.3MHz
Fs/2=300kHz
SelectcrossoverfrequencyF0=120kHz
SinceFLC<F0<Fs/2<FESR,TypeIIIisselectedtoplacethe
poleandzeros.
DetailedcalculationofcompensationTypeIII:
DesiredPhaseBoostΘ=70°
2
1sin 21.2 KHz
1sin
Zo
FF
2
1sin 680.6 kHz
1sin
Po
FF
Select:
12
0.5* 10.6 kHz and
ZZ
FF
30.5* 300 kHz
Ps
FF
SelectC4=2.2nF.
CalculateR3,C3andC2:
33
4
2* * * * ;3.08Ω
*
oo oosc
in
FLCV
R
Rk
CV
SelectR3=3.01kΩ:
33 3
13
1; 4.9 nF, Select: 10 nF
2* *
Z
CC C
FR
22 2
33
1; 176 pF, Select: 120 pF
2* *
P
CC C
FR
CalculateR4,R5andR6:
44 4
42
1; 106 Ω, Select: 100 Ω
2* *P
RR R
CF
545
42
1- ; 3.41 kΩ,
2* *Z
RRR
CF
SelectR5=3.32kΩ:
656 6
*; 2.37 kΩ Select: 2.37 kΩ
-
ref
oref
V
RRR R
VV
SettingthePowerGoodThreshold
InthisdesignIR3897isusedinnormal(non‐tracking,
non‐sequencing)mode,thereforethePGoodthresholdsare
internallysetat90%and120%ofVref.Atstartupassoonas
Vsnsvoltagereaches0.9*0.5V=0.45V(Fig.15),after1.28ms
delay,PGoodsignalisasserted.AslongastheVsnsvoltage
isbetweenthethresholdrange,Enableishigh,andnofault
happens,thePGoodremainshigh.
Thefollowingformulacanbeusedtosetthethreshold.
VoutPGood_Thcanbetakenas90%ofVout.ChooseR7=3.32KΩ:
_
*0.9* 7
8 (34)
*0.9
82.37
PGood Th
Vref R
RVout Vref
RK
ThePGoodisanopendrainoutput.Hence,itisnecessaryto
useapullupresistor,RPG,fromPGoodpintoVcc.Thevalue
ofthepull‐upresistormustbechosensuchastolimitthe
currentflowingintothePGoodpintolessthan5mAwhen
theoutputvoltageisnotinregulation.Atypicalvalueused
is49.9kΩ.
OVPcomparatoralsousesVsnssignalforoverVoltage
dectection.WithabovevaluesforR7andR8,OVPtrippoint
(Vout_OVP)is
_
*1.2*( 7 8) / 8 1.44 (35)OVPVout Vref R R R V
VrefBypassCapacitor
Aminimumvalueof100pFbypasscapacitorisrecommended
tobeplacedbetweenVrefandGndpins.Thiscapacitorshould
beplacedascloseaspossibletoVrefpin..
- 34 -
June24,2014 |DATASHEET|Rev3.6
34
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
APPLICATIONDIAGRAM
Figure28a:ApplicationCircuitfora12Vto1.2V,4APointofLoadConverter
Suggestedbillofmaterialsfortheapplicationcircuit
Part Reference Qty Value Description Manufacturer Part Number
Cin 2 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M
C1 C5 C6 4 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B
Cref 1 100pF 0603,50V,NP0, 5% Murata GRM1885C1H101JA01D
C4 1 2200pF 0603,50V,X7R Murata GRM188R71H222KA01B
C2 1 120pF
0603, 50V, NP0, 5% Murata GRM1885C1H121JA01D
Co 4 22uF
0805, 6.3V, X5R, 20% TDK C2012X5R0J226M
CVcc 1 2.2uF
0603, 16V, X5R, 20% TDK C1608X5R1C225M
C3 1 10nF
0603, 25V, X7R, 10% Murata GRM188R71E103KA01J
Cvin 1 1.0uF
0603, 25V, X5R, 10% Murata GRM188R61E105KA12D
Lo 1 1.5H SMD 7.05x6.6x4.8mm,6.7mΩ Cyntec PCMB065T-1R5MS
R3 1 3.01K
Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3011V
R5 R7 2 3.32K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3321V
R6 R8 2 2.37K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF2371V
R4 1 100
Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1000V
Rt 1 39.2K
Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3922V
R1 Rpg 2 49.9K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V
R2 1 7.5K
Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF7551V
U1 1 IR3897 PQFN 4x5mm IR IR3897MPBF
- 35 -
June24,2014 |DATASHEET|Rev3.6
35
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
Boot
Vcc/LDO_out
Fb
Comp
Gnd PGnd
SW
S_Ctrl
Vo=1.2V
PGood
Enable
Rt/Sync
Vin=12 V
Vin
Vp
R5
3.32k
2.37K
Co=4X22uF
Lo
1.5 uH
C4
2.2nF
R4
143
R3
1.78k
C3
10nF
C2
120pF
C1
0. 1 uF
Cin = 3 X 10uF
Rt
39.2.K
RPG
49.9K
R1
49.9K
R2
7.5K
IR3897
2.2uF
CVcc
PVin
Vref
100pF
Cref
Vsns
R6
R7
3.32k
2.37K
R8
U1
C5
0.1uF
C6
0.1uF
External VCC=5V
Figure28b:ApplicationCircuitfora12Vto1.2V,4APointofLoadConverterwithExternal5VVCC
- 36 -
June24,2014 |DATASHEET|Rev3.6
36
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
Boot
Vcc/LDO_out
Fb
Comp
Gnd PGnd
SW
S_Ctrl
Vo=1V
PGood
Enable
Rt/Sync
Vin=5V
Vin
Vp
R5
3.32k
3.32k
Co=4X22uF
Lo
1uH
C4
2.2nF
R4
100
R3
3.01k
C3
5.6nF
C2
100pF
C1
0. 1 uF
Cin = 3 X 10uF
Rt
39.2.K
RPG
49.9K
IR3897
2.2uF
CVcc
PVin
Vref
100pF
Cref
Vsns
R6
R7
3.32k
3.32k
R8
U1
C5
0.1uF
C6
0.1uF
PGood
Enable
Figure29:ApplicationCircuitfora5Vto1V,4APointofLoadConverter
Suggestedbillofmaterialsfortheapplicationcircuit5Vto1V
Part Reference Qty Value Description Manufacturer Part Number
Cin 3 10uF 1206, 25V, X5R, 20% TDK C3216X5R1E106M
C1 C5 C6 3 0.1uF 0603, 25V, X7R, 10% Murata GRM188R71E104KA01B
Cref 1 100pF 0603,50V,NP0, 5% Murata GRM1885C1H101JA01D
C4 1 2200pF 0603,50V,X7R Murata GRM188R71H222KA01B
C2 1 100pF
0603, 50V, NP0, 5% Murata GRM1885C1H101JA01D
Co 4 22uF
0805, 6.3V, X5R, 20% TDK C2012X5R0J226M
CVcc 1 2.2uF
0603, 16V, X5R, 20% TDK C1608X5R1C225M
C3 1 5.6nF
0603, 50V, X7R, 10% Murata GRM188R71H562KA01D
Cvin 1 1.0uF
0603, 25V, X5R, 10% Murata GRM188R61E105KA12D
Lo 1 1uH SMD 6.86x6.47x5mm,4.7mΩ TDK SPM6550T-1R0M
R3 1 3.01k
Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3011V
R5 R6 R7 R8 4 3.32K Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3321V
R4 1 100
Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF1000V
Rt 1 39.2K
Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF3922V
Rpg 2 49.9K
Thick Film, 0603,1/10W,1% Panasonic ERJ-3EKF4992V
U1 1 IR3897 PQFN 4x5mm IR IR3897MPBF
- 37 -
June24,2014 |DATASHEET|Rev3.6
37
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
Vo=0.6V
Boot
Vcc/LDO_out
Fb
Comp
Gnd PGnd
SW
S_Ctrl
PGood
PGood
Enable
Rt/Sync
Vin=12 V
Vin
Vp
R5
3.32k
Co=4X47uF
Lo
0.82uH
C4
3.3nF
R4
100
R3
1.6k
C3
8.2nF
C2
150pF
C1
0. 1 uF
Cin = 3 X 10
uF
Rt
60.4 K
RPG
49.9k
IR3897
2.2uF
CVcc
PVin
Vref
Vsns
R7
3.32k
Cvin
1.0uF
U1
C5
0.1uF
C6
0.1uF
1k
1k
R6
VDDQ=
1.2V
R8 10nF
C7
N/S
(optional)
Enable
Figure30:ApplicationCircuitfora12Vto0.6V,4A,VTTrail
Boot
Vcc/LDO_out
Fb
Comp
Gnd PGnd
SW
S_Ctrl
Vo=0.6V
PGood
PGood
Enable
Rt/Sync
Vin=1.2V
Vin
Vp
R5
5.62k
Co=5X22uF
Lo
0.36uH
C4
2.2nF
R4
182
R3
4.64k
C3
5.6nF
C2
110pF
C1
0. 1 uF
Cin = 3 X 22uF
Rt
39.2 K
RPG
49.9k
IR3897
2.2uF
CVcc
PVin
Vref
Vsns
R7
5.62k
U1
C5
0.1uF
C6
0.1uF
1k
1k
R6
R8 10nF
C7
Ext VCC
Enable
Vin=1.2V N/S
(optional)
Figure31:ApplicationCircuitfora1.2Vto0.6V,4A,VTTrail
- 38 -
June24,2014 |DATASHEET|Rev3.6
38
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
TYPICALOPERATINGWAVEFORMS
Vin=12V,Vo=1.2V,Iout=0‐4A,RoomTemperature,NoAirFlow
Figure32:Startupat4ALoad,Figure33:Startupat4ALoad,
Ch1:Vin,Ch2:Vo,Ch3:PGood,Ch4:Enable Ch1:Vin,Ch2:Vo,Ch3:PGood,Ch4:Vcc
Figure34:Startupwith1Vprebias,Figure35:OutputVoltageRipple
0ALoad,Ch2:Vo 4ALoad,Ch2:Vo
Figure36:Inductornodeat4ALoad,Ch2‐LX Figure37:ShortCircuitRecovery,
Ch2:Vo,Ch4:Iout(2A/Div)
- 39 -
June24,2014 |DATASHEET|Rev3.6
39
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
TYPICALOPERATINGWAVEFORMS
Vin=12V,Vo=1.2V,Iout=0‐4A,RoomTemperature,NoAirFlow
Figure38:TurnonatNoLoadshowingVcclevel, Figure39:TurnonatFullLoadshowingVcclevel,
Ch1:Vin,Ch2:Vo,Ch3:Vcc,Ch4:InductorCurrent Ch1:Vin,Ch2:Vo,Ch3:Vcc,Ch4:InductorCurrent
40:TransientResponse,2Ato4Astep@2.5A/uSecslewrate,
Ch2:Vout,Ch4‐Iout(1A/Div)
- 40 -
June24,2014 |DATASHEET|Rev3.6
40
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
TYPICALOPERATINGWAVEFORMS
Vin=12V,Vo=1.2V,Iout=0‐4A,RoomTemperature,NoAirFlow
Figure41:BodePlotat4Aloadshowsabandwidthof112.6KHzandphasemarginof52.4degrees
Figure42:ThermalImageoftheBoardat4ALoad,
TestPoint1isIR3897,
TestPoint2isinductor
- 41 -
June24,2014 |DATASHEET|Rev3.6
41
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
TYPICALOPERATINGWAVEFORMS
Vin=12V,Vo=1.2V,Iout=0‐4A,RoomTemperature,NoAirFlow
Figure43:FeedForwardforVinchangefrom7to16V Figure44:Start/StopusingS‐Ctrlpin,
andbackto7V,Ch2:Vo,Ch4:Vin Ch1:Enable,Ch2:Vo,Ch3:pGood,Ch4:S‐Ctrl
Figure45:ExternalFrequencySynchronizationto Figure46:OverVoltageprotection,
800KHzfromfreerunning600KHz,Ch1:LX,Ch2:Vo,Ch4‐Rt/SyncCh2‐Vo,Ch3‐PGood
Figure47:VoltageMarginingusingVrefpin 48:VoltagetrackingusingVppin
Ch2‐Vo,Ch3‐Vref,Ch4‐PGood Ch2‐Vo,Ch3‐Vp,Ch4‐PGood
- 42 -
June24,2014 |DATASHEET|Rev3.6
42
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
LAYOUTRECOMMENDATIONS
Thelayoutisveryimportantwhendesigninghigh
frequencyswitchingconverters.Layoutwillaffectnoise
pickupandcancauseagooddesigntoperformwithless
thanexpectedresults.
Maketheconnectionsforthepowercomponentsinthe
toplayerwithwide,copperfilledareasorpolygons.In
general,itisdesirabletomakeproperuseofpowerplanes
andpolygonsforpowerdistributionandheatdissipation.
Theinductor,outputcapacitorsandtheIR3897shouldbe
asclosetoeachotheraspossible.Thishelpstoreducethe
EMIradiatedbythepowertracesduetothehighswitching
currentsthroughthem.Placetheinputcapacitordirectly
atthePVinpinofIR3897.
Thefeedbackpartofthesystemshouldbekeptawayfrom
theinductorandothernoisesources.
ThecriticalbypasscomponentssuchascapacitorsforVin,
VccandVrefshouldbeclosetotheirrespectivepins.Itis
importanttoplacethefeedbackcomponentsincluding
feedbackresistorsandcompensationcomponentscloseto
FbandComppins.
InamultilayerPCBuseonelayerasapowergroundplane
andhaveacontrolcircuitground(analogground),towhich
allsignalsarereferenced.Thegoalistolocalizethehigh
currentpathtoaseparateloopthatdoesnotinterfere
withthemoresensitiveanalogcontrolfunction.Thesetwo
groundsmustbeconnectedtogetheronthePCboard
layoutatasinglepoint.Itisrecommendedtoplaceall
thecompensationpartsovertheanaloggroundplanein
toplayer.
ThePowerQFNisathermallyenhancedpackage.Basedon
thermalperformanceitisrecommendedtouseatleasta
4‐layersPCB.Toeffectivelyremoveheatfromthedevice
theexposedpadshouldbeconnectedtothegroundplane
usingvias.Figures46a‐dillustratestheimplementationof
thelayoutguidelinesoutlinedabove,ontheIRDC38974‐
layerdemoboard.
Figure49a:IRDC3897DemoboardLayoutConsiderations–TopLayer
Compensation parts
should be placed
as close as possible
to the Comp pin
Resistor Rt and Vref
decoupling cap should
be placed as close as
possible to their pins
Enough copper &
minimum ground length
path between Input and
Output
A
ll bypass caps
should be placed
as close as possible
to their connecting pins
SW node copper is
kept only at the top
layer to minimize
the switching noise
- 43 -
June24,2014 |DATASHEET|Rev3.6
43
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
Figure49b:IRDC3897DemoboardLayoutConsiderations–BottomLayer
AnalogGroundplanePowerGroundplane
Figure49c:IRDC3897DemoboardLayoutConsiderations–MidLayer1
Figure49d:IRDC3897DemoboardLayoutConsiderations–MidLayer2
Single point connection
between AGND & PGND,
should be close to the
SupIRBuck kept away from
noise sources
Feedback andVsnstrace
routingshouldbekeptaway
fromnoisesources
- 44 -
June24,2014 |DATASHEET|Rev3.6
44
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
PCBMETALANDCOMPONENTPLACEMENT
Evaluationshaveshownthatthebestoverall
performanceisachievedusingthesubstrate/PCBlayout
asshowninfollowingfigures.PQFNdevicesshouldbe
placedtoanaccuracyof0.050mmonbothXandYaxes.
Self‐centeringbehaviorishighlydependentonsolders
andprocesses,andexperimentsshouldberuntoconfirm
thelimitsofself‐centeringonspecificprocesses.
Forfurtherinformation,pleasereferto“SupIRBuck™
Multi‐ChipModule(MCM)PowerQuadFlatNo‐Lead
(PQFN)BoardMountingApplicationNote.”(AN1132)
Figure50:PCBMetalPadSpacing(alldimensionsinmm)
*ContactInternationalRectifiertoreceiveanelectronicPCBLibraryfileinyourpreferredformat
- 45 -
June24,2014 |DATASHEET|Rev3.6
45
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
SOLDERRESIST
IRrecommendsthatthelargerPowerorLand
AreapadsareSolderMaskDefined(SMD.)
ThisallowstheunderlyingCoppertracestobeas
largeaspossible,whichhelpsintermsofcurrent
carryingcapabilityanddevicecoolingcapability.
WhenusingSMDpads,theunderlyingcopper
tracesshouldbeatleast0.05mmlarger(oneach
edge)thantheSolderMaskwindow,inorderto
accommodateanylayertolayermisalignment.
(i.e.0.1mminX&Y.)
However,forthesmallerSignaltypeleadsaround
theedgeofthedevice,IRrecommendsthatthese
areNonSolderMaskDefinedorCopperDefined.
WhenusingNSMDpads,theSolderResist
WindowshouldbelargerthantheCopperPad
byatleast0.025mmoneachedge,(i.e.0.05mm
inX&Y,)inordertoaccommodateanylayerto
layermisalignment.
Ensurethatthesolderresistin‐betweenthe
smallersignalleadareasareatleast0.15mm
wide,duetothehighx/yaspectratioofthe
soldermaskstrip.
Figure51:Solderresist
*ContactInternationalRectifiertoreceiveanelectronicPCBLibraryfileinyourpreferredformat
- 46 -
June24,2014 |DATASHEET|Rev3.6
46
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
STENCILDESIGN
StencilsforPQFNcanbeusedwiththicknesses
of0.100‐0.250mm(0.004‐0.010").Stencilsthinner
than0.100mmareunsuitablebecausethey
depositinsufficientsolderpastetomakegood
solderjointswiththegroundpad;highreductions
sometimescreatesimilarproblems.Stencilsin
therangeof0.125mm‐0.200mm(0.005‐0.008"),
withsuitablereductions,givethebestresults.
Evaluationshaveshownthatthebestoverall
performanceisachievedusingthestencildesign
showninfollowingfigure.Thisdesignisfor
astencilthicknessof0.127mm(0.005").
Thereductionshouldbeadjustedforstencils
ofotherthicknesses.
Figure52:StencilPadSpacing(alldimensionsinmm)
*ContactInternationalRectifiertoreceiveanelectronicPCBLibraryfileinyourpreferredformat
- 47 -
June24,2014 |DATASHEET|Rev3.6
47
IR3897
4AHighlyIntegratedSupIRBuckTM
Single‐InputVoltage,SynchronousBuckRegulator
PD
‐
9766
3
MARKING INFORMATION
PACKAGE INFORMATION
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Industrial market
Visit us at www.irf.com for sales contact information
Data and specifications su bje ct to change without notice.9/11
Figure54:PackageDimensions
Figure53:MarkingInformation
