CPLD Development/Programmer Kit
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User Guide
-2 CPLD Development/Programmer Kit User Guide
xxxxA–XXXXX–xx/xx
CPLD Development/Programmer Kit User Guide i
3300A–PLD–08/02
Table of Contents
Section 1
Introduction ........................................................................................... 1-1
1.1 CPLD Development/Programmer Kit ........................................................1-1
1.3 Kit Features...............................................................................................1-2
1.3.1 CPLD Development/Programmer Board ............................................1-2
1.3.2 Logic Doubling CPLDs .......................................................................1-2
1.3.3 CPLD ISP Download Cable................................................................1-2
1.3.4 PLD Software CD-ROM......................................................................1-2
1.3.5 Atmel CD-ROM Data Books ...............................................................1-3
1.4 Device Support .........................................................................................1-3
1.5 System Requirements...............................................................................1-3
1.7 Technical Support .....................................................................................1-4
1.8.1 ProChip Designer ...............................................................................1-5
1.8.2 Atmel-WinCUPL .................................................................................1-5
1.8.3 ATMISP ..............................................................................................1-5
1.8.4 POF2JED ...........................................................................................1-5
Section 2
Hardware Description ........................................................................... 2-1
2.1 Atmel CPLD Development/Programmer Board.........................................2-1
2.1.1 8-segment Display LEDs ....................................................................2-2
2.1.2 Push-button Switches.........................................................................2-6
2.1.3 Clock Select Jumper...........................................................................2-6
2.1.4 VCC Select Jumper ............................................................................2-7
2.1.5 JTAG Port Header ..............................................................................2-7
2.1.6 Power Connectors ..............................................................................2-8
2.2.1 Expansion Terminal Holes..................................................................2-9
2.3 Atmel CPLD ISP Cable .............................................................................2-9
Section 3
CPLD Design Flow Tutorial .................................................................. 3-1
3.1 Overview ...................................................................................................3-1
3.2 Create a Project Using the “New Project Wizard”.....................................3-1
3.3 Add a Design File......................................................................................3-6
Section 4
Schematic Diagrams............................................................................. 4-1
Table of Contents
ii CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
CPLD Development/Programmer Kit User Guide 1-1
Rev. 3300A–PLD–08/02
Section 1
Introduction
1.1 CPLD
Development/
Programmer Kit
The Atmel CPLD Development/Programmer Kit (P/N: ATF15xx-DK2) is a complete
development system and an In-System Programming (ISP) programmer for the
ATF15xx family of industry-standard pin-compatible Complex Programmable Logic
Devices (CPLDs) with Logic Doubling™features. This kit provides designers a very
quick and easy way to develop, prototype and evaluate new designs with an ATF15xx
CPLD. With the availability of the different Socket Adapter Boards to support all the
package types offered in the ATF15xx family of ISP CPLDs, this CPLD Develop-
ment/Programmer Board can be used as an ISP programmer to program the ATF15xx
ISP CPLDs in all the available package types through the industry-standard JTAG inter-
face (IEEE 1149.1a-1993).
Figure 1-1.
Contents of the ATF15xx-DK2
Introduction
1-2 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
1.2 Kit Contents
n
CPLD Development/Programmer Board
n
84-lead PLCC Socket Adapter Board (P/N: ATF15xx-SAJ84)(1)
n
Atmel CPLD ISP Download Cable
n
Atmel PLD Software CD-ROM (includes ProChip Designer™, Atmel-WinCUPL™and
other EPLD software)
n
Atmel CD-ROM Data Books
n
One ATF1508AS 5V 84-lead PLCC Sample Device
n
One ATF1508ASVL 3.3V, low-power, 84-lead PLCC Sample Device
n
Atmel CPLD Development/Programmer Kit User Guide
Note: 1. Only the 84-lead PLCC Socket Adapter Board is included in this kit. Other Socket
Adapter Boards are sold separately. Please refer to Section 1.6 for ordering informa-
tion of the Socket Adapter Boards.
1.3 Kit Features
1.3.1 CPLD Development/
Programmer Board
n
10-lead JTAG-ISP Port
n
Regulated Power Supply Circuitry for 9V DC Power Source
n
5V or 3.3V VCC Operation
n
84-lead PLCC Socket Adapter Board
n
Socket Adapter Board Headers
n
Expansion Terminal Holes for all Input and I/O pins of the ATF15xx Device
n
2 MHz Crystal Oscillator
n
Eight 8-segment LED Displays
n
Global Clear and Output Enable Push Button Switches
1.3.2 Logic Doubling
CPLDs
n
ATF1508AS-15JC84, 5V 128-Macrocell ISP CPLD with Logic Doubling Architecture
n
ATF1508ASVL-20JC84, 3.3V Low-power 128-Macrocell ISP CPLD with Logic
Doubling Architecture
1.3.3 CPLD ISP Download
Cable
n
5V/3.3V ISP Download Cable for PC Parallel Printer (LPT) Port
1.3.4 PLD Software
CD-ROM
n
Free Atmel-WinCUPL™Design Software
n
30-day Trial Version of Atmel ProChip Designer™Software
n
Full Licensed Version of Atmel ProChip Designer Software (permanent license
required)
n
Atmel CPLD ISP Software (ATMISP)
n
POF2JED Conversion Utility
n
Logic Doubling Support and Documentation
Introduction
CPLD Development/Programmer Kit User Guide 1-3
3300A–PLD–08/02
1.3.5 Atmel CD-ROM
Data Books
n
Data Sheets
n
Application Notes
n
Manuals and User Guides
1.4 Device Support The Atmel CPLD Development/Programmer Board supports the following devices in all
speed grades and packages:
1.5 System
Requirements
The minimum hardware and software requirements to program an ATF15xx ISP CPLD
on the CPLD Development/Programmer Board through the Atmel CPLD ISP Software
(ATMISP) V4.0 or later are:
n
Pentium®or Pentium-compatible microprocessor based computer
n
Windows®98, Windows NT®4.0, Windows ME, or Windows 2000
n
16-MByte RAM
n
10-MByte free hard disk space
n
Windows-supported mouse
n
Available parallel printer (LPT) port
n
9V DC power supply with 500 mA of supply current
n
SVGA monitor (800 x 600 resolution)
ATF1502AS/ASL ATF1508AS/ASL
ATF1502ASV ATF1508ASV/ASVL
ATF1502SE/SEL ATF1508SE/SEL
ATF1502AE/AEL ATF1508AE/AEL
ATF1504AS/ASL ATF1516SE/SEL (Future)
ATF1504ASV/ASVL ATF1516AE/AEL (Future)
ATF1504SE/SEL ATF1532AE/AEL (Future)
ATF1504AE/AEL
Introduction
1-4 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
1.6 Ordering
Information
1.7 Technical
Support
For technical support on any Atmel PLD related issues, please contact the Atmel PLD
Applications Group at:
Hotline: 1-408-436-4333
Email: pld@atmel.com
URL: www.atmel.com/atmel
Part Number Description
ATF15xx-DK2 Atmel CPLD Development/Programmer Kit
ATF15xx-SAA44 44-lead TQFP Socket Adapter Board
ATF15xx-SAJ44 44-lead PLCC Socket Adapter Board
ATF15xx-SAC49 49-lead BGA Socket Adapter Board
ATF15xx-SAJ68 68-lead PLCC Socket Adapter Board
ATF15xx-SAJ84 84-lead PLCC Socket Adapter Board
ATF15xx-SAA100 100-lead TQFP Socket Adapter Board
ATF15xx-SAQ100 100-lead PQFP Socket Adapter Board
ATF15xx-SACT100 100-lead BGA Socket Adapter Board
ATF15xx-SAA144 144-lead TQFP Socket Adapter Board
ATF15xx-SAQ160 160-lead PQFP Socket Adapter Board
ATF15xx-SAC169 169-lead BGA Socket Adapter Board
ATF15xx-SAQ208 208-lead PQFP Socket Adapter Board
ATF15xx-SACT256 256-lead BGA Socket Adapter Board
Introduction
CPLD Development/Programmer Kit User Guide 1-5
3300A–PLD–08/02
1.8 References To help PLD designers use the different Atmel PLD software, documentation such as
Help Files, Tutorials, Application Notes/Briefs, and User Guides are available.
1.8.1 ProChip Designer
1.8.2 Atmel-WinCUPL
1.8.3 ATMISP
1.8.4 POF2JED
ProChip Designer
Help Files
From the ProChip Designer main window, click on HELP and then
select PROCHIP DESIGNER HELP.
Tutorials From the ProChip Designer main window, click on HELP and then
select TUTORIALS.
Known Problems &
Solutions
From the ProChip Designer main window, click on HELP and then
select REVIEW KPS.
Help Files From the Atmel-WinCUPL main window, click on HELP and then
select CONTENTS.
CUPL Programmers
Reference Guide
From the Atmel-WinCUPL main window, click on HELP and then
select CUPL PROGRAMMERS REFERENCE.
Tutorial From the Atmel-WinCUPL main window, click on HELP, select ATMEL
INFO and then select TUTORIAL1.PDF.
Known Problems &
Solutions
From the Atmel-WinCUPL main window, click on HELP, select ATMEL
INFO and then select CUPL_BUG.PDF.
Help Files From the ATMISP main window, click on HELP and then select ISP
HELP.
Tutorial From the ATMISP main window, click on HELP, and then select
ATMISP TUTORIAL.
Known Problems &
Solutions
Using Windows Explorer, go to the directory where ATMISP is
installed and open the README.TXT file through any ASCII text
editor.
ATF15xx Conversion
Application Brief
From the POF2JED main window, click on HELP and then select
CONVERSION OPTIONS.
Introduction
1-6 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
CPLD Development/Programmer Kit User Guide 2-1
Rev. 3300A–PLD–08/02
Section 2
Hardware Description
2.1 Atmel CPLD
Development/
Programmer
Board
The Atmel CPLD Development/Programmer Board, along with the Socket Adapter
Board as shown in Figure 2-1, contains many features that designers will find very use-
ful when developing, prototyping, or evaluating their ATF15xx CPLD design. Features
such as push-button switches, 8-segment display LEDs, 2 MHz crystal oscillator,
5V/3.3V VCC selector, JTAG-ISP port, and expansion terminal holes make this a very
versatile starter/development kit and an ISP programmer for the ATF15xx family of
JTAG-ISP CPLDs.
Figure 2-1.
CPLD Development/Programmer Board with 84-lead PLCC Socket Adapter Board
8-segment
Display LEDs
Clock Select
Jumper
84-pin PLCC
Socket
JTAG Port
Header
Expansion
Terminal Holes
GOE
Push-button
Switch
GCLR
Push-button
Switch
V
CC
Select
Jumper
2 MHz Crystal
Oscillator
Power Switch
Power LED
Power Supply
Jack
Power Supply
Header
Hardware Description
2-2 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
2.1.1 8-segment Display
LEDs
The Atmel CPLD Development/Programmer Board contains eight 8-segment LEDs to
allow the designer to observe the outputs of the ATF15xx. These eight LEDs are labeled
DSP1 to DSP8 on the board. These eight display LEDs are common anode LEDs with
the common anode lines connected to VCC and the individual cathode lines connected
to the I/O pins of the ATF15xx CPLD on the CPLD Development/Programmer Board. To
turn on a particular segment of an LED, the corresponding ATF15xx I/O pin connected
to this LED segment must be in a logical-0 state. Hence, the outputs of the ATF15xx
need to be configured as active-low outputs in the design file.
Figure 2-2.
8-segment Display LED
Each segment of the display LED is hard-wired to one specific I/O pin of the ATF15xx.
For the higher pin count devices (100-lead and larger), all eight segments of the eight
LEDs are connected to the I/O pins of the ATF15xx. However, for the lower pin count
devices (84-lead and smaller), only a subset of the LED segments are connected to the
ATF15xx's I/O pins. Table 2-1 to Table 2-8 below show the connections of the LEDs to
the ATF15xx in all the different package types.
Dot
A
B
C
E
F
G
D
Table 2-1.
Connections of LEDs to ATF15xx 44-lead PLCC
DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #
1/A NC 3/A 28 5/A 6 7/A NC
1/B NC 3/B 26 5/B 4 7/B NC
1/C NC 3/C 24 5/C 5 7/C NC
1/D NC 3/D 25 5/D 8 7/D NC
1/E NC 3/E 27 5/E 11 7/E NC
1/F NC 3/F 29 5/F 9 7/F NC
1/G NC 3/G 31 5/G 12 7/G NC
1/DOT NC 3/DOT NC 5/DOT NC 7/DOT NC
2/A NC 4/A 36 6/A 18 8/A NC
2/B NC 4/B 33 6/B 16 8/B NC
2/C NC 4/C 34 6/C 14 8/C NC
2/D NC 4/D 40 6/D 17 8/D NC
2/E NC 4/E 37 6/E 19 8/E NC
2/F NC 4/F 39 6/F 20 8/F NC
2/G NC 4/G 41 6/G 21 8/G NC
2/DOT NC 4/DOT NC 6/DOT NC 8/DOT NC
Hardware Description
CPLD Development/Programmer Kit User Guide 2-3
3300A–PLD–08/02
Table 2-2.
Connections of LEDs to ATF15xx 44-lead TQFP
DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #
1/A NC 3/A 21 5/A 44 7/A NC
1/B NC 3/B 19 5/B 42 7/B NC
1/C NC 3/C 18 5/C 43 7/C NC
1/D NC 3/D 20 5/D 2 7/D NC
1/E NC 3/E 22 5/E 5 7/E NC
1/F NC 3/F 23 5/F 3 7/F NC
1/G NC 3/G 25 5/G 6 7/G NC
1/DOT NC 3/DOT NC 5/DOT NC 7/DOT NC
2/A NC 4/A 30 6/A 12 8/A NC
2/B NC 4/B 27 6/B 10 8/B NC
2/C NC 4/C 28 6/C 8 8/C NC
2/D NC 4/D 34 6/D 11 8/D NC
2/E NC 4/E 31 6/E 13 8/E NC
2/F NC 4/F 33 6/F 14 8/F NC
2/G NC 4/G 35 6/G 15 8/G NC
2/DOT NC 4/DOT NC 6/DOT NC 8/DOT NC
Table 2-3.
Connections of LEDs to ATF15xx 68-lead PLCC
DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #
1/A NC 3/A 47 5/A 5 7/A 25
1/B NC 3/B 45 5/B 4 7/B 24
1/C NC 3/C 44 5/C 7 7/C 27
1/D NC 3/D 46 5/D 9 7/D 29
1/E NC 3/E 49 5/E 13 7/E 32
1/F NC 3/F 51 5/F 8 7/F 28
1/G NC 3/G 52 5/G 10 7/G 30
1/DOT NC 3/DOT NC 5/DOT NC 7/DOT NC
2/A 37 4/A 56 6/A 17 8/A NC
2/B 33 4/B 54 6/B 14 8/B NC
2/C 36 4/C 55 6/C 15 8/C NC
2/D 39 4/D 61 6/D 18 8/D NC
2/E 41 4/E 59 6/E 22 8/E NC
2/F 40 4/F 60 6/F 20 8/F NC
2/G 42 4/G 64 6/G 23 8/G NC
2/DOT NC 4/DOT NC 6/DOT NC 8/DOT NC
Hardware Description
2-4 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Table 2-4.
Connections of LEDs to ATF15xx 84-lead PLCC
DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #
1/A 49 3/A 67 5/A 6 7/A 25
1/B 46 3/B 64 5/B 4 7/B 22
1/C 48 3/C 65 5/C 5 7/C 24
1/D 50 3/D 68 5/D 8 7/D 27
1/E 52 3/E 70 5/E 10 7/E 29
1/F 51 3/F 69 5/F 9 7/F 28
1/G 54 3/G 73 5/G 11 7/G 30
1/DOT NC 3/DOT NC 5/DOT 45 7/DOT 41
2/A 57 4/A 76 6/A 16 8/A 34
2/B 55 4/B 74 6/B 12 8/B 31
2/C 56 4/C 75 6/C 15 8/C 33
2/D 58 4/D 77 6/D 17 8/D 35
2/E 61 4/E 80 6/E 20 8/E 37
2/F 60 4/F 79 6/F 18 8/F 36
2/G 63 4/G 81 6/G 21 8/G 39
2/DOT NC 4/DOT NC 6/DOT 44 8/DOT 40
Table 2-5.
Connections of LEDs to ATF15xx 100-lead TQFP
DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #
1/A 47 3/A 67 5/A 96 7/A 20
1/B 52 3/B 64 5/B 93 7/B 17
1/C 48 3/C 63 5/C 94 7/C 19
1/D 46 3/D 65 5/D 97 7/D 21
1/E 44 3/E 68 5/E 99 7/E 25
1/F 45 3/F 69 5/F 98 7/F 23
1/G 42 3/G 71 5/G 100 7/G 29
1/DOT 49 3/DOT 61 5/DOT 92 7/DOT 22
2/A 54 4/A 80 6/A 12 8/A 32
2/B 41 4/B 76 6/B 9 8/B 30
2/C 40 4/C 78 6/C 8 8/C 31
2/D 56 4/D 84 6/D 10 8/D 33
2/E 58 4/E 81 6/E 13 8/E 36
2/F 57 4/F 83 6/F 14 8/F 35
2/G 60 4/G 85 6/G 16 8/G 37
2/DOT 55 4/DOT 75 6/DOT 6 8/DOT 28
Hardware Description
CPLD Development/Programmer Kit User Guide 2-5
3300A–PLD–08/02
Table 2-6.
Connections of LEDs to ATF15xx 100-lead PQFP
DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #
1/A 48 3/A 69 5/A 98 7/A 22
1/B 50 3/B 66 5/B 95 7/B 19
1/C 49 3/C 65 5/C 96 7/C 21
1/D 47 3/D 67 5/D 99 7/D 23
1/E 44 3/E 70 5/E 3 7/E 27
1/F 46 3/F 71 5/F 100 7/F 25
1/G 43 3/G 73 5/G 4 7/G 39
1/DOT 51 3/DOT 63 5/DOT 94 7/DOT 24
2/A 56 4/A 82 6/A 14 8/A 37
2/B 54 4/B 78 6/B 11 8/B 38
2/C 42 4/C 81 6/C 10 8/C 35
2/D 58 4/D 86 6/D 12 8/D 33
2/E 60 4/E 83 6/E 15 8/E 31
2/F 59 4/F 85 6/F 16 8/F 34
2/G 62 4/G 87 6/G 18 8/G 32
2/DOT 52 4/DOT 77 6/DOT 8 8/DOT 30
Table 2-7.
Connections of LEDs to ATF15xx 144-lead TQFP
DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #
1/A 79 3/A 100 5/A 134 7/A 25
1/B 78 3/B 98 5/B 137 7/B 22
1/C 74 3/C 99 5/C 136 7/C 23
1/D 80 3/D 101 5/D 133 7/D 26
1/E 82 3/E 106 5/E 138 7/E 28
1/F 81 3/F 102 5/F 132 7/F 27
1/G 83 3/G 107 5/G 131 7/G 29
1/DOT 77 3/DOT 97 5/DOT 139 7/DOT 21
2/A 88 4/A 118 6/A 9 8/A 41
2/B 86 4/B 119 6/B 7 8/B 31
2/C 87 4/C 117 6/C 6 8/C 32
2/D 91 4/D 114 6/D 8 8/D 38
2/E 93 4/E 112 6/E 10 8/E 37
2/F 92 4/F 116 6/F 11 8/F 40
2/G 94 4/G 113 6/G 15 8/G 39
2/DOT 84 4/DOT 111 6/DOT 5 8/DOT 30
Hardware Description
2-6 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
2.1.2 Push-button
Switches
Two push-button switches are provided to allow the user to control the logic states of the
OE1 and GCLR inputs of the ATF15xx. These two switches are labeled GOE and GCLR
on the board. The GCLR push-button switch is a momentary Single-Pole Single-Throw
(SPST)normallyopenswitchwhiletheGOEpush-buttonswitchisasnap-acting
momentary SPST normally open switch. As shown in the CPLD Development/Program-
mer Board schematic in Figure 4-1, these two switches are normally open and the
GCLR and GOE signals are pulled-up to VCC when they are not depressed. When the
switches are depressed, the GCLR and GOE signals are connected to GND.
The output of the GCLR switch is connected to the GCLR dedicated input pin of the
ATF15xx, and it is intended to be used as an active-low reset signal to reset the regis-
ters in the ATF15xx. The output of the GOE switch is connected to the OE1 dedicated
input pin of the ATF15xx. It is intended to be used as an active-high or active-low output
enable signal to control the enabling/disabling of the tri-state output buffers in the
ATF15xx. However, these two switches can also be used to generate general logic input
signals to the GCLR and OE1 input pins of the ATF15xx.
2.1.3 Clock Select Jumper The Clock Select Jumper, labeled JPCLK, on the CPLD Development/Programmer
Board is a two-position jumper that allows the user to select which GCLK dedicated
input pin (either GCLK1 or GCLK2) of the ATF15xx should be connected to the output of
the 2 MHz crystal oscillator. In addition, the jumper can be removed to allow an external
clock source to be connected to GCLK1 and/or GCLK2 of the ATF15xx.
Table 2-9 shows the pin numbers for the GCLR, OE1, GCLK1 and GCLK2 dedicated
input pins of the ATF15xx in all the available package types.
Table 2-8.
Connections of LEDs to ATF15xx 160-lead PQFP
DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin # DSP/Sgt PLD Pin #
1/A 91 3/A 102 5/A 11 7/A 29
1/B 89 3/B 100 5/B 159 7/B 27
1/C 90 3/C 98 5/C 160 7/C 28
1/D 80 3/D 101 5/D 10 7/D 52
1/E 73 3/E 103 5/E 12 7/E 50
1/F 78 3/F 105 5/F 13 7/F 53
1/G 72 3/G 106 5/G 14 7/G 51
1/DOT 88 3/DOT 97 5/DOT 158 7/DOT 25
2/A 69 4/A 110 6/A 20 8/A 43
2/B 71 4/B 108 6/B 18 8/B 49
2/C 68 4/C 109 6/C 16 8/C 30
2/D 92 4/D 123 6/D 19 8/D 31
2/E 94 4/E 111 6/E 21 8/E 32
2/F 93 4/F 121 6/F 23 8/F 41
2/G 96 4/G 122 6/G 24 8/G 33
2/DOT 70 4/DOT 107 6/DOT 15 8/DOT 48
Hardware Description
CPLD Development/Programmer Kit User Guide 2-7
3300A–PLD–08/02
2.1.4 VCC Select Jumper The VCC Select Jumper, labeled VCC Select, on the CPLD Development/Programmer
Board is a two-position jumper that allows the users to select the VCC voltage level
(either 3.3V or 5.0V) used by various components on the CPLD Development/Program-
mer Board. This voltage generated by the on-board voltage regulation circuitry is
appliedtotheV
CC input pins (both VccINT and VccIO) of the ATF15xx, the common
anode lines of the eight 8-segment LEDs, the VCC input of the 2 MHz crystal oscillator,
the two push-button switches, and the VCC pin (Pin 4) of the 10-pin JTAG port header
labeled JTAG.
Therefore, when a 3.3V device (ATF15xxASV/ASVL/AE/AEL) is used on this board, the
VCC Select Jumper must be in the 3.3V position. On the other hand, when a 5V device
(ATF15xxAS/ASL/SE/SEL) is used on this board, the VCC Select Jumper must be in the
5.0V position. This is also true when the ATF15xx is being programmed through ISP on
this board.
2.1.5 JTAG Port Header The JTAG Port Header, labeled JTAG, on the CPLD Development/Programmer Board
is used to connect the ATF15xx's JTAG port pins (TCK, TDI, TMS and TDO) through the
ISP download cable to the parallel printer (LPT) port of a PC for ISP programming of the
ATF15xx. Table 2-10 shows the pin numbers for the four JTAG port pins of the ATF15xx
in all the available package types.
The ISP algorithm is controlled by the ATMISP software, which runs on the PC. The
four JTAG signals are generated by the LPT port and they are buffered by the ISP
download cable before going into the ATF15xx on the CPLD Development/Programmer
Board. The pinout for the 10-pin JTAG Port Header on the CPLD Development/Pro-
grammer Board is shown in Figure 2-3 and the dimensions of this 10-pin male JTAG
header are shown in Figure 2-4.
Table 2-9.
Pin Numbers of GCLR, OE1, GCLK1 and GCLK2
Signal
44-lead
TQFP
44-lead
PLCC
68-lead
PLCC
84-lead
PLCC
100-lead
PQFP
100-lead
TQFP
144-lead
TQFP
160-lead
PQFP
GCLR 39 1 1 1 91 89 127 141
OE1384468849088126140
GCLK1374367838987125139
GCLK2 40 2 2 2 92 90 128 142
Table 2-10.
Pin Numbers of JTAG Port Signals
Signal
44-lead
TQFP
44-lead
PLCC
68-lead
PLCC
84-lead
PLCC
100-lead
PQFP
100-lead
TQFP
144-lead
TQFP
160-lead
PQFP
TDI1 712146 4 4 9
TDO323857717573104112
TMS 7 13 19 23 17 15 20 22
TCK2632506264628999
Hardware Description
2-8 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Figure 2-3.
Pinout Diagram of 10-pin JTAG Port Header (Top-view)
Figure 2-4.
10-pin Male Header Dimensions
The pinout of this 10-pin JTAG Port Header is compatible with the Altera®ByteBlaster™
and ByteBlasterMV™cables. In addition, the ATMISP software allows users to choose
either the Atmel CPLD ISP Cable or the ByteBlaster/ByteBlasterMV cable to implement
ISP.
2.1.6 Power Connectors The Atmel CPLD Development/Programmer Board contains two different types of power
connectors, and either one can be used to connect to a 9V DC power source to power
the board. The first power connector, labeled JPower, is a barrel power jack with a
2.1 mm diameter post and it mates to a 2.1 mm (inner diameter) x 5.5 mm (outer diame-
ter) female plug. The second power connector, labeled JP Power, is a 4-pin male 0.1"
header with 0.025" square posts. The availability of these two types of power connec-
tors allows the users to choose the type of power supply equipment to use for the CPLD
Development/Programmer Board.
1
34
5
8
910
6
TCK GND
TDO VCC
TMS
NCNC
NC
TDI GND
2
7
0.100 0.025 S
q
.
0.235
Top View Side View
0.100
All dimensions are in inches
Hardware Description
CPLD Development/Programmer Kit User Guide 2-9
3300A–PLD–08/02
2.2 Socket Adapter
Board
Atmel CPLD Development/Programmer Socket Adapter Boards are circuit boards that
interface with the Atmel CPLD Development/Programmer Board. They are used in con-
junction with the CPLD Development/Programmer Board to evaluate/program Atmel ISP
CPLDs in different package types. Currently, there are nine Socket Adapter Boards
available covering all the package types offered in the ATF15xx family of CPLDs. They
include 44-lead PLCC, 44-lead TQFP, 68-lead PLCC, 84-lead PLCC, 100-lead TQFP,
100-lead PQFP, 144-lead TQFP and 160-lead PQFP. New Socket Adapter Boards will
become available when new packages are offered.
Each socket adapter board contains a socket for the Atmel ATF15xx device on the top
side and male headers on the bottom side. The headers on the bottom side mate with
the female headers, labeled JPLEFT and JPRIGHT, on the CPLD Development/Pro-
grammer Board. The eight 8-segment LEDs, push-button switches, JTAG port signals,
crystal oscillator, VCC, and GND on the CPLD Development/Programmer Board are con-
nected to the ATF15xx device on the Socket Adapter Board through these two rows of
connectors.
2.2.1 Expansion Terminal
Holes
Rows of expansion terminal holes suitable for 0.1" headers with 0.025" square posts are
available on each of the Socket Adapter Boards to allow users to interface the ATF15xx
to an external circuit board. All input and I/O pins except the four JTAG port pins of the
ATF15xx are routed to these expansion terminal holes, and the corresponding pin num-
bers are marked next to the terminal holes. Please refer to the Socket Adapter Board
schematics in Section 4 for the pinouts of the expansion terminal holes.
On the bottom side of the Socket Adapter Boards, traces connecting the pairs of expan-
sion terminal holes can be cut to isolate the LEDs, push-button switches and crystal
oscillator from the ATF15xx on the Socket Adapter Board. This allows the users to gain
complete control and access to all input and I/O pins of the ATF15xx.
2.3 Atmel CPLD ISP
Cable
The Atmel CPLD ISP Cable connects the parallel printer (LPT) port of the user’sPCto
the 10-pin JTAG header on the Atmel CPLD Development/Programmer Board or a cus-
tom circuit board. This is shown in Figure 2-5. This ISP cable acts as a buffer to buffer
the JTAG signals between the PC's LPT port and the ATF15xx on the circuit board. The
circuit schematic of the Atmel CPLD ISP Cable is shown in Figure 4-10 and Figure 4-11.
The Power-On LED on the back of the 25-pin male connector housing indicates that the
cable is connected properly. Make sure this LED is turned on before using the Atmel
CPLD ISP Software (ATMISP).
This ISP cable consists of a 25-pin (DB25) male connector, which is connected to the
LPT port of a PC. The 10-pin female plug connects to the 10-pin male JTAG header on
the ISP circuit board. The red color stripe on the ribbon cable indicates the orientation of
Pin 1 of the female plug. The 10-pin male JTAG header on the CPLD Development/Pro-
grammer Board is polarized to prevent users from inserting the female plug in the wrong
orientation.
If the user is attempting to program low voltage (3.3V) devices, the user needs to use
Rev. 4 or later of the Atmel CPLD ISP Cable. This and later revisions will support both
the 3.3V and 5V ATF15xx ISP CPLDs. Earlier revisions of the cable only supported 5V
devices.
When programming 3.3V devices, the VCC supplied to the ISP cable should also be
3.3V. Similarly, the VCC supplied to the ISP cable should be 5.0V when programming
5V devices.
Hardware Description
2-10 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Figure 2-5.
Atmel ISP Cable Connection to ISP Hardware Board/Circuit Board
Figure 2-6 shows the pinout for the 10-pin Female header on the Atmel-ISP Cable. The
pinout on the 10-pin male header on the PC board (if used for ISP) must match this
pinout.
Figure 2-6.
Atmel ISP Download Cable 10-pin Female Header Pinout
Note:
The user’s circuit board must supply VCC and GND to the Atmel CPLD ISP
Cable through the 10-pin male header (See Figure 2-3).
CPLD Development/Programmer Kit User Guide 3-1
Rev. 3300A–PLD–08/02
Section 3
CPLD Design Flow Tutorial
3.1 Overview This tutorial will guide the user through a complete design cycle for the Atmel ATF15xx
CPLD with Logic Doubling architecture. It will go through each phase of the design cycle
step-by-step from design entry, logic synthesis, device fitting, in-system programming,
and finally verifying the design on the Atmel CPLD Development/Programming Board.
Note:
To complete this tutorial, ProChip Designer V4.0 or later and Atmel-ISP Soft-
ware (ATMISP) V4.0 or later are required.
3.2 Create a Project
Using the “New
Project Wizard”
Before starting the design process, a Project File must be created within ProChip
Designer. ProChip Designer's New Project Wizard provides a very easy way to create
a new Project File.
1. Click on the START .... PROGRAMS .... PROCHIP Icon to launch ProChip
Designer. Or double-click on the PROCHIP icon on the desktop.
(1) Click to launch
ProChip Designer
CPLD Design Flow Tutorial
3-2 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
2. Click on PROJECT .... NEW or double-click on the NEW PROJECT shortcut but-
ton to launch the New Project Wizard.
3. Click on the NEXT button to start the project file creation process.
4. Click on the BROWSE button to open the browser window.
5. Use C:\PROCHIP\DESIGNS\CUPL as the directory of the project.
6. Enter DEV_KIT.APJ as the project filename. The extension of a project file must
be .APJ.
Note:
The name and directory of the design project is specified in this window. All
design, simulation and other project files must be placed in this project direc-
tory.
Click to create
New Project
(2)
(3) Click Next to Start
(4) Click on
Browse
(5) Select the
Project Directory
(6) Enter the
Project Filename
CPLD Design Flow Tutorial
CPLD Development/Programmer Kit User Guide 3-3
3300A–PLD–08/02
7. Choose [ATF1508AS-10JC84] as the target device type for the project. Also
review the
Filters
that allow for selection of a specific
Speed Grade
or
Package
Ty p e
.
8. Select CUPL – ALTIUM as the software tool for this design flow.
With ProChip Designer V4.0 and later, the five possible design flows and their corre-
sponding design entry types supported are listed in the table below:
Note: 1. Design flow require Mentor Graphics®Leonardo Spectrum software with Atmel CPLD
support.
Design Flow Design Entry Type
CUPL –Altium™CUPL design entry through Altium Protel™99SE
Verilog –Exemplar™(1) Verilog®design entry through Exemplar Leonardo Spectrum™
VHDL –Altium VHDL design entry through the Altium PeakFPGA
VHDL –Exemplar(1) VHDL design entry through Exemplar Leonardo Spectrum
Schematic –Altium Schematic design entry through Altium Protel 99SE
(7) Select the
Device Type
(8)Select the
Design Flow
CPLD Design Flow Tutorial
3-4 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
9. Select DONE WITH PARTS so that there will be only one device in this project.
On the other hand, users can select ADD MORE PARTS to include more parts to the
current Project Directory.
10. Click the FINISH button to finish the New Project Wizard and the project creation
process.
This closes the
New Project Wizard
and opens the
ProChip Designer
window. The
Sources
in the project are shown in the Left window.
(9)
Select Done
with Parts
(10)Click Finish to End
New Project Wizard
CPLD Design Flow Tutorial
CPLD Development/Programmer Kit User Guide 3-5
3300A–PLD–08/02
11. Click on the Device Icon [ATF1508AS-10JC84] to view the
Design Flow
window.
Project Sources Window Information Dialog Box
Messa
g
e Window (11) Click on the Device Icon
Project File Window Design Flow Window
CPLD Design Flow Tutorial
3-6 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
3.3 Add a Design
File
Once the Project File is created, the next step is to add the design source file(s) into the
user’s project. For this tutorial, a single CUPL design file will be added into the project.
1. Click on the ADD/EDIT button from
Source Manager
to open the
Source Man-
ager Window
. The user can view the
Source Manager
Help File by clicking on
the Help buttonwithinthe
Source Manager Window
to view the description for
the different processes.
2. In the
Source Manager Window
, click on the ADD button to add a CUPL design
file to the project.
3. In the
File Manager Window
,selectLOGIC_D8.PLD from the
C:\PROCHIP\DESIGNS\CUPL
directory as the source design file for this project.
This "LOGIC_D8.PLD" is a CUPL design that uses the eight 8-segment LED displays
and the 2 MHz oscillator on the Atmel CPLD Development/Programmer Board to gener-
ate a scrolling message that displays the words "logic doubling" on the LEDs. The GOE
push-button switch is used to control the direction that the message scrolls in (left or
right). The GCLR push-button switch is used to reset the counter registers. When the
GCLR push-button switch is depressed, the message will stop scrolling. This CUPL
design can be compiled using either the ProChip Designer or the Atmel-WinCUPL
software.
The first section of the LOGIC_D8.PLD as shown below pre-defines which segments of
the LED should be asserted in order to display the desired letter or number. For exam-
ple, to display the upper case letter "C", segments A, D, E, and F need to be set to low
(active low) and the remaining segments need to be set to high.
Click Add/Edit
to Open Source
Manager Window
(1)
Select CUPL
Source File
(3)
Click ADD to
add Design File
(2)
$define Font0 'b'1000000 /* = ( _f_e_d_c_b_a ); 0 */
$define Font1 'b'1111001 /* = ( _c_b ); 1 */
:
$define FontA 'b'0001000 /* = (_g_f_e _c_b_a ); A */
CPLD Design Flow Tutorial
CPLD Development/Programmer Kit User Guide 3-7
3300A–PLD–08/02
The next section of this CPLD design as shown below illustrates how to declare and
assign pin numbers in the CUPL language to the input and output signals. The input and
output pin assignments are assigned according to the connections between the CPLD
and the eight 8-segment LED's as shown in the connection tables (Table 2-1 to Table 2-
8) in Section 2.
Next, the buried signals for the counter and state machine are declared as PINNODE's
as shown below. The feedback and/or the foldback paths available in each macrocell
implement these buried signals. For the listing of the pinnode numbers, please refer to
the "ATF15xx Device Help" section of the ProChip Designer Help File.
After assigning the input, output and buried signals, the related signals (i.e. the LED
segments and buried counter) are grouped together as shown below to make the design
source code more readable and manageable. In CUPL, the "Field" declaration can be
used to group a specific set of signals.
Next, a 21-bit buried up-counter implemented using D-type Flip-flops is shown below
and it is used to divide the 2.0 MHz clock into a 0.954 Hz (2 MHz ÷ 221 = 0.954 Hz) sig-
nal that can be used to display the text messages. The last bit of this counter is used as
the clock for the state machine that controls the display sequence of the messages on
the LEDs.
/* Inputs */
pin 1 = GCLR; /* Global Clear input */
pin 83 = MCLK; /* Global Clock input */
pin 84 = GOE; /* GOE1 button used as direction control */
/* Outputs */
/* DSP1 */
pin 49 = LED1A; /* LED1 segment A */
pin 46 = LED1B; /* LED1 segment B */
pin 48 = LED1C; /* LED1 segment C */
pin 50 = LED1D; /* LED1 segment D */
pin 52 = LED1E; /* LED1 segment E */
pin 51 = LED1F; /* LED1 segment F */
pin 54 = LED1G; /* LED1 segment G */
pinnode [618,634,650,687]= [CA20..CA17];
pinnode = [CA16..CA0];
pinnode = [SM7..SM0];
Field DSP1 = [LED1G,LED1F,LED1E,LED1D,LED1C,LED1B,LED1A];
Field DSP2 = [LED2G,LED2F,LED2E,LED2D,LED2C,LED2B,LED2A];
:
Field CNT_A = [CA20..CA0];
Field SM = [SM7..SM0];
CA0.d = !CA0;
CA1.d = CA0 $ CA1;
:
CA7.d = (CA6 & CA5 & CA4 & CA3 & CA2 & CA1 & CA0) $ CA7;
:
CNT_A.ck = MCLK;
CNT_A.ar = !GCLR;
CPLD Design Flow Tutorial
3-8 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
The next section of this PLD design is a state machine with 15 states to control the dis-
play sequence of the text messages on the LEDs. The GOE push-button switch on the
CPLD Development/Programmer Board controls the flow of this state machine. When
this switch is in the "up" position, the state machine will go from RESET to State-0 to
State-1 to State-2 and so on until it reaches State-14 and then it will go back to State-0.
On the other hand, if the GOE switch is in the "down" position, the state machine will go
in the opposite direction (i.e. State-14 to State13 .. etc).
Finally, the last section of the PLD design will assign the appropriate letters or numbers
to the eight 8-segment LEDs to be displayed during the different states of the state
machine. The user can easily change the letters/numbers to be displayed by changing
this section of the code to the appropriate pre-defined letters/numbers.
SM.ck = COUNTER_1;
sequence SM
{
present RESET
next S0;
present S0
if SM_DIR next S1;
if !SM_DIR next S14;
:
present S14
if SM_DIR next S0;
if !SM_DIR next S13;
}
LED1 = FontBK & SM:[RESET]
# FontBK & SM:[S0]
# FontLl & SM:[S1]
# FontLo & SM:[S2]
# FontLg & SM:[S3]
# FontLi & SM:[S4]
# FontLc & SM:[S5]
# FontBK & SM:[S6]
# FontLd & SM:[S7]
# FontLo & SM:[S8]
# FontLu & SM:[S9]
# FontLb & SM:[S10]
# FontLl & SM:[S11]
# FontLi & SM:[S12]
# FontLn & SM:[S13]
# FontLg & SM:[S14];
CPLD Design Flow Tutorial
CPLD Development/Programmer Kit User Guide 3-9
3300A–PLD–08/02
3.4 Compile the
CUPL Design
In this part of the tutorial, the CUPL design will be compiled through the Logic Synthesis
process into a set of optimized/minimized logic equations.
1. Click on the CUPL – Design Ex. button in the Design Flow Window to open the
Logic Synthesis Window.
2. Make sure all of the options in the
Optimization
section are unchecked.
3. Make sure the
Minimization
setting is set to Quick.
4. Click on the Compile button to start the CUPL compile process.
The user can click on the Set Defaults button and it will automatically specify the Syn-
thesis tool in the Tool Text box.
If the user clicks on the CUPL Tab, it shows the various Synthesis options. Please refer
to the HELP file for further description.
(1) Open Logic
Synthesis
(2) Make sure these
Options are
Not Checked
(3) Set to
Quick
(4) Start the
Compile
Process
CPLD Design Flow Tutorial
3-10 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
3.5 Fit the
Synthesized
Design File
In Section 3.4, the Logic Synthesis portion of the CPLD Design Flow was completed. On
successful compilation, the CUPL compiler tool produces a PLA output file (with exten-
sion .pla). A PLA file contains the netlist of the optimized and minimized logic equations.
It is now necessary to map this netlist into a specific Atmel PLD architecture using the
Atmel Fitter.
1. The user can now proceed to the Device Fitter portion of the Design Flow by
clicking on the Atmel Fitter button.
The user can either use the Default options or specify Fitter properties. ProChip
Designer will automatically select the PLA file associated to the current design project
and the tool type. In this example, since the target device is an ATF1508AS, the
fit1508.exe device fitter will be selected.
The fitter creates the important JEDEC and FIT REPORT output files. They contain the
data for programming the Device (using In-System Programming or on a third party
device programmer) and the pin assignments required for board layout respectively.
Please review the Global Device Parameters and Pin/Node Options as well. The Help
Files also show the Device Pin_Node lists for each of the ATMEL CPLDs.
2. Make sure the JTAG box is checked. This enables the JTAG port for ISP
programming.
3. Make sure the
PIN FIT CONTROL
setting is set to Keep. This will ensure that the
pin assignments in the PLD file will be kept during the Place-and-Route process.
4. When all the fitter options are set, click on the Run Fitter button to fit the design.
(1) Open the Atmel
Fitter Window
(2)Check the
JTAG box
(3) Set the Pin Fit
Control setting
to KEEP
(4) Start the
Fitting Process
CPLD Design Flow Tutorial
CPLD Development/Programmer Kit User Guide 3-11
3300A–PLD–08/02
The Fitter Report (.FIT) File generated for this design is shown below.
The ATF15xx Family devices Logic Doubling features provide extra I/O connectivity and
logic reusability. Some of the Logic Doubling features available in the ATF15xx family of
CPLDs are:
n
Bury either Register or Combinatorial signal while using the other for output
n
Dual independent feedback allows multiple latch functions per macrocell
n
5 product terms per macrocell, expandable to 40 per macrocell with cascade logic,
plus 15 more with foldback logic
n
D/T/Latch configurable flip-flops plus transparent latches
n
Global and/or per macrocell Output Enable
n
Single level Switch Matrix
n
Up to 40 inputs per Logic Block
In the LOGIC_D8.PLD example given in this tutorial, Logic Blocks B, C D, and F have
37 or more signal inputs (Fan-In's) as shown in the Universal-Interconnect-Multiplexer
assignments section of the .FIT file. The availability of wide Fan-In's to the Logic Blocks
is one of the many Logic Doubling features. This feature improves the possibility of rout-
ing all the necessary signals from the Global Bus to the Logic Blocks.
In addition, macrocells 37 and 59 of the ATF1508 are able to implement both combina-
torial outputs (LED1G and LED8D) and buried registered signals (CA0 and RST) within
the same macrocells. This is shown in the Resource Usage section of the .FIT file.
For more examples of design techniques that utilize the Logic Doubling features of the
ATF15xx Family, refer to Atmel's Logic Doubling White Paper and Reference Designs
available on the Atmel website. These examples show how to apply Logic Doubling
techniques to new product designs, to obtain the benefits of more features in a smaller
and possibly less expensive chip, or spare logic resources for future revisions and
reduce the risk of PCB re-spin.
Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN
Cascades
A: LC1 - LC16 16/16(100%) 8/16(50%) 5/16(31%) 46/80(57%) (19) 0
B: LC17 - LC32 16/16(100%) 8/16(50%) 3/16(18%) 51/80(63%) (38) 0
C: LC33 - LC48 16/16(100%) 8/16(50%) 2/16(12%) 48/80(60%) (38) 0
D: LC49 - LC64 16/16(100%) 6/16(37%) 2/16(12%) 40/80(50%) (38) 0
E: LC65 - LC80 16/16(100%) 6/16(37%) 6/16(37%) 55/80(68%) (32) 0
F: LC81 - LC96 16/16(100%) 8/16(50%) 2/16(12%) 47/80(58%) (38) 0
G: LC97 - LC112 16/16(100%) 8/16(50%) 3/16(18%) 43/80(53%) (25) 0
H: LC113- LC128 16/16(100%) 8/16(50%) 2/16(12%) 42/80(52%) (34) 0
Total dedicated input used: 3/4 (75%)
Total I/O pins used 60/64 (93%)
Total Logic cells used 128/128 (100%)
Total Flip-Flop used 31/128 (24%)
Total Foldback logic used 25/128 (19%)
Total Nodes+FB/MCells 153/128 (119%)
Total cascade used 0
Total input pins 7
Total output pins 56
Total Pts 372
:
CPLD Design Flow Tutorial
3-12 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
3.6 Program and
Verify Design
In this step of the tutorial, the user will program an ATF1508AS 84-pin PLCC device on
the Atmel CPLD Development/Programmer Board through ISP and then verify the
design by observing the text messages displayed on the eight 8-segment LED displays
of the CPLD Development/Programmer Board.
The user will need to follow the steps below to setup the ATMISP software in order to
program the ATF1508AS 84-pin PLCC on the CPLD Development/Programmer Board.
1. To create a new chain file, the ATMISP Software first needs to be launched
either through the PROGRAM CHIP button in the ProChip Designer window, the
ATMISPdesktopiconorthe
Start ... Programs .. Atmel ISP
menu.
If ATMISP is launched through ProChip Designer, steps 2 to 6 below can be skipped
since ProChip Designer will automatically setup the appropriate chain file for the ISP
operation.
2. To create a new chain file, select the New command under the File menu or click
on the New Shortcut Button.
3. The first piece of information that the software asks for when creating a new
chain is the number of devices in the JTAG chain. Therefore, enter 1and then
click OK since a 1-device JTAG chain will be programmed.
4. Next the user will need to specify the properties of each JTAG device in the
Device Properties window. First, select the target device type of the first device in
the JTAG chain. For this tutorial, please select ATF1508AS as the target device
type.
5. In the JTAG Instruction field, the user can specify the appropriate JTAG instruc-
tion to be executed on this device in the chain. Please select Program/Verify to
program and verify the ATF1508AS.
Launch
ATMISP
(1)
(2)Create New
Chain File
(3) Enter the
number of
devices
CPLD Design Flow Tutorial
CPLD Development/Programmer Kit User Guide 3-13
3300A–PLD–08/02
6. The next step is to specify the JEDEC file to be programmed into the target
device in the JEDEC File field. Click on the Browse button, change the directory
to [..\PROCHIP\DESIGNS\CUPL"] and then select LOGIC_D8.JED as the tar-
get JEDEC file. Click OK to close the JTAG Device Properties window when all
properties are specified.
The next few steps require the user to setup the Atmel CPLD Development/Programmer
Board to program the ATF1508AS through ISP.
7. Connect the 25-DB side of the Atmel-ISP Cable to the PC's parallel port and the
10-pin header side of the Atmel-ISP Cable to the Atmel CPLD Development
Board as shown Figure 2-5.
8. Connect a 9V AC/DC power adapter to the power connector (JPower) of the
Atmel CPLD Development/Programmer Board.
9. Set the 5V/3.3V jumper to 5V. This will set the system board VCC to 5V.
10. Set the JPCLK jumper to GCLK1 so that the output of the crystal oscillator will
be connected to Pin 83 of the ATF1508AS.
11. Connect the 84-pin PLCC Socket Adapter Board onto the main Develop-
ment/Programmer Board.
Note: If a device in a different package type is to be programmed, then the appropriate Socket
Adapter Board must be used.
12. Switch the Power Switch to the ON position.
13. Select the appropriate LPT port in the
Port Setting
field. LPT 1 is the default port.
14. Select the ISP download cable type in the
Cable Types
field. The default cable
type is the Atmel ISP Cable but it can be changed to the Altera ByteBlaster cable
if the ByteBlaster cable is being used.
Now both the user’s software and hardware are setup for ISP programming, and the
user can execute the PROGRAM/VERIFY instruction to program the ATF1508AS on
the Atmel CPLD Development/Programmer Board.
(5) Specify
JTAG
Instruction
(4) Specify
Target
Device Type
(6) Select
JEDEC
File
CPLD Design Flow Tutorial
3-14 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
15. Click on the Run button in the ATMISP main window to execute the JTAG
instruction to program the ATF1508AS on the CPLD Development/Programmer
Board.
After successfully programming the ATF1508AS with the LOGIC_D8.JED file, the eight
8-segment LED's will display the words "Logic Doubling".
If these two text messages are correctly displayed on the CPLD Development/Program-
mer Board, then the user has successfully completed this tutorial.
(13)Select
LPT Port
Number
(14)Select
Cable
Type
(15) Click on the
RUN Button
CPLD Development/Programmer Kit User Guide 4-1
Rev. 3300A–PLD–08/02
Section 4
Schematic Diagrams
Schematic Diagrams
4-2 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Figure 4-1.
Schematic Diagram of the Atmel CPLD Development/Programmer Board
1 2
3 4
5 6
7 8
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
JPRIGHT
HEADER 20X2
VCC
GND
GCLK1
TCK
DOT6
D1C
D1D
D1E
D2B
D2A
D2F
D3B
D3A
D3F
D3E
D4B
D4A
D4F
D4G
VCC
GND
GCLK2
TDO
DOT5
D1B
D1A
D1F
D1G
D2C
D2D
D2E
D2G
D3C
D3D
D3G
D4C
D4D
D4E
VCC
GND
GCLR
TDI
D5B
D5A
D5F
D5G
D6A
D6F
D6G
D7C
D7A
D7F
D7G
D8C
D8D
D8E
DOT8
VCC
GND
GOE
TMS
D5C
D5D
D5E
D6B
D6C
D6D
D6E
D7B
D7D
D7E
D8B
D8A
D8F
D8G
DOT7
DOT4
DOT3
DOT2
DOT1
LED1
Vin
3
ADJ
1
+Vout
2
VR1
D1
1N4001
POWER SWITCH
C1
100uF
C2
0.1uF
R2
330
R3
270
R1
200
R4
1K
1
2
3
Vcc Select
1
2
3
4
JP
JP Power
C5
0.1uF
C6
0.1uF
VCC
3.3V
5.0V
9
V
JPower
C3
0.1
LM317
VCC
C7
0.1uF
1 2
3 4
5 6
GCLR
GCLR
1 2
3 4
5 6
GOE1
GOE
1 4
2 3
OSC
2MHZ
GCLK2
GCLK1
1
2
3
JPCLK
R12
1K
R11
1K
R5
1K
R6
1K
VCC
1 2
3 4
5 6
7 8
910
JTAG
TCK
TDO
TDI
TMS
R8
4.7K
R10
4.7K
R7
4.7K
R9
10K
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP1
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP2
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP3
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP4
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP5
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP6
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP7
a
b
c
d
e
f
Vc1
Vc2
g
a
b
c
d
e
fg
DOT
DSP8
RDSP11
RDSP12
RDSP13
RDSP14
RDSP15
RDSP16
RDSP17
RDSP21
RDSP22
RDSP23
RDSP24
RDSP25
RDSP26
RDSP27
RDSP31
RDSP32
RDSP33
RDSP34
RDSP35
RDSP36
RDSP37
RDSP41
RDSP42
RDSP43
RDSP44
RDSP45
RDSP46
RDSP47
RDSP51
RDSP52
RDSP53
RDSP54
RDSP55
RDSP56
RDSP57
RDSP61
RDSP62
RDSP63
RDSP64
RDSP65
RDSP66
RDSP67
RDSP71
RDSP72
RDSP73
RDSP74
RDSP75
RDSP76
RDSP77
RDSP81
RDSP82
RDSP83
RDSP84
RDSP85
RDSP86
RDSP87
VCC
DOT1
DOT2
DOT3
DOT4
DOT5
DOT6
DOT7
DOT8
RDOT1
RDOT2
RDOT3
RDOT4
RDOT5
RDOT6
RDOT7
RDOT8
D1A
D1B
D1C
D1D
D1E
D1F
D1G
D2A
D2B
D2C
D2D
D2E
D2F
D2G
D3A
D3B
D3C
D3D
D3E
D3F
D3G
D4A
D4B
D4C
D4D
D4E
D4F
D4G
D5A
D5B
D5C
D5D
D5E
D5F
D5G
D6A
D6B
D6C
D6D
D6E
D6F
D6G
D7A
D7B
D7C
D7D
D7E
D7F
D7G
D8A
D8B
D8C
D8D
D8E
D8F
D8G
Schematic Diagrams
CPLD Development/Programmer Kit User Guide 4-3
3300A–PLD–08/02
Figure 4-2.
Schematic Diagram of 44-pin PLCC Socket Adapter Board
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCC
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPRIGHT
HEADER 20X2
VCC
GND
GCLK1
TCK
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D3G
D3E
VCC
GND
GCLK2
TDO
D3C
D3D
D4C
D4D
D4E
VCC
D5B
D5A
D5F
D5G
D6A
D6F
D6G
GOE
D6B
GCLR
TDI
GND
TMS
D5C
D5D
D5E
D6C
D6D
D6E
P8
P9
P11
P12
P14
P16
P17
P18
P19
P20
P21
P24
P25
P26
P27
P28
P29
P31
P33
P34
P36
P37
P39
P40
P41
P43
P44
P1
P2
P4
P5
P6
GOE
GCLK1
GND
GND
GND
GND
VCC
VCC
VCC
VCC
TDI
TMS
TDO
TCK
GND VCC
D5B
D5C
D5A
D5D
D5F
D5E
D5G
D6C
D6B
D6D
D6A
D6E
D6F
D6G
GCLK2
GCLR
D4G
D4D
D4F
D4E
D4A
D4C
D4B
D3G
D3F
D3E
D3A
D3D
D3B
D3C
ATMEL PLCC44
TDI
7
I/O
8
I/O
9
GND
10
I/O
11
TMS
13
I/O
14
VCC
15
I/O
16
I/O
17
I/O
12
I/O
18
I/O
19
I/O
20
I/O
21
GND
22
VCC
23
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O 29
GND 30
I/O 31
TCK 32
I/O 33
I/O 34
VCC 35
I/O 36
I/O 37
TDO 38
I/O 39
I/O 40
GCLK3 41
GND 42
GCLK1 43
OE1 44
GCLR 1
I/OE2/GCLK2 2
VCC 3
I/O 4
I/O 5
I/O 6
U1
PLCC44
Schematic Diagrams
4-4 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Figure 4-3.
Schematic Diagram of 44-pin TQFP Socket Adapter Board
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCC
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPRIGHT
HEADER 20X2
VCC
GND
GCLK1
TCK
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D3G
D3E
VCC
GND
GCLK2
TDO
D3C
D3D
D4C
D4D
D4E
VCC
D5B
D5A
D5F
D5G
D6A
D6F
D6G
GOE
D6B
GCLR
TDI
GND
TMS
D5C
D5D
D5E
D6C
D6D
D6E
P2
P3
P5
P6
P8
P10
P11
P12
P13
P14
P15
P18
P19
P20
P21
P22
P23
P25
P27
P28
P30
P31
P33
P34
P35
P37
P38
P39
P40
P42
P43
P44
ATMEL TQFP44
TDI
1
I/O
2
I/O
3
GND
4
I/O
5
TMS
7
I/O
8
VCC
9
I/O
10
I/O
11
I/O
6
I/O
12
I/O
13
I/O
14
I/O
15
GND
16
VCC
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O 23
GND 24
I/O 25
TCK 26
I/O 27
I/O 28
VCC 29
I/O 30
I/O 31
TDO 32
I/O 33
I/O 34
GCLK3 35
GND 36
GCLK1 37
OE1 38
GCLR 39
I/OE2/GCLK2 40
VCC 41
I/O 42
I/O 43
I/O 44
U1
TQFP44
GOE
GCLK1
GND
GND
GND
GND
VCC
VCC
VCC
VCC
TDI
TMS
TDO
TCK
GND VCC
D5B
D5C
D5A
D5D
D5F
D5E
D5G
D6C
D6B
D6D
D6A
D6E
D6F
D6G
GCLK2
GCLR
D4G
D4D
D4F
D4E
D4A
D4C
D4B
D3G
D3F
D3E
D3A
D3D
D3B
D3C
Schematic Diagrams
CPLD Development/Programmer Kit User Guide 4-5
3300A–PLD–08/02
Figure 4-4.
Schematic Diagram of 68-pin PLCC Socket Adapter Board
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCC
ATMEL PLCC68
I/O
10
VCC
11
TDI
12
I/O
13
I/O
14
I/O
15
GND
16
I/O
17
I/O
18
TMS
19
I/O
20
VCC
21
I/O
22
I/O
23
I/O
24
I/O
25
GND
26
I/O
27
I/O
28
I/O
29
I/O
30
VCC
31
I/O
32
I/O
33
GND
34
VCC
35
I/O
36
I/O
37
GND
38
I/O
39
I/O
40
I/O
41
I/O
42
VCC
43
I/O 44
I/O 45
I/O 46
I/O 47
GND 48
I/O 49
TCK 50
I/O 51
I/O 52
VCC 53
I/O 54
I/O 55
I/O 56
TDO 57
GND 58
I/O 59
I/O 60
I/O 61
TCK 62
VCC 63
I/O 64
GCLK3 65
GND 66
GCLK1 67
OE1 68
GCLR 1
GCLK2 2
VCC 3
I/O 4
I/O 5
GND 6
I/O 7
I/O 8
I/O 9
U1
P1
P2
P4
P5
P7
P8
P9
P10
P13
P14
P15
P17
P18
P20
P22
P23
P24
P25
P27
P28
P29
P30
P32
P33
P36
P37
P39
P40
P41
P42
P44
P45
P46
P47
P49
P51
P52
P54
P55
P56
P59
P60
P61
P64
P65
P67
P68
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TDI
TMS
TCK
TDO
GCLR
GOE
GCLK1
GCLK2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPRIGHT
HEADER 20X2
VCC
GND
GCLK1
TCK
D2B
D2A
D2F
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D2G
D3G
D3E
VCC
GND
GCLK2
TDO
D2C
D2D
D2E
D3C
D3D
D4C
D4D
D4E
VCC
GND
D5B
D5A
D5F
D5G
D6A
D6F
D6G
D7A
D7F
D7G
GOE
D6B
D7B
GCLR
TDI
D7C
VCC
GND
TMS
D5C
D5D
D5E
D6C
D6D
D6E
D7D
D7E
P62
D5B
D5A
D5C
D5F
D5D
D5G
D5E
D6B
D6C
D6A
D6D
D6F
D6E
D6G
D7B
D7A
D7C
D7F
D7D
D7G
D7E
D4G
D4D
D4F
D4E
D4A
D4C
D4B
D3G
D3F
D3E
D3A
D3D
D3B
D3C
D2G
D2E
D2F
D2D
D2A
D2C
D2B
Schematic Diagrams
4-6 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Figure 4-5.
Schematic Diagram of 84-pin PLCC Socket Adapter Board
INPUT/GCLRn 1
INPUT/OE2/GCLK2 2
VCC_INT 3
I/O 4
I/O 5
I/O 6
GND 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O
12
VCC_IO
13
I/O / TDI
14
I/O
15
I/O
16
I/O
17
I/O
18
GND
19
I/O
20
I/O
21
I/O
22
I/O / TMS
23
I/O
24
I/O
25
VCC_IO
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
GND
32
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
VCC_IO
38
I/O
39
I/O
40
I/O
41
GND
42
VCC_INT
43
I/O
44
I/O
45
I/O
46
GND
47
I/O
48
I/O
49
I/O
50
I/O
51
I/O
52
VCC_IO
53
I/O 54
I/O 55
I/O 56
I/O 57
I/O 58
GND 59
I/O 60
I/O 61
I/O / TCK 62
I/O 63
I/O 64
I/O 65
VCC_IO 66
I/O 67
I/O 68
I/O 69
I/O 70
I/O / TDO 71
GND 72
I/O 73
I/O 74
I/O 75
I/O 76
I/O 77
VCC_IO 78
I/O 79
I/O 80
I/O 81
GND 82
INPUT/GCLK1 83
INPUT/OE1 84
ATMEL
ATF1508AS-15JC84
U1
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPRIGHT
HEADER 20X2
PIN1
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
PIN84
PIN83
PIN2
TDI
TMS
TDO
TCK
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCC
SMALLATMEL
MARK
PIN4
PIN5
PIN6
PIN8
PIN9
PIN10
PIN11
PIN12
PIN15
PIN16
PIN17
PIN18
PIN20
PIN21
PIN22
PIN24
PIN25
PIN27
PIN28
PIN29
PIN30
PIN31
PIN33
PIN34
PIN35
PIN36
PIN37
PIN39
PIN40
PIN41
PIN44
PIN45
PIN46
PIN48
PIN49
PIN50
PIN51
PIN52
PIN54
PIN55
PIN56
PIN57
PIN58
PIN60
PIN61
PIN63
PIN64
PIN65
PIN67
PIN68
PIN69
PIN70
PIN73
PIN74
PIN75
PIN76
PIN77
PIN79
PIN80
PIN81
JR1 JR2
JR3 JR4
JR32
JR5 JR6
JR30
JR7 JR8
JR28
JR9 JR10
JR26
JR11
JR13JR12
JR24
JR16JR14
JR22
JR15 JR17
JR21
JR19
JR18
JR31
JR20
JR29
JR27
JR25
JR23
JL1 JL2
JL3 JL4
JL5 JL6
JL7 JL8
JL9 JL10
JL11
JL12 JL13
JL14 JL15
JL16 JL17
JL18
JL19 JL20
JL21 JL22
JL23 JL24
JL25 JL26
JL27 JL28
JL29 JL30
JL31 JL32
PIN83 PIN2
PIN84 PIN1
PIN5
PIN4
PIN8
PIN6
PIN10
PIN15
PIN9
PIN17
PIN20
PIN11
PIN24
PIN27
PIN12
PIN29
PIN33
PIN16
PIN35
PIN48
PIN18
PIN49
PIN50
PIN21
PIN51
PIN22
PIN52
PIN25
PIN54
PIN55
PIN28
PIN56PIN57
PIN30
PIN58PIN60
PIN31
PIN61
PIN34
PIN63
PIN65
PIN36
PIN64
PIN68PIN67
PIN70PIN69
PIN73
PIN74
PIN75PIN76
PIN80PIN79
PIN77PIN81
JR33 JR34
JL33 JL34
PIN46
PIN37
PIN40
PIN44
PIN45
PIN41
PIN39
VCC
GND
GCLK1
TCK
D2B
D2A
D2F
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D1B
D1A
D1F
D1G
D2G
D3G
D1C
D1D
D1E
D3E
VCC
GND
GCLK2
TDO
D2C
D2D
D2E
D3C
D3D
D4C
D4D
D4E
DOT6
VCC
GND
D5B
D5A
D5F
D5G
D6A
D6F
D6G
D7A
D7F
D7G
GOE
D6B
D7B
D8B
D8A
D8F
D8G
DOT5
GCLR
TDI
D7C
D8C
D8D
D8E
DOT8
VCC
GND
TMS
D5C
D5D
D5E
D6C
D6D
D6E
D7D
D7E
DOT7
Schematic Diagrams
CPLD Development/Programmer Kit User Guide 4-7
3300A–PLD–08/02
Figure 4-6.
Schematic Diagram of 100-pin PQFP Socket Adapter Board
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCC
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPRIGHT
HEADER 20X2
VCC
GND
GCLK1
TCK
D2B
D2A
D2F
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D1B
D1A
D1F
D1G
D2G
D3G
D1C
D1D
D1E
D3E
VCC
GND
GCLK2
TDO
D2C
D2D
D2E
D3C
D3D
D4C
D4D
D4E
DOT1
DOT2
DOT3
DOT4
DOT6
VCC
GND
D5B
D5A
D5F
D5G
D6A
D6F
D6G
D7A
D7F
D7G
GOE
D6B
D7B
D8B
D8A
D8F
D8G
DOT5
GCLR
TDI
D7C
D8C
D8D
D8E
DOT8
VCC
GND
TMS
D5C
D5D
D5E
D6C
D6D
D6E
D7D
D7E
DOT7
I/On
1
I/On
2
I/O
3
I/O
4
VCCIO
5
TDI
6
I/On
7
I/O
8
I/On
9
I/O
10
I/O
11
I/O
12
GND
13
I/O
14
I/O
15
I/O
16
TMS
17
I/O
18
I/O
19
VCCIO
20
I/O
21
I/O
22
I/O
23
I/On
24
I/O
25
I/On
26
I/O
27
GND
28
I/On
29
I/On
30
I/O
31
I/O
32
I/O
33
I/O
34
I/O
35
VCCIO
36
I/O
37
I/O
38
I/O
39
GND
40
VCCINT
41
I/O
42
I/O
43
I/O
44
GND
45
I/O
46
I/O
47
I/O
48
I/O
49
I/O
50
I/On 51
I/On 52
VCCIO 53
I/O 54
I/On 55
I/O 56
I/On 57
I/O 58
I/O 59
I/O 60
GND 61
I/O 62
I/O 63
TCK 64
I/O 65
I/O 66
I/O 67
VCCIO 68
I/O 69
I/O 70
I/O 71
I/On 72
I/O 73
I/On 74
TDO 75
GND 76
I/O 77
I/O 78
I/On 79
I/On 80
I/O 81
I/O 82
I/O 83
VCCIO 84
I/O 85
I/O 86
I/O/GCLK3 87
GND 88
GCLK1 89
OE1 90
GCLR 91
GCLK2 92
VCCINT 93
I/O 94
I/O 95
I/O 96
GND 97
I/O 98
I/O 99
I/O 100
ATMEL PQFP100
U1
P1
P2
P3
P4
P7
P8
P9
P10
P11
P12
P14
P15
P16
P18
P19
P21
P22
P23
P24
P25
P26
P27
P29
P30
P31
P32
P33
P34
P35
P37
P38
P39
P42
P43
P44
P46
P47
P48
P49
P50
P51
P52
P54
P55
P56
P57
P58
P59
P60
P62
P63
P65
P66
P67
P69
P70
P71
P72
P73
P74
P77
P78
P79
P80
P81
P82
P83
P85
P86
P87
P89
P90
P91
P92
P94
P95
P98
P99
P96
P100
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GCLK1
GCLK2
GOE
GCLR
TDO
TCKTMS
TDI
DOT5
D5B
D5C
D5A
D5F
D5E
D5G
DOT6
D5D
D6C
D6B
D6D
D6A
D6E
D6F
D6G
D7B
D7C
D7A
D7D
DOT7
D7F
D7E
D7G
DOT8
D8B
D8C
D8A
D8D
D8F
D8E
D8G
D4G
D4D
D4F
D4E
D4A
D4C
D4B
DOT4
D3G
D3F
D3E
D3A
D3D
D3B
D3C
DOT3
D2G
D2E
D2F
D2D
DOT2
D2A
D1B
DOT1
D1C
D1A
D1D
D1F
D1E
D1G
D2B
D2C
Schematic Diagrams
4-8 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Figure 4-7.
Schematic Diagram of 100-pin TQFP Socket Adapter Board
I/On
1
I/On
2
VCCIO
3
TDI
4
I/On
5
I/O
6
I/On
7
I/O
8
I/O
9
I/O
10
GND
11
I/O
12
I/O
13
I/O
14
TMS
15
I/O
16
I/O
17
VCCIO
18
I/O
19
I/O
20
I/O
21
I/On
22
I/O
23
I/On
24
I/O
25
GND
26
I/On
27
I/On
28
I/O
29
I/O
30
I/O
31
I/O
32
I/O
33
VCCIO
34
I/O
35
I/O
36
I/O
37
GND
38
VCCINT
39
I/O
40
I/O
41
I/O
42
GND
43
I/O
44
I/O
45
I/O
46
I/O
47
I/O
48
I/On
49
I/On
50
VCCIO 51
I/O 52
I/On 53
I/O 54
I/On 55
I/O 56
I/O 57
I/O 58
GND 59
I/O 60
I/O 61
TCK 62
I/O 63
I/O 64
I/O 65
VCCIO 66
I/O 67
I/O 68
I/O 69
I/On 70
I/O 71
I/On 72
TDO 73
GND 74
I/O 75
ATMEL TQFP100
I/O 76
I/On 77
I/O 78
I/On 79
I/O 80
I/O 81
VCCIO 82
I/O 83
I/O 84
I/O GCLK3 85
GND 86
GCLK1 87
OE1 88
GCLR 89
GCLK2 90
VCCINT 91
I/O 92
I/O 93
I/O 94
GND 95
I/O 96
I/O 97
I/O 98
I/O 99
I/O 100
U1
TQFP100
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPRIGHT
HEADER 20X2
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCC
P1
P2
P5
P6
P7
VCC
GND
GCLK1
TCK
D2B
D2A
D2F
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D1B
D1A
D1F
D1G
D2G
D3G
D1C
D1D
D1E
D3E
VCC
GND
GCLK2
TDO
D2C
D2D
D2E
D3C
D3D
D4C
D4D
D4E
DOT1
DOT2
DOT3
DOT4
DOT6
VCC
GND
D5B
D5A
D5F
D5G
D6A
D6F
D6G
D7A
D7F
D7G
GOE
D6B
D7B
D8B
D8A
D8F
D8G
DOT5
GCLR
TDI
D7C
D8C
D8D
D8E
DOT8
VCC
GND
TMS
D5C
D5D
D5E
D6C
D6D
D6E
D7D
D7E
DOT7
TMS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
TDI
TCK
TDO
GCLK1
GOE
GCLR
GCLK2
D2B
D2A
D2F
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D1B
D1A
D1F
D1G
D2G
D3G
D1C
D1D
D1E
D3E
D2C
D2D
D2E
D3C
D3D
D4C
D4D
D4E
DOT1
DOT2
DOT3
DOT4
DOT6
D5B
D5A
D5F
D5G
D6A
D6F
D6G
D7A
D7F
D7G
D6B
D7B
D8B
D8A
D8F
D8G
DOT5
D7C
D8C
D8D
D8E
DOT8
D5C
D5D
D5E
D6C
D6D
D6E
D7D
D7E
DOT7
P8
P9
P10
P12
P13
P14
P16
P17
P19
P20
P21
P22
P23
P24
P25
P27
P28
P29
P30
P31
P32
P33
P35
P36
P37
P40
P41
P42
P44
P45
P46
P47
P48
P49
P50
P52
P53
P54
P55
P56
P57
P58
P60
P61
P63
P64
P65
P67
P68
P69
P70
P71
P72
P75
P76
P77
P78
P79
P80
P81
P83
P84
P85
P87
P88
P89
P90
P92
P93
P94
P96
P97
P98
P99
P100
Schematic Diagrams
CPLD Development/Programmer Kit User Guide 4-9
3300A–PLD–08/02
Figure 4-8.
Schematic Diagram of 144-pin TQFP Socket Adapter Board
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCC
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPRIGHT
HEADER 20X2
VCC
GND
GCLK1
TCK
D2B
D2A
D2F
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D1B
D1A
D1F
D1G
D2G
D3G
D1C
D1D
D1E
D3E
VCC
GND
GCLK2
TDO
D2C
D2D
D2E
D3C
D3D
D4C
D4D
D4E
DOT1
DOT2
DOT3
DOT4
DOT6
VCC
GND
D5B
D5A
D5F
D5G
D6A
D6F
D6G
D7A
D7F
D7G
GOE
D6B
D7B
D8B
D8A
D8F
D8G
DOT5
GCLR
TDI
D7C
D8C
D8D
D8E
DOT8
VCC
GND
TMS
D5C
D5D
D5E
D6C
D6D
D6E
D7D
D7E
DOT7
I/On
1
I/On
2
GND
3
TDI
4
I/O
5
I/O
6
I/O
7
I/O
8
I/O
9
I/O
10
I/O
11
I/On
12
GND
13
I/O
14
I/O
15
I/O
16
GND
17
I/O
18
I/On
19
TMS
20
I/O
21
I/O
22
I/O
23
VCCIO
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
GND
33
I/On
34
I/On
35
I/On
36
I/O
41
I/O
42
I/On
43
I/O
44
I/O
45
I/On
46
I/On
47
I/On
48
I/On
49
VCCIO
50
VCCINT
51
GND
52
I/O
53
I/O
54
I/O
55
I/O
56
GND
57
VCCINT
58
GND
59
I/O
60
I/O
61
I/O
62
I/O
63
GND
64
I/O
65
I/On
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O
71
I/O 81
I/O 82
I/O 83
I/O 84
GND 85
I/O 86
I/O 87
I/O 88
TCK 89
I/On 90
I/O 91
I/O 92
I/O 93
I/O 94
VCCIO 95
I/O 96
I/O 97
I/O 98
I/O 99
I/O 100
I/O 101
I/O 102
I/On 103
TDO 104
GND 105
I/O 106
I/O 107
I/On 108
I/O 109
I/O 110
I/O 111
I/O 112
I/O 113
I/O 114
VCCIO 115
I/O 116
I/O 117
I/O 118
I/O 119
I/On 120
I/On 121
I/On 122
VCINT 123
GND 124
GCLK 125
GOE 126
GCLR 127
GCLK2 128
GND 129
VCCINT 130
I/O 131
I/O 132
I/O 133
I/O 134
GND 135
I/O 136
I/O 137
I/O 138
I/O 139
I/O 140
I/O 141
I/O 142
I/O 143
VCCIO 144
ATMEL TQFP144
VCCIO 76
I/O 77
I/O 78
I/O 79
I/O 80
VCCIO 73
I/O 74
I/On 75
I/O
72
I/O
37
I/O
38
I/O
39
I/O
40
U1
TQFP144
P5
P6
P7
P8
P9
P10
P11
P14
P15
P16
P18
P21
P22
P23
P25
P26
P27
P28
P29
P30
P31
P32
P37
P38
P39
P40
P41
P42
P44
P45
P53
P54
P55
P56
P60
P61
P62
P63
P65
P67
P68
P69
P70
P71
P72
P74
P77
P78
P79
P80
P81
P82
P83
P84
P86
P87
P88
P91
P92
P93
P94
P96
P97
P98
P99
P100
P101
P102
P106
P107
P109
P110
P111
P112
P113
P114
P116
P117
P118
P119
P125
P126
P127
P128
P131
P132
P133
P134
P136
P137
P138
P139
P140
P141
P142
P143
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
TDO
TCKTMS
TDI
GCLK1
GOE
GCLR
GCLK2
DOT5
D5B
D5C
D5A
D5D
D5F
D5E
D5G
DOT6
D6C
D6B
D6D
D6A
D6E
D6F
D6G
DOT7
D7B
D7C
D7A
D7D
D7F
D7E
D7G
DOT8
D8B
D8C
D8A
D8D
D8F
D8E
D8G
D4D
D4G
D4E
D4F
D4C
D4A
D4B
DOT4
D3G
D3E
D3F
D3D
D3A
D3C
D3B
DOT3
D2G
D2E
D2F
D2D
D2A
D2C
D2B
DOT2
D1G
D1E
D1F
D1D
D1A
D1C
D1B
DOT1
Schematic Diagrams
4-10 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Figure 4-9.
Schematic Diagram of 160-pin PQFP Socket Adapter Board
NC
1
NC
2
NC
3
NC
4
NC
5
NC
6
NC
7
VCCIO
8
TDI
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
I/O
16
GND
17
I/O
18
I/O
19
I/O
20
I/O
21
TMS
22
I/O
23
I/O
24
I/O
25
VCCIO
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
I/O
33
NC
34
NC
35
NC
36
NC
37
NC
38
NC
39
NC
40
I/O
41
GND
42
I/O
43
NC
44
NC
45
NC
46
NC
47
I/O
48
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
I/O
54
VCCIO
55
I/O
56
I/O
57
I/O
58
I/O
59
GND
60
VCCINT
61
I/O
62
I/O
63
I/O
64
I/O
65
GND
66
I/O
67
I/O
68
I/O
69
I/O
70
I/O
71
I/O
72
I/O
73
NC
74
NC
75
NC
76
NC
77
I/O
78
VCCIO
79
I/O
80
NC 81
NC 82
NC 83
NC 84
NC 85
NC 86
NC 87
I/O 88
I/O 89
I/O 90
I/O 91
I/O 92
I/O 93
I/O 94
GND 95
I/O 96
I/O 97
I/O 98
TCK 99
I/O 100
I/O 101
I/O 102
I/O 103
VCCIO 104
I/O 105
I/O 106
I/O 107
I/O 108
I/O 109
I/O 110
I/O 111
TDO 112
GND 113
NC 114
NC 115
NC 116
NC 117
NC 118
NC 119
NC 120
I/O 121
I/O 122
I/O 123
NC 124
NC 125
NC 126
NC 127
I/O 128
I/O 129
I/O 130
I/O 131
I/O 132
VCCIO 133
I/O 134
I/O 135
I/O 136
I/O/GCLK3 137
GND 138
GCLK1 139
OE1 140
GCLR 141
GCLK2 142
VCCINT 143
I/O 144
I/O 145
I/O 146
I/O 147
GND 148
I/O 149
I/O 150
I/O 151
I/O 152
I/O 153
NC 154
NC 155
NC 156
NC 157
I/O 158
I/O 159
I/O 160
ATMEL PQFP160
U1
c1
0.1uF
c2
0.1uF
c3
0.1uF
c4
0.1uF
VCC
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPLEFT
HEADER 20X2
1 2
3 4
5 6
7 8
910
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
JPRIGHT
HEADER 20X2
VCC
GND
GCLK1
TCK
D2B
D2A
D2F
D3B
D3A
D3F
D4B
D4A
D4F
D4G
D1B
D1A
D1F
D1G
D2G
D3G
D1C
D1D
D1E
D3E
VCC
GND
GCLK2
TDO
D2C
D2D
D2E
D3C
D3D
D4C
D4D
D4E
DOT1
DOT2
DOT3
DOT4
DOT6
VCC
GND
D5B
D5A
D5F
D5G
D6A
D6F
D6G
D7A
D7F
D7G
GOE
D6B
D7B
D8B
D8A
D8F
D8G
DOT5
GCLR
TDI
D7C
D8C
D8D
D8E
DOT8
VCC
GND
TMS
D5C
D5D
D5E
D6C
D6D
D6E
D7D
D7E
DOT7
P11
P10
P12
P13
P14
P15
P16
P18
P19
P20
P21
P23
P24
P25
P27
P28
P29
P30
P31
P32
P33
P41
P43
P48
P49
P50
P51
P52
P53
P54
P56
P57
P58
P59
P62
P63
P64
P65
P67
P68
P69
P70
P71
P72
P73
P78
P80
P88
P89
P90
P91
P92
P93
P94
P96
P97
P98
P100
P101
P102
P103
P105
P106
P107
P108
P109
P110
P111
P121
P122
P123
P128
P129
P130
P131
P132
P134
P135
P136
P137
P139
P140
P141
P142
P144
P145
P146
P147
P149
P150
P151
P152
P153
P158
P159
P160
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
GND
GND
GND
GND
GND
GND
GND
GND
GOE
GCLR
GCLK2
GCLK1
TMS
TDI TDO
TCK
DOT5
D5B
D5C
D5A
D5D
D5F
D5E
D5G
DOT6
D6C
D6B
D6D
D6A
D6E
D6F
D6G
D7B
D7C
D7A
D7D
DOT7
D7F
D7E
D7G
DOT8
D8B
D8C
D8A
D8D
D8F
D8E
D8G
D4G
D4D
D4F
D4E
D4A
D4C
D4B
DOT4
D3G
D3F
D3E
D3A
D3D
D3B
D3C
DOT3
D2G
D2E
D2F
D2D
D2A
D2C
DOT2
D1G
D1E
D1F
D1D
D1A
D1C
D1B
DOT1
D2B
Schematic Diagrams
CPLD Development/Programmer Kit User Guide 4-11
3300A–PLD–08/02
Figure 4-10.
Schematic Diagram of Atmel CPLD ISP Cable
R16 100
1 2
3 4
5 6
7 8
910
JP1
HEADER 5X2
R22
4.7k
R21
4.7k
R26
4.7k
1A1
21Y1 18
1A2
41Y2 16
1A3
61Y3 14
1A4
81Y4 12
2A1
11 2Y1 9
2A2
13 2Y2 7
2A3
15 2Y3 5
2A4
17 2Y4 3
1G
1VCC 20
2G
19 GND 10
U1
74VHC244
R17 100
R1
330ohm
R18 100
R19 100
R23
4.7k
R20 100
D1
1N4148
R24
4.7k
C1
0.1uF
L1
LED
R25
4.7k
INI
TCK
AF
TMS
TDI
INIT
SEL_IN
AUTO
STROBE
nACK
BUSY
TDO
TDO
INI
AF
TCK
TMS
TDI
D7
D0
GND
GND
GND
VCC
VCC
GND
VCC
20-SOIC
Buffer/Line Driver
10 Pin Header to ISP Board
Schematic Diagrams
4-12 CPLD Development/Programmer Kit User Guide
3300A–PLD–08/02
Figure 4-11.
Schematic Diagram of Atmel CPLD ISP Cable, Continued
R15 30K
R11 4.7K
R3 100
R13 4.7K
R14 3.3K
R10 4.7K
D 4 1N4148
R4 100
D3 1N4148
D2 1N4148
R2 100
R7 100
R6 100
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
P1
DB25
-
+
5
6
7
84
U2BLM393
R8 100
R5 100
R9 100
-
+
3
2
1
84
U2ALM393
R12 10K
STROBE
AUTO
INIT
SEL_IN
ERROR
D0
ERROR
D7
BUSY
nACK
GND
VCC
GND
VCC
GND
VCC
VCC
Parallel Port Section
Vref1.5V - 1.6V
Voltage Detection
8-SOP 8-SOP
3V = 0
5V = 1
1.36V at VCC = 3.3
2.06V at VCC = 5.0
Printed on recycled paper.
3300A–PLD–08/02 /1M
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
whichisdetailedinAtmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
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by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
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