1
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 – Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
4Mb
ZBT® SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 6ns, 7.5ns and 10ns
Single +3.3V ±5% power supply (VDD)
Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
Advanced control logic for minimum control
signal interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or interleaved burst modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 8Mb, and
16Mb ZBT SRAM family
Automatic power-down
165-pin FBGA package
100-pin TQFP package
119-pin BGA package
OPTIONS MARKING
Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz -6
4.2ns/7.5ns/133 MHz -7.5
5ns/10ns/100 MHz -10
Configurations
3.3V I/O
256K x 18 MT55L256L18P1
128K x 32 MT55L128L32P1
128K x 36 MT55L128L36P1
2.5V I/O
256K x 18 MT55L256V18P1
128K x 32 MT55L128V32P1
128K x 36 MT55L128V36P1
Package
100-pin TQFP T
165-pin FBGA F*
119-pin, 14mm x 22mm BGA B
Operating Temperature Range
Commercial (0°C to +70°C) None
Industrial (-40°C to +85°C)** IT
Part Number Example:
MT55L256L18P1T-10
MT55L256L18P1, MT55L256V18P1,
MT55L128L32P1, MT55L128V32P1,
MT55L128L36P1, MT55L128V36P1
3.3V VDD, 3.3V or 2.5V I/O
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
2. JEDEC-standard MS-028 BHA (PBGA).
100-Pin TQFP1
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
165-Pin FBGA
(Preliminary Package Data)
119-Pin BGA2
2
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 – Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams
for detailed information.
FUNCTIONAL BLOCK DIAGRAM
256K x 18
SA0, SA1, SA
K
MODE
18
BWa#
BWb#
R/W#
CE#
CE2
CE2#
OE#
READ LOGIC
E
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1 WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
18
18 16 18
BURST
LOGIC SA0'
SA1'
D1
D0 Q1
Q0
SA0
SA1
K
18
ADV/LD#
ADV/LD#
CLK
CKE#
DQPa
DQPb
36
36 36
36
INPUT
REGISTER 0
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
256K x 9 x 2
MEMORY
ARRAY
WRITE
DRIVERS
E
INPUT
REGISTER 1
E
36
36 36
36
K
MODE
17
BWa#
BWb#
BWc#
BWd#
R/W#
CE#
CE2
CE2#
OE#
READ LOGIC
DQs
DQPa
DQPb
DQPc
DQPd
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
128K x 8 x 4
(x32)
128K x 9 x 4
(x36)
MEMORY
ARRAY
E
E
INPUT
REGISTER 0
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1 WRITE ADDRESS
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
17
17 15 17
BURST
LOGIC SA0'
SA1'
D1
D0 Q1
Q0
SA0
SA1
K
17
ADV/LD#
ADV/LD#
E
INPUT
REGISTER 1
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
CLK
CKE#
WRITE
DRIVERS
SA0, SA1, SA
FUNCTIONAL BLOCK DIAGRAM
128K x 32/36
3
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
be internally generated as controlled by the burst ad-
vance pin (ADV/LD#). Use of burst mode is optional.
It is allowable to give an address for each individual
READ and WRITE cycle. BURST cycles wrap around
after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock cycle
one, the address is present on rising edge one. BYTE
WRITEs need to be asserted on the same cycle as the
address. The data associated with the address is required
two cycles later, or on the rising edge of clock cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa#
controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; and BWd# controls DQd pins. Cycle
types can only be defined when an address is loaded,
i.e., when ADV/LD# is LOW. Parity/ECC bits are only
available on the x18 and x36 versions.
Micron’s 4Mb ZBT SRAMs operate from a +3.3V VDD
power supply, and all inputs and outputs are LVTTL-
compatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requir-
ing high bandwidth and zero bus turnaround delays.
Please refer to Micron’s Web site (www.micron.com/
products/datasheets/zbtds.html) for the latest data
sheet.
GENERAL DESCRIPTION
The Micron® Zero Bus Turnaround (ZBT®) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,
128K x 32, or 128K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles when
transitioning from READ to WRITE, or vice versa. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#) and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The data-out (Q),
enabled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.
All READ, WRITE and DESELECT cycles are initiated
by the ADV/LD# input. Subsequent burst addresses can
4
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
PIN # x18 x32 x36 PIN # x18 x32 x36 PIN # x18 x32 x36
TQFP PIN ASSIGNMENT TABLE
PIN # x18 x32 x36
1NCNCDQc
2NCDQc DQc
3NCDQc DQc
4VDDQ
5VSS
6NCDQc DQc
7NCDQc DQc
8DQb DQc DQc
9DQb DQc DQc
10 VSS
11 VDDQ
12 DQb DQc DQc
13 DQb DQc DQc
14 VDD
15 VDD
16 VDD
17 VSS
18 DQb DQd DQd
19 DQb DQd DQd
20 VDDQ
21 VSS
22 DQb DQd DQd
23 DQb DQd DQd
24 DQb DQd DQd
25 NC DQd DQd
* Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively.
26 VSS
27 VDDQ
28 NC DQd DQd
29 NC DQd DQd
30 NC NC DQd
31 MODE (LBO#)
32 SA
33 SA
34 SA
35 SA
36 SA1
37 SA0
38 DNU
39 DNU
40 VSS
41 VDD
42 DNU
43 DNU
44 SA
45 SA
46 SA
47 SA
48 SA
49 SA
50 SA
51 NC NC DQa
52 NC DQa DQa
53 NC DQa DQa
54 VDDQ
55 VSS
56 NC DQa DQa
57 NC DQa DQa
58 DQa
59 DQa
60 VSS
61 VDDQ
62 DQa
63 DQa
64 ZZ
65 VDD
66 VDD
67 VSS
68 DQa DQb DQb
69 DQa DQb DQb
70 VDDQ
71 VSS
72 DQa DQb DQb
73 DQa DQb DQb
74 DQa DQb DQb
75 NC DQb DQb
76 VSS
77 VDDQ
78 NC DQb DQb
79 NC DQb DQb
80 SA NC DQb
81 SA
82 SA
83 NF*
84 NF*
85 ADV/LD#
86 OE# (G#)
87 CKE#
88 R/W#
89 CLK
90 VSS
91 VDD
92 CE2#
93 BWa#
94 BWb#
95 NC BWc# BWc#
96 NC BWd# BWd#
97 CE2
98 CE#
99 SA
100 SA
5
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
SA
SA
NF**
NF**
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
NC
NC
V
DD
Q
V
SS
NC
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
V
DD
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
DD
V
DD
V
DD
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
NC
V
SS
V
DD
Q
NC
NC
NC
x18
SA
SA
NF**
NF**
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC/DQb*
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
V
DD
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NC/DQa*
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NC/DQc*
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
V
DD
V
DD
V
DD
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NC/DQd*
x32/x36
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively.
6
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS
x18 x32/x36 SYMBOL TYPE DESCRIPTION
37 37 SA0 Input Synchronous Address Inputs: These inputs are registered
36 36 SA1 and must meet the setup and hold times around the rising
32-35, 44-50, 32-35, 44-50, SA edge of CLK. Pins 83 and 84 are reserved as address bits
80-82, 99, 100 81, 82, 99, 100 for higher-density 8Mb and 16Mb ZBT SRAMs, respectively.
SA0 and SA1 are the two least significant bits (LSB) of the
address field and set the internal burst counter if burst is
desired.
93 93 BWa# Input Synchronous Byte Write Enables: These active LOW inputs
94 94 BWb# allow individual bytes to be written when a WRITE cycle is
95 BWc# active and must meet the setup and hold times around the
96 BWd# rising edge of CLK. BYTE WRITEs need to be asserted on
the same cycle as the address. BWs are associated with
addresses and apply to subsequent data. BWa# controls
DQa pins; BWb# controls DQb pins; BWc# controls DQc
pins; BWd# controls DQd pins.
89 89 CLK Input Clock: This signal registers the address, data, chip enables,
byte write enables and burst control inputs on its rising
edge. All synchronous inputs must meet setup and hold
times around the clocks rising edge.
98 98 CE# Input Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW).
92 92 CE2# Input Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input can
be used for memory depth expansion.
97 97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input can
be used for memory depth expansion.
86 86 OE# Input Output Enable: This
active LOW, asynchronous input
(G#) enables the data I/O output drivers. G# is the JEDEC-
standard term for OE#.
85 85 ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.
87 87 CKE# Input Synchronous Clock Enable: This active LOW input permits
CLK to propagate throughout the device. When CKE# is
HIGH, the device ignores the CLK input and effectively
internally extends the previous CLK cycle. This input must
meet setup and hold times around the rising edge of CLK.
64 64 ZZ Input Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ is
active, all other inputs are ignored.
(continued on next page)
7
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS (continued)
x18 x32/x36 SYMBOL TYPE DESCRIPTION
88 88 R/W# Input Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted into
WRITEs (and vice versa) other than by loading a new
address. A LOW on this pin permits BYTE WRITE operations
and must meet the setup and hold times around the rising
edge of CLK. Full bus-width WRITEs occur if all byte write
enables are LOW.
(a) 58, 59, 62, 63, (a) 52, 53, 56-59, DQa Input/ SRAM Data I/Os: Byte a is DQa pins; Byte b is DQb
68, 69, 72-74 62, 63 Output pins; Byte c is DQc pins; Byte d is DQd pins. Input data
(b) 8, 9, 12, 13, (b) 68, 69, 72-75, DQb must meet setup and hold times around the rising edge of
18, 19, 22-24 78, 79 CLK.
(c) 2, 3, 6-9, DQc
12, 13
(d) 18, 19, 22-25, DQd
28, 29
N/A 51 NC/DQa NC/ No Connect/Data Bits: On the x32 version, these pins are
80 NC/DQb I/O no connect (NC) and can be left floating or connected to
1NC/DQc GND to minimize thermal impedance. On the x36 version,
30 NC/DQd these bits are DQs.
31 31 MODE Input Mode: This input selects the burst sequence. A LOW on
(LBO#) this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
1-3, 6, 7, 25, N/A NC NC No Connect: These pins can be left floating or connected
28-30, 51-53, 56, to GND to minimize thermal impedance.
57, 75, 78, 79,
95, 96
83, 84 83, 84 NF No Function: These are internally connected to the die and
will have the capacitance of input pins. It is allowable to
leave these pins unconnected or driven by signals.
Reserved for address expansion, pin 83 becomes an SA at
8Mb density and pin 84 becomes an SA at 16Mb density.
38, 39, 42, 43 38, 39, 42, 43 DNU Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
14, 15, 16, 41, 65, 14, 15, 16, 41, 65, V
DD
Supply Power Supply:
See DC Electrical Characteristics and
66, 91 66, 91 Operating Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27, V
DD
Q Supply Isolated Output Buffer Supply:
See DC Electrical
54, 61, 70, 77 54, 61, 70, 77 Characteristics and Operating Conditions for range.
5, 10, 17, 21, 5, 10, 17, 21, V
SS
Supply Ground:
GND.
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
8
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
PIN LAYOUT (TOP VIEW)
165-PIN FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
V
DD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
DQb
DQb
DQb
DQb
DQPb
NC
MODE
(LBO#)
BWb#
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
NC
BWa#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
CE2#
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
SA1
SA0
CKE#
R/W#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
DNU
DNU
ADV/LD#
OE# (G#)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
NC
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
SA
SA
SA
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
SA
TOP VIEW
3456789
10 11
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NC
NC
NC
NC
NC
NC/DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NC/DQPd
NC
MODE
(LBO#)
BWc#
BWd#
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
BWb#
BWa#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
CE2#
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
SA1
SA0
CKE#
R/W#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
DNU
DNU
ADV/LD#
OE# (G#)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
NC
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
SA
SA
NC
NC
NC/DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC/DQPa
NC
SA
TOP VIEW
3456789
10 11
1
x18 x32/x36
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
NOTE: Pins 9A, and 9B reserved for address pin expansion; 8Mb, and 16Mb respectively.
9
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS
x18 x32/x36 SYMBOL TYPE DESCRIPTION
6R 6R SA0 Input Synchronous Address Inputs: These inputs are registered and must
6P 6P SA1 meet the setup and hold times around the rising edge of CLK.
2A, 2B, 3P, 3R, 2A, 2B, 3P, 3R, SA
4P, 4R, 8P, 8R, 4P, 4R, 8P, 8R,
9P, 9R, 10A, 9P, 9R, 10A,
10B, 10P, 10B, 10P,
10R, 11A, 11R 10R, 11R
5B 5B BWa# Input Synchronous Byte Write Enables: These active LOW inputs allow
4A 5A BWb# individual bytes to be written and must meet the setup and hold
4A BWc# times around the rising edge of CLK. A byte write enable is LOW
4B BWd# for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
6B 6B CLK Input Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clocks rising
edge.
3A 3A CE# Input Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded.
6A 6A CE2# Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
7A 7A CKE# Input Synchronous Clock Enable: This active LOW input permits CLK to
propagate throughout the device. When CKE# is HIGH, the device
ignores the CLK input and effectively internally extends the
previous CLK cycle. This input must meet setup and hold times
around the rising edge of CLK.
11H 11H ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
7B 7B R/W# Input Read/Write: This input determines the cycle type when ADV/LD# is
LOW and is the only means for determining READs and WRITEs.
READ cycles may not be converted into WRITEs (and vice versa)
other than by loading a new address. A LOW on this pin permits
BYTE WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs occur if all
byte write enables are LOW.
3B 3B CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
8B 8B OE#(G#) Input Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
(continued on next page)
10
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS (continued)
x18 x32/x36 SYMBOL TYPE DESCRIPTION
8A 8A ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new
address at the CLK rising edge.
1R 1R MODE Input Mode: This input selects the burst sequence. A LOW on this input
(LB0#) selects linear burst. NC or HIGH on this input selects interleaved
burst. Do not alter input state while device is operating.
(a) 10J, 10K, (a) 10J, 10K, DQa Input/ SRAM Data I/Os: For the x18 version, Byte a is associated DQas;
10L, 10M, 11D, 10L, 10M, 11J, Output Byte b is associated with DQbs. For the x32 and x36 versions,
11E, 11F, 11G 11K, 11L, 11M Byte a is associated with DQas; Byte b is associated with DQb's;
(b) 1J, 1K, (b) 10D, 10E, DQb Byte c is associated with DQcs; Byte d is associated with DQds.
1L, 1M, 2D, 10F, 10G, 11D, Input data must meet setup and hold times around the rising edge
2E, 2F, 2G 11E, 11F, 11G of CLK.
(c) 1D, 1E, DQc
1F, 1G, 2D,
2E, 2F, 2G
(d) 1J, 1K, 1L, DQd
1M, 2J, 2K,
2L, 2M
11C 11N NC/DQPa N C / No Connect/Parity Data I/Os: On the x32 version, these are No
1N 11C NC/DQPb I/O Connect (NC). On the x18 version, Byte a parity is DQPa; Byte b
1C NC/DQPc parity is DQPb. On the x36 version, Byte a parity is DQPa; Byte
1N NC/DQPd b parity is DQPb; Byte c parity is DQPc; Byte d parity is DQPd.
1H, 2H, 4D, 1H, 2H, 4D, V
DD
Supply Power Supply: See DC Electrical Characteristics and Operating
4E, 4F, 4G, 4E, 4F, 4G, Conditions for range.
4H, 4J, 4K, 4H, 4J, 4K,
4L, 4M, 7N, 4L, 4M, 7N,
8D, 8E, 8F, 8D, 8E, 8F,
8G, 8H, 8J, 8G, 8H, 8J,
8K, 8L, 8M 8K, 8L, 8M
3C, 3D, 3E, 3C, 3D, 3E, V
DD
Q Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
3F, 3G, 3J, 3F, 3G, 3J, Operating Conditions for range.
3K, 3L, 3M, 3K, 3L, 3M,
3N, 9C, 9D, 3N, 9C, 9D,
9E, 9F, 9G, 9E, 9F, 9G,
9J, 9K, 9L, 9J, 9K, 9L,
9M, 9N 9M, 9N
(continued on next page)
11
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS (continued)
x18 x32/x36 SYMBOL TYPE DESCRIPTION
4C, 4N, 5C, 4C, 4N, 5C, V
SS
Supply Ground: GND.
5D, 5E 5F, 5D, 5E 5F,
5G, 5H, 5J, 5G, 5H, 5J,
5K, 5L, 5M, 5K, 5L, 5M,
6C,
6D,
6E,
6F, 6C,
6D,
6E,
6F,
6G, 6H, 6J, 6G, 6H, 6J,
6K, 6L, 6M, 6K, 6L, 6M,
7C, 7D, 7E, 7C, 7D, 7E,
7F, 7G, 7H, 7F, 7G, 7H,
7J, 7K, 7L, 7J, 7K, 7L,
7M, 8C, 8N 7M, 8C, 8N
5P, 5R, 7P, 7R 5P, 5R, 7P, 7R DNU Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1A, 1B, 1C, 1A, 1B, 1P, NC No Connect: These signals are not internally connected and
1D, 1E, 1F, 2C, 2N, may be connected to ground to improve package heat
1G, 1P, 2C, 2P, 2R, 3H, dissipation. Pins 9A, and 9B reserved for address pin
2J, 2K, 2L, 5N, 6N, 9A, expansion; 8Mb, and 16Mb respectively.
2M, 2N, 2P, 9B, 9H, 10C,
2R, 3H, 4B, 10H, 10N,
5A, 5N, 6N, 11A, 11B,
9A, 9B, 9H, 11P
10C, 10D,
10E, 10F,
10G, 10H,
10N, 11B,
11J, 11K,
11L, 11M,
11N, 11P
12
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 – Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
PIN LAYOUT (TOP VIEW)
119-PIN BGA
x18 x32/x36
NOTE: 1. Pins 4G and 4A are reserved for address pin expansion, 8Mb and 16Mb respectively.
2. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
3. Pins 3J, 5J, and 5R do not have to be connected directly to VDD if the input voltage is VIH.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
V
DD
Q
NC
NC
DQc
DQc
V
DD
Q
DQc
DQc
V
DD
Q
DQd
DQd
V
DD
Q
DQd
DQd
NC
NC
V
DD
Q
SA
CE2
SA
NC/DQc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NF/DQPd
SA
NC
DNU
SA
SA
SA
V
SS
V
SS
V
SS
BWc#
V
SS
V
DD
V
SS
BWd#
V
SS
V
SS
V
SS
MODE (LBO#)
SA
DNU
NF
ADV/LD#
V
DD
NC
CE#
OE#(G#)
NF
R/W#
V
DD
CLK
NC
CKE#
SA0
SA0
V
DD
SA
DNU
SA
SA
SA
V
SS
V
SS
V
SS
BWb#
V
SS
V
DD
V
SS
BWa#
V
SS
V
SS
V
SS
V
DD
SA
DNU
SA
CE2#
SA
NC/DQb
DQb
DQb
DQb
DQb
V
DD
DQa
DQa
DQa
DQa
NC/DQPa
SA
NC
DNU
V
DD
Q
NC
NC
DQb
DQb
V
DD
Q
DQb
DQb
V
DD
Q
DQa
DQa
V
DD
Q
DQa
DQa
DNU
ZZ
V
DD
Q
TOP VIEW
234567
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
V
DD
Q
NC
NC
DQb
NC
V
DD
Q
NC
DQb
V
DD
Q
NC
DQb
V
DD
Q
DQb
NC
NC
NC
V
DD
Q
SA
CE2
SA
NC
DQb
NC
DQb
NC
V
DD
DQb
NC
DQb
NC
DQa
SA
SA
DNU
SA
SA
SA
V
SS
V
SS
V
SS
BWb#
V
SS
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
MODE (LBO#)
SA
DNU
NF
ADV/LD#
V
DD
NC
CE#
OE#(G#)
NF
R/W#
V
DD
CLK
NC
CKE#
SA1
SA0
V
DD
NC
DNU
SA
SA
SA
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
SS
BWa#
V
SS
V
SS
V
SS
V
DD
SA
DNU
SA
CE2#
SA
DQa
NC
DQa
NC
DQa
V
DD
NC
DQa
NC
DQa
NC
SA
SA
DNU
V
DD
Q
NC
NC
NC
DQa
V
DD
Q
DQa
NC
V
DD
Q
DQa
NC
V
DD
Q
NC
DQa
DNU
ZZ
V
DD
Q
TOP VIEW
234567
13
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
BGA PIN DESCRIPTIONS
x18 x32/x36 SYMBOL TYPE DESCRIPTION
4P 4P SA0 Input Synchronous Address Inputs: These inputs are registered and
4N 4N SA1 must meet the setup and hold times around the rising edge
2A, 3A, 5A, 2A, 2C, 2R, S A of CLK.
6A, 3B, 5B, 3A, 3B, 3C,
2C, 3C, 5C, 3T, 4T, 5A,
6C, 2R, 6R, 5B, 5C, 5T,
2T, 3T, 5T, 6T 6A, 6C, 6R
5L 5L BWa# Input Synchronous Byte Write Enables: These active LOW inputs allow
3G 5G BWb# individual bytes to be written and must meet the setup and hold
3G BWc# times around the rising edge of CLK. A byte write enable is LOW
3L BWd# for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb.
For the x32 and x36 versions, BWa# controls DQas and DQPa;
BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc;
BWd# controls DQds and DQPd. Parity is only available on the x18
and x36 versions.
4M 4M CKE# Input Synchronous Clock Enable: This active LOW input permits CLK to
propagate throughout the device. When CKE# is HIGH, the
device ignores the CK input and effectively internally extends
the previous CLK cycle. This input must meet the setup and
hold times around the rising edge of CLK.
4H 4H R/W# Input Read/Write: This input determines the cycle type when ADV/
LD# is lOW and is the only means for determining READs and
WRITEs. READ cycles may not be converted into WRITEs (and
vice versa) other than by loading a new address. A LOW on this
pin permits BYTE WRITE operations must meet the setup and
hold times around the rising edge of CLK. Full bus-width
WRITEs occur if all byte write enables are LOW.
4K 4K CLK Input Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clocks rising
edge.
4E 4E CE# Input Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
6B 6B CE2# Input Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
7T 7T ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
2B 2B CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
(continued on next page)
14
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
BGA PIN DESCRIPTIONS (continued)
x18 x32/x36 SYMBOL TYPE DESCRIPTION
4F 4F OE# Input Output Enable: This
active LOW, asynchronous input enables the
data I/O output drivers.
4B 4B ADV#/LD# Input Synchronous Address Advance/Load: When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external addressis loaded. When ADV#/LD# is
HIGH, R/W# is ignored. A LOW on ADV#/LD# clocks a new
address at the CLK rising edge.
3R 3R MODE Input Mode: This input selects the burst sequence. A LOW on this
input selects linear burst. NC or HIGH on this input selects
interleaved burst. Do not alter input state while device is
operating.
4A, 4G 4A, 4G NF Input No Function: These pins are internally connected to the die and
will have the capacitance of input pins. It is allowable to leave
these pins unconnected or driven by signals. These pins are
reserved for address expansion; 4G becomes an SA at 8Mb
density and 4A becomes an SA at 16Mb density.
(a) 6F, 6H, 6L, (a) 6K, 6L, DQa Input/ SRAM Data I/Os: For the x18 version, Byte a is DQas; Byte b
6N, 7E, 7G, 6M, 6N, 7K, Output is DQbs. For the x32 and x36 versions, Byte a is DQas;
7K, 7P 7L, 7N, 7P Byte b is DQbs; Byte c is DQcs; Byte d is DQds. Input
(b) 1D, 1H, (b) 6E, 6F, DQb data must meet setup and hold times around the rising edge of
1L, 1N, 2E, 6G, 6H, 7D, CLK.
2G, 2K, 2M 7E, 7G, 7H
(c) 1D, 1E, DQc
1G, 1H, 2E,
2F, 2G, 2H
(d) 1K, 1L, DQd
1N, 1P, 2K,
2L, 2M, 2N
6D 6P NC/DQPa NC/ No Connect/Parity Data I/Os: On the x32 version, these are No
2P 6D NC/DQPb I/O Connect (NC). On the x18 version, Byte a parity is DQPa; Byte
2D NC/DQPc b parity is DQPb. On the x36 version, Byte a parity is DQPa;
2P NC/DQPd Byte b parity is DQPb; Byte c parity is DQPc; Byte d parity
is DQPd.
2J, 4C, 4J, 2J, 4C, 4J, V
DD
Supply Power Supply: See DC Electrical Characteristics and Operating
4R, 5R, 6J 4R, 5R, 6J Conditions for range.
1A, 1F, 1J, 1A, 1F, 1J, V
DD
Q Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
1M, 1U, 7A, 1M, 1U, 7A, and Operating Conditions for range.
7F, 7J, 7M, 7F, 7J, 7M,
7U 7U
3D, 3E, 3F, 3D, 3E, 3F, V
SS
Supply Ground: GND.
3H, 3K, 3L, 3H, 3K, 3M,
3M, 3N, 3P, 3N, 3P, 5D,
5D, 5E, 5F, 5E, 5F, 5H,
5G, 5H, 5K, 5K, 5M, 5N,
5M, 5N, 5P 5P
(continued on next page)
15
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
x18 x32/x36 SYMBOL TYPE DESCRIPTION
2U, 3U, 4U, 2U, 3U, 4U, DNU Do Not Use: These signals may either be unconnected or wired
5U 5U to GND to improve package heat dissipation.
1B, 1C, 1E, 1B, 1C, 1R, N C No Connect: These signals are not internally connected and
1G, 1K, 1P, 1T, 2T, 3J, may be connected to ground to improve package heat
1R, 1T, 2D, 4D, 4L, 5J, dissipation.
2F, 2H, 2L, 6T, 6U, 7B,
2N, 3J, 4D, 7C, 7R
4L, 4T, 5J,
6E, 6G, 6K,
6M, 6P, 6U,
7B, 7C, 7D,
7H, 7L, 7N,
7R
BGA PIN DESCRIPTIONS (continued)
16
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
FUNCTION R/W# BWa# BWb# BWc# BWd#
READ H X X X X
WRITE Byte aLLHHH
WRITE Byte bLHLHH
WRITE Byte cLHHLH
WRITE Byte dLHHHL
WRITE All Bytes LLLLL
WRITE ABORT/NOP L H H H H
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00 X...X01 X...X10 X...X11
X...X01 X...X00 X...X11 X...X10
X...X10 X...X11 X...X00 X...X01
X...X11 X...X10 X...X01 X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00 X...X01 X...X10 X...X11
X...X01 X...X10 X...X11 X...X00
X...X10 X...X11 X...X00 X...X01
X...X11 X...X00 X...X01 X...X10
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)
NOTE: Using R/W# and BYTE WRITE(s), any one or more bytes may be written.
FUNCTION R/W# BWa# BWb#
READ H X X
WRITE Byte aLLH
WRITE Byte bLHL
WRITE All Bytes L L L
WRITE ABORT/NOP L H H
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)
NOTE: Using R/W# and BYTE WRITE(s), any one or more bytes may
be written.
17
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
State Diagram for ZBT SRAM
DESELECT
BEGIN
READ
BURST
READ
BEGIN
WRITE
DS
DS DS
BURST
WRITE
READ
DS
WRITE
WRITE
BURST
READ
WRITE
READ
BURSTBURST
READ
BURST
DS
WRITE
KEY: COMMAND
DS
READ
WRITE
BURST
OPERATION
DESELECT
New READ
New WRITE
BURST READ,
BURST WRITE or
CONTINUE DESELECT
BURSTREAD
WRITE
NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the
clock (CLK) input and does not change the state of the device.
2. States change on the rising edge of the clock (CLK).
18
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TRUTH TABLE
(Notes 5-10)
OPERATION ADDRESS ADV/
USED CE# CE2# CE2 ZZ LD# R/W# BWx OE# CKE# CLK DQ NOTES
DESELECT Cycle None H X X L L X X X L LÆH High-Z
DESELECT Cycle None X H X L L X X X L LÆH High-Z
DESELECT Cycle None X X L L L X X X L LÆH High-Z
CONTINUE DESELECT Cycle None X X X L H X X X L LÆH High-Z 1
READ Cycle External L L H L L H X L L LÆHQ
(Begin Burst)
READ Cycle Next X X X L H X X L L LÆH Q 1, 11
(Continue Burst)
NOP/DUMMY READ External L L H L L H X H L LÆH High-Z 2
(Begin Burst)
DUMMY READ Nex t X X X L H X X H L LÆH High-Z 1, 2,
(Continue Burst) 11
WRITE Cycle External L L H L L L L X L LÆHD 3
(Begin Burst)
WRITE Cycle Next X X X L H X L X L LÆHD 1, 3,
(Continue Burst) 11
NOP/WRITE ABORT None L L H L L L H X L LÆH High-Z 2, 3
(Begin Burst)
WRITE ABORT Next X X X L H X H X L LÆH High-Z 1, 2,
(Continue Burst) 3, 11
IGNORE CLOCK EDGE Current X X X L X X X X H LÆH4
(Stall)
SNOOZE MODE None X X X H X X X X X X High-Z
NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle
is executed first.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.
A WRITE ABORT means a WRITE command is given, but no operation is performed.
3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off
the output drivers during a WRITE cycle. Some users may use OE# when the bus turn-on and turn-off times do not
meet their requirements.
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it
occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE
CLOCK EDGE cycle.
5. X means Dont Care. H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,
BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.
6. BWa# enables WRITEs to Byte a (DQas); BWb# enables WRITEs to Byte b (DQbs); BWc# enables WRITEs to
Byte c (DQcs); BWd# enables WRITEs to Byte d (DQds).
7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
19
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply
Relative to VSS ............................... -0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS ...................................-0.5V to VDD
VIN ........................................... -0.5V to VDDQ + 0.5V
Storage Temperature (plastic) ............-55°C to +150°C
Junction Temperature**................................... +150°C
Short Circuit Output Current...........................100mA
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Junction temperature depends upon package type,
cycle time, loading, ambient temperature and airflow.
See Micron Technical Note TN-05-14 for more
information.
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C TA +70°C; VDD, V DDQ = 3.3V ±0.165 unless otherwise noted)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage VIH 2.0 VDD + 0.3 V 1, 2
Input High (Logic 1) Voltage DQ pins VIH 2.0 VDD + 0.3 V 1, 2
Input Low (Logic 0) Voltage VIL -0.3 0.8 V 1, 2
Input Leakage Current 0V VIN VDD ILI-1.0 1.0 µA 3
Output Leakage Current Output(s) disabled, ILO-1.0 1.0 µA
0V VIN VDD
Output High Voltage IOH = -4.0mA VOH 2.4 V 1, 4
Output Low Voltage IOL = 8.0mA VOL 0.4 V 1, 4
Supply Voltage VDD 3.135 3.465 V 1
Isolated Output Buffer Supply VDDQ 3.135 VDD V 1, 5
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot: VIH +4.6V for t tKHKH/2 for I 20mA
Undershoot: VIL -0.7V for t tKHKH/2 for I 20mA
Power-up: VIH +3.465V and VDD 3.135V for t 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O
curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply for 3.3V I/O
operation.
20
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C TA +70°C; VDD = +3.3V ±0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Input High (Logic 1) Voltage Data bus (DQx) VIHQ 1.7 VDDQ + 0.3 V 1, 2
Inputs VIH 1.7 VDD + 0.3 V 1, 2
Input Low (Logic 0) Voltage VIL -0.3 0.7 V 1, 2
Input Leakage Current 0V VIN VDD ILI-1.0 1.0 µA 3
Output Leakage Current Output(s) disabled, ILO-1.0 1.0 µA
0V VIN VDDQ (DQx)
Output High Voltage IOH = -2.0mA VOH 1.7 V1
IOH = -1.0mA VOH 2.0 V1
Output Low Voltage IOL = 2.0mA VOL 0.7 V 1
IOL = 1.0mA VOL 0.4 V 1
Supply Voltage VDD 3.135 3.6 V 1
Isolated Output Buffer Supply VDDQ 2.375 2.9 V 1
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot: VIH +4.6V for t tKHKH/2 for I 20mA
Undershoot: VIL -0.7V for t tKHKH/2 for I 20mA
Power-up: VIH +3.465V and VDD 3.135V for t 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. This parameter is sampled.
TQFP CAPACITANCE
DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES
Control Input Capacitance TA = 25°C; f = 1 MHz C I34pF4
Input/Output Capacitance (DQ) VDD = 3.3V CO45pF4
Address Capacitance CA3 3.5 pF 4
Clock Capacitance CCK 3 3.5 pF 4
FBGA CAPACITANCE
DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES
Address/Control Input Capacitance CI2.5 3.5 pF 4
Output Capacitance (Q) TA = 25°C; f = 1 MHz CO45pF4
Clock Capacitance CCK 2.5 3.5 pF 4
BGA CAPACITANCE
DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES
Address/Control Input Capacitance TA = 25°C; f = 1 MHz C I47pF4
Input/Output Capacitance (DQ) VDD = 3.3V CO4.5 5.5 pF 4
Address Capacitance CA47pF4
Clock Capacitance CCK 4.5 5.5 pF 4
21
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C TA +70°C; VDD = +3.3V ±0.165V unless otherwise noted)
DESCRIPTION CONDITIONS SYMBOL TYP -6 -7.5 -10 UNITS NOTES
Power Supply Device selected; All inputs VIL
Current: or VIH; Cycle time tKC (MIN); IDD 200 500 400 300 mA 2, 3, 4
Operating VDD = MAX; Outputs open
Power Supply Device selected; VDD = MAX;
Current: Idle CKE# VIH;IDD110 25 25 20 mA 2, 3, 4
All inputs VSS + 0.2 or VDD - 0.2;
Cycle time tKC (MIN)
CMOS Standby Device deselected; VDD = MAX;
All inputs VSS + 0.2 or VDD - 0.2; ISB20.5 10 10 10 mA 3, 4
All inputs static; CLK frequency = 0
TTL Standby Device deselected; VDD = MAX;
All inputs VIL or VIH;ISB36 252525mA3, 4
All inputs static; CLK frequency = 0
Clock Running Device deselected; VDD = MAX;
ADV/LD# VIH; All inputs VSS + 0.2 ISB445 120 75 60 mA 3, 4
or VDD - 0.2; Cycle time tKC (MIN)
SNOOZE MODE ZZ VIH ISB2Z0.5 10 10 10 mA 4
MAX
NOTE: 1. VDDQ = +3.3V ±0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O
configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
3. Device deselected means device is in a deselected cycle as defined in the truth table. Device selected means device
is active (not in deselected mode).
4. Typical values are measured at 3.3V, 25°C and 10ns cycle time.
5. This parameter is sampled.
6. Preliminary package data.
22
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
NOTE: 1. VDDQ = +3.3V ±0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O
configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
3. Device deselected means device is in a deselected cycle as defined in the truth table. Device selected means device
is active (not in deselected mode).
4. Typical values are measured at 3.3V, 25°C and 10ns cycle time.
5. This parameter is sampled.
6. Preliminary package data.
TQFP THERMAL RESISTANCE
DESCRIPTION CONDITIONS SYMBOL TYP UNITS NOTES
Thermal Resistance Test conditions follow standard test methods θ
JA
46 °C/W 5
(Junction to Ambient) and procedures for measuring thermal
Thermal Resistance impedance, per EIA/JESD51. θ
JC
2.8 °C/W 5
(Junction to Top of Case)
FBGA THERMAL RESISTANCE
DESCRIPTION CONDITIONS SYMBOL TYP UNITS NOTES
Junction to Ambient Test conditions follow standard test methods θJA 40 °C/W 5, 6
(Airflow of 1m/s) and procedures for measuring thermal
Junction to Case (Top) impedance, per EIA/JESD51. θJC 9°C/W 5, 6
Junction to Pins θJB 17 °C/W 5, 6
(Bottom)
TQFP THERMAL RESISTANCE
DESCRIPTION CONDITIONS SYMBOL TYP UNITS NOTES
Thermal Resistance Test conditions follow standard test methods θJA 46 °C/W 5
(Junction to Ambient) and procedures for measuring thermal
Thermal Resistance impedance, per EIA/JESD51. θJC 2.8 °C/W 5
(Junction to Top of Case)
BGA THERMAL RESISTANCE
DESCRIPTION CONDITIONS SYMBOL TYP UNITS NOTES
Junction to Ambient Test conditions follow standard test methods θJA 40 °C/W 5
(Airflow of 1m/s) and procedures for measuring thermal
Junction to Case (Top) impedance, per EIA/JESD51. θJC 9°C/W 5
Junction to Pins θJB 17 °C/W 5
(Bottom)
23
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
NOTE: 1. This parameter is sampled.
2. Measured as HIGH above VIH and LOW below VIL.
3. Refer to Technical Note TN-55-01, Designing with ZBT SRAMs, for a more thorough discussion on these parameters.
4. This parameter is sampled.
5. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
6. Transition is measured ±200mV from steady state voltage.
7. OE# can be considered a Dont Care during WRITEs; however, controlling OE# can help fine-tune a system for
turnaround timing.
8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times
with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each
rising edge of CLK when ADV/LD# is LOW to remain enabled.
9. Test conditions as specified with output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V ±0.165V) and Figure 3
for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V).
10. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
AC ELECTRICAL CHARACTERISTICS
(Notes 6, 8, 9) (0°C TA +70°C; VDD = +3.3V ±0.165V; ZBT mode)
-6 -7.5 -10
DESCRIPTION SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
Clock
Clock cycle time tKHKH 6.0 7.5 10 ns
Clock frequency fKF 166 133 100 MHz
Clock HIGH time tKHKL 1.7 2.0 3.2 ns 1
Clock LOW time tKLKH 1.7 2.0 3.2 ns 1
Output Times
Clock to output valid tKHQV 3.5 4.2 5.0 ns
Clock to output invalid tKHQX 1.5 1.5 1.5 ns 2
Clock to output in Low-Z tKHQX1 1.5 1.5 1.5 ns 2, 3, 4, 5
Clock to output in High-Z tKHQZ 1.5 3.5 1. 5 3.5 1.5 3.5 ns 2, 3, 4, 5
OE# to output valid tGLQV 3.5 4.2 5.0 ns 6
OE# to output in Low-Z tGLQX 0 0 0 ns 2, 3, 4, 5
OE# to output in High-Z tGHQZ 3.5 4.2 5.0 ns 2, 3, 4, 5
Setup Times
Address tAVKH 1.5 1.7 2.0 ns 7
Clock enable (CKE#) tEVKH 1.5 1.7 2.0 ns 7
Control signals tCVKH 1.5 1.7 2.0 ns 7
Data-in tDVKH 1.5 1.7 2.0 ns 7
Hold Times
Address tKHAX 0.5 0.5 0.5 ns 7
Clock enable (CKE#) tKHEX 0.5 0.5 0.5 ns 7
Control signals tKHCX 0.5 0.5 0.5 ns 7
Data-in tKHDX 0.5 0.5 0.5 ns 7
24
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
Q50
V = 1.5V
Z = 50
O
T
Figure 1
Q351
317
5pF
+3.3V
Figure 2
3.3V I/O AC TEST CONDITIONS
Input pulse levels ...................................VSS to 3.3V
Input rise and fall times..................................... 1ns
Input timing reference levels .......................... 1.5V
Output reference levels ................................... 1.5V
Output load ............................. See Figures 1 and 2
LOAD DERATING CURVES
The Micron 256K x 18, 128K x 32, and 128K x 36 ZBT
SRAM timing is dependent upon the capacitive loading
on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
Q50
V = 1.25V
Z = 50
O
T
Figure 3
Q
225
225
5pF
+2.5V
Figure 4
2.5V I/O AC TEST CONDITIONS
Input pulse levels ...................................VSS to 2.5V
Input rise and fall times..................................... 1ns
Input timing reference levels ........................ 1.25V
Output reference levels ................................. 1.25V
Output load ............................. See Figures 3 and 4
3.3V I/O Output Load Equivalents 2.5V I/O Output Load Equivalents
25
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down”
mode in which the device is deselected and current is
reduced to ISB2Z. The duration of SNOOZE MODE is
dictated by the length of time the ZZ pin is in a HIGH
state. After the device enters SNOOZE MODE, all inputs
except ZZ become disabled and all outputs go to
High-Z.
The ZZ pin is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE. When
the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed
after the time tZZI is met. Any READ or WRITE opera-
tion pending when the device enters SNOOZE MODE is
not guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pend-
ing operations are completed. Similarly, when exiting
SNOOZE MODE during tRZZ, only a DESELECT or
READ cycle should be given.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES
Current during SNOOZE MODE ZZ VIH ISB2Z 10 mA
Current during SNOOZE MODE ZZ VIH ISB2ZP 1mA
(P Version)
ZZ active to input ignored tZZ 0 2(tKHKH) ns 1
ZZ inactive to input sampled tRZZ 0 2(tKHKH) ns 1
ZZ active to snooze current tZZI 2(tKHKH) ns 1
ZZ inactive to exit snooze current tRZZI 0 ns 1
SNOOZE MODE WAVEFORM
tZZ
ISUPPLY
CLK
ZZ
tRZZ
ALL INPUTS
(except ZZ)
DONT CARE
IISB2Z
tZZI
tRZZI
Outputs (Q) High-Z
DESELECT or READ Only
NOTE: 1. This parameter is sampled.
26
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
READ/WRITE TIMING
WRITE
D(A1)
123456789
CLK
tKHKH
t
KLKH
t
KHKL
10
CE#
t
KHCX
t
CVKH
R/W#
CKE#
t
KHEX
t
EVKH
BWx#
ADV/LD#
t
KHAX
t
AVKH
ADDRESS A1 A2 A3 A4 A5 A6 A7
t
KHDX
t
DVKH
DQ
COMMAND
t
KHQX1
D(A1) D(A2) D(A5)Q(A4)Q(A3)
D(A2+1)
t
KHQX
t
KHQZ
t
KHQV
WRITE
D(A2) BURST
WRITE
D(A2+1)
READ
Q(A3) READ
Q(A4) BURST
READ
Q(A4+1)
WRITE
D(A5) READ
Q(A6) WRITE
D(A7) DESELECT
OE#
t
GLQV
t
GLQX
t
GHQZ
t
KHQX
DONT CARE UNDEFINED
Q(A6)
Q(A4+1)
NOTE: 1. For this waveform, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
-6 -7.5 -10
SYM MIN MAX MIN MAX MIN MAX UNITS
tGHQZ 3.5 4.2 5.0 ns
tAVKH 1.5 1.7 2.0 ns
tEVKH 1.5 1.7 2.0 ns
tCVKH 1.5 1.7 2.0 ns
tDVKH 1.5 1.7 2.0 ns
tKHAX 0.5 0.5 0.5 ns
tKHEX 0.5 0.5 0.5 ns
tKHCX 0.5 0.5 0.5 ns
tKHDX 0.5 0.5 0.5 ns
READ/WRITE TIMING PARAMETERS
-6 -7.5 -10
SYM MIN MAX MIN MAX MIN MAX UNITS
tKHKH 6.0 7.5 10 ns
fKF 166 133 100 MHz
tKHKL 1.7 2.0 3.2 ns
tKLKH 1.7 2.0 3.2 ns
tKHQV 3.5 4.2 5.0 ns
tKHQX 1.5 1.5 1.5 ns
tKHQX1 1.5 1.5 1.5 ns
tKHQZ 1.5 3.5 1.5 3.5 1.5 3.5 ns
tGLQV 3.5 4.2 5.0 ns
tGLQX 0 0 0 ns
27
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
NOP, STALL, AND DESELECT CYCLES
READ
Q(A3)
45678910
CLK
CE#
R/W#
CKE#
BWx#
ADV/LD#
ADDRESS A3 A4 A5
D(A4)
DQ
COMMAND
A1
Q(A5)
WRITE
D(A4) STALLWRITE
D(A1)
123
READ
Q(A2) STALL NOP READ
Q(A5) DESELECT CONTINUE
DESELECT
DONT CARE UNDEFINED
t
KHQZ
t
KHQX
A2
D(A1) Q(A2) Q(A3)
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a pause. A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
NOP, STALL, AND DESELECT TIMING PARAMETERS
-6 -7.5 -10
SYM MIN MAX MIN MAX MIN MAX UNITS
tKHQX 1.5 1.5 1.5 ns
tKHQZ 1.5 3.5 1.5 3.5 1.5 3.5 ns
28
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
14.00 ±0.10
20.10 ±0.10
0.62
22.10 +0.10
-0.15
16.00 +0.20
-0.05
PIN #1 ID
0.65
1.50 ±0.10
0.25
0.60 ±0.15 1.40 ±0.05
0.32 +0.06
-0.10
0.15 +0.03
-0.02
0.10 +0.10
-0.05
DETAIL A
DETAIL A
1.00 (TYP)
GAGE PLANE
0.10
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
29
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
165-PIN FBGA
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
10.00
14.00
15.00 ±0.10
1.00
TYP
1.00
TYP
5.00 ±0.05
13.00 ±0.10
PIN A1 ID
PIN A1 ID
BALL A1
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
6.50 ±0.05
7.00 ±0.05
7.50 ±0.05
1.20 MAX
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: Ø .33mm
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40
SEATING PLANE
0.85 ±0.075 0.12 C
C
165X Ø 0.45
BALL A11
30
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc., and Motorola, Inc.
Ø
7.62
20.32
19.94 ±0.10
11.94 ±0.10
1.27 (TYP)
1.27 (TYP)
0.60 ±0.10
2.40 MAX
0.90 ±0.10
14.00 ±0.10
22.00 ±0.20
A1 CORNER
A1 CORNER
(dimension applies to a
noncollapsed solder ball)
Substrate material:
BT resin laminate
0.15
SEATING PLANE
0.75 ±0.15
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Solder ball land pad is 0.6mm.
119-PIN BGA
31
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT55L256L18P1_D.p65 Rev. 10/01 ©2001, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
REVISION HISTORY
Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................June 7/01
Added Industrial Temperature note and references, Rev. 3/01, FINAL.....................................................March 6/01
Added 119-pin PBGA package, Rev. 1/01, FINAL ................................................................................. January 10/01
Removed FBGA Part Marking Guide, REV 8/00-A, FINAL .....................................................................August 22/00
Changed FBGA capacitance values, REV 8/00, FINAL..............................................................................August 7/00
CI; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF
CO; TYP 4pF from 6pF; MAX. 5pF from 7pF
CCK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF
Added FBGA Part Marking Guide, Rev. 7/00, Preliminary .......................................................................... July 13/00
Removed 119-pin PBGA package and references
Added 165-pin FBGA package, Rev. 6/00, Preliminary ............................................................................... May 23/00
Removed all “Smart ZBT” references