MAX533BEEE+T - Maxim Integrated Products, Inc.

_______________General Description

The MAX533 serial-input, voltage-output, 8-bit quad

digital-to-analog converter (DAC) operates from a sin-

gle +2.7V to +3.6V supply. Internal precision buffers

swing rail to rail, and the reference input range includes

both ground and the positive rail. The MAX533 features

a 1µA shutdown mode.

The serial interface is double buffered: a 12-bit input

shift register is followed by four 8-bit buffer registers

and four 8-bit DAC registers. The 12-bit serial word

consists of eight data bits and four control bits (for DAC

selection and special programming commands). Both

the input and DAC registers can be updated indepen-

dently or simultaneously with a single software com-

mand. Two additional asynchronous control pins, LDAC

and CLR, provide simultaneous updating or clearing of

the input and DAC registers.

The interface is compatible with SPI™, QSPI™ (CPOL =

CPHA = 0 or CPOL = CPHA = 1), and Microwire™. A

buffered data output allows daisy chaining of serial

devices.

In addition to 16-pin DIP and CERDIP packages, the

MAX533 is available in a 16-pin QSOP that occupies

the same area as an 8-pin SO.

________________________Applications

Digital Gain and Offset Adjustments

Programmable Attenuators

Programmable Current Sources

Portable Instruments

____________________________Features

♦+2.7V to +3.6V Single-Supply Operation

♦Ultra-Low Supply Current:

0.7mA while Operating

1µA in Shutdown Mode

♦Ultra-Small 16-Pin QSOP Package

♦Ground to VDD Reference Input Range

♦Output Buffer Amplifiers Swing Rail to Rail

♦10MHz Serial Interface, Compatible with SPI, QSPI

(CPOL = CPHA = 0 or CPOL = CPHA = 1), and

Microwire

♦Double-Buffered Registers for Synchronous

Updating

♦Serial Data Output for Daisy Chaining

♦Power-On Reset Clears Serial Interface and Sets

All Registers to Zero

♦Software Shutdown

♦Software-Programmable Logic Output

♦Asynchronous Hardware Clear Resets All Internal

Registers to Zero

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

________________________________________________________________

Maxim Integrated Products

OUTC

OUTD

AGND

VDD

DGND

DIN

SCLK

OUTB

OUTA

REF

UPO

PDE

LDAC

CLR

DOUT

TOP VIEW

MAX533

DIP/QSOP

__________________Pin Configuration

19-1080; Rev 0; 6/96

PART

MAX533ACPE

MAX533BCPE

MAX533ACEE 0°C to +70°C

0°C to +70°C

TEMP. RANGE PIN-PACKAGE

16 Plastic DIP

16 QSOP

______________Ordering Information

*Dice are tested at T

= +25°C.

**Contact factory for availability and processing to MIL-STD-883.

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

Functional Diagram appears at end of data sheet.

For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800

MAX533BCEE 0°C to +70°C 16 QSOP

MAX533BC/D 0°C to +70°C Dice*

MAX533AEPE -40°C to +85°C 16 Plastic DIP

MAX533BEPE -40°C to +85°C 16 Plastic DIP

MAX533AEEE -40°C to +85°C 16 QSOP

MAX533BEEE -40°C to +85°C 16 QSOP

MAX533AMJE -55°C to +125°C 16 CERDIP**

MAX533BMJE -55°C to +125°C 16 CERDIP**

INL

(LSB)

±1

±2

±1

±2

±1

±2

±1

±2

±1

±2

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

2 _______________________________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

(VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at VDD = +3V and TA= +25°C.)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

VDD to DGND ..............................................................-0.3V, +6V

VDD to AGND...............................................................-0.3V, +6V

Digital Input Voltage to DGND ....................................-0.3V, +6V

Digital Output Voltage to DGND....................-0.3V, (VDD + 0.3V)

AGND to DGND..................................................................±0.3V

REF................................................................-0.3V, (VDD + 0.3V)

OUT_ ...........................................................................-0.3V, VDD

Maximum Current into Any Pin............................................50mA

Continuous Power Dissipation (TA= +70°C)

Plastic DIP (derate 10.53mW/°C above +70°C) .........842mW

QSOP (derate 8.3mW/°C above +70°C).....................667mW

CERDIP (derate 10.00mW/°C above +70°C)..............800mW

Operating Temperature Ranges

MAX533 _ C_ E..................................................0°C to +70°C

MAX533 _ E_ E ...............................................-40°C to +85°C

MAX533 _ MJE .............................................-55°C to +125°C

Storage Temperature Range.............................-65°C to +150°C

Lead Temperature (soldering, 10sec).............................+300°C

Code = FF hex, RLfrom 10kΩto ∞

RL= open

(Note 3)

Code = FF hex

(Note 2)

Code = FF hex, VDD = 2.7V to 3.6V

Code = 00 hex

Guaranteed monotonic (all codes)

Code = 00 hex

Code = 00 hex, VDD = 2.7V to 3.6V

CONDITIONS

LSB0.25Load Regulation V0V

REF

Output Voltage Range

DAC OUTPUTS dB-70AC Feedthrough dB-60Channel-to-Channel Isolation pF10Input Capacitance kΩ322 460 598Input Resistance V0V

Input Voltage Range

±1 Bits8Resolution

REFERENCE INPUTS

µV/°C±10

Full-Scale Temperature

Coefficient

LSB1

Full-Scale Error Supply

Rejection

µV/°C±10

Zero-Code Temperature

Coefficient

±2 LSB±1.0DNLDifferential Nonlinearity (Note 1) mV±20ZCEZero-Code Error

LSB1

Zero-Code-Error Supply

Rejection

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX533B LSBINL

Integral Nonlinearity

(Note 1)

Code = FF hex mV±30Full-Scale Error

STATIC ACCURACY

MAX533A

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

_______________________________________________________________________________________ 3

ELECTRICAL CHARACTERISTICS (continued)

(VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, RL= 10kΩ, CL= 100pF, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at VDD = +3V and TA= +25°C.)

MAX533M

MAX533C/E

VREF = 0.5Vp-p, 3dB bandwidth

To 1/2LSB, from code 00 to code FF hex

(Note 5)

CODE = FF hex

VREF = 2.5Vp-p at 10kHz

VREF = 2.5Vp-p at 1kHz, VDD = 3V,

code = FF hex

ISINK = 1.6mA

VIN = 0V or VDD

(Note 4)

Code 80 hex to code 7F hex

ISOURCE = TBDmA

VREF = 0V, code 00 to code FF hex (Note 6)

CONDITIONS

µA110Shutdown Current

0.68 1.5

IDD

Supply Current 0.68 1.3 V2.7 3.6VDD

Power-Supply Voltage

POWER SUPPLIES µVRMS

60Wideband Amplifier Noise kHz380Multiplying Bandwidth -62

SINAD

Signal-to-Noise Plus

Distortion Ratio dB

-70

nV-s50Digital-to-Analog Glitch Impulse

nV-s5

Digital Feedthrough and

Crosstalk

V0.3VDD

VIL

Input Low Voltage V0.7VDD

VIH

DIGITAL INPUTS

Input High Voltage

µs6Output Settling Time

V/µs0.6Voltage-Output Slew Rate

DYNAMIC PERFORMANCE V0.4VOL

Output Low Voltage

µA±1.0IIN

Input Current pF10CIN

Input Capacitance

DIGITAL OUTPUTS VVDD - 0.5VOH

Output High Voltage

UNITSMIN TYP MAXSYMBOLPARAMETER

TIMING CHARACTERISTICS

(VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, CDOUT = 100pF, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at VDD = +3V and TA= +25°C.)

MAX533C/E

MAX533M

MAX533C/E

40 20 ns

50 25

tLDAC

LDAC Pulse Width Low

MAX533C/E

MAX533M

MAX533C/E

40 20

CONDITIONS

50 25

tCLW

CLR Pulse Width Low

MAX533M 40 ns

tCLL

CS Rise to LDAC Fall Setup

Time (Note 7)

50 µs

tVDCS

VDD Rise to CS Fall Setup Time

(Note 4)

UNITSMIN TYP MAXSYMBOLPARAMETER

MAX533C/E

MAX533M 90 ns

100

tCSW

CS Pulse Width High

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

4 _______________________________________________________________________________________

TIMING CHARACTERISTICS (continued)

(VDD = +2.7V to +3.6V, VREF = 2.5V, AGND = DGND = 0V, CDOUT = 100pF, TA= TMIN to TMAX, unless otherwise noted.

Typical values are at VDD = +3V and TA= +25°C.)

Note 1: INL and DNL are measured with RLreferenced to ground. Nonlinearity is measured from the first code that is greater than

or equal to the maximum offset specification to code FF hex (full scale). See

DAC Linearity and Voltage Offset

section.

Note 2: VREF = 2.5Vp-p, 10kHz. Channel-to-channel isolation is measured by setting one DAC’s code to FF hex and setting all

other DAC’s codes to 00 hex.

Note 3: VREF = 2.5Vp-p, 10kHz. DAC code = 00 hex.

Note 4: Guaranteed by design, not production tested.

Note 5: Output settling time is measured from the 50% point of the rising edge of CS to 1/2LSB of VOUT’s final value.

Note 6: Digital crosstalk is defined as the glitch energy at any DAC output in response to a full-scale step change on any other

DAC.

Note 7: If LDAC is activated prior to CS’s rising edge, it must stay low for tLDAC or longer after CS goes high.

Note 8: When DOUT is not used. If DOUT is used, fCLK max is 4MHz, due to the SCLK to DOUT propagation delay.

Note 9: Serial data clocked out at SCLK’s rising edge (measured from 50% of the clock edge to 20% or 80% of VDD).

Note 10: Serial data clocked out at SCLK’s falling edge (measured from 50% of the clock edge to 20% or 80% of VDD).

CS Rise to SCLK Rise Setup

Time tCS1 50 ns

SCLK Rise to CS Fall Delay tCS0 50 ns

MAX533M

MAX533M 40

MAX533C/E

SCLK Fall to DOUT Valid

Propagation Delay (Note 10) tDO2 250 ns

MAX533M 210MAX533C/E

SCLK Rise to DOUT Valid

Propagation Delay (Note 9) tDO1 230 ns

MAX533M 200MAX533C/E

CS Fall to SCLK Rise Setup

Time tCSS 50

SCLK Pulse Width Low tCL 50 ns

MAX533C/E

MAX533M

MAX533C/E

MAX533M

SCLK Pulse Width High tCH 50 ns

MAX533C/E

MAX533M

PARAMETER SYMBOL MIN TYP MAX UNITS

SERIAL-INTERFACE TIMING 10

SCLK Clock Frequency (Note 8) fCLK 8.3 MHz

SCLK Rise to CS Rise Hold Time tCSH 0 ns

DIN to SCLK Rise to Setup Time tDS 50

DIN to SCLK Rise to Hold Time tDH 0 ns

CONDITIONS

MAX533C/E

MAX533M

MAX533C/E

MAX533M

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

_______________________________________________________________________________________

DAC ZERO-CODE OUTPUT VOLTAGE vs.

OUTPUT SINK CURRENT

MAX533-TOC1

DAC OUTPUT SINK CURRENT (mA)

DAC ZERO-CODE OUTPUT VOLTAGE (V)

0.25

0.50

0.75



1.00

1.25

1.50

12345678

DD = VREF = 3.0V

VDD = VREF = 5.0V

DAC CODE = 00 HEX

LOAD TO VDD

2.0 0

DAC FULL-SCALE OUTPUT VOLTAGE vs.

OUTPUT SOURCE CURRENT

MAX533-TOC2

DAC OUTPUT SOURCE CODE (mA)

DAC FULL-SCALE OUTPUT VOLTAGE (V)

2.5

3.0

3.5



4.0

4.5

5.0

246810 12

VDD = VREF = 3.0V

VDD = VREF = 5.0V

DAC CODE = FF HEX

LOAD TO GND

0-55

SUPPLY CURRENT vs.

TEMPERATURE

MAX533-TOC3

TEMPERATURE (°C)

SUPPLY CURRENT (µA)



200

400



600

800

1000

-35 -15 5 25 45 65 85 105 125

VDD = +3.0V

VREF = +2.5V

VDD = +5.0V

VREF = +4.5V

DAC CODE = 00 HEX

DAC CODE = FF HEX

0-55

SHUTDOWN SUPPLY CURRENT vs.

TEMPERATURE

MAX533-TOC4

TEMPERATURE (°C)

SHUTDOWN SUPPLY CURRENT (µA)



-35 -15 5 25 45 65 85 105 125

VDD = +3.0V



VDD = +5.0V



-70 0

THD + NOISE AT DAC OUTPUT vs.

REFERENCE AMPLITUDE

MAX533-TOC7

REFERENCE AMPLITUDE (Vp-p)

THD + NOISE (dB)



-50

-60



-40

-30

0.5 1.0 1.5 2.0

VDD = +3.0V

VREF = SINE WAVE

CENTERED AT 1.2V

DAC C0DE = FF HEX

80kHz LOWPASS FILTER

VREF = 20kHz

VREF = 1kHz

SUPPLY CURRENT vs.

REFERENCE VOLTAGE (VDD = +3.0V)

REFERENCE VOLTAGE (V)

SUPPLY CURRENT (µA)



200

400



600

800

1000

0.5 1.0 1.5 2.0 2.5 3.0

ALL DAC CODES = 00 HEX

ALL DAC CODES = FF HEX

MAX533-TOC5

SUPPLY CURRENT vs.

REFERENCE VOLTAGE (VDD = +5.0V)

REFERENCE VOLTAGE (V)

SUPPLY CURRENT (µA)



200

400



600

800

1000

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

ALL DAC CODES = 00 HEX

ALL DAC CODES = FF HEX

MAX533-TOC6

-20

-70 1 0.1 101 100

THD + NOISE AT DAC OUTPUT vs.

REFERENCE FREQUENCY

-60

MAX533-TOC8

FREQUENCY (kHz)

THD + NOISE (dB)

-50

-40

-30

VDD = +3.0V

VREF = SINE WAVE

CENTERED AT 1.2V

DAC CODE = FF HEX

500kHz LOWPASS FILTER

VREF = 2Vp-p

VREF = 1VP-P

VREF = 0.5Vp-p

__________________________________________Typical Operating Characteristics

(VDD = +3V, TA = +25°C, unless otherwise noted.)

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

6 _______________________________________________________________________________________

____________________________Typical Operating Characteristics (continued)

(VDD = +3V, TA = +25°C, unless otherwise noted.)

WORST-CASE 1LSB DIGITAL

STEP CHANGE (NEGATIVE)

MAX533-TOC10

2µs/div

CS

2V/div

OUTA

50mV/div

VDD = 3.0V

VREF = 2.5V



DAC CODE = 80 TO 7F hex

NO LOAD

WORST-CASE 1LSB DIGITAL

STEP CHANGE (POSITIVE)MAX533-TOC11

2µs/div

CS

2V/div

OUTA

50mV/div

VDD = 3.0V

VREF = 2.5V DAC CODE = 7F TO 80 hex

NO LOAD

-80 0.01 0.1 10



REFERENCE FEEDTHROUGH vs. FREQUENCY

-60

-70

-20

-30

-40

-50

MAX533-TOC12

FREQUENCY (MHz)

RELATIVE OUTPUT (dB)

VDD = +3.0V

VREF = 3Vp-p SINE WAVE

DAC CODE = 00 HEX



CLOCK FEEDTHROUGH MAX533-TOC13

2µs/div

SCLK

2V/div

OUTA

10mV/div

SCLK = 333kHz

SCLK tR = tF = 25ns

VDD = 3.0V

VREF = 2.5V

DAC CODE = 80 hex

NO LOAD



POSITIVE SETTLING TIMEMAX533-TOC14

5µs/div

CS

2V/div

OUTA

1V/div

VDD = 3.0V

VREF = 2.5V



DAC CODE = 00 TO FF hex

NO LOAD

-30 0.01 0.1 10



REFERENCE INPUT FREQUENCY RESPONSE

-20

-25

-5

-10

-15

MAX533-TOC9

FREQUENCY (MHz)

RELATIVE OUTPUT (dB)

VREF = 0.1Vp-p SINE WAVE

CENTERED AT 2.5V

DAC CODE = FF HEX

VDD = +3.0V



MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

_______________________________________________________________________________________

______________________________________________________________Pin Description

____________________________Typical Operating Characteristics (continued)

(VDD = +3V, TA = +25°C, unless otherwise noted.)

POSITIVE SETTLING TIMEMAX533-TOC15

5µs/div

CS

2V/div

OUTA

1V/div

VDD = 3.0V

VREF = 2.5V



DAC CODE = 01 TO FF hex

NO LOAD

NEGATIVE SETTLING TIME

MAX533-TOC16

5µs/div

CS

2V/div

OUTA

1V/div

VDD = 3.0V

VREF = 2.5V



DAC CODE = FF TO 00 hex

NO LOAD

DAC B Voltage OutputOUTB1

FUNCTIONNAME

DAC A Voltage OutputOUTA2

Software-Programmable Logic OutputUPO4 Reference-Voltage InputREF3

Load DAC Input (active low). Driving this asynchronous input low (level sensitive) transfers the contents

of each input latch to its respective DAC latch.

LDAC

Serial Data Output. Sinks and sources current. Data at DOUT can be clocked out on the rising or falling

edge of SCLK (Table 1).

DOUT8

Clear DAC Input (active low). Driving CLR low asynchronously clears the input and DAC registers, and

sets all DAC outputs to zero.

CLR

Power-Down Enable. Must be high to enter software shutdown mode.PDE5

Serial Clock Input. Data is clocked in on the rising edge and clocked out on the falling (default) or rising

edge (A0 = A1 = 1, see Table 1).

SCLK10

Digital GroundDGND12 Serial Data Input. Data is clocked in on the rising edge of SCLK.DIN11

Analog GroundAGND14

DAC C Voltage OutputOUTC16 DAC D Voltage OutputOUTD15

Power Supply, +2.7V to +3.6VVDD

Chip-Select Input (active low). Data is shifted in and out when CS is low. Programming commands are

executed when CS returns high.

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

8 _______________________________________________________________________________________

• • •

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

DACA

DATA FROM PREVIOUS DATA INPUT DATA FROM PREVIOUS DATA INPUT

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

MSB LSB

DACD

A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 C1 C0 D7

A0 C1 C0 D7

D6 D5 D4 D3 D2 D1 D0 A1

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 A1 D6 D5 D4 D3 D2 D1 D0 A1

DOUT

MODE 0

(DEFAULT)

DOUT

MODE 1

DIN

SCLK

• • •

INSTRUCTION

EXECUTED

Figure 1. 3-Wire Interface Timing

tCS0 tCL

tDH

tDS

tCP tCSH

tD02

tCLL

tD01

tCS1

tCH

tCSS

tCSW

SCLK

DIN

DOUT

LDAC

tLDAC

Figure 2. Detailed Serial-Interface Timing Diagram

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

_______________________________________________________________________________________ 9

_______________Detailed Description

Serial Interface

At power-on, the serial interface and all digital-to-

analog converters (DACs) are cleared and set to code

zero. The serial data output (DOUT) is set to transition

on SCLK's falling edge.

The MAX533 communicates with microprocessors

through a synchronous, full-duplex, 3-wire interface

(Figure 1). Data is sent MSB first and can be transmit-

ted in one 4-bit and one 8-bit (byte) packet or in one

12-bit word. If a 16-bit word is used, the first four bits

are ignored. A 4-wire interface adds a line for LDAC

and allows asynchronous updating. The serial clock

(SCLK) synchronizes the data transfer. Data is transmit-

ted and received simultaneously.

Figure 2 shows the detailed serial-interface timing.

Please note that the clock should be low if it is stopped

between updates. DOUT does not go into a high-

impedance state if the clock idles or CS is high.

Serial data is clocked into the data registers in MSB-first

format, with the address and configuration information

preceding the actual DAC data. Data is clocked in on

SCLK’s rising edge while CS is low. Data at DOUT is

clocked out 12 clock cycles later, either at SCLK’s falling

edge (default or mode 0) or rising edge (mode 1).

Chip select (CS) must be low to enable the DAC. If CS

is high, the interface is disabled and DOUT remains

unchanged. CS must go low at least 40ns before the

first rising edge of the clock pulse to properly clock in

the first bit. With CS low, data is clocked into the

MAX533’s internal shift register on the rising edge of

the external serial clock. Always clock in the full 12 bits

because each time CS goes high the bits currently in

the input shift register are interpreted as a command.

SCLK can be driven at rates up to 10MHz.

Serial Input Data Format and Control Codes

The 12-bit serial input format shown in Figure 3 com-

prises two DAC address bits (A1, A0), two control bits

(C1, C0), and eight bits of data (D7...D0).

The 4-bit address/control code configures the DAC as

shown in Table 1.

Load Input Register, DAC Registers Unchanged

(Single Update Operation)

When performing a single update operation, A1 and A0

select the respective input register. At the rising edge

of CS, the selected input register is loaded with the cur-

rent shift-register data. All DAC outputs remain

unchanged. This preloads individual data in the input

Load Input and DAC Registers

This command directly loads the selected DAC register at

CS’s rising edge. A1 and A0 set the DAC address. Current

shift-register data is placed in the selected input and DAC

registers.

For example, to load all four DAC registers simultaneously

with individual settings (DAC A = 0.5V, DAC B = 1V,

DAC C = 1.5V, and DAC D = 2V), four commands are

required. First, perform three single input register

update operations for DACs A, B, and C (C1 = 0). The

final command loads input register D and updates all

four DAC registers from their respective input registers.

Software “

LDAC

” Command

All DAC registers are updated with the contents of their

respective input registers at CS’s rising edge. With the

exception of using CS to execute, this performs the

same function as the asynchronous LDAC.

Figure 3. Serial Input Format

THIS IS THE FIRST BIT SHIFTED IN

A1 A0 C1 C0 D7 D6 ... D1 D0 DIN

DOUT

CONTROL AND

ADDRESS BITS 8-BIT DAC DATA

MSB LSB

(LDAC = H)

(LDAC = 1)

(LDAC = H)

8-Bit Data0 1Address D0

D1D2D3D4D5D6D7

8-Bit Data1 1Address D0

D1D2D3D4D5D6D7

xxx xxxxx0 00 1 D0D1D2D3D4D5D6D7C0

Load All DACs with Shift-Register Data

All four DAC registers are updated with shift-register

data. This command allows all DACs to be set to any

analog value within the reference range. This command

can be used to substitute CLR if code 00 hex is pro-

grammed, which clears all DACs.

Software Shutdown

Shuts down all output buffer amplifiers, reducing sup-

ply current to 10µA max.

User-Programmable Output (UPO)

User-programmable logic output for controlling another

device across an isolated interface. Example devices

are gain control of an amplifier, a 4mA to 20mA amplifi-

er, and a polarity output for a motor speed control.

No Operation (NOP)

The NOP command (no operation) allows data to be

shifted through the MAX533 shift register without affect-

ing the input or DAC registers. This is useful in daisy

chaining (also see the

Daisy Chaining Devices

section).

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

10 ______________________________________________________________________________________

Set DOUT phase—SCLK rising (mode 1). DOUT

clocked out on rising edge of SCLK. All DACs updated

from their respective input registers.

Software shutdown (provided PDE is high)

Load all DACs with shift-register data. Also bring the

part out of shutdown mode.

12-BIT SERIAL WORD

FUNCTION

LDAC

D7 . . . . . . . . D0

XX X X X X X X X1

X8-bit DAC data1

Software LDAC commands. Update all DACs from

their respective input registers. Also bring the part out

of shutdown mode.

1X X X X X X X X 0

Load input register A; all DAC outputs updated

Load input register B; all DAC outputs updated

Load input register C; all DAC outputs updated

Load input register D; all DAC outputs updated.

8-bit DAC data

Load input register A; all DAC outputs unchanged.

Load input register B; all DAC outputs unchanged.

Load input register C; all DAC outputs unchanged.

Load input register D; all DAC outputs unchanged.

8-bit DAC data

UPO goes low.010 XX X X X X X X X0 UPO goes high.0 No operation (NOP); shift data in shift registers.

10XX X X X X X X X0 0 XX X X X X X X X0

Set DOUT phase—SCLK falling (mode 0). DOUT

clocked out on falling edge of SCLK. All DACs up-

dated from their respective registers (default).

010 XX X X X X X X X1

(LDAC = X)

(LDAC = X, PDE = H)

(LDAC = X)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

1 0 0 0 8-Bit Data

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

1 1 0 0 xxx xxxxx

UPO

Output

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 1 0 xxxxxxxx Low

0 1 1 0 xxxxxxxxHigh

xxx xxxxx0 00 0 D0

D1D2D3D4D5D6D7

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

______________________________________________________________________________________ 11

For this command, the data bits are “Don't Cares.” As

an example, three MAX533s are daisy chained (A, B,

and C), and devices A and C need to be updated. The

36-bit-wide command would consist of one 12-bit word

for device C, followed by an NOP instruction for device

B and a third 12-bit word with data for device A. At CS’s

rising edge, device B will not change state.

Set DOUT Phase—SCLK Rising (Mode 1)

Mode 1 resets the serial-output DOUT to transition at

SCLK’s rising edge. Once this command is issued,

DOUT’s phase is latched and will not change except on

power-up or if the specific command to set the phase

to falling edge is issued.

This command also loads all DAC registers with the con-

tents of their respective input registers, and is identical to

the “LDAC” command.

Set DOUT Phase—SCLK Falling (Mode 0, Default)

This command resets DOUT to transition at SCLK’s falling

edge. The same command also updates all DAC registers

with the contents of their respective input registers, identical

to the “LDAC” command.

LDAC Operation (Hardware)

LDAC is typically used in 4-wire interfaces (Figure 7). This

command is level sensitive, and it allows asynchronous

hardware control of the DAC outputs. With LDAC low, the

DAC registers are transparent, and any time an input regis-

ter is updated, the DAC output immediately follows.

Clear DACs with

CLR

Strobing the CLR pin low causes an asynchronous

clear of input and DAC registers and sets all DAC out-

puts to zero. Similar to the LDAC pin, CLR can be

invoked at any time, typically when the device is not

selected (CS = H). When the DAC data is all zeros, this

function is equivalent to the “Update all DACs from Shift

Registers” command.

Serial Data Output

DOUT is the internal shift register’s output. DOUT can

be programmed to clock out data on SCLK’s falling

edge (mode 0) or rising edge (mode 1). In mode 0, out-

put data lags input data by 12.5 clock cycles, maintain-

ing compatibility with Microwire and SPI. In mode 1,

output data lags input data by 12 clock cycles. On

power-up, DOUT defaults to mode 0 timing. DOUT

never three-states; it always actively drives either high

or low and remains unchanged when CS is high.

1 01 1 xxxxxxxx

D0D1D2D3D4D5D6D7C0

(LDAC = x)

A1 A0 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0

xxxxxxxx1 0 1 0

(LDAC = x)

SCLK

DIN



I/0

MICROWIRE

PORT

MAX533

Figure 4. Connections for Microwire

DIN

SCLK

MOSI

SCK

I/0

SPI/QSPI

PORT

MAX533

CPOL = 0, CPHA = 0

Figure 5. Connections for SPI/QSPI

Interfacing to the Microprocessor

The MAX533 is Microwire™ and SPI™/QSPI™ compati-

ble. For SPI and QSPI, clear the CPOL and CPHA con-

figuration bits (CPOL = CPHA = 0). The SPI/QSPI CPOL

= CPHA = 1 configuration can also be used if the

DOUT output is ignored.

The MAX533 can interface with Intel’s 80C5X/80C3X

family in mode 0 if the SCLK clock polarity is inverted.

More universally, if a serial port is not available, three

lines from one of the parallel ports can be used for bit

manipulation.

Digital feedthrough at the voltage outputs is greatly

minimized by operating the serial clock only to update

the registers. Also see the Clock Feedthrough photo in

the

Typical Operating Characteristics

section. The

clock idle state is low.

Daisy-Chaining Devices

Any number of MAX533s can be daisy-chained by con-

necting DOUT of one device to DIN of the following

device in the chain. The NOP instruction (Table 1)

allows data to be passed from DIN to DOUT without

changing the input or DAC registers of the passing

device. A 3-wire interface updates daisy-chained or

individual MAX533s simultaneously by bringing CS

high (Figure 6).

Analog Section

DAC Operation

The MAX533 uses a matrix decoding architecture for

the DACs, which saves power in the overall system.

The external reference voltage is divided down by a

resistor string placed in a matrix fashion. Row and col-

umn decoders select the appropriate tab from the

resistor string to provide the needed analog voltages.

The resistor string presents a code-independent input

impedance to the reference and guarantees a mono-

tonic output. Figure 8 shows a simplified diagram of the

four DACs.

Reference Input

The voltage at REF sets the full-scale output voltage for

all four DACs. The 460kΩtypical input impedance at

REF is code independent. The output voltage for any

DAC can be represented by a digitally programmable

voltage source as follows:

VOUT = (NB x VREF) / 256

where NB is the numerical value of the DAC’s binary

input code.

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

12 ______________________________________________________________________________________

SCLK

DIN

DEVICE A DEVICE B DEVICE C

MAX533

SCLK

DIN

MAX533

SCLK

DIN

MAX533

SCLK

DIN

MAX533

DOUT DOUT DOUT

SCLK

DIN

SCLK

DIN

TO OTHER

SERIAL DEVICES

Figure 6. Daisy-chained or individual MAX533s are simultaneously updated by bringing CS high. Only three wires are required.

SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp.

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

______________________________________________________________________________________ 13

LDAC

SCLK

DIN

MAX533

LDAC

SCLK

DIN

MAX533

LDAC

SCLK

DIN

MAX533

TO OTHER

SERIAL

DEVICES

DIN

SCLK

LDAC

CS1

CS2

CS3

Figure 7. Multiple MAX533s sharing one DIN line. Simultaneously update by strobing LDAC, or specifically update by enabling an

individual CS.

Output Buffer Amplifiers

All MAX533 voltage outputs are internally buffered by

precision unity-gain followers that slew at about

0.6V/µs. The outputs can swing from GND to VDD. With

a 0V to +2.5V (or +2.5V to 0V) output transition, the

amplifier outputs will typically settle to 1/2LSB in 6µs

when loaded with 10kΩin parallel with 100pF.

The buffer amplifiers are stable with any combination of

resistive (≥10kΩ) or capacitive loads.

__________Applications Information

DAC Linearity and Voltage Offset

The output buffer can have a negative input offset volt-

age that would normally drive the output negative, but

since there is no negative supply the output stays at 0V

(Figure 9). When linearity is determined using the end-

point method, it is measured between zero code (all

inputs 0) and full-scale code (all inputs 1) after offset

and gain error are calibrated out. However, in single-

supply operation the next code after zero may not

change the output (Figure 9), so the lowest code that

produces a positive output is the lower endpoint.

MAX533

Power Sequencing

The voltage applied to REF should not exceed VDD at

any time. If proper power sequencing is not possible,

connect an external Schottky diode between REF and

VDD to ensure compliance with the absolute maximum

ratings. Do not apply signals to the digital inputs before

the device is fully powered up.

Power-Supply Bypassing

and Ground Management

Connect AGND and DGND together at the IC. This

ground should then return to the highest-quality ground

available. Bypass VDD with a 0.1µF capacitor, located

as close to VDD and DGND as possible.

Careful PC board layout minimizes crosstalk among

DAC outputs and digital inputs. Figure 10 shows sug-

gested circuit board layout to minimize crosstalk.

Unipolar-Output,

Two-Quadrant Multiplication

In unipolar operation, the output voltages and the refer-

ence input are the same polarity. Figure 11 shows the

MAX533 unipolar configuration, and Table 2 shows the

unipolar code.

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

14 ______________________________________________________________________________________

Table 2. Unipolar Code Table

Note: 1LSB = (VREF) (2-8) = +VREF (––––)

256

+VREF (––––)

256

0 0 0 10 0 0 0

0V0 0 0 00 0 0 0

127

+VREF (––––)

256

1 1 1 10 1 1 1

128 VREF

+VREF (––––)= + ––––

256 2

0 0 0 01 0 0 0

129

+VREF (––––)

256

0 0 0 11 0 0 0

255

+VREF (––––)

256

1 1 1 11 1 1 1

ANALOG

OUTPUT

LSBMSB

DAC CONTENTS

DAC CODE



NEGATIVE

OFFSET



OUTPUT

VOLTAGE

Figure 9. Effect of Negative Offset (Single Supply)

REF

R15

R16

R255

LSB DECODER

D2D3

DAC A

D1 D0

MSB DECODER

Figure 8. DAC Simplified Circuit Diagram

MAX533

2.7V, Low-Power, 8-Bit Quad DAC

with Rail-to-Rail Output Buffers

______________________________________________________________________________________ 15

_________________________________________________________Functional Diagram

MAX533

OUTA

DAC A

DAC B

DAC C

DAC D

REF

DAC

DECODE

CONTROL

INPUT

DAC

INPUT

DAC

INPUT

DAC

INPUT

12-BIT

SHIFT

SR

CONTROL

CS DIN SCLK

OUTB

OUTC

OUTD

DOUT LDAC

CLR VDD

PDE DGND AGND

UPO

OUTC

OUTD

AGND



OUTB

OUTA

REF

SYSTEM GND

Figure 10. Suggested PC Board Layout for Minimizing

Crosstalk (Bottom View)

DAC A

DAC B

DAC C

DAC D

REFAB

MAX533

OUTA

OUTB

OUTC

OUTD

SERIAL

INTERFACE

NOT SHOWN

REFERENCE INPUT

VDD

+3V

313

14 12

AGND DGND

Figure 11. Unipolar Output Circuit

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

__________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600