PIC16LF870-I/SS - Microchip Technology

 2003 Microchip Technology Inc. DS30569B

PIC16F870/871

Data Sheet

28/40-Pin, 8-Bit CMOS

FLASH Microcontrollers

DS30569B-page ii  2003 Microchip Technology Inc.

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Microchip received QS-9000 quality system

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The Company’s quality system processes and

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 2003 Microchip Technology Inc. DS30569B-page 1

PIC16F870/871

Devices Included in thi s Data Sheet:

Microcontroller Core Features:

• High performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 2K x 14 words of FLASH Program Memory

128 x 8 bytes of Data Memory (RAM)

64 x 8 bytes of EEPROM Data Memory

• Pinout compatible to the PIC16CXXX 28 and

40-pin devices

• Interrupt capability (up to 11 sources)

• Eight level deep hardware stack

• Direct, Indirect and Relative Addressing modes

• Power-on Reset (POR )

• Power-up Timer (PWRT) and

Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator f or relia ble opera tion

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillat or optio ns

• Low power, high speed CMOS FLASH/EEPROM

technology

• Fully static design

• In-Circuit Serial Programming (ICSP) via

two pins

• Single 5V In-Circuit Seria l P rogramming c apabilit y

• In-Circuit Debugging via two pins

• Processor read/write access to program memory

• Wide operating voltage range: 2.0V to 5.5V

• High Sink/Source Current: 25 mA

• Commercial and Industrial temperature ranges

• Low power consumption:

- < 1.6 mA typical @ 5V, 4 MHz

-20 µA typical @ 3V, 32 kHz

-< 1 µA typical standby current

Pin Diagram

Peripheral Feat ures:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler,

can be increm ent ed duri ng SLEEP via external

crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period

• One Capture, Compare, PWM module

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

• 10-bit multi-channel Analog-to-Digital converter

• Universal Synchronous Asynchronous Receiver

Transmit ter (USART/SCI) with 9-bit addre ss

detection

• Parallel Slave Port (PSP) 8-bits wide, with

external RD , WR and CS controls (40/44-pin only)

• Brown-out detection circuitry for

Brown-out Reset (BOR)

•PIC16F870 •PIC16F871

RB7/PGD

RB6/PGC

RB5

RB4

RB3/PGM

RB2

RB1

RB0/INT

VDD

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RC6/TX/CK

RC5

RC4

RD3/PSP3

RD2/PSP2

MCLR/VPP/THV

RA0/AN0

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

VDD

VSS

OSC1/CLKI

OSC2/CLKO

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3

RD0/PSP0

RD1/PSP1

PIC16F871

PDIP

28/40-Pin, 8-Bit CMOS FLAS H Microcontrollers

PIC16F870/871

DS30569B-page 2  2003 Microchip Technology Inc.

Pin Diagrams

PIC16F870

14 15

MCLR/VPP/THV

RA0/AN0

RA1/AN1

RA2/AN2/VREF-

RA3/AN3/VREF+

RA4/T0CKI

RA5/AN4

VSS

OSC1/CLKI

OSC2/CLKO

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3

RB7/PGD

RB6/PGC

RB5

RB4

RB3/PGM

RB2

RB1

RB0/INT

VDD

VSS

RC7/RX/DT

RC6/TX/CK

RC5

RC4

PIC16F871

RA4/T0CKI

RA5/AN4

RE0/RD/AN5

OSC1/CLKI

OSC2/CLKO

RC0/T1OSO/T1CK1

RE1/WR/AN6

RE2/CS/AN7

VDD

VSS

RB3/PGM

RB2

RB1

RB0/INT

VDD

VSS

RD7/PSP7

RD6/PSP6

RD5/PSP5

RD4/PSP4

RC7/RX/DT

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

MCLR/VPP/THV

RB7/PGD

RB6/PGC

RB5

RB4

RC6/TX/CK

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

RC2/CCP1

RC1/T1OSI

PIC16F871

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

MCLR/VPP/THV

RB7/PGD

RB6/PGC

RB5

RB4

NC RC6/TX/CK

RC5

RC4

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3

RC2/CCP1

RC1/T1OSI

RC0/T1OSO/T1CKI

OSC2/CLKO

OSC1/CLKI

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/AN4

RA4/T0CKI

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

VDD

RB0/INT

RB1

RB2

RB3/PGM

PLCC

TQFP

DIP, SOIC, SSOP

 2003 Microchip Technology Inc. DS30569B-page 3

PIC16F870/871

Key Features

PICmicroTM Mid-Range MCU Family Reference Manual

(DS33023) PIC16F870 PIC16F871

Operating Frequency DC - 20 MHz DC - 20 MHz

RESETS (and Delays) POR, BOR (PWRT, OST) POR, BOR (PWRT, OST)

FLASH Program Memory (14-bit words) 2K 2K

Data Memory (bytes) 128 128

EEPROM Data Memory 64 64

Interrupts 10 11

I/O Ports Ports A,B,C Ports A,B,C,D,E

Timers 3 3

Capt ure/Compare/PWM modules 1 1

Serial Communications USART USART

Parallel Communications — PSP

10-bit Analog-to-Digital Module 5 input channels 8 input channels

Instruction Set 35 Instructions 35 Instructions

PIC16F870/871
DS30569B-page 4  2003 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory O rganization................................................................................................................................................................. 11
3.0 Data EEPROM and Flash Program Memory.............................................. ............... ...... ............. ...... ........................................ 27
4.0 I/O Ports....... ...... ...... ....... ...... ................. ...... ................. ................. ...... ................. ..................................................................... 33
5.0 Timer0 Module ........................................................................................................................................................................... 45
6.0 Timer1 Module ........................................................................................................................................................................... 49
7.0 Timer2 Module ........................................................................................................................................................................... 53
8.0 Capture/Compare/PWM Modules ........................................... ....... .... .... .. .... ....... .... .... .. .... ......... .. .............................................. 55
9.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................................ 61
10.0 Analog-t o-Digital (A/D) Conver ter Module.................................................................................................................................. 79
11.0 Specia l Features of the CPU.............. ...... ...... ....... ................ ....... ...... ...... ................. ...... ..... ...................................................... 87
12.0 Instruction Set Summary.......................................................................................................................................................... 103
13.0 Development Support............................................................................................................................................................... 111
14.0 Electrical Characteristics.......................................................................................................................................................... 117
15.0 DC and AC Characteristics Graphs and Tables.............. .... .... ....... .... .... .... .. ......... .... .... .... ....... .... .... ........................................ 137
16.0 Packagin g  In fo rmation................. ....... ...... ...... ................. ...... ....... ...... ................. ...... ...... ......................................................... 149
Appendix A: Revision History............................................................................................................................................................. 157
Appendix B: Device Differences......................................................................................................................................................... 157
Appendix C: Conversion Considerations ..................... ....... .... .. .... .. ....... .... .. .... .. .... ....... .. .... .. .... .. ....................................................... 158
Appendix D: Migration from Mid-Range to Enhanced Devices.......................................................................................................... 158
Appendix E: Migration from High-End to Enhanced Devices................... .... .... .... .. ......... .... .... .. ......... .... .... ........................................ 159
Index .................................................................................................................................................................................................. 161
On-Line Support................................ .... ......... .. .... .... .. ......... .. .... .... .. ......... .... .. .... .. ......... .... ................................................................. 167
Systems Information and Upgrade Hot Line...................................................................................................................................... 167
Reader Response.............................................................................................................................................................................. 168
PIC16F870/871 Product Identification System .................................................................................................................................. 169
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 2003 Microchip Technology Inc. DS30569B-page 5

PIC16F870/871

1.0 DEVICE OVERVIEW

This document contains device specific information.

Additional information may be found in the PICmicroTM

Mid-Range MCU Family Reference Manual

(DS33023), which may be obtained from your local

Microchip Sales Representative or downloaded from

the Microchip web site. The Reference Manual should

be considered a complementary document to this data

sheet, and is highly recommended reading for a better

underst a nding of the dev ice archi tecture and oper atio n

of the peripheral modul es.

There are two devices (PIC16F870 and PIC16F871)

covered by this data sheet. The PIC16F870 device

comes in a 28-pin package and the PIC16F871 device

comes in a 40-pi n packa ge. The 28-p in device does not

have a Parallel Slave Port implemented.

The following two figures are device block diagrams

sorted by pin number: 28-pin for Figure 1-1 and 40-pin

for Figure 1-2. The 28- pin an d 4 0-pin pin ou t s are listed

in Table 1-1 and Table 1-2, respectively.

FIGURE 1-1 : PIC16F 87 0 B LO CK D IA G RAM

FLASH

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr 7

RAM Addr (1) 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKI

OSC2/CLKO

MCLR VDD, VSS

PORTA

PORTB

PORTC

RA4/T0CKI

RA5/AN4

RB0/INT

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3

RC4

RC5

RC6/TX/CK

RC7/RX/DT

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

USART

CCP1

10-bit A/DTimer0 Timer1 Timer2

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

Data EEPROM

RB1

RB2

RB3/PGM

RB4

RB5

RB6/PGC

RB7/PGD

Device Program FLASH Data Memory Data EEPROM

PIC16F870 2K 128 Bytes 64 Bytes

In-Circuit

Debugger

Low-Voltage

Programming

PIC16F870/871

DS30569B-page 6  2003 Microchip Technology Inc.

FIGURE 1-2 : PIC16F 87 1 B LO CK D IA G RAM

FLASH

Program

Memory

13 Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr 7

RAM Addr (1) 9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKI

OSC2/CLKO

MCLR VDD, VSS

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI

RA5/AN4

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/CCP1

RC3

RC4

RC5

RC6/TX/CK

RC7/RX/DT

RD7/PSP7:RD0/PSP0

RE0/RD/AN5

RE1/WR/AN6

RE2/CS/AN7

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

USART

CCP1

10-bit A/DTimer0 Timer1 Timer2

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

Data EEPROM

RB0/INT

RB1

RB2

RB3/PGM

RB4

RB5

RB6/PGC

RB7/PGD

Device Program FLASH Data Memory Data EEPROM

PIC16F871 2K 128 Bytes 64 Bytes

In-Circuit

Debugger

Low-Voltage

Programming

Parallel Slave Port

 2003 Microchip Technology Inc. DS30569B-page 7

PIC16F870/871

TABLE 1-1: PIC16F870 PINOUT DESCRIPTION

Pin Name DIP

Pin# SOIC

Pin# I/O/P

Type Buffer

Type Description

OSC1/CLKI 9 9 I ST/CMOS(3) Oscillator crystal inpu t/external clock source input.

OSC2/CLKO 10 10 O — Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillat or mode. In RC mode, t he OSC2 pin outpu ts

CLKO, which has 1/4 the frequency of OSC1, and denotes the

instruction cycle rate.

MCLR/VPP/THV 1 1 I/P ST Master Clear (Reset) input or prog ramming volta ge input or High

Voltage Test mode control. This pin is an active low RESET to the

device.

PORTA is a bi-directional I/O port.

RA0/AN0 2 2 I/O TTL RA0 can also be analog input 0.

RA1/AN1 3 3 I/O TTL RA1 can also be analog input 1.

RA2/AN2/VREF- 4 4 I/O TTL RA2 can also be analog input 2 or negative analog reference

voltage.

RA3/AN3/VREF+ 5 5 I/O TTL RA3 can also be analog input 3 or positive analog reference

voltage.

RA4/T0 CKI 6 6 I/O ST/OD RA4 can als o be th e clock i nput to t he T imer0 mod ule. Ou tput

is open drain t ype.

RA5/AN4 7 7 I/O TTL RA5 can also be analog input 4.

PORTB is a bi-directi onal I/O port . PORTB can be software

programmed for internal weak pull-up on all inputs.

RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interr upt pin.

RB1 22 22 I/O TTL

RB2 23 23 I/O TTL

RB3/PGM 24 24 I/O TTL/ST(1) RB3 can also be the low voltage programming input.

RB4 25 25 I/O TTL Interrupt-on-change pin.

RB5 26 26 I/O TTL Interrupt-on-change pin.

RB6/PGC 27 27 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Se rial

programming clock.

RB7/PGD 28 28 I/O TTL/ST(2) Interrupt-on-change pin or In-Circuit Debugger pin. Se rial

programmi ng data.

PORT C is a bi-directional I/O port.

RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock

input.

RC1/T1OSI 12 12 I/O ST RC1 can also be the Timer1 os cillator input.

RC2/CCP1 13 13 I/O ST RC2 can also be the Capt ure1 input/ Compare1 output/

PWM1 output.

RC3 14 14 I/O ST

RC4 15 15 I/O ST

RC5 16 16 I/O ST

RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous T ransmit or

Synchronous Clock.

RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchr onous Receive or

Synchronous Data.

VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins.

VDD 20 20 P — Positive supply for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

OD = Open Drain — = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

PIC16F870/871

DS30569B-page 8  2003 Microchip Technology Inc.

TABLE 1-2: PIC16F871 PINOUT DESCRIPTION

Pin Name DIP

Pin# PLCC

Pin# QFP

Pin# I/O/P

Type Buffer

Type Description

OSC1/CLKI 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input.

OSC2/CLKO 14 15 31 O — Oscillator crystal output. Connect s to cryst al or resonator in

Cryst al Oscillator mode. In RC mode, OSC2 pin output s CLKO,

which has 1/4 the frequency of OSC1, and denotes the

instruction cycle rate.

MCLR/VPP/THV 1 2 18 I/P ST Master Clear (Reset) input or programming voltage input or

High Voltage Test mode control. This pin is an active low

RESET to the device.

PORTA is a bi-direc t i on al I/O po r t.

RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input 0.

RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input 1.

RA2/AN2/VREF- 4 5 21 I/O TTL RA2 can also be analog input 2 or negative analog

refer enc e vo ltage.

RA3/AN3/VREF+ 5 6 22 I/O TTL RA3 can also be analog input 3 or positive analog

refer enc e vo ltage.

RA4/T0 CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0

timer/counter. Output is open drain type.

RA5/AN4 7 8 24 I/O TTL RA5 can also be analog input 4.

PORT B is a bi-direct i onal I/O port. PORTB can be software

programmed for internal weak pull-up on all inpu ts.

RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin.

RB1 34 37 9 I/O TTL

RB2 35 38 10 I/O TTL

RB3/PGM 36 39 11 I/O TTL/ST(1) RB3 can also be the low volt age programming inp ut.

RB4 37 41 14 I/O TTL Inter rupt-on-change pin.

RB5 38 42 15 I/O TTL Inter rupt-on-change pin.

RB6/PGC 39 43 16 I/O TTL/ST(2) Interrupt-on-c hange pin or In-Cir cu it Debugger pin.

Serial programming clock.

RB7/PGD 40 44 17 I/O TTL/ST(2) Interrupt-on-c hange pin or In-Cir cu it Debugger pin.

Serial programming data .

PORTC is a b i- d i r ection a l I/O port.

RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1

clock input.

RC1/T1OSI 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input.

RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.

RC3 18 20 37 I/O ST

RC4 23 25 42 I/O ST

RC5 24 26 43 I/O ST

RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or

Synchronous Data .

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

 2003 Microchip Technology Inc. DS30569B-page 9

PIC16F870/871

PORTD is a bi-directional I/O port or parallel slave port when

interfacing to a microprocessor bus.

RD0/PSP0 19 21 38 I/O ST/TTL(3)

RD1/PSP1 20 22 39 I/O ST/TTL(3)

RD2/PSP2 21 23 40 I/O ST/TTL(3)

RD3/PSP3 22 24 41 I/O ST/TTL(3)

RD4/PSP4 27 30 2 I/O ST/TTL(3)

RD5/PSP5 28 31 3 I/O ST/TTL(3)

RD6/PSP6 29 32 4 I/O ST/TTL(3)

RD7/PSP7 30 33 5 I/O ST/TTL(3)

PORTE is a bi-directional I/O port.

RE0/RD/AN5 8 9 25 I/O ST/TTL(3) RE0 can als o be read cont rol for t he par allel sla ve port, or

analog input 5.

RE1/WR/AN6 9 10 26 I/O ST/TTL(3) RE1 ca n a lso be write cont rol for t he p a ralle l slav e por t, or

analog input 6.

RE2/CS/AN7 10 11 27 I/O ST/TTL(3) RE2 can also be select control for the parallel slave port,

or analog input 7.

VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.

VDD 11,32 12,35 7, 28 P — Positiv e supply for logic and I/O pins.

NC — 1,17,28,

40 12,13,

33,34 — These pins are not internally connected. Th ese pins should be

left unconnected.

TABLE 1-2: PIC16F871 PINOUT DESCRIPTION (CONTINUED)

Pin Name DIP

Pin# PLCC

Pin# QFP

Pin# I/O/P

Type Buffer

Type Description

Legend: I = input O = output I/O = input/output P = power

— = Not used T TL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt or LVP mode.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel

Slave Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

PIC16F870/871

DS30569B-page 10  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 11

PIC16F870/871

2.0 MEMORY ORGANIZATION

The PIC16F870/871 devices have three memory

blocks. The Program Memory and Data Memory have

separat e buses, so that c oncurrent access can occur,

and is detailed in this section. The EEPROM data

memory block is detailed in Section 3.0.

Addit ional informat ion on devi ce memory may be found

in the PICmicroTM Mid-Range MCU Family Reference

Manual (DS33023).

2.1 Program Memory Organization

The PIC16F870/871 devices have a 13-bit program

counter capable of addressing an 8K x 14 program

memory space. The PIC16F870/871 devices have

2K x 14 words of FLASH program memory. Accessing

a location above the physically implemented address

will cause a wraparou nd.

The RESET vector is at 0000h and the interrupt vector

is at 0004h.

FIGURE 2-1: PIC16F870/871 PROGRAM

MEMORY MAP AND STACK

2.2 Data Memory Organization

The data memory is partitioned into multiple banks

which contain the General Purpose Registers and the

Special Function Registers. Bits RP1 (STATUS<6>)

and RP0 (STATUS<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower

locations of each bank are reserved for the Special

Functio n Register s. Above the Spe cial Function Regis-

ters are General Purpose Registers, implemented as

static RAM. All implemented banks contain Special

Function Registers. Some “high use” Special Function

Registers from one bank may be mirrored in another

bank for code reduction and quicker access.

2.2. 1 GENERAL PURPOSE REGISTER

FILE

The register file can be accessed either directly, or

indirectly through the File Select Register FSR.

PC<12:0>

0000h

0004h

0005h

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Ve ctor

On-Chip

CALL, RETURN

RETFIE, RETLW

1FFFh

Stack Level 2

Program

Memory Page 0 07FFh

0800h

RP<1:0> Bank

00 0

01 1

10 2

11 3

Note: EEPROM Data Memory description can

be found in Sec tion 3.0 of this Data Sheet.

PIC16F870/871

DS30569B-page 12  2003 Microchip Technology Inc.

FIGURE 2- 2 : PIC16F 87 0/871 R EG ISTER FIL E MA P

Indirect addr.(*)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PORTC

PCLATH

INTCON

PIR1

TMR1L

TMR1H

T1CON

TMR2

T2CON

CCPR1L

CCPR1H

RCSTA

OPTION_REG

PCL

STATUS

FSR

TRISA

TRISB

TRISC

PCLATH

INTCON

PIE1

PCON

PR2

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

20h A0h

7Fh FFh

Bank 0 Bank 1

File

Address

Indirect addr.(*) Indirect addr.(*)

PCL

STATUS

FSR

PCLATH

INTCON

PCL

STATUS

FSR

PCLATH

INTCON

100h

101h

102h

103h

104h

105h

106h

107h

108h

109h

10Ah

10Bh

180h

181h

182h

183h

184h

185h

186h

187h

188h

189h

18Ah

18Bh

17Fh 1FFh

Bank 2 Bank 3

Indirect addr.(*)

ADRESL

TMR0 OPTION_REG

PIR2 PIE2

ADRESH

ADCON0 ADCON1

General

Purpose

General

Purpose

1EFh

1F0h

accesses

A0h - BFh

16Fh

170h

accesses

70h-7Fh

TRISB

PORTB

96 Bytes

32 Bytes

10Ch

10Dh

10Eh

10Fh

110h

18Ch

18Dh

18Eh

18Fh

190h

EEDATA

EEADR EECON1

EECON2

EEDATH

EEADRH Reserved(1)

Reserved(1)

Unimplemente d data memory locations, read as '0'.

* Not a physical register.

Note 1: These registers are reserved; maintain these registers clear.

2: These registers are not implemented on the PIC16F870.

120h 1A0h

accesses

70h-7Fh accesses

70h-7Fh

accesses

20h-7Fh

C0h

EFh

F0h

1C0h

1BFh

BFh

TXREG

RCREG

CCP1CON TXSTA

SPBRG

PORTD(2)

PORTE(2) TRISD(2)

TRISE(2)

File

Address

File

Address

File

Address

 2003 Microchip Technology Inc. DS30569B-page 13

PIC16F870/871

2.2.2 SPECIAL FUNCTION REGISTERS

The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the

desired operation of the device. These registers are

implemented as static RAM. A list of these registers is

given in Ta ble 2-1.

The Special Function Registers can be classified into

two sets: core (CPU) and peripheral. Those registers

associated with the core functions are described in

detail in this section. Those related to the operation of

the peripheral features are described in detail in the

peripheral feature section.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS(2)

Bank 0

00h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu

02h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

04h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

05h PORTA —— PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000

06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

08h(5) PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

09h(5) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

0Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(3) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

0Dh PIR2 — — —EEIF— — — — ---0 ---- ---0 ----

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

13h —Unimplemented — —

14h —Unimplemented — —

15h CCPR1L Capture/Compare/P WM R egist er1 (LS B) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/C o mpare /PW M Regi st er1 (MS B) xxxx xxxx uuuu uuuu

17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USART Transmit Data Register 0000 0000 0000 0000

1Ah RCREG USART Receive Data Register 0000 0000 0000 0000

1Bh —Unimplemented — —

1Ch —Unimplemented — —

1Dh —Unimplemented — —

1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset .

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.

4: These registers can be addressed from any bank.

5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.

PIC16F870/871

DS30569B-page 14  2003 Microchip Technology Inc.

Bank 1

80h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

83h(4) STATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

84h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111

86h TRISB PORTB Data Direction Register 1111 1111 1111 1111

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

88h(5) TRISD PORTD Data Direction Register 1111 1111 1111 1111

89h(5) TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111

8Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

8Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

8Ch PIE1 PSPIE(3) ADIE RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

8Dh PIE2 — — — EEIE — — — — ---0 ---- ---0 ----

8Eh PCON — — — — — —PORBOR ---- --qq ---- --uu

8Fh —Unimplemented — —

90h —Unimplemented — —

91h —Unimplemented — —

92h PR2 Timer2 Period Register 1111 1111 1111 1111

93h —Unimplemented — —

94h —Unimplemented — —

95h —Unimplemented — —

96h —Unimplemented — —

97h —Unimplemented — —

98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

9Ah —Unimplemented — —

9Bh —Unimplemented — —

9Ch —Unimplemented — —

9Dh —Unimplemented — —

9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu

9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 0--- 0000 0--- 0000

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset .

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.

4: These registers can be addressed from any bank.

5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.

 2003 Microchip Technology Inc. DS30569B-page 15

PIC16F870/871

Bank 2

100h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu

102h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

103h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

104h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

105h —Unimplemented — —

106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu

107h —Unimplemented — —

108h —Unimplemented — —

109h —Unimplemented — —

10Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

10Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

10Ch EEDATA EEPROM Data Register xxxx xxxx uuuu uuuu

10Dh EEADR EEPROM Address Register xxxx xxxx uuuu uuuu

10Eh EEDATH —— EEPROM Dat a Register High Byte xxxx xxxx uuuu uuuu

10Fh EEADRH — — — EEPROM Address Register High Byte xxxx xxxx uuuu uuuu

Bank 3

180h(4) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

182h(4) PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

183h(4) STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

184h(4) FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

185h —Unimplemented — —

186h TRISB PORTB Data Direction Register 1111 1111 1111 1111

187h —Unimplemented — —

188h —Unimplemented — —

189h —Unimplemented — —

18Ah(1,4) PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

18Bh(4) INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 x--- u000

18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- ---- ----

18Eh —Reserved maintain clear 0000 0000 0000 0000

18Fh —Reserved maintain clear 0000 0000 0000 0000

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', r = reserved.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter.

2: Other (non Power-up) Resets include external RESET through MCLR and Watchdog Timer Reset .

3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.

4: These registers can be addressed from any bank.

5: PORTD, PORTE, TRISD and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.

PIC16F870/871

DS30569B-page 16  2003 Microchip Technology Inc.

2.2.2.1 STATUS Register

The STATUS register contains the arithmetic status of

the ALU, th e RESET s tatu s and the b ank sele ct bit s for

data memory.

The STATUS register can be the destination for any

instruction, as with any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabl ed. These bit s are set or clea red according to the

device logic. Furthermore, the TO and PD bits are not

writable, therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affe ct the Z, C or D C bits from th e ST ATUS regist er . For

other instructions not affecting any status bits, see the

“Instruction Set Summary”.

Note 1: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in sub-

traction. See the SUBLW and SUBWF

instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD ZDCC

bit 7 bit 0

bit 7-6 IRP: Register Bank Sele ct bit (used for indir ect addressing )

1 = Bank 2, 3 (100h - 1FFh)

0 = Bank 0, 1 (00h - FFh)

bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)

10 = Bank 2 (100h - 17Fh)

11 = Bank 1 (80h - FFh)

10 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes.

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP ins truction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

(for borrow, the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred

0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s

complement of the second operand. For rotate (RRF, RLF) instructions, this bit is

loaded with either the high or low order bit of the source register.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30569B-page 17

PIC16F870/871

2.2.2.2 OPTION_RE G Regist er

The OPTION_REG register is a readable and writable

the TMR0 prescaler/WDT postscaler (single assign-

able re gister known a lso as the pres caler), t he Ext ernal

INT interrupt , TMR0 and the weak pull-u ps on PORTB.

Note: To achieve a 1:1 prescaler assignment for

the TMR 0 re gis te r, assign the presca ler to

the Watchdog Timer.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled

0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin

0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin

0 = Internal instruction cycle clock (CLKO)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin

0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F870/871

DS30569B-page 18  2003 Microchip Technology Inc.

2.2.2.3 INTCON Register

The INTCON register is a readable and writable regis-

ter, which contains various enable and flag bits for the

TMR0 register overflow, RB Port change and External

RB0/INT pin interrupts.

Note: Interru pt flag bit s get set when an interru pt

conditi on occ urs, regar dless o f the s tate of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all unmasked interrupts

0 = Disables all inte rrupts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all unmasked peripheral interrupts

0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Inter rupt Enable bit

1 = Enables the TMR0 interrupt

0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt

0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt

0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)

0 = TMR0 reg i ster did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external int errupt o c curred (must be cleared in software)

0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)

0 = None of the RB7:RB4 pins have changed state

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30569B-page 19

PIC16F870/871

2.2.2.4 PIE1 Register

The PIE1 regi ster cont ains the indivi dual enable b its for

the peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0

PSPIE(1) ADIE RCIE TXIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt

0 = Disables the PSP read/write interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt

0 = Disables the A/D converter interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt

0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt

0 = Disables the USART transmit interrupt

bit 3 Unimplemented: Read as ‘0’

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Ov erfl ow Interr upt Enab le bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

Note 1: PSPIE is reserved on the PIC16F870; always maintain this bit clear.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F870/871

DS30569B-page 20  2003 Microchip Technology Inc.

2.2.2.5 PIR1 Register

The PIR1 register contains the individual flag bits for

the peripheral interrupts.

Note: Interru pt flag bit s get set when an interru pt

conditi on occ urs, regardle ss of the st ate of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt bits are clear prior to enabling an

interrupt.

R/W-0 R/W-0 R-0 R-0 U-0 R/W-0 R/W-0 R/W-0

PSPIF(1) ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 PSPIF(1): Parall el Slav e Port Re ad/ W ri te Interru pt Fla g bit

1 = A read or a write operation has taken place (must be cleared in software)

0 = No read or write has occur red

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed

0 = The A/D conversion is not complete

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full

0 = The USART receive buffer is empty

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty

0 = The USART transmit buffer is full

bit 3 Unimplemented: Read as ‘0’

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture mode:

1 = A TMR 1 register capture oc curred (must be cl eare d in software)

0 = No TMR1 re gister capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in software)

0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)

0 = TMR1 reg i ster did not overflow

Note 1: PSPIF is reserved on the PIC16F870; always maintain this bit clear.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30569B-page 21

PIC16F870/871

2.2.2.6 PIE2 Register

The PIE2 register contains the individual enable bit for

the EEPROM write operation interrupt.

U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0

— — — EEIE — — — —

bit 7 bit 0

bit 7-5 Unimplemented: Read as '0'

bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit

1 = Enable EE write interrupt

0 = Disable EE write i nter rupt

bit 3-0 Unimplemented: Read as '0'

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F870/871

DS30569B-page 22  2003 Microchip Technology Inc.

2.2.2.7 PIR2 Register

The PIR2 regis ter contains the flag bit for the EEPROM

write operation interrupt.

Note: Interru pt flag bit s get set when an interru pt

conditi on occ urs, regardle ss of the st ate of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0

— — — EEIF — — — —

bit 7 bit 0

bit 7-5 Unimplemented: Read as '0'

bit 4 EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation is not complete or has not been started

bit 3-0 Unimplemented: Read as '0'

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30569B-page 23

PIC16F870/871

2.2.2.8 PCON Register

The Power Control (PCON) register contains flag bits

to allow differentiation between a Power-on Reset

(POR), a Brown-out Reset (BOR), a Watchdog Reset

(WDT) and an external MCLR Reset.

Note: BOR is unknown on POR. It must be set

by the user and checked on subsequent

RESETS to see if BOR is clear, indicating

a brown-out has occurred. The BOR

status bit is a don’t care and is not

predictable if the brown-out circuit is dis-

abled (by clearing the BOREN bit in the

configu r ati on word).

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1

— — — — — —PORBOR

bit 7 bit 0

bit 7-2 Unimplemented: Read as '0'

bit 1 POR: Power-on Reset Status bit

1 = No Power-on Reset occurred

0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred

0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F870/871

DS30569B-page 24  2003 Microchip Technology Inc.

2.3 PCL and PCLATH

The Program Counter (PC) is 13-bits wide. The low

byte comes from the PCL register, which is a readable

and writable register. The upper bits (PC<12:8>) are

not readable, but are indirectly writable through the

PCLATH register. On any RESET, the upper bit s of the

PC will b e clea red. Fig ure 2-3 shows the two situat ion s

for the l oading of th e PC. The up per ex ample in the fi g-

ure shows how the PC is loaded on a write to PCL

(PCLATH<4:0> → PCH). The low e r ex am pl e i n th e fi g-

ure shows how the PC is loaded during a CALL or GOTO

instruction (PCLATH<4:3> → PCH).

FIGU RE 2-3 : LOADING O F PC IN

DIFF ERENT SI T UA TIO NS

2.3.1 CO MPUT ED GOTO

A comput ed GOTO is a ccom pli shed by a ddi ng a n offset

to the program counter (ADDWF PCL). When doing a

table read using a computed GOTO method, care

should be ex ercise d if th e t able loca tion c rosse s a PCL

memory boundary (each 256-byte block). Refer to the

application note, “Implementing a Table Read"

(AN556).

2.3.2 STACK

The PIC16FXXX family has an 8-level deep x 13-bit

wide hardware stack. The stack space is not part of

either program or data space and the stack pointer is

not readable or writable. The PC is PUSHed onto the

stack when a CALL instruction is execut ed, or an in ter-

rupt cau se s a bra nch . Th e s tack is POP ed i n th e e ve nt

of a RETURN, RETLW or a RETFIE instruction

execution. PCLATH is not affected by a PUSH or POP

operation.

The st ack operates as a circular buf fer . This means that

after the stack has been PUSHed eight times, the ninth

push ov erwrite s the va lue tha t was store d from th e first

push. The tenth p us h ov erwr i tes the se co nd push (an d

so on).

2.4 Program Memory Paging

The PIC16FXXX architecture is capable of addressing

a continuous 8K word block of program memory. The

CALL and GOTO instructions provide 11 bits of the

address , which a llows bra nches wi thin any 2K program

memory page. Therefore, the 8K words of program

memory are broken into four pages. Since the

PIC16F872 has only 2K words of program memory or

one p age, ad ditional code i s not re quired to ensure th at

the correct page is selected before a CALL or GOTO

instruction is executed. The PCLATH<4:3> bits should

always be maintained as zeros. If a return from a CALL

instruction (or interrupt) is executed, the entire 13-bit

PC is popped off the stack. Manipulation of the

PCLATH is not required for the return instructions.

2.5 Indirect Addressing, INDF and

FSR Registers

The INDF register is no t a physical reg ister . Addr essing

the INDF register will cause indi rect addressing.

Indirect addressing is possible by using the INDF reg-

ister. Any instruction using the INDF register actually

acces ses the regist er po int ed to by the Fi le Select reg-

ister, FSR. Reading the INDF register itself indirectly

(FSR = 0) will read 00h. Writing to the INDF register

indirec tly resu lts in a no op erat ion (alth oug h status bits

may be affec ted). An ef fectiv e 9-bit add ress is o btaine d

by conc atenati ng the 8 -bit FS R registe r and t he IRP bit

(STATUS<7>), as shown in Figure 2-4.

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: INDIRECT ADDRESSING

12 8 7 0

5PCLATH<4:0>

PCLATH

Instruction with

ALU

GOTO,CALL

Opcode < 10:0 >

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as

Destination

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions

that occur from the execution of the CALL,

RETURN, RETLW and RETFIE instruc-

tions, or the vectoring to an interrupt

address.

movlw 0x20 ;initialize pointer

movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer

btfss FSR,4 ;all done?

goto NEXT ;no clear next

CONTINUE

: ;yes continue

 2003 Microchip Technology Inc. DS30569B-page 25

PIC16F870/871

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING

Note 1: For register file map detail see Figure 2-2.

Data

Memory(1)

Indirect AddressingDirect Addressing

Bank Select Location Select

RP1: RP0 6 0

from opc ode IRP FSR Register

Bank Select Location Select

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

PIC16F870/871

DS30569B-page 26  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 27

PIC16F870/871

3.0 DATA EEPROM AND FLASH

PROGRAM MEMORY

The Data EEPROM and FLASH Program Memory are

readable and writ able durin g normal ope ration over the

entire VDD range. A bulk erase operation may not be

issued from user code (which includes removing code

prote ction). The d at a m em ory is n ot d ire ctl y ma pped in

the register file space. Instead, it is indi rectly addressed

through the Special Function Registers (SFR).

There are six SFRs used to read and write the pro gram

and data EEPROM memory. These registers are:

• EECON1

• EECON2

• EEDATA

• EEDATH

• EEADR

• EEADRH

The EEPROM dat a memory allows byte read and write.

When interfacing to the data memory block, EEDATA

holds the 8-bit dat a for read/write and EEADR holds the

address of the EEPROM locati on bein g access ed. The

registers EEDATH and EEADRH are not used for data

EEPROM access. The PIC16F870/871 devices have

64 bytes of da ta EEPROM with an addre ss rang e fro m

0h to 3Fh.

The EEPROM data memory is rated for high erase/

write cycles. The write time is controlled by an on-chip

timer. The write time will vary with voltage and temper-

ature, as well as from chip-to-chip. Please refer to the

specifications for exact limits.

The program memory allows word reads and writes.

Program m em ory ac ce ss a llo ws fo r c hec ks um c alc ul a-

tion and calibration table storage. A byte or word write

automatically erases the location and writes the new

data (erase before write). Writing to program memory

will cease operation until the writ e is complete. T he pro-

gram memory cannot be accessed during the write,

therefore co de ca nnot e xecut e. During the w rite opera-

tion, the oscillator continues to clock the peripherals,

and therefore, they continue to operate. Interrupt

events will be detected and essentially “queued” until

the write is completed. When the write completes, the

next instruction in the pipeline is executed and the

branch to the interrupt vector address will occur.

When interfacing to the program memory block, the

EEDATH:EEDATA registers form a two-byte word,

which holds the 14-bit data for read/write. The

EEADRH:EEADR registers form a two-byte word,

which holds the 13-bit address of the FLASH location

being accessed. The PIC16F870/871 devices have

2K words of program FLASH with an address range

from 0h to 7FFh. The unused upper bits in both the

EEDATH and EEDATA registers all read as ‘0’s.

The value written to pr ogram memory does not need to

be a valid instruction. Therefore, up to 14-bit numbers

can be stored in memory for use as calibration pa ram-

eters, serial numbers, packed 7-bit ASCII, etc. Execut-

ing a program memory location containing data that

forms an invalid instruction results in a NOP.

3.1 EEADR

The addres s registers can addres s up to a maximum of

256 bytes of data EEPROM or up to a maximum of

8K words of program FLASH. However, the

PIC16F870/871 have 64 bytes of data EEPROM and

2K words of program FLASH.

When selecting a program address value, the MSByte

of the address is written to the EEADRH register and

the LSByte is written to the EEADR register. When

selecting a data address value, only the LSByte of the

address is written to the EEADR register.

On the PIC16F870/871 devices, the upper two bits of

the EEADR must always be cleared to prevent inad-

vertent ac c ess to th e wr on g lo ca tion in data EEPR OM .

This also applies to the program memory. The upper

five MSbits of EEADRH must always be clear during

program FLASH access.

3.2 EECON1 and EECON2 Registers

The EECON1 register is the control register for config-

uring and initiatin g the access. The EECON2 reg ister is

not a physically implemented register, but is used

exclusively in the memory write sequence to prevent

inadvertent writes.

There are many bits used to control the read and write

operations to EEPROM data and FLASH program

memory. The EEPGD bit determines if the access will

be a program or data memory access. When clear , any

subsequent operations will work on the EEPROM data

memory. When set, all subsequent operations will

operate in the program memory.

Read ope rations onl y use one additio nal bit, RD, wh ich

initiates the read operation from the desired memory

location. Once this bit is set, the value of the desired

memory location will be available in the data registers.

This bit cannot be cleared by firmware. It is automati-

cally cleared at the end of the read operation. For

EEPROM data memory reads, the data will be avail-

able in th e EEDATA register in the very next i nstruc tion

cycle after the RD bit is set. For program memory

reads, the data will be loaded into the

EEDATH:EEDATA registers, following the second

instruction after the RD bit is set.

PIC16F870/871

DS30569B-page 28  2003 Microchip Technology Inc.

Wr ite operations hav e two control bit s, WR and WREN,

and two status bits, WRERR and EEIF. The WREN bit

is used to enable or disable the write operation. When

WREN is clear, the write operation will be disabled.

Therefore , the WREN bit mu st be set befo re ex ec utin g

a write operation. Th e WR bit is used to in itiate the write

operation. It also is automatically cleared at the end of

the write operation. The interrupt flag EEIF is used to

deter mine wh en the memory write c omple tes. Th is fla g

must be cleared in software before setting the WR bit.

For EEPROM data memory, once the WREN bit and

the WR bit have bee n set, the desired mem ory address

in EEADR will be erased, followed by a write of the data

in EEDATA. This operation takes place in parallel with

the microcontroller continuing to execute normally.

When the write is c omplete, the EEIF fl ag bit will be set.

For program memory, once the WREN bit and the WR

bit have been set , the microc ontroller w ill cease to exe-

cute i nstruc tions. T he de sired memory loca tion pointe d

to by EEADRH:EEADR will be erased. Then, the data

value in EEDATH:EEDATA will be programmed. When

complete, the EEIF flag bit will be set and the

microcontroller will continue to execute code.

The WRERR bit is used to indicate when the

PIC16F8 70/871 devices have been re set during a write

operation. WRERR should be cleared after Power-on

Reset. Thereafter, it should be checked on any other

RESET. The WRERR bit is set when a write operation

is interrupted by a MCLR Reset, or a WDT Time-out

Reset , during normal o peration. In these situ ations, fo l-

lowing a RESET , the user should check the WRERR bit

and rewri te the memory loc ation, if set . The content s of

the data registers, address registers and EEPGD bit

are not affected by either MCLR Reset, or WDT

Time-out Reset, during normal operation.

R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0

EEPGD — — — WRERR WREN WR RD

bit 7 bit 0

bit 7 EEPGD: Program/Data EEPROM Select bit

1 = Accesses program memory

0 = Accesses data memory

(This bit cannot be chang ed wh il e a read or write operation is in progres s.)

bit 6-4 Unimplemented: Read as '0'

bit 3 WRERR: EEPROM Error Flag bit

1 = A write operation is prematurely terminated (any MCLR Reset or any WDT Reset during

normal operation)

0 = The write operation completed

bit 2 WREN: EEPROM Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the EEPROM

bit 1 WR: Write Control bi t

1 = Initiates a write cycle. (The bit is cleared by hardware once write is complete. The WR bit

can only be set (not cleared) in software.)

0 = Write cycle to the EEPROM is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read. (RD is cleared in hardware. The RD bit can only be set (not

cleared) in software.)

0 = Does not initiate an EEPROM read

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30569B-page 29

PIC16F870/871

3.3 Reading the EEPROM Data

Memory

Reading EEPROM data memory only requires that the

desired address to access be written to the EEADR

data will be available in the EEDATA register on the

very next instruction cycle. EEDATA will hold this value

until another read operation is initiated or until it is

written by firmware.

The steps to reading the EEPROM data memory are:

1. Write the address to EEDATA. Make sure that

the address is not larger than the memory size

of the PIC16F870/871 devices.

2. Clear the EEPGD bit to point to EEPROM data

memory.

3. Set the RD bit to start the read operation.

4. Read the data from t he EEDATA register.

EXAMPLE 3-1: EEPROM DATA READ

3.4 Writing to the EEPROM Data

Memory

There are many steps in writing to the EEPROM data

memory. Both ad dress and d ata va lues must be written

to the SFRs. The EEPGD bit must be cleared, and the

WREN bi t mus t be set, t o enab le wr ites. The WREN b it

should be kept clear at all times, ex cept when writing to

the EEPROM data. The WR bit can only be set if the

WREN bit was set in a previous operation (i.e., they

both cann ot be set in the same opera tio n). The WREN

bit should then be cleared by firmware after the write.

Clearing the WREN bit before the write actually

completes will not terminate the write in progress.

Writes to EEPROM data memory must also be pref-

aced with a special sequence of instructions that pre-

vent in advertent wri te operations . This is a s equence of

five instructions that must be executed without interrup-

tions. The firmware should verify that a write is not in

progress before starting another cycle.

The steps to write to EEPROM data memory are:

1. If step 10 is not implemented, check the WR bit

to see if a write is in progress.

2. Write the address to EEADR. Make sure that the

address is not larger than the memory size of

the PIC16F870/871 devices.

3. Write the 8-bit data value to be programmed in

the EEDATA register.

4. Clear the EEPGD bit to point to EEPROM data

memory.

5. Set the WREN bit to en able program operations.

6. Disable interrupts (if enabled).

7. Execute the special five instruction sequence:

• Write 55h to EECO N2 in two step s (first to W ,

then to EECON2)

• Write AAh to EECON2 in two steps (first to

W, then to EECON2)

• Set the WR bit

8. Enable interrupts (if using interrupts).

9. Clear the WREN bit to disable program

operations.

10. At the completion of the write cycle, the WR bit

is cleared and the EEIF interrupt flag bit is set.

(EEIF must be cleared by firmware.) If step 1 is

not implemented, then firmware should check

for EEIF to be set, or WR to clear, to indi cate the

end of the program cycle.

EXAMPLE 3-2: EEPROM DATA WRITE

BSF STATUS, RP1 ;

BCF STATUS, RP0 ;Bank 2

MOVF ADDR, W ;Write address

MOVWF EEADR ;to read from

BSF STATUS, RP0 ;Bank 3

BCF EECON1, EEPGD ;Point to Data memory

BSF EECON1, RD ;Start read operation

BCF STATUS, RP0 ;Bank 2

MOVF EEDATA, W ;W = EEDATA

BSF STATUS, RP1 ;

BSF STATUS, RP0 ;Bank 3

BTFSC EECON1, WR ;Wait for

GOTO $-1 ;write to finish

BCF STATUS, RP0 ;Bank 2

MOVF ADDR, W ;Address to

MOVWF EEADR ;write to

MOVF VALUE, W ;Data to

MOVWF EEDATA ;write

BSF STATUS, RP0 ;Bank 3

BCF EECON1, EEPGD ;Point to Data memory

BSF EECON1, WREN ;Enable writes

;Only disable interrupts

BCF INTCON, GIE ;if already enabled,

;otherwise discard

MOVLW 0x55 ;Write 55h to

MOVWF EECON2 ;EECON2

MOVLW 0xAA ;Write AAh to

MOVWF EECON2 ;EECON2

BSF EECON1, WR ;Start write operation

;Only enable interrupts

BSF INTCON, GIE ;if using interrupts,

;otherwise discard

BCF EECON1, WREN ;Disable writes

PIC16F870/871

DS30569B-page 30  2003 Microchip Technology Inc.

3.5 Reading the FLASH Program

Memory

Reading FLASH program memory is much like that of

EEPROM data memory , only two NOP instructions must

be inserted after the RD bit is set. These two instruction

cycles that the NOP instructions execute, will be used by

the microcontroller to read the data out of program

memory and insert the value into the EEDA TH:EEDA T A

registers. Data will be available following the second

NOP instruction. EEDATH and EEDATA will hold their

value until another read operation is initiated, or until

they are written by firmware.

The ste p s to rea din g the FLASH pro gram m em ory a re:

1. Write the address to EEADRH:EEADR. Make

sure that the address is not larger than the

memory size of the PIC16F870/871 devices.

2. Set the EEPGD bit to point to FLASH program

memory.

3. Set the RD bit to start the read operation.

4. Execute two NOP instructions to allow the

microcontroller to read out of program memory.

5. Read the data from the EEDATH:EEDATA

registers.

EXAMPLE 3-3: FLASH PROGRAM READ

3.6 Writing to the FLASH Program

Memory

Writing to FLASH program memory is unique, in that

the microcontroller does not execute instructions while

programming is taking place. The oscillator continues

to run and all peripherals continue to operate and

queue interrupts, if enabled. Once the write operation

completes (specification D133), the processor begins

executing code from where it left off. The other impor-

tant difference when writing to FLASH program mem-

ory is that the WRT configuration bit, when clear,

prevents any writ es to program memory (see Table 3-1).

Just lik e EEPROM data memory, there are many s teps

in writ ing to the FLASH program mem ory . Bot h address

and data values must be written to the SFRs. The

EEPGD bit must be set, an d the WREN bi t must be set

to enabl e writ es. The WREN bi t shou ld be k ept cl ear at

all times, except when writing to the FLASH program

memory. The WR bit can only be set if the WREN bit

was set in a previous operation (i.e., they both cannot

be set in the same operation). The WREN bit should

then be cleared by firmware after the write. Clearing the

WREN bit before the write actually completes will not

terminate the write in progress.

Writes to program memory must also be prefaced with

a special sequence of instructions that prevent inad-

vertent write operations. This is a sequence of five

ins tru cti o ns t h at mu st b e e xe cu t ed w it hou t i n ter r upt i on

for e ach byt e writ ten. These ins truct ions must th en be

follow ed by two NOP instructions to allow the microcon-

troller to setup f or the w rite op eratio n. Onc e the wri te is

complete, the execution of instructions starts with the

instruction after the second NOP.

The steps to write to program memory are:

1. Write the address to EEADRH:EEADR. Make

sure that the address is not larger than the

memory size of the PIC16F870/871 devices.

2. Write th e 14-bit da t a va lue to be prog ram me d i n

the EEDATH:EEDATA registers.

3. Set the EEPGD bit to point to FLASH program

memory.

4. Set the WREN bit to en able program operations.

5. Disable interrupts (if enabled).

6. Execute the special five instruction sequence:

• Write 55h to EEC ON2 in two s teps (fi rst to W ,

then to EECON2)

• Write AAh to EECON2 in two steps (fi rst to W ,

then to EECON2)

• Set the WR bit

7. Execute two NOP instructions to allow the

microcontroller to setup for write operation.

8. Enable interrupts (if using interrupts).

9. Clear the WREN bit to disable program

operations.

BSF STATUS, RP1 ;

BCF STATUS, RP0 ;Bank 2

MOVF ADDRL, W ;Write the

MOVWF EEADR ;address bytes

MOVF ADDRH,W ;for the desired

MOVWF EEADRH ;address to read

BSF STATUS, RP0 ;Bank 3

BSF EECON1, EEPGD ;Point to Program memory

BSF EECON1, RD ;Start read operation

NOP ;Required two NOPs

NOP ;

BCF STATUS, RP0 ;Bank 2

MOVF EEDATA, W ;DATAL = EEDATA

MOVWF DATAL ;

MOVF EEDATH,W ;DATAH = EEDATH

MOVWF DATAH ;

 2003 Microchip Technology Inc. DS30569B-page 31

PIC16F870/871

At the completion of the write cycle, the WR bit is

cleared and the EEIF interrupt flag bit is set. (EEIF

must be cleared by firmware.) Since the microcont roller

does not execute instructions during the write cy cle, the

firmware does not necessarily have to check either

EEIF, or WR, to determine if the write had finished.

EXAMPLE 3-4: FLASH PROGRAM WRITE

3.7 Write Verify

The PIC16F870/871 devices do not automatically ver-

ify the value written during a write operation. Depend-

ing on the appl ication, good programming prac tice ma y

dictate that the value written to memory be verified

agains t the origi nal value . This shoul d be used in appli-

cations where ex cessive w rites can stress bit s near th e

specified endurance limits.

3.8 Protection Against Spurious

Writes

There are conditions when the device may not want to

write to t he EEPROM d ata memory or FL ASH program

memory. To protect against these spurious write condi-

tions, various mechanisms have been built into the

PIC16F870/871 devices. On power-up, the WREN bit

is cleared and the Power-up Timer (if enabled)

prevents writes.

The wri te initiate sequenc e and the W REN bit toge ther ,

help prevent any accidental writes during brown-out,

power glitches, or firmware malfunction.

3.9 Operation While Code Protected

The PIC16F870/871 devices have two code protect

mechanisms, one bit for EEPROM data memory and

two bits for FLASH program memory. Data can be read

and written to the EEPROM data memory, regardless

of the state of the code protection bit, CPD. When code

protection is enabled and CPD cleared, external

access via ICSP is disabled, regardless of the state of

the program memory code protect bits. This prevents

the content s of EEPROM data memory from being read

out of the device.

The state of the program memory code protect bits,

CP0 and CP1, do not affect the execution of instruc-

tions out of program memory. The PIC16F870/871

devices can always read the values in program mem-

ory, regardless of the state of the code protect bits.

However, the state of the code protect bits and the

WR T bit will have dif ferent effec ts on writi ng to program

memory. Table 4-1 shows the ef fec t of the c ode prot ect

bits and the WRT bit on program memory.

Once code protection has been enabled for either

EEPROM data memory or FLASH program memory,

only a full erase of the entire device will disable code

protection.

BSF STATUS, RP1 ;

BCF STATUS, RP0 ;Bank 2

MOVF ADDRL, W ;Write address

MOVWF EEADR ;of desired

MOVF ADDRH, W ;program memory

MOVWF EEADRH ;location

MOVF VALUEL, W ;Write value to

MOVWF EEDATA ;program at

MOVF VALUEH, W ;desired memory

MOVWF EEDATH ;location

BSF STATUS, RP0 ;Bank 3

BSF EECON1, EEPGD ;Point to Program memor

BSF EECON1, WREN ;Enable writes

;Only disable interrupt

BCF INTCON, GIE ;if already enabled,

;otherwise discard

MOVLW 0x55 ;Write 55h to

MOVWF EECON2 ;EECON2

MOVLW 0xAA ;Write AAh to

MOVWF EECON2 ;EECON2

BSF EECON1, WR ;Start write operation

NOP ;Two NOPs to allow micr

NOP ;to setup for write

;Only enable interrupts

BSF INTCON, GIE ;if using interrupts,

;otherwise discard

BCF EECON1, WREN ;Disable writes

PIC16F870/871

DS30569B-page 32  2003 Microchip Technology Inc.

3.10 FLASH Program Memory Write

Protection

The configuration word contains a bit that write protects

the FLASH program memory, called WRT. This bit can

only be accessed when programming the

PIC16F870/871 devices via ICSP. Once write protec-

tion is enabled, only an erase of the entire device will

disabl e it. When enab led, write protection prevent s any

writes to FLASH program memory. Write protection

does not affect program memory reads.

TABLE 3-1: READ/WRITE STATE OF INTERNAL FLASH PROGRAM MEMORY

TABLE 3-2: REGISTERS ASSOCIATED WITH DATA EEPROM/PROGRAM FLASH

Configuration Bits Memory Location Internal

Read Internal

Write ICSP Read ICSP Write

CP1 CP0 WRT

00x Al l program memory Yes No No No

010 Unprotected areas Yes No Yes No

010 Protected areas Yes No No No

011 Unprotected areas Yes Yes Yes No

011 Protected areas Yes No No No

100 Unprotected areas Yes No Yes No

100 Protected areas Yes No No No

101 Unprotected areas Yes Yes Yes No

101 Protected areas Yes No No No

110 All program memory Yes No Yes Yes

111 All program memory Yes Yes Yes Yes

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

0Bh, 8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

10Dh E EAD R EEPROM Addres s Register, Low Byte xxxx xxxx uuuu uuuu

10Fh EEADRH — — — EEPROM Address, High Byte xxxx xxxx uuuu uuuu

10Ch EEDATA E EP RO M Data Register, Low Byte xxxx xxxx uuuu uuuu

10Eh EEDATH —— EEPROM Data Register, High Byte xxxx xxxx uuuu uuuu

18Ch EECON1 EEPGD — — — WRERR WREN WR RD x--- x000 x--- u000

18Dh EECO N2 E EPRO M Control Register2 (not a physical register) — —

Legend: x = unknown, u = unchanged, r = reserved, - = unimplemented, read as '0'.

Shaded cells are not used during FLASH/EEPROM access.

Note 1: These bits are reserved; always maintain these bits clear.

 2003 Microchip Technology Inc. DS30569B-page 33

PIC16F870/871

4.0 I/O P ORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

Addit ion al inf orm atio n o n I/O por t s ma y be foun d i n th e

PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023).

4.1 PORTA and the TRISA Register

PORTA is a 6-bit wide bi-directional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (= 1) will make the corresponding PORT A pin

an input (i.e., put the corresponding output driver in a

Hi-Impedance mode). Clearing a TRISA bit (= 0) will

make the correspon ding POR TA pin an out put (i.e., put

the contents of the output latch on the selected pin).

Reading the PORT A register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. Therefore,

a write to a port implies that the port pins are read, the

value is modified and the n written to the port dat a la tch.

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin. The RA4/T0CKI

pin is a Schm itt Trigger inp ut and an ope n dr ain o utput.

All other PORTA pins have TTL input levels and full

CMOS output drivers.

Other PORTA pins are multiplexed with analog inputs

and analog VREF input. The operation of each pin is

selected by clearing/setting the control bits in the

ADCON1 register (A/D Control Register 1).

The TRISA register controls the direction of the RA

pins, ev en when they are be ing us ed as ana lo g inputs .

The user mu st ensure the bit s in the TRISA regi ster are

maintained set when using t hem as analog inputs.

EXAMPLE 4-1: INITIALIZING PORTA

FIGU RE 4-1 : BLOCK DI AGR AM OF

RA3:RA0 AND RA5 PINS

FIGU RE 4-2 : BLOCK DI AGR AM OF

RA4/T0CKI PIN

Note: On a Power-on Reset, these pins are

configured as analog inputs and read as

'0'.

BCF STATUS, RP0 ;

BCF STATUS, RP1 ;Bank0

CLRF PORTA ;Initialize PORTA by

;clearing output

;data latches

BSF STATUS, RP0 ;Select Bank 1

MOVLW 0x06 ;Configure all pins

MOVWF ADCON1 ;as digital inputs

MOVLW 0xCF ;Value used to

;initialize data

;direction

MOVWF TRISA ;Set RA<3:0> as

;inputs

;RA<5:4> as outputs

;TRISA<7:6> are

;always read as '0'.

Data

Bus

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VSS

VDD

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Analog

Input

Mode

TTL

Input

Buffer

To A/D Converter

Data

Bus

PORT

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

VSS

I/O pin(1)

TMR0 Clock Input

Note 1: I/O pin has protection diodes to VSS only.

PIC16F870/871

DS30569B-page 34  2003 Microchip Technology Inc.

TABLE 4-1: PORTA FUNCTIONS

TABLE 4-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input.

RA1/AN1 bit1 TTL Input/output or analog input.

RA2/AN2 bit2 TTL Input/output or analog input.

RA3/AN3/VREF bit3 TTL Input/output or analog input or VREF.

RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type.

RA5/AN4 bit5 TTL Input/output or analog input.

Legend: TTL = TTL input, ST = Schmit t Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

05h PORTA —— RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000

85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111

9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.

Shaded cells are not used by PORTA.

 2003 Microchip Technology Inc. DS30569B-page 35

PIC16F870/871

4.2 PORTB and the TRISB Register

PORTB is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a Hi- Imp ed a nc e m od e ). C l e ari ng a T RI SB bi t (= 0) will

make the co rresponding POR TB pin an output (i.e., put

the contents of the output latch on the selected pin).

Three pins of PORTB are multiplexed with the Low

Voltage Programming function: RB3/PGM, RB6/PGC

and RB7/PGD. The alternate functions of these pins

are described in the Specia l Featu res Sectio n.

Each of th e POR TB pins has a we ak inte rnal pul l-up. A

single control bit can turn on all the pull-ups. This is per-

formed by clearing bit RBPU (OPTION_REG<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

FIGU RE 4-3 : BLOCK DI A GR AM OF

RB3:RB0 PINS

Four of POR TB’s pi ns, RB7:RB4, hav e an interrupt-o n-

change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RB Port Change

Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The

user, in the Interrupt Service Routine, can clear the

interr upt in the foll owin g man ner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF.

A mism at c h c ond it i on wi ll co nti n ue to s et f lag bi t RB IF.

Reading PORTB will end the mismatch condition and

allow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

This interrupt on mismatch feature, together with soft-

ware configurable pull-ups on these four pins, allow

easy interface to a keypad and make it possible for

wake-up on key-depression. Refer to the Embedded

Control Handbook, “Implementing Wake-up on Key

Stroke” (AN552).

RB0/INT is an external interrupt input pin and is

configured using the INTEDG bit (OPTION_REG<6>).

RB0/INT is discussed in detail in Section 11.10.1.

FIGU RE 4-4 : BLOCK DI AGR AM OF

RB7:RB4 PINS

Data Latch

RBPU(2) P

VDD

Data Bus

WR Port

WR TRIS

RD TRIS

RD Port

Weak

Pull-up

RD Port

RB0/INT

I/O pin(1)

TTL

Input

Buffer

Schmitt Trigger

Buffer

TRIS Latch

Note 1: I/O pins have diode protection to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (OPTION_REG<7>).

RB3/PGM

Data Latch

From other

RBPU(2) P

VDD

I/O pin(1)

Data Bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

Weak

Pull-up

RD Port

Latch

TTL

Input

Buffer ST

Buffer

RB7:RB6 in Serial Programming Mode Q3

Note 1: I/O pins have diode protecti on to VDD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (OPTION_REG<7>).

PIC16F870/871

DS30569B-page 36  2003 Microchip Technology Inc.

TABLE 4-3: PORTB FUNCTIONS

TABLE 4-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software

programmable weak pull-up.

RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.

RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.

RB3/PGM bit3 TTL/ST(1) Input/output pin or programming pin in LVP mode. Internal software

programmable weak pull-up.

RB4 bit4 TTL Input/output pi n (with interrupt-on -change). Interna l software programm able

weak pull-up.

RB5 bit5 TTL Input/output pi n (with interrupt-on -change). Interna l software programm able

weak pull-up.

RB6/PGC bit6 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.

Internal software programmable weak pull-up. Serial programming clock.

RB7/PGD bit7 TTL/ST(2) Input/output pin (with interrupt-on-change) or In-Circuit Debugger pin.

Internal software programmable weak pull-up. Serial programming data.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt or LVP mode.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value o n:

POR, BOR

Value on

all othe r

RESETS

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu

86h, 186h TRISB PO RTB Data Direction Register 1111 1111 1111 1111

81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

 2003 Microchip Technology Inc. DS30569B-page 37

PIC16F870/871

4.3 PORTC and the TRISC Register

PORTC is an 8-bit wide, bi-directional port. The corre-

sponding data direction register is TRISC. Setting a

TRISC bit (= 1) will make the corresponding PORTC

pin an input (i.e., put the corresponding output driver in

a Hi-Impedance mode). Clearing a TRISC bit (= 0) will

make th e corresponding PO RTC pin an output (i.e., put

the contents of the output latch on the selected pin).

PORT C is multip lexed with s everal periphe ral function s

(Table 4-5). PORTC pins have Schmitt Trigger input

buffers.

When enabling peripheral functions, care should be

taken in defini ng TRIS bit s fo r each POR TC pin. Some

peripherals override the TRIS bit to make a pin an out-

put, while other peripherals override the TRIS bit to

make a pin an input. Since the TRIS bit override is in

effect while the peripheral is enabled, read-modify-

write instructions (BSF, BCF, XORWF) with TRISC as

the destination should be avoided. The user should

refer to the corresponding peripheral section for the

correct TRIS bit settings.

FIGURE 4-5: PORTC BLOCK DIAGRAM

(PERIPHERAL OUTPUT

OVER RI DE )

TABLE 4-5: PORTC FUNCTIONS

TABLE 4-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Port/Peripheral Select(2)

Data Bus

PORT

TRIS

Data Latch

TRIS Latch

RD TRIS Schmitt

Trigger

Peripheral Data Out 0

VDD

Vss

PORT

Peripheral

OE(3)

Peripheral Input

I/O

pin(1)

Note 1: I/O pins have diode protection to VDD and VSS.

2: Port/Peripheral Select signal selects between

port data and peripheral output.

3: Peripheral OE (Output Enable) is only activated

if Peripheral Select is active.

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input.

RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input.

RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/

PWM1 output.

RC3 bit3 ST Input/output port pin.

RC4 bit4 ST Input/output port pin.

RC5 bit5 ST Input/output port pin.

RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or

Synchrono us D at a.

Legend: ST = Schmitt T rigg er inpu t

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged

PIC16F870/871

DS30569B-page 38  2003 Microchip Technology Inc.

4.4 PORTD and TRISD Registers

This section is not applicable to the PIC16F870.

PORTD is an 8-bit port with Schmitt Trigger input buff-

ers. Each pin is indivi du all y co nfig ura ble as an inp ut or

output.

PORTD can be configured as an 8-bit wide micropro-

cessor port (parallel slave port) by setting control bit

PSPMODE (TRISE<4>). In this mod e, the input buffe rs

are TTL.

FIGURE 4-6: PORTD BLOCK DIAGRAM

(IN I/ O PORT MODE )

TABLE 4-7: PORTD FUNCTIONS

TABLE 4-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Data

Bus

Port

TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

Input

Buffer

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Name Bit# Buffer Type Function

RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0.

RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1.

RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2.

RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3.

RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4.

RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5.

RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6.

RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7.

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all othe r

RESETS

08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu

88h TRISD PORTD Data Direction Register 1111 1111 1111 1111

89h TRISE IBF OBF IBOV PSPMODE —PORTE Data Dir e ction Bi ts 0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.

 2003 Microchip Technology Inc. DS30569B-page 39

PIC16F870/871

4.5 PORTE and TRISE Register

This section is not applicable to the PIC16F870.

PORTE has three pins, RE0/RD/AN5, RE1/WR/AN6

and RE2/CS/AN7, which are individually configurable

as inputs or outputs. These pins have Schmitt Trigger

input buffers.

I/O PORTE becomes control inputs for the micropro-

cessor port when bit PSPMODE (TRISE<4>) is set. In

this mode, the user must make sure that the

TRISE<2:0> bits are set (pins are configured as digital

input s). Ensure ADCO N1 is configure d for digital I/O. In

this mode, the input buffers are TTL.

controls the parallel slave port operation.

PORTE pins are multiplexed with analog inputs. When

select ed as an a nalog input, these pins wi ll read as '0 's.

TRISE controls the direction of the RE pins, even when

they are being used as analog inputs. The user must

make sure to keep the pins configured as inputs when

using them as analog inputs.

FIGU RE 4-7 : PORTE B LOCK DI AGR AM

(IN I/ O PO RT MODE )

Note: On a Power-on Reset, these pins are

configured as analog inputs.

Data

Bus

PORT

TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt

Trigger

input

buffer

I/O pin(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

PIC16F870/871

DS30569B-page 40  2003 Microchip Technology Inc.

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1

IBF OBF IBOV PSPMODE — Bit2 Bit1 Bit0

bit 7 bit 0

bit 7 Parallel Slave Port Status/Control Bits

IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU

0 = No word has been received

bit 6 OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word

0 = The output buffer has been read

bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1 = A write occurred when a previously input word has not been read

(must be cleared in software)

0 = No overflow occurred

bit 4 PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel Slave Port mode

0 = General Purpose I/O mode

bit 3 Unimplemented: Read as '0'

PORTE Data Direction Bits

bit 2 Bit2: Direction Control bit for pin RE2/CS/AN7

1 = Input

0 = Output

bit 1 Bit1: Direction Control bit for pin RE1/WR/AN6

1 = Input

0 = Output

bit 0 Bit0: Direction Control bit for pin RE0/RD/AN5

1 = Input

0 = Output

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30569B-page 41

PIC16F870/871

TABLE 4-9: PORTE FUNCTIONS

TABLE 4-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit# Buffer Type Function

RE0/RD/AN5 bit0 ST/TTL(1) Input/out put port pin or read contro l input in Parallel Sla ve Port mode or

analog input:

1 = Not a read operation

0 = Read operation. Reads PORTD register (if chip selected.)

RE1/WR/AN6 bit1 ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode

or analog input:

1 = Not a write operation

0 = Write operation. Writes PORTD register (if chip selected).

RE2/CS/AN7 bit2 ST/TTL(1) Input/output port pin or chip select control input in Parallel Slave Port

mode or analog input:

1 = Device is not selected

0 = Device is selected

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

Addr Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Val ue on:

POR, BOR

Value on

all other

RESETS

09h PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu

89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111

9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.

PIC16F870/871

DS30569B-page 42  2003 Microchip Technology Inc.

4.6 Parallel Slave Port

The Parallel Slave Port is not implemented on the

PIC16F870.

PORT D operates as an 8-bit wide Parallel Slave Port or

microprocessor port when control bit PSPMODE

(TRISE<4> ) i s se t. I n Sl av e mode, it is a sy nchro nou sly

readable and writa ble by the extern al world throu gh RD

control input pin RE0/RD and WR control input pin

RE1/WR.

It can directl y int erfa ce to an 8-bi t mic rop roc es sor dat a

bus. The extern al mic roproc essor can read or w rite th e

PORTD latch as an 8-bit latch. Setting bit PSPMODE

enables port pin RE0/RD to be the RD input, RE1/WR

to be the WR input and RE2/CS to be the CS (chip

select) input. For this functionality, the corresponding

data direction bits of the TRISE register (TRISE<2:0>)

must be configured as inputs (set ). The A/D port confi g-

uration bits PCFG3:PCFG0 (ADCON1<3:0>) must be

set to configure pins RE2:RE0 as digital I/O.

There are actually two 8-bit latches. One for data out-

put and one for data input. The user writes 8-bit data to

the POR TD da ta la tch and reads dat a from the port pin

latch (note that they have the same address). In this

mode, the TRISD register is ignored, since the

microp roc ess or is co ntro lli ng the dire ction of data flow.

A write to the PSP occurs when both the CS and WR

lines are first detected low. When either the CS or WR

lines become hi gh (level triggered ), the Input Buffer Full

(IBF) status flag bit (TRISE<7>) is set on the Q4 clock

cycle, following the next Q2 cycle, to signal the write is

complete (Figure 4-9). The interrupt flag bit, PSPIF

(PIR1<7>), is also set on the same Q4 clock cycle. IBF

can onl y be cleare d b y re adi ng the PO R TD i npu t l atc h.

The Input Buffer Overflow (IBOV) status flag bit

(TRISE<5>) is set if a second write to the PSP is

attempted when the previous byte has not been read

out of the buffer.

A read from t he PSP occurs when both the CS and R D

lines are first detected low. The Output Buffer Full

(OBF) status flag bit (TRISE<6>) is cleared immedi-

ately (Figure 4-10), indicating that the PORTD latch is

waitin g to be read by the ext ernal bus. Whe n eithe r the

CS or RD pin be co me s hi gh ( lev el trigg ere d), the inter-

rupt flag bit PSPIF is set on the Q4 clock cycle, follow-

ing the next Q2 cycle, indicating that the read is

complete. OBF remains low until data is written to

PORTD by the user firmware.

When not in PSP mo de, the IBF and OB F b it s are hel d

clear. However, if flag bit IBOV was previously set, it

must be cleared in firmware.

An interrupt is generated and latched into flag bit

PSPIF when a read or write operation is completed.

PSPIF must be cleared by the us er in fi rmware and th e

interrupt can be disabled by clearing the interrupt

enable bit PSPIE (PIE1<7> ).

FIGURE 4-8: PORTD AND PORTE

BLOC K DIAG RAM

(PARALLEL SLAVE PORT)

Data Bus

Port

RDx

Port

One bit of PORTD

Set Interrupt Flag

PSPIF (PIR 1<7>)

Read

Chip Select

Write

Note: I/O pin has protection diodes to VDD and VSS.

TTL

 2003 Microchip Technology Inc. DS30569B-page 43

PIC16F870/871

FIGURE 4-9: PARALLEL SLAVE PORT WRITE WAVEFORMS

FIGURE 4-10: PARALLEL SLAVE PORT READ W AVEFORMS

TABLE 4-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all othe r

RESETS

08h PORTD P ort Data Latch when written: Port pins when read xxxx xxxx uuuu uuuu

09h PORTE — — — — —RE2RE1RE0---- -xxx ---- -uuu

89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111

0Ch PIR1 PSPIF ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

9Fh ADCON1 ADFM — — — PCFG3 PCFG2 PCFG1 PCFG0 --0- 0000 --0- 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port.

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

OBF

PSPIF

PORTD<7:0>

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

PSPIF

OBF

PORTD<7:0>

PIC16F870/871

DS30569B-page 44  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 45

PIC16F870/871

5.0 TIMER0 MODULE

The Timer0 module timer/counter has the following

features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 5-1 is a bl ock diagram of the T imer0 m odule and

the prescaler shared with the WDT.

Additional information on the Timer0 module is avail-

able in the PICmicro™ Mid-Range MCU Family

Reference Manual (DS33023).

Timer mode is selected by clearing bit T0CS

(OPTION_REG<5>). In Timer mode, the Timer0 mod-

ule wi ll i ncr em en t ev ery ins truction cy cle (w ith ou t pre s-

caler). If the TMR0 register is written, the increment is

inhibited for the following two instruction cycles. The

user can work around this by writing an adjusted value

to the TMR0 register.

Counter mode is selected by setting bit T0CS

(OPTION_REG<5>). In Counter mode, Timer0 will

increment either on every rising, or falling edge of pin

RA4/T0CKI. The incrementing edge is determined by

the Timer0 Source Edge Select bit, T0SE

(OPTION_REG<4>). Clearing bit T0SE selects the ris-

ing edge. Restrictions on the external clock input are

discussed in detail in Section 5.2.

The prescaler is mutually exclusively shared between

the Timer0 modu le and t he W a tchdo g T im er. The pres -

caler i s not readabl e or wr it able. Sectio n 5.3 det ails the

operation of the prescaler.

5.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 reg-

ister overflows from FFh to 00h. This overflow sets bit

T0IF (INTCON<2>). The interrupt can be masked by

clearing bit T0IE (INTCON<5>). Bit T0IF must be

cleared in software by the T imer0 modul e Interrupt Ser-

vice Routine before re-enabling this interrupt. The

TMR0 interrupt cannot awaken the processor from

SLEEP, since the timer is shut-off during SLEEP.

FIGU RE 5-1 : BLOC K DI A GR AM OF T H E TIMER0/W DT P RESCALE R

RA4/T0CKI

T0SE

CLKO (= FOSC/4)

SYNC

Cycles TMR0 Reg

8-bit Prescaler

8 - to - 1MUX

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

Data Bus

Set Flag Bit T0IF

on Overflow

PSA

T0CS

PRESCALER

PIC16F870/871

DS30569B-page 46  2003 Microchip Technology Inc.

5.2 Using Timer0 with an External

Clock

When no pr escal er is used, t he ex tern al clo ck inp ut is

the same as the pre sc al er outp ut. Th e sy nch ron iz atio n

of T0CKI with the internal phase clocks is accom-

plishe d by sampling the prescale r output on the Q2 and

Q4 cycles of the internal phase clocks. Therefore, it is

necess ary fo r T0CKI t o b e high fo r at least 2 TOSC (and

a small RC delay of 20 ns) and low for at least 2 TOSC

(and a small RC delay of 20 ns). Refer to the electrical

specification of the desired device.

5.3 Prescaler

There is only one pr escaler availab le, which is m utually

exclus ively shar ed between the T imer0 module and the

Watchdog Timer. A prescaler assignment for the

T i mer0 m odule m eans that t here i s no presc aler fo r the

Watchdog Timer, and vice-versa. This prescaler is not

readable or writable (see Figure 5-1).

The PSA and PS2:PS0 bits (OPTION_REG<3:0>)

determine the presca ler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing to the TMR0 register (e.g., CLRF1, MOVWF1,

BSF1,x....etc.) will clear the prescal er . Wh en assigne d

to WDT, a CLRWDT instruction will clear the prescaler

along with the Watchdog Timer. The prescaler is not

readable or writable.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0, will clear the

prescaler count, but will not change the

prescaler assignment.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU

bit 6 INTEDG

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin

0 = Internal instruction cycle clock (CLKO)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin

0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT

0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note: To avoid an unintende d device RESET, the instr uction sequence shown in the PICmicro™ Mid-Ra nge MCU

Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from

Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

1 : 1

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

Bit Value TMR0 Rate WDT Rate

 2003 Microchip Technology Inc. DS30569B-page 47

PIC16F870/871

TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

01h,101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu

0Bh,8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'.

Shaded cells are not used by Timer0.

PIC16F870/871

DS30569B-page 48  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 49

PIC16F870/871

6.0 TIMER1 MODULE

The Timer1 module is a 16-bi t tim er/c ou nter cons is tin g

of two 8-bit registers (TMR1H and TMR1L), which are

readable and writable. The TMR1 register pair

(TMR1H:TMR1L) increments from 0000h to FFFFh

and rol ls over to 0000h. Th e TMR1 inter rupt, if e nabled,

is generated on overflow, which is latched in interrupt

flag bit, TMR1IF (PIR1<0>). This interrupt can be

enabled/disabled by setting/clearing TMR1 interrupt

enable bit, TMR1IE (PIE1<0>).

Timer1 can operate in one of two modes:

•As a timer

•As a counter

The Operating mode is determined by the clock select

bit, TMR1CS (T1CON<1>).

In Timer mode, Timer1 increments every instruction

cycle. In Counter mode, it increments on every rising

edge of the external clock input.

Timer1 can be enabled/disabled by setting/clearing

control bit, TMR1ON (T1CON<0>).

Timer1 also has an internal “RESET input”. This

RESET can be generated by either of the two CCP

modules (Section 8.0). Register 6-1 shows the Timer1

control regi ster.

When the Timer1 oscillator is enabled (T1OSCEN is

set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins

become inputs. That is, the TRISC<1:0> value is

ignored, and these pins read as ‘0’.

Additional information on timer modules is available in

the PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023).

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value

10 = 1:4 Prescale value

01 = 1:2 Prescale value

00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabl ed

0 = Osci llator is shut-off (the oscilla tor i nverter is turned off to eliminate p ower drai n)

bit 2 T1SYNC: Timer1 External Clock Input Synchronization Control bit

When TMR1CS = 1:

1 = Do not synchronize external clock input

0 = Synchronize external clock input

When TMR1CS = 0:

This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)

0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer 1 On bit

1 = Enables Timer1

0 = Stops Timer1

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F870/871

DS30569B-page 50  2003 Microchip Technology Inc.

6.1 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS

(T1CON<1>) bit. In this mode, the input clock to the

timer is FOSC/4. The synchronize control bit, T1SYNC

(T1CON<2>), has no effect, since the internal clock is

always in sync.

6.2 Timer1 Counter Operation

Timer1 may operate in either a Synchronous, or an

Asynchronous mode, depending on the setting of the

TMR1CS bit.

When Timer1 is being incremented via an external

source, increments occur on a ri sing edge. After T imer1

is enab led in Coun ter mode, the module must fi rst have

a falling edge before the counter begins to increment.

FIGURE 6-1: TIMER1 IN CREMENTIN G ED GE

6.3 Timer1 Operat ion in Synchronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In

this mod e, the timer incr ement s on every risin g edge of

clock input on pin RC1/T1OSI, when bit T1OSCEN is

set, or on pi n RC 0/ T1O SO/T1C KI , when bi t T1O SC EN

is cl eare d.

If T1SYNC is cleared, then the external clock input is

synchronized with internal phase clocks. The synchro-

nization is done after the prescaler stage. The

prescaler stage is an asynchronous ripple counter.

In this configuration, during SLEEP mode, Timer1 will

not increment even if the external clock is present,

since the synchronization circuit is shut-off. The

prescaler, however, will contin ue to increment.

FIGU RE 6-2: TI MER 1 BLOCK DIAG RAM

T1CKI

(Default High)

T1CKI

(Default Low)

Note: Arrows indicate counter increments.

TMR1H TMR1L

T1OSC T1SYNC

TMR1CS

T1CKPS1:T1CKPS0 Q Clock

T1OSCEN

Enable

Oscillator(1)

FOSC/4

Internal

Clock

TMR1ON

On/Off

Prescaler

1, 2, 4, 8 Synchronize

det

Synchronized

Clock Input

RC0/T1OSO/T1CKI

RC1/T1OSI

Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.

Set Flag bit

TMR1IF on

Overflow TMR1

 2003 Microchip Technology Inc. DS30569B-page 51

PIC16F870/871

6.4 Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external

clock input is not synchronized. The timer continues to

increment asynchronous to the internal phase clocks.

The timer will continue to run during SLEEP and can

generate an interrupt-on-overflow, which will wake-up

the processor. However, special precautions in

software are needed to read/write the timer

(Section 6.4.1).

In Asynchronous Counter mode, Timer1 cannot be

used as a time base for capture or compare operations.

6.4.1 READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running

from an external asynchronous clock, will ensure a

valid read (taken care of in hardware). However, the

user shoul d keep i n mind that r eadi ng the 16-b it time r

in two 8-b it va lu es i t self, pose s c ert a in pro bl em s, s inc e

the timer may overflow between the reads.

For write s, it is re commend ed that the us er simply stop

the timer and write the desired values. A write conten-

tion may occur by writing to the timer registers, while

the register is incrementing. This may produce an

unpredictable value in the timer registe r.

Reading the 16-bit value requires some care.

Exampl es 12-2 an d 12-3 in the PICmicro™ Mid -Range

MCU Family Reference Manual (DS33023) show how

to read and write Timer1 when it is running in

Asynchronous mode.

6.5 Timer1 Oscillator

A crystal oscillator circuit is built-in between pins T1OSI

(input) and T1OSO (amplifier output). It is enabled by

setting control bit, T1OSCEN (T1CON<3>). The oscil-

lator is a low power oscillator, rated up to 200 kHz. It will

continue to run during SLEEP. It is primarily intended

for use with a 32 kHz crystal. Table 6-1 shows the

capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator.

The user m us t pro vi de a sof tware time delay to en su re

proper oscillator start-up.

T ABLE 6-1: CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

6.6 Resetting Ti mer 1 Using a CCP

Trigger Output

If the CCP1 module is configured in Compare mode to

generate a “special event trigger” (CCP1M3:CCP1M0

= 1011), this signal will reset Timer1.

T imer 1 must be co nfigured fo r either T i mer or Synch ro-

nized Counter mode to take advantage of this feature.

If Timer1 is running in Asynchronous Counter mode,

this RESET operation may not work.

In the event that a write to Timer1 coincides with a

special event trigger from CCP1, the write will take

precedence.

In this mode of operation, the CCPRH:CCPRL register

pair ef fectivel y becomes the period reg ister for T imer1.

Osc Type Freq. C1 C2

LP 32 kHz 33 pF 33 pF

100 k Hz 15 pF 15 pF

200 k Hz 15 pF 15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM

100 kHz Epson C-2 100.00 KC-P ± 20 PPM

200 kHz STD XTL 200.000 kHz ± 20 PPM

Note 1: Higher capacitance increases the st a bility

of oscilla tor, but also increases the s t art-up

time.

2: Since each resonator/cryst al has its own

characteristics, the use r should con sult the

resonator/crysta l manufac turer for

appropriate valu es of external component s.

Note: The special event triggers from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

PIC16F870/871

DS30569B-page 52  2003 Microchip Technology Inc.

6.7 Resetting of Ti mer1 Register Pair

(TMR1H, TMR1L)

TMR1H an d TMR1L reg isters are not rese t to 00h on a

POR, or any o ther RESET, except by the CCP1 special

event trigger.

T1CON register is reset to 00h on a Power-on Reset,

or a Brown-out Reset, which shuts off the timer and

leaves a 1:1 prescale. In all other RESETS, the register

is unaffected.

6.8 Timer1 Prescaler

The prescaler counter is cleared on writes to the

TMR1H or TMR1L registers.

TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

0Bh,8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

0Eh T MR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the T imer1 module.

Note 1: B i ts PSPIE and PSPIF are reserv ed on the PIC16F870; always maintain these bits clear.

 2003 Microchip Technology Inc. DS30569B-page 53

PIC16F870/871

7.0 TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a

post scaler . It can be used as the PWM time base for the

PWM mode of the CCP module(s). The TMR2 register

is readable and writable, and is cleared on any device

RESET.

The input clock (FOSC/4) has a prescale option of 1:1,

1:4, or 1:16, selected by control bits

T2CKPS1:T2CKPS0 (T2CON<1: 0>).

The Timer2 module has an 8-bit period register, PR2.

Timer2 increments from 00h until it matches PR2 and

then resets to 00h on the next increment cycle. PR2 is

a readable and writable register. The PR2 register is

initialized to FFh upon RESET.

The match output of TMR2 goes through a 4-bit

postscaler (which gives a 1:1 to 1:16 scaling inclusive)

to generate a TMR2 interrupt (latched in flag bit

TMR2IF (PIR1<1>)).

T imer2 can b e shut-of f by clearing control bit, T MR2ON

(T2CON<2>), to mini mize power consumpti on.

Additional information on timer modules is available in

the PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023).

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets Fla g

TMR2 Reg

Output(1)

RESET

Postscaler

Prescaler

PR2 Reg

FOSC/4

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

Note 1: TMR2 register output can be software selected by the

SSP module as a baud clock.

T2OUTPS3:

T2OUTPS0

T2CKPS1:

T2CKPS0

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

bit 7 Unimplemented: Read as '0'

bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale

0001 = 1:2 Postscale

0010 = 1:3 Postscale

•

1111 = 1:16 P ostscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on

0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Pres caler is 1

01 = Pres caler is 4

1x = Prescaler is 16

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F870/871

DS30569B-page 54  2003 Microchip Technology Inc.

7.1 Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared

when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device RESET (POR, MCLR Reset, WDT

Reset, or BOR)

TMR2 is not cleared when T2CON is written.

7.2 Output of TMR2

The output of TMR2 (before the postscaler) is fed to the

SSP module, which optionally uses it to generate shift

clock.

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

0Bh,8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

11h TMR2 T imer2 Module’s Register 0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

92h PR2 Timer2 Period Register 1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module.

Note 1: B i ts PSPIE and PSPIF are reserv ed on the PIC16F870; always maintain these bits clear.

 2003 Microchip Technology Inc. DS30569B-page 55

PIC16F870/871

8.0 CAPTURE/COMPARE/ PWM

MODULES

Each Capture/Compare/PWM (CCP) module contains

a 16-bit register which can operate as a:

• 16-bit Capture register

• 16-bit Compare register

• PWM Master/Slave Duty Cycle register

Ta ble 8- 1 shows th e resourc es and i nteract ions of the

CCP mod ule. In the followin g sections , the operati on of

a CCP module is described.

8.1 CCP1 Module

Capture/Compare/PWM Register1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. The special event trigger is

generated by a compare match and will reset Timer1

and start an A/D conversion (if the A/D module is

enabled).

Additional information on CCP modules is available in

the PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023) and in application note AN594,

“Using the CCP Modules” (DS00594).

TABLE 8-1: CCP MODE - TIMER

RESOURCES REQUIRED

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1

Timer2

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

—— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0

bit 7 bit 0

bit 7-6 Unimplemented: Read as '0'

bit 5-4 CCP1X:CCP1Y: PWM Least Signi ficant bits

Capture mode:

Unused

Compare mode:

Unused

PWM mode:

These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPR1L.

bit 3-0 CCP1M3:CCP1M0: CCP1 Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCP1 module)

0100 = Capture mode, ev ery fal lin g edge

0101 = Capture mode, ev ery ris ing edge

0110 = Capture mode, ev ery 4th rising edge

0111 = Capture mode, ev ery 16t h risin g edge

1000 = Compare mode, set output on match (CCP1IF bit is set)

1001 = Compare mode, clear output on match (CCP1IF bit is set)

1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is

unaffected)

1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected);

CCP1resets TMR1, and starts an A/D conversion (if A/D module is enabled)

11xx = PWM mode

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F870/871

DS30569B-page 56  2003 Microchip Technology Inc.

8.2 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the

16-bit val ue of the TMR1 register when an event occu rs

on pin RC2/CCP1. An event is defined as one of the

following:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

The type of event is configured by control bits

CCP1M3:CCP1M0 (CCP1CON<3:0>). When a cap-

ture is made, the interrupt request flag bit CCP1IF

(PIR1<2>) is set. The interrupt flag must be cleared in

software. If another capture occurs before the value in

overwritten by the new value.

8.2.1 CCP PIN CONFIGURATION

In Capture mode, the RC2/CCP1 pin should be

configured as an input by setting the TRISC<2> bit.

FIGURE 8-1: CAPTURE MODE

OPER ATI ON BLO CK

DIAGRAM

8.2.2 TIMER1 MODE SELECTION

Timer1 must be running in Timer mode, or Synchro-

nized Counter mode, for the CCP module to use the

capture feature. In Asynchronous Counter mode, the

capture operation may not work.

8.2.3 SOFTWARE INTERRUPT

When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit

CCP1IE (PIE1<2>) clear to avoid false interrupts and

should clear the flag bit, CCP1IF, following any such

change in Operating mode .

8.2.4 CCP PRESCALER

There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is

turned off, or the CCP module is not in Capture mode,

the prescaler counter is cleared. Any RESET will clear

the prescaler counter.

Switching from one capture prescaler to another may

generate an interrupt. Also, the prescaler counter will

not be cleare d, therefore , the first cap ture may be from

a non-zero prescaler. Example 8-1 shows the recom-

mended method for switching between capture pres-

calers. This example also clears the prescaler counter

and will not generate the “false” interrupt.

EXAMPLE 8-1: CHANGING BETWEEN

CAPTURE PRESCALERS

Note: If the RC2/CCP1 pin is configured as an

output, a write to the port can cause a

capture co ndition.

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

(PIR1<2>)

Capture

Enable

Qs CCP1CON<3:0>

RC2/CCP1

Prescaler

÷ 1, 4, 16

and

Edge Dete ct

pin CLRF CCP1CON ; Turn CCP module off

MOVLW NEW_CAPT_PS ; Load the W reg with

; the new prescaler

; move value and CCP ON

MOVWF CCP1CON ; Load CCP1CON with this

; value

 2003 Microchip Technology Inc. DS30569B-page 57

PIC16F870/871

8.3 Compare Mode

In C ompare mo de, t he 16- bit CC PR1 re gist er va lue is

constantly compared against the TMR1 register pair

value. Whe n a match occu rs, the RC2/CCP1 pin is:

• Driven high

•Driven low

• Remains unchanged

The action on the pin is based on the value of control

bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the

same time, interrupt flag bit CCP1IF is set.

FIGURE 8-2: COMPARE MODE

OPER ATI ON BLO CK

DIAGRAM

8.3.1 CCP PIN CONFIGURATION

The user must configure the RC2/CCP1 pin as an

output by clearing the TRISC<2> bi t.

8.3.2 TIMER 1 MODE SELECTION

Timer1 must be running in Timer mode, or Synchro-

nized Counter mode, if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

8.3.3 SOFTWARE INTERRUPT MODE

When Generate Software Interrupt mode is chosen , the

CCP1 pin is n ot af fected. Th e CCPIF bit is set, caus ing

a CCP interrupt (if enabled).

8.3.4 SPECIAL EVENT TRIGGER

In this mod e, an internal hardw are trigger is generated,

which may be used to initiate an action.

The special event trigger output of CCP1 resets the

TMR1 register p air , and st arts an A/D conversion (if A/D

module is enabled). This allows the CCPR1 register to

effect iv ely be a 16 -bit programma ble peri od regis ter for

Timer1.

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare output latch to

the default low level. This is not the

PORTC I/O data latch.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

ROutput

Logic

Special Event Trigger

Set Flag bit CCP1IF

(PIR1<2>)

Match

RC2/CCP1

TRISC<2> CCP1CON<3:0>

Mode Select

Output Enable

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),

and set bit GO/DONE (ADCON0<2>).

Note: The special event trigger from the CCP1

module will not set interrupt flag bit

TMR1IF (PIR1<0>).

PIC16F870/871

DS30569B-page 58  2003 Microchip Technology Inc.

8.4 PWM Mode (PWM)

In Pulse Width Modulation mode, the CCP1 pin pro-

duces up to a 10-bit resolution PWM output. Since the

CCP1 pin is mul tiplexed with the PORTC data latch, the

TRISC<2> bit must be cleared to make the CCP1 pin

an output.

Figure 8-3 shows a simplified block diagram of the

CCP module in PWM mo de.

For a ste p-by-step proc edure on how t o set up the CC P

module for PWM operation, see Section 8.4.3.

FIGURE 8-3: SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 8-4) has a time base (period)

and a time that the output stays high (duty cycle). The

frequency of the PWM is the inverse of the period

(1/period).

FIGURE 8-4: PWM OUTPUT

8.4.1 PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

PWM period = [(PR2) + 1] • 4 • TOSC •

(TMR 2 pr e sc ale value)

PWM frequency is defined as 1 / [PWM period].

When TM R2 is equal to PR2, t he following three event s

occur on the next increment cycle:

•TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

• The PWM duty cycle is latched from C CPR1L into

CCPR1H

8.4.2 PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10- b i t re so l uti on is av ai l ab le. T he CC PR 1 L c ontai ns

the eight MSbs and the CCP1CON<5:4> contains the

two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

TOSC • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

The CCPR1H register and a 2-bit internal latch are

used to dou ble buf fer th e PWM duty cycle. Thi s doubl e

buffering is essential for glitch-free PWM operation.

When the CCPR1H and 2-bit latch match TMR2, con-

catenate d with an in terna l 2-b it Q clo ck , or 2 bits of the

TMR2 pres caler, the CCP1 pin i s cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the formula:

Note: Clearing the CCP1CON register will force

the CCP1 PWM o utpu t latch to th e de fau lt

low level. This is not the PORTC I/O data

latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers CCP1CON<5:4>

Clear Time r,

CCP1 pin and

latch D.C.

TRISC<2>

RC2/CCP1

Note 1: The 8-bit timer is concatenated with 2-bit internal Q

clock, or 2 bits of the prescaler, to create 10-bit time

base.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note: The T imer2 post scaler (see Secti on 7.1) is

not used in the determination of the PWM

frequency. The postscaler could be used

to have a servo update rate at a different

frequency than the PWM output.

Note: If the PWM d uty c ycle v alu e i s lon ger tha n

the PWM period, the CCP1 pin will not be

cleared.

log(FPWM

log(2)

FOSC )bits

Resolution

 2003 Microchip Technology Inc. DS30569B-page 59

PIC16F870/871

8.4.3 SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PWM period by writing to the PR2

2. Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the

TRISC< 2> bit.

4. Set the TMR2 prescale value and e nable Timer2

by writing to T2CON.

5. Configure the CCP1 modu le for PWM operation.

TABLE 8-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

TABLE 8-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12kHz 156.3 kHz 208.3 kHz

Timer Prescaler (1, 4, 16) 16 4 1 1 1 1

PR2 Value 0xFFh 0xFFh 0xFFh 0x3Fh 0x1Fh 0x17h

Maximum Resolution (bits) 10 10 10 8 7 6. 5

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

0Bh,8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IETMR2IE TMR1IE 0000 -000 0000 -000

87h T RISC P ORTC Data Direction Register 1111 1111 1111 1111

0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu

10h T1CON —— T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

15h CCPR1L Capt ure/Compare/PW M Register1 (LSB) xxxx xxxx uuuu uuuu

16h CCPR1H Capture/ Compare/PW M Register1 (MSB ) xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1.

Note 1: The PSP is not implemented on the PIC16F870; always maintain these bits clear.

PIC16F870/871

DS30569B-page 60  2003 Microchip Technology Inc.

TABLE 8-4: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Va lue on:

POR, BOR

Value on

all other

RESETS

0Bh,8Bh,

10Bh, 18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

87h TRISC PORTC Dat a Di re ct i on Re gi s ter 1111 1111 1111 1111

11h TMR2 Timer2 Module’s Register 0000 0000 0000 0000

92h PR2 T imer2 Module’s Period Register 1111 1111 1111 1111

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000

15h CCPR1L Capture /Co mp ar e/ P WM Re gis t er 1 (L SB) xxxx xxxx uuuu uuuu

16h CCPR1H Ca pt ur e/ Compare/PWM Re g is ter 1 (MS B) xxxx xxxx uuuu uuuu

17h CCP1CON —— CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2.

Note 1: B i ts PSPIE and PSPIF are reserv ed on the PIC16F870; always maintain these bits clear.

 2003 Microchip Technology Inc. DS30569B-page 61

PIC16F870/871

9.0 ADDRESSABLE UNIVERSAL

SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver

Transmitter (USART) module is one of the two serial

I/O mo dules . (USA RT is als o kno wn as a S erial Com-

munications Interface or SCI.) The USART can be con-

figured as a full duplex asynchronous system that can

communicate with peripheral devices, such as CRT ter-

minals and perso nal comp uters, or it can be confi gured

as a half-d uplex synch ronous syste m that ca n comm u-

nicate with peripheral devices, such as A/D or D/A

integrated circuits, serial EEPROMs, etc.

The USART can be configured in the following modes:

• Asynchronous (full-duplex)

• Synchronous - Master (half-duplex)

• Synchronous - Slave (half-duplex)

Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to

be set in order to configure pins RC6/TX/CK and

RC7/RX/DT as the Universal Synchronous

Asynchronous Receiver Transmitter.

The USART module also has a multi-processor

communication capability using 9-bit address

detection.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN SYNC — BRGH TRMT TX9D

bit 7 bit 0

bit 7 CSRC: Cloc k Sourc e Sele ct bit

Asynchronous mode:

Don’t care

Synchronous mode:

1 = Master mode (clock generated internally from BRG)

0 = Slave mode (clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission

0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit

1 = Transmit enabled

0 = Transmit disabled

Note: SREN/CREN overrides TXEN in Sync mode.

bit 4 SYNC: USART Mode Select bit

1 = Synchronous mode

0 = Asynchronous mode

bit 3 Unimplemented: Read as '0'

bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed

0 = Low speed

Synchronous mode:

Unused in this mode

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty

0 = TSR full

bit 0 TX9D: 9th bit of Transmit Data, can be parity bit

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F870/871

DS30569B-page 62  2003 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x

SPEN RX9 SREN CREN ADDEN FERR OERR RX9D

bit 7 bit 0

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins)

0 = Serial port disabled

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception

0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode:

Don’t care

Synchronous mode - master:

1 = Enables single receive

0 = Disables single receive

This bit is cleared after reception is complete.

Synchronous mode - slave:

Don’t care

bit 4 CREN: Continuous Receive Enable bit

Asynchronous mode:

1 = Enables continuous receive

0 = Disables continuous receive

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN)

0 = Disables continuous receive

bit 3 ADDEN: Address Detect Enable bit

Asynchronous mode 9-bit (RX9 = 1):

1 = Enables address detection, enables interrupt and load of the receive buffer when

RSR<8> is set

0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit

bit 2 FERR: Framing Error bit

1 = Framing error (can be updated by reading RCREG register and receive next valid byte)

0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (can be cleared by clearing bit CREN)

0 = No overrun error

bit 0 RX9D: 9th bit of Received Data (can be parity bit, but must be calculated by user firmware)

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

 2003 Microchip Technology Inc. DS30569B-page 63

PIC16F870/871

9.1 USART Baud Rate Generator

(BRG)

The BRG supports both the Asynchronous and Syn-

chronous modes of the USART. It is a dedicated 8-bit

baud rate generator. The SPBRG register controls the

period of a free running 8-bit timer. In Asynchronous

mode, bit BRGH (TXSTA<2>) also controls the baud

rate. In Synchronous mode, bit BRGH is ignored.

Table 9-1 shows the formula for computation of the

baud rate for diff eren t US ART modes whic h on ly a ppl y

in Master mode (internal clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRG register can be calculate d

using the formula in Table 9-1. From this, the error in

baud rate can be determined.

It may be advantageous to use the high baud rate

(BRGH = 1), even for slower baud clocks. This is

becaus e the FOSC/(16(X + 1)) equat ion c an red uce th e

baud rate error in some cases.

Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the

BRG does not wait for a timer overflow before

outputting the new baud rate.

9.1.1 SAMPLING

The dat a on the RC7/RX/D T pin is sa mpled three time s

by a majority detect circuit to determine if a high or a

low level is present at the RX pin.

TABLE 9-1: BAUD RATE FORMULA

TABLE 9-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)

(Asynchronous) Baud Rate = F OSC/(64(X+1))

(Synchronous) Baud Rate = FOSC/(4(X+1)) Baud Rate = FOSC/(16(X+1))

N/A

Legend: X = value in SPBRG (0 to 255)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG.

PIC16F870/871

DS30569B-page 64  2003 Microchip Technology Inc.

TABLE 9-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

BAUD

RATE

(K)

FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz

KBAUD %

ERROR

SPBRG

value

(decimal) KBAUD %

ERROR

SPBRG

value

(decimal) KBAUD %

ERROR

SPBRG

value

(decimal)

0.3------- --

1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129

2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64

9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15

19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7

28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4

33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4

57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2

HIGH 1.221 - 255 0.977 - 255 0.610 - 255

LOW 312.500 - 0 250.000 - 0 156.250 - 0

BAUD

RATE

(K)

FOSC = 4 MHz FOSC = 3.6864 MHz

KBAUD

ERROR

SPBRG

value

(decimal) KBAUD

ERROR

SPBRG

value

(decimal)

0.3 0.300 0 207 0.3 0 191

1.2 1.202 0.17 51 1.2 0 47

2.4 2.404 0.17 25 2.4 0 23

9.6 8.929 6.99 6 9.6 0 5

19.2 20.833 8.51 2 19.2 0 2

28.8 31.250 8.51 1 28.8 0 1

33.6 - - - - - -

57.6 62.500 8.51 0 57.6 0 0

HIGH 0.244 - 255 0.225 - 255

LOW 62.500 - 0 57.6 - 0

 2003 Microchip Technology Inc. DS30569B-page 65

PIC16F870/871

TABLE 9-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

BAUD

RATE

(K)

FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz

KBAUD %

ERROR

SPBRG

value

(decimal) KBAUD %

ERROR

SPBRG

value

(decimal) KBAUD %

ERROR

SPBRG

value

(decimal)

0.3---------

1.2---------

2.4 - - - - - - 2.441 1.71 255

9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64

19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31

28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21

33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18

57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10

HIGH 4.883 - 255 3.906 - 255 2.441 - 255

LOW 1250.000 - 0 1000.000 0 625.000 - 0

BAUD

RATE

(K)

FOSC = 4 MHz FOSC = 3.6864 MHz

KBAUD

ERROR

SPBRG

value

(decimal) KBAUD

ERROR

SPBRG

value

(decimal)

0.3------

1.2 1.202 0.17 207 1.2 0 191

2.4 2.404 0.17 103 2.4 0 95

9.6 9.615 0.16 25 9.6 0 23

19.2 19.231 0.16 12 19.2 0 11

28.8 27.798 3.55 8 28.8 0 7

33.6 35.714 6.29 6 32.9 2.04 6

57.6 62.500 8.51 3 57.6 0 3

HIGH 0.977 - 255 0.9 - 255

LOW 250.000 - 0 230.4 - 0

PIC16F870/871

DS30569B-page 66  2003 Microchip Technology Inc.

9.2 USART Asynchronous Mode

In this mode, the USART uses standard non-return-to-

zero (NRZ) format (one START bit, eight or nine data

bits, and one STOP bit). The most common data format

is 8-bits. An on-chip, dedicated, 8-bit baud rate gener-

ator can be used to de rive st and ard baud rate freque n-

cies from the oscillator. The USART transmits and

receive s t he L S b fi rst. The t r ans mitte r and rec eiv er a re

functio nally in dependen t, but use the sam e dat a format

and baud rate. The baud rate generator produces a

clock, either x16 or x64 of the bit shift rate, depending

on bit BRGH (TXSTA<2>). Parity is not supported by

the hardw are, but can be implemente d in software (an d

stored as the ninth data bit). Asynchronous mode is

stopped during SLEEP.

Asynchronous mode is selected by clearing bit SYNC

(TXSTA<4>).

The USART Asynchronous module consists of the

following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

9.2.1 USART ASYNCHRONOUS

TRANSMITTER

The USART transmitter block diagram is shown in

Figure 9-1. The heart of the transmitter is the Transmit

(Serial) Shift register (TSR). The Shift register obtains

its data from the read/write transmit buffer, TXREG. The

TXREG register is loaded with data in software. The

TSR register is not loaded until the STOP bit has been

transmitted from the previous load. As soon as the

STOP bit is transmitted, the TSR is loaded with new

data from the TXREG register (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCY), the TXR EG re gist er i s em pty and

flag bit TXIF (PIR1<4>) is set. This interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

( PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will re set only wh en ne w dat a is loa ded i nto the

TXREG register . While flag bit TXIF indicates the statu s

of the TXREG register , another bit, TRMT (TXST A<1>),

shows the status of the TSR register. Status bit TRMT

is a re ad onl y bit, wh ic h i s se t w he n the TSR r egi ste r i s

empty. No interrupt logic is tied to this bit, so the user

has to poll this bit in order to determine if the TSR

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data

and the baud rate generator (BRG) has produced a

shift clock (Figure 9-2). The transmission can also be

started by first loading the TXREG register and then

setting enable bit TXEN. Normally, when transmission

is first started, the TSR register is empty. At that point,

transfer to the TXREG register will result in an immedi-

ate transfer to TSR, resulting in an empty TXREG. A

back-to-back transfer is thus possible (Figure 9-3).

Clearing enable bit TXEN during a transmission will

cause the tra nsm is s ion to be ab orte d a nd will re se t th e

transmitter. As a result, the RC6/TX/CK pin will revert

to hi-impedance.

In order to select 9-bit transmission, transmit bit TX9

(TXSTA<6>) should be set and the ninth bit should be

written to TX9D (TXSTA<0>). The ninth bit must be

written before writing the 8-bit data to the TXREG reg-

ister. This is because a data write to the TXREG regis-

ter can resu lt in an immediate tra nsfer of the dat a to the

TSR register (if the TSR is empty). In such a case, an

incorrect ninth data bit may be loaded in the TSR

FIGURE 9-1: USART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit T XIF is set when en able bit TXEN

is set. TXIF is cle ared by loadi ng TXREG.

TXIF

TXIE

Interrupt

TXEN Baud Rate CLK

SPBRG

Baud Rate Generator TX9D

MSb LSb

Data Bus

TXREG Register

TSR Register

(8) 0

TX9

TRMT SPEN

RC6/TX/CK pin

Pin Buffer

and Control

• • •

 2003 Microchip Technology Inc. DS30569B-page 67

PIC16F870/871

When setting up an Asynchronous Transmission,

follow these steps:

1. Initialize th e SPBRG re gis te r for the ap prop ria te

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 9.1) .

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, then set enable bit

TXIE.

4. If 9-bit transmission is desired, then set transmit

bit TX9.

5. Enable the transmission by setting bit TXEN,

which will also set bit TXIF.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Load data to the TXREG register (starts

transmission).

8. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

FIGURE 9-2: ASYNCHRONOUS MASTER TRANSMISSION

FIGURE 9-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)

TABLE 9-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Address Name Bit 7 Bit 6 Bit 5 B it 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all othe r

RESETS

0Bh, 8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x

19h TXREG USART Transmit Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.

Word 1 STOP Bit

Word 1

Trans m i t Sh i f t R e g

START Bit Bit 0 Bit 1 Bit 7/8

Write to TXREG Word 1

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

TXIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Transmit Shift Reg.

Write to TXREG

BRG Output

(Shift Clock)

RC6/TX/CK (pin)

TXIF bit

(Interrupt Reg. Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

Word 1 Word 2

START Bit STOP Bit START Bit

Transmit Shift Reg.

Word 1 Word 2

Bit 0 B it 1 Bi t 7 /8 Bit 0

Note: This timing diagram shows two consecutive transmissions.

PIC16F870/871

DS30569B-page 68  2003 Microchip Technology Inc.

9.2.2 USART ASYNCHRONOUS

RECEIVER

The receiv er block diagra m is show n in Figure 9-4. The

data is received on the RC7/RX/DT pin and drives the

data recovery block. The d ata recovery block is actually

a high speed shifter, operating at x16 times the baud

rate; whereas, the main receive serial shifter operates

at the bit rate or at FOSC.

Once Asynchronous mode is selected, reception is

enabled by setti ng bit CRE N (RCSTA<4>).

The heart of the receiver is the Receive (Serial) Shift

received data in the RSR is transferred to the RCREG

bit R CIF ( PIR1<5 >) is set. T he ac tual interr upt can be

enabled/disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read only bit, which is

cleared by the hardware. It is cleared when the RCREG

double-buffered register (i.e., it is a two-deep FIFO). It

is possible for two bytes of data to be received and

transferred to the RCREG FIFO and a third byte to

begin shifting to the RSR register. On the detection of

the STOP bit of the third byte, if the RCREG register is

still f ull, the overrun error bit OE RR (RCST A<1>) will be

set. The word in the RSR will be lost. The RCREG reg-

ister can be read twice to retrieve the two bytes in the

FIFO. O verrun bit OE RR ha s to b e cle ared in softwar e.

This is done by resetting the receive logic (CREN is

cleared and then s et). If bit OE RR is set, transfe rs from

the RSR register to the RCREG register are inhibited,

and no further data will be received. It is therefore,

essential to clear error bit OERR if it is set. Framing

error bit FERR (RCSTA<2>) is set if a STOP bit is

detected as cle ar. Bit FERR and the 9th re cei ve bit a re

buffered the same way as the receive data. Reading

the RCREG will load bits RX9D and FERR with new

values , the refo re, it is essent ial for the us er to re ad th e

RCSTA regis ter befo re reading the RCREG register in

order not to lose the old FERR and RX9D inform ation .

FIGURE 9-4: USART RECEIVE BLOCK DIAGRAM

FIGURE 9-5: ASYNCHRONOUS RECEPTION

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RC7/RX/DT Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR FERR

RSR Register

MSb LSb

RX9D RCREG Register FIFO

Interrupt RCIF

RCIE Data Bus

÷64

÷16

or STOP START

(8) 710

RX9

• • •

FOSC

START

bit bit7/8

bit1bit0 bit7/8 bit0STOP

bit

START

bit START

bit

bit7/8 STOP

bit

RX (pin)

Reg

Rcv Buffer Reg

Rcv Shift

Read Rcv

Buffer Reg

RCREG

RCIF

(Interrupt Flag)

OERR bit

CREN

Word 1

RCREG Word 2

RCREG

STOP

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set.

 2003 Microchip Technology Inc. DS30569B-page 69

PIC16F870/871

When setting up an Asynchronous Reception, follow

these steps:

1. Initialize th e SPBRG re gis te r for the ap prop ria te

baud rate. If a high speed baud rate is desired,

set bit BRGH (Section 9.1) .

2. Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

3. If interrupts are desired, then set enable bit

RCIE.

4. If 9-bit reception is desired, then set bit RX9.

5. Enable the reception by setting bit CREN.

6. Flag bit RCI F wi ll b e se t w he n rec ept ion is com -

plete an d an interru pt will be generate d if enabl e

bit RCIE is set.

7. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

8. Read the 8-bit received data by reading the

RCREG register.

9. If any error occurred, clear the error by clearing

enable bit CREN.

10. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

TABLE 9-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Addres s N a m e Bit 7 B it 6 Bit 5 Bit 4 Bit 3 B it 2 B it 1 Bit 0 Value on :

POR, BOR

Value on

all other

RESETS

0Bh, 8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF -000 0000 -000 0000

18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x

1Ah R CREG USART Receive Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.

PIC16F870/871

DS30569B-page 70  2003 Microchip Technology Inc.

9.2.3 SETTING UP 9-BIT MODE WITH

ADDR ES S DET E CT

When setting up an Asynchronous Reception with

Address Detect enabled:

• Initialize the SPBRG register for the appropriate

baud r ate. If a high spee d baud rate is desire d, set

bit BRGH.

• Enable the asynchronous serial port by clearing

bit SYNC and setting bit SPEN.

• If interrupts are desired, then set enable bit RCIE.

• Set bit RX9 to enable 9-bit reception.

• Set ADDEN to enable address detect.

• Enable the reception by setting enable bit CREN.

• Flag bit RCIF will be set when reception is com-

plete, and an interrupt will be generated if enable

bit RCIE was set.

• Read the RCSTA register to get the ninth bit and

determine if any error occurred during reception.

• Read the 8-bit received data by reading the

RCREG register, to determine if the device is

being addressed.

• If any error occurred, clear the error by clearing

enable bit CREN.

• If the device has been addressed, clear the

ADDEN bi t to al low da t a b yte s an d address b ytes

to be rea d into the receive buf fer, and interrupt the

CPU.

FIGURE 9-6: USART RECEIVE BLOCK DIAGRAM

x64 B aud R ate CLK

SPBRG

Baud Rate Generator

RC7/RX/DT Pin Buffer

and Control

SPEN

Data

Recovery

CREN OERR FERR

RSR Register

MSb LSb

RX9D RCREG Register FIFO

Interrupt RCIF

RCIE Data Bus

÷ 64

÷ 16

or STOP START

(8) 710

RX9

• • •

RX9

ADDEN

RX9

ADDEN

RSR<8>

Enable

Load of

Receive

Buffer

FOSC

 2003 Microchip Technology Inc. DS30569B-page 71

PIC16F870/871

FIGURE 9-7: ASYNCHRONOUS RECEPTION WI TH ADDR ESS DETECT

FIGURE 9-8: ASYNCHRONOUS RECEPTION WI TH ADDRESS B YTE FIRST

TABLE 9-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

START

bit bit1bit0 bit8 bit0STOP

bit

START

bit bit8 STOP

bit

RC7/RX/DT (pin)

Load RSR

Read

RCIF

Word 1

RCREG

Bit8 = 0, Data Byte Bit8 = 1, Address Byt e

Note: This timing diagr am shows a data byt e followed by an ad dress byte. The da ta byte is no t read into the RCREG (rec eive buffer)

because ADDEN = 1.

START

bit bit1bit0 bit8 bit0STOP

bit

START

bit bit8 STOP

bit

RC7/RX/DT (pin)

Load RSR

Read

RCIF

Word 1

RCREG

Bit8 = 1, Address Byte Bit8 = 0, Data Byte

Note: This timing di agram shows a data byte followed by an addre ss byte. The data byte is not read into the RCREG (rec eive buffer)

because ADDEN was not updated and still = 0.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all other

RESETS

0Bh, 8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCREG USART Receive Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGHTRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.

PIC16F870/871

DS30569B-page 72  2003 Microchip Technology Inc.

9.3 USART Synchronous

Master Mode

In Sync hronous Ma ster mode, the data is transmi tted in

a half-duplex manner (i.e., transmission and reception

do not occur at the sa me time). When tran smitting dat a,

the reception is inhibited and vice versa. Synchronous

mode is entered by setting bit SYNC (TXSTA<4>). In

addition, enable bit SPEN (RCSTA<7>) is set in order

to configure the RC6/TX/CK and RC7/RX/DT I/O pins

to CK (clock) and DT (data) lines, respectively. The

Master mode ind icates t hat the pr ocessor transmit s the

master clock on the CK line. The Master mode is

entered by setting bit CSRC (TXSTA<7>).

9.3.1 USART SYNCHRONOUS MASTER

TRANSMISSION

The USART transmitter block diagram is shown in

Figure 9-6. The heart of the transmitter is the Transmit

(Serial) Shift register (TSR). The Shift register obtains

its data from the Read/Write Transmit Buffer register

TXREG. The TXREG register is loaded with data in

software. The TSR register is not loaded until the last

bit has been transmitted from the previous load. As

soon as the last bit is transmitted, the TSR is loaded

with new data from the TXREG (if available). Once the

TXREG register transfers the data to the TSR register

(occurs in one TCYCLE), the TXREG i s empt y and in ter-

rupt bit TXIF (PIR1<4>) is set. The interrupt can be

enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set, regardless of the

state of enable bit TXIE and cannot be cleared in soft-

ware. It will re set o nly when ne w dat a i s loaded into the

TXREG register . While flag bit TXIF indicates the st atus

of th e T XR EG r egi st e r, an oth er b it T RMT ( TX STA<1>)

shows the status of the TSR register. TRMT is a read

only bit which is set when the TSR is empty. No inter-

rupt logic is tied to this bit, so the user has to poll this

bit in order to determine if the TSR register is empty.

The TSR is not mapped in data memory, so it is not

availa ble to the user.

Transmission is enabled by setting enable bit TXEN

(TXSTA<5>). The actual transmission will not occur

until the TXREG register has been loaded with data.

The fir st data bit will be shifte d out on the next av ailable

rising edge of the clock on the CK line. Data out is sta-

ble around the falling edge of the synchronous clock

(Figure 9-9). The transmission can also be started by

first loading the TXREG register and then setting bit

TXEN (Figure 9-10). This is advantageous when slow

baud rates are selected, since the BRG is kept in

RESET when bits TXEN, CREN and SREN are clear.

Setting enable bit TXEN will start the BRG, creating a

shift c lock immed iately. Normally, when trans missio n i s

first started, the TSR register is empty, so a transfer to

the TXREG reg is ter wi ll re sult in an immediate tra ns fer

to TSR, resulting in an empty TXREG. Back-to-back

transfers are possible.

Clearing enable bit TXEN during a transmission will

cause the tra nsm is s ion to be ab orte d a nd will re se t th e

transmitter. The DT and CK pins will revert to hi-

impeda nce. If ei ther bit C REN or bi t SREN is set durin g

a transmis sion , the transm issi on is abor ted and the DT

pin reverts to a hi-impedance state (for a reception).

The CK pin will remain an output if bit CSRC is set

(internal clock). The transmitter logic, however, is not

reset, although it is disconnected from the pins. In order

to reset the tran sm itte r, the user has to cle ar bi t TXEN.

If bit SREN is set (t o interrupt an on-goin g trans mission

and rec eive a sing le word ), then after th e single word is

received, bit SREN will be cleared and the serial port

will revert back to transmitting, since bit TXEN is still

set. The DT line will immediately switch from Hi-

Impedan ce R eceiv e mode to tra nsmit and st art d rivin g.

To avoid this, bit TXEN should be cleared.

In order to select 9-bit transmission, the TX9

(TXSTA<6>) bit should be set and the ninth bit should

be written to bit TX9D (TXSTA<0>). The ninth bit must

be written before writing the 8-bit data to the TXREG

result in an immediate transfer of the data to the TSR

the TXREG was writt en befo re writ ing the “new” T X9D,

the “present” value of bit TX9D is loaded.

Steps to follow when setting up a Synchronous Master

Transmission:

1. Initialize the SPBRG re gister for the ap prop ria te

baud rate (Section 9.1).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the tr ansmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. S tart transmission b y loading dat a to the TXREG

8. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

 2003 Microchip Technology Inc. DS30569B-page 73

PIC16F870/871

TABLE 9-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

FIGURE 9-9: SYNCHRONOUS TRANSMISSION

FIGURE 9-10: SYNCHRONOUS TRANSMISSION (TH ROUGH TXEN)

Addres s N a me Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 B it 1 B i t 0 Value on:

POR, BOR

Value on

all other

RESETS

0Bh, 8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN —FERR OERR RX9D 0000 -00x 0000 -00x

19h TXREG U SART Transmit Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.

bit 0 bit 1 bit 7

Word 1

Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q3Q4 Q1Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1 Q2Q3Q4

bit 2 bit 0 bit 1 bit 7

RC7/RX/DT pin

RC6/TX/CK pin

Write t o

TXREG reg

TXIF bit

(Inte rru pt Flag )

TXEN bit'1' '1'

Wo rd 2

TRMT bit

Write Word1 Write Word2

Note: Sync Master mode; S PBRG = 0. Continuous transmission of two 8-bit words.

RC7/RX/DT pin

RC6/TX/CK pin

Write to

TXREG Reg

TXIF bit

TRMT bit

bit0 bit1 bit2 bit6 bit7

TXEN b it

PIC16F870/871

DS30569B-page 74  2003 Microchip Technology Inc.

9.3.2 USART SYNCHRONOUS MASTER

RECEPTION

Once Synchronous mode is selected, reception is

enabled by setting either enable bit SREN

(RCST A<5>), or enable bit CREN (RCSTA<4>). Data is

sampled on the RC7/RX/DT pin on the falling edge of

the clock. If enable bit SREN is set, then only a single

word is received. If enable bit CREN is set, the recep-

tion is c ontinuous until CREN is cleared. If bo th bits are

set, CREN t akes precedence. After clocking the last bit,

the recei ved dat a in the Re ceiv e Shift regi ster (RSR) is

transferred to the RCREG register (if it is emp ty). When

the transfer is complete, interrupt flag bit RCIF

(PIR 1<5 >) i s se t. Th e ac tua l in ter ru pt c an be enab led /

disabled by setting/clearing enable bit RCIE

(PIE1<5>). Flag bit RCIF is a read only bit, which is

reset by the ha rdware . In thi s c ase, it i s r ese t whe n th e

RCREG register has been read and is empty. The

RCREG is a double-buffered register (i.e., it is a two-

deep FIFO). It is possible for two bytes of data to be

received and transferred to the RCREG FIFO and a

third byte to beg in shifting into the RSR register. On the

clocking of the last bit of the third byte, if the RCREG

(RCSTA<1>) is set. The word in the RSR will be lost.

The RCREG register can be read twice to retrieve the

two bytes in the FIFO. Bit OERR has to be cleared in

software (by clearing bit CREN). If bit OERR is set,

transfers from the RSR to the RCREG are inhibited, so

it is essential to clear bit OERR if it is set. The ninth

receive bit is buffered the same way as the receive

data. Reading the RCREG register will load bit RX9D

with a new value, therefore, it is essential for the user

to read the RCSTA register before reading RCREG, in

order not to lose the old RX9D information.

When sett ing up a Synchronous Master Reception:

1. Initialize the SPBRG re gister for the ap prop ria te

baud rate (Section 9.1).

2. Enable the synchronous master serial port by

setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, then set enable bit

RCIE.

5. If 9-bit reception is desired, then set bit RX9.

6. If a single reception is required, set bit SREN.

For continuous reception, set bit CREN.

7. Interrupt fla g bit RCIF will be se t when receptio n

is complete and an interrupt will be generated if

enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

9. Read the 8-bit received data by reading the

RCREG register.

10. If any error occurred, clear the error by clearing

bit CREN.

11. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

 2003 Microchip Technology Inc. DS30569B-page 75

PIC16F870/871

TABLE 9-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

FIGURE 9-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Addres s N a me Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B it 2 B it 1 B i t 0 Value on:

POR, BOR

Value on

all other

RESETS

0Bh, 8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x

1Ah RCREG USART Receive Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.

CREN bit

RC7/RX/DT pin

RC6/TX/CK pin

Write t o

bit SREN

SREN b i t

RCIF bit

(Interrupt)

Read

RXREG

Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit B RG = 0.

Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q2 Q1Q2Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3Q4Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q1 Q2Q3 Q4 Q1Q2Q3 Q4

'0'

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7

'0'

Q1Q2Q3Q4

PIC16F870/871

DS30569B-page 76  2003 Microchip Technology Inc.

9.4 USART Synchronous Slave Mode

Synchronous Slave mo de differs from the Master mode

in the fact that the shift clock is supplied externally at

the RC6/TX/ CK pin (inst ead of being supplied internally

in Master mode). This allows the device to transfer or

receive data while in SLEEP mode. Slave mode is

entered by clearing bit CSRC (TXSTA<7>).

9.4.1 USART SYNCHRONOUS SLAVE

TRANSMIT

The operation of the Synchronous Master and Slave

modes is identical, exce pt in the case of the SLEEP mode.

If two words are written to the TXREG and then the

SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit.

b) The second word will remain in TXREG register .

c) Flag bit TXIF will not be set.

d) When the first word has been shifted out of TSR,

the TXREG register will transfer the second word

to the TSR and flag bit TXIF will now be set.

e) If enable bit TXIE is set, the interrupt will wake

the chip from SLEEP and if the global interrupt

is enabled, the program will branch to the

inter rupt ve cto r (0004h ).

When setting up a Synchronous Slave Transmission,

follow these steps:

1. Enable the synchronou s slave s erial port by se t-

ting bits SYNC and SPEN and clearing bit

CSRC.

2. Clear bits CREN and SREN.

3. If interrupts are desired, then set enable bit

TXIE.

4. If 9-bit transmis si on is des ired , then set bi t TX9.

5. Enable the transmission by setting enable bit

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. S tart transmission b y loading dat a to the TXREG

8. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

TABLE 9-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on:

POR, BOR

Value on

all othe r

RESETS

0Bh, 8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

19h TXREG USA RT Transmit Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870; always maintain these bits clear.

 2003 Microchip Technology Inc. DS30569B-page 77

PIC16F870/871

9.4.2 USART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of the SLEEP

mode. Bit SREN is a “don't care” in Slave mode.

If receive is enabled by setting bit CREN prior to the

SLEEP inst ruction , then a w ord m ay be rec eived durin g

SLEEP. On completely receiving the word, the RSR

and if enabl e bit RCIE bit is set , the interrupt gene rated

will wake the chip from SLEEP. If the glob al interrupt is

enabled , the pro gram wil l branc h to the interru pt vec tor

(0004h).

When setting up a Synchronous Slave Reception,

follow these steps:

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

2. If interrupts are desired, set enable bit RCIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

5. Flag bit RCI F wi ll b e se t w he n rec ept ion is com -

plete and an interrupt will be generated, if

enable bit RCIE was set.

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit CREN.

9. If using interrupts, ensure that GIE and PEIE

(bits 7 and 6) of the INTCON register are set.

TABLE 9-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Addres s N a me Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 B it 1 Bit 0 Value on:

POR, BOR

Value on

all othe r

RESETS

0Bh, 8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF R0IF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x

1Ah RCREG USART Receive Register 0000 0000 0000 0000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

98h TXSTA CSRC TX9 TXEN SYNC —BRGH TRMT TX9D 0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous slave reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F870, always maintain these bits clear.

PIC16F870/871

DS30569B-page 78  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 79

PIC16F870/871

10.0 ANALOG-TO-DIGITAL (A/D)

CONVERTER MODULE

The Analog-to-Digital (A/D) Converter module has five

inputs for the 28-pin devices and eight for the other

devices.

The ana log inpu t char ges a sample and hol d ca pac itor.

The output of th e sample and hold capa citor is the inp ut

into the c on ve rter. The conver ter t hen gen era tes a di g-

ital result of this analog level via successive approxima-

tion. The A/D conversion of the analog input signal

results in a corresponding 10-bit digital number. The

A/D module has high and low voltage reference input

that is software selectable to so me combination of VDD,

VSS, RA2, or RA3.

The A/D converter has a unique feature of being able

to opera te while th e device i s in SLEEP mod e. To oper-

ate in SLEEP, the A/D clock must be derived from the

A/D’s internal RC oscillator.

The A/D module has four registers. These registers

are:

• A/D Result High Register (ADRESH)

• A/D Result Low Register (ADRESL)

• A/D Control Register0 (ADCON0)

• A/D Control Register1 (ADCON1)

The ADCON0 register, shown in Register 10-1, con-

trols the operation of the A/D module. The ADCON1

tions of the port pins. The port pins can be configured

as analog inputs (RA3 can also be the voltage

reference), or as digital I/O.

Addition al informa tion on usi ng the A/D mo dul e c an b e

found in the PICmicro™ Mid-Range MCU Family

Reference Manual (DS33023).

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON

bit 7 bit 0

bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = FOSC/2

01 = FOSC/8

10 = FOSC/32

11 = FRC (clock derived from the internal A/D module RC oscillator)

bit 5-3 CHS2:CHS0: Analog Ch an nel Select bits

000 = Channel 0, (RA0/AN0)

010 = Channel 2, (RA2/AN2)

011 = Channel 3, (RA3/AN3)

100 = Channel 4, (RA5/AN4)

101 = Channel 5, (RE0/AN5)(1)

110 = Channel 6, (RE1/AN6)(1)

111 = Channel 7, (RE2/AN7)(1)

bit 2 GO/DONE: A/D Conversion Status bit

If ADON = 1:

1 = A/D conversion in progress (setting this bit starts the A/D conversion)

0 = A/D convers ion not in p rogres s (this bit is automatic ally cl eared by ha rdware whe n the A/D

conve rsi on is co mp let e)

bit 1 Unimplemented: Read as '0'

bit 0 ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shut-off and consumes no operating current

Note 1: These channels are not available on the PIC16F870 device.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

PIC16F870/871

DS30569B-page 80  2003 Microchip Technology Inc.

The ADRESH:ADRESL registers contain the 10-bit

result of the A/D convers ion. When the A/D conver sion

is compl ete, the re sult is loaded i nto this A/D re sult reg-

ister pair, the GO/DONE bit (ADCON0<2>) is cleared

and the A/D interrupt flag bit ADIF is set. The block

diagram of the A/D module is sh ow n in Figu re 10-1.

After the A/D module has been configured as desired,

the sele cted cha nne l m ust be acq uire d b efore the co n-

version is started. The analog input channels must

have the ir corres pondin g TRIS bi ts selected as input s.

To determine sample time, see Section 10.1. After this

acquisition time has elapsed, the A/D conversion can

be started.

U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

ADFM ——— PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

bit 7 ADFM: A/D Result Format Select bit

1 = Right justified. 6 Most Significant bits of ADRESH are read as ‘0’.

0 = Left justified. 6 Least Significant bits of ADRESL are read as ‘0’.

bit 6-4 Unimplemented: Read as '0'

bit 3-0 PCFG3:PCFG0: A/D Port Configuration Control bits:

Note 1: These channels are not available on the PIC16F870 device.

2: This column indicates the number of analog channels available as A/D inputs and

the number of analog channels used as voltage reference inputs.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

A = Analog input D = Digital I/O

PCFG3:

PCFG0 AN7(1)

RE2 AN6(1)

RE1 AN5(1)

RE0 AN4

RA5 AN3

RA3 AN2

RA2 AN1

RA1 AN0

RA0 VREF+VREF-CHAN/

Refs(2)

0000 AAAAAAAAVDD VSS 8/0

0001 AAAAV

REF+A A A RA3VSS 7/1

0010 DDDA A AAAV

DD VSS 5/0

0011 DDDAV

REF+A A A RA3VSS 4/1

0100 DDDD ADAAV

DD VSS 3/0

0101 DDDDV

REF+D A A RA3VSS 2/1

011x DDDDDDDDV

DD VSS 0/0

1000 AAAAV

REF+VREF-A A RA3RA2 6/2

1001 DDAA A AAAV

DD VSS 6/0

1010 DDAAV

REF+A A A RA3VSS 5/1

1011 DDAAV

REF+VREF-A A RA3RA2 4/2

1100 DDDAV

REF+VREF-A A RA3RA2 3/2

1101 DDDDV

REF+VREF-A A RA3RA2 2/2

1110 DDDDDDDAV

DD VSS 1/0

1111 DDDDV

REF+VREF-D A RA3RA2 1/2

 2003 Microchip Technology Inc. DS30569B-page 81

PIC16F870/871

These steps should be followed for doing an A/D

Conversion:

1. Configure th e A/D modul e:

• Configure analog pins/voltage reference and

digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/ D int err upt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set PEIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE bit to be cleared

(with interrupts enabled); OR

• W aiting for the A/D interrupt

6. Read A/D Result register pair

(ADRESH:ADRESL), clear bit ADIF if required.

7. For the next conversion, go to step 1 or step 2,

as required. The A/D conversion time per bit is

defined as TAD. A minimum wait of 2 TAD is

required before the next acquisition starts.

FIGURE 10-1: A/D BLOCK DIAGRAM

(Input Voltage)

VAIN

VREF+

(Reference

Voltage)

VDD

PCFG3:PCFG0

CHS2:CHS0

RE2/AN7(1)

RE1/AN6(1)

RE0/AN5(1)

RA5/AN4

RA3/AN3/VREF+

RA2/AN2/VREF-

RA1/AN1

RA0/AN0

111

110

101

100

011

010

001

000

A/D

Converter

Note 1: Not available on the PIC16F870 device.

VREF-

(Reference

Voltage) VSS

PCFG3:PCFG0

PIC16F870/871

DS30569B-page 82  2003 Microchip Technology Inc.

10.1 A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 10-2. The

source impedance (RS) and the internal sampling

switch (RSS) impedance directly affect the time

required to charge the capacitor CHOLD. The sampling

switch (RSS) impedance va rie s over the dev ice vol tag e

(VDD), see Figure 10-2. The maximum recom-

mended im pedance for ana log sources is 10 k Ω. As

the impedance is decreased, the acquisition time may

be decreased. After the analog input channel is

selected (changed), this acquisition must be done

before the conversion can be started.

To calculate the minimum acquisition time,

Equation 10-1 may be used. This equation assumes

that 1/2 LSb error is used (1024 st eps for the A/D). The

1/2 LSb er ror is the ma ximu m error allow ed for the A/D

to meet its specified resolution.

To calculate the minimum acquisition time, TACQ, see

the PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023).

EQUATION 10-1: ACQUISITION TIME

FIGU RE 10- 2: ANALOG IN PUT MODE L

TACQ

Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

TAMP + TC + TCOFF

2 µs + TC + [(Temperature – 25°C)(0.05 µs/°C)]

CHOLD (RIC + RSS + RS) In(1/2047)

- 120 pF (1 kΩ + 7 kΩ + 10 kΩ) In(0.0004885)

16.47 µs

2 µs + 16.47 µs + [(50°C – 25°C)(0.05 µs/°C)

19.72 µs

Note 1: The reference voltage (VREF) ha s no effect on the equation, since it cancels itself out.

2: The charge holding capacitor (CHOLD) is not discharged after each conversion.

3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin

leakage specification.

4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.

During this time, the holding capacitor is not connected to the selected A/D input channel.

CPIN

RSANx

5 pF

VDD

VT = 0.6V

VT = 0.6V I LEAKAGE

RIC ≤ 1k

Sampling

Switch

SS RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

567891011

(kΩ)

VDD

= 120 pF

± 500 nA

Legend CPIN

I LEAKAGE

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

 2003 Microchip Technology Inc. DS30569B-page 83

PIC16F870/871

10.2 Selecting the A/D Conversion

Clock

The A/D conversion time per bit is defined as TAD. The

A/D con versio n requires a minimum 1 2 TAD per 10-bit

conversion. The source of the A/D conversion clock is

software selected. The four possible options for TAD

are:

•2 T

OSC

•8 TOSC

•32 TOSC

• Internal A/D module RC osc il lat or (2-6 µs)

For correct A/D conversions, the A/D conversion clock

(TAD) must be selected to ensure a minimum TAD time

of 1.6 µs.

Table 10-1 shows the resultant TAD t im es de ri ve d f ro m

the device operating frequencies and the A/D clock

source selected.

TABLE 10-1: TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (ST ANDARD DEVICES (C))

10.3 Configuring Analog Port Pins

The AD CON1 and TRI S re gis te rs control the o per ation

of the A/D port pins. The port pins that are desired as

analog inputs must have their corresponding TRIS bits

set (input ). If the TRIS bit is cleared (out put) , the digit al

output le vel (VOH or VOL) will be converted.

The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

AD Clock Source (TAD) Maximum Device Frequency

Operation ADCS1:ADCS0 Max.

2 TOSC 00 1.25 MHz

8 TOSC 01 5 MHz

32 TOSC 10 20 MHz

RC(1 , 2, 3) 11 (Note 1)

Note 1: The R C source ha s a typical TAD time of 4 µs, but can vary between 2-6 µs.

2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only

recommended for SLEEP operation.

3: For extended voltage devices (LC), please refer to the Electrical Characteristics (Section 14.1 and 14.2).

Note 1: When reading the port register, any pin

configu red as an analog input channel will

read as c lea red (a lo w l evel). Pins config-

ured as digital inputs will convert an ana-

log input. Analog levels on a digitally

configured input will not affect the

conversion accuracy.

2: Analog le vels on any pin that is defined as

a digital input (including the AN7:AN0

pins), may cause the input buffer to con-

sume current that is out of the device

specifications.

PIC16F870/871

DS30569B-page 84  2003 Microchip Technology Inc.

10.4 A/D Conversions

Clearing the GO/DONE bit during a conversion will

abort the current conversion. The A/D result register

pair will NOT be updated with the partially completed

A/D conversion sample. That is, the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers). After the A/D conversion

is aborted, a 2 TAD wait is required before the next

acquisition is started. After this 2 TAD wait, acquisition

on the selected channel is automatically started. The

GO/DONE bit can then be set to start the conversion.

In Figure 10-3, after the GO bit is set, the first time

segment has a minimum of T CY and a maximum of TAD.

FIGURE 10 -3: A/D CO NVERSI ON TAD CYCLES

10.4.1 A/D RESULT REGISTERS

The ADRESH:ADRESL register pair is the location

where the 10-bit A/D result is loaded at the completion of

the A/D conversion. This register pair is 16-bits wide.

The A/D module gives the flexibility to left or right justify

the 10-bit result in the 16-bit result register . The A/D For-

mat Select bit (ADFM) controls this justification.

Figure 10-4 shows the operation of the A/D result justifi-

cation. The extra bits are loaded with ‘0’. When an A/D

result will not overwrite these locations (A/D disable),

these registers may be used as two general purpose

8-bit registers.

FIGURE 10- 4: A/D RESU LT JU STI FIC AT ION

Note: The GO/DONE bit should NOT be set in

the sam e inst ructio n that tu rns on the A/D.

TAD1TAD2 TAD3

TAD5TAD6

7 T

Set GO bit

Holding capacitor is disconnected from analog input (typically 100 ns)

b9 b8 b7 b6 b5 b4 b3 b2

TAD10 TAD11

b1 b0

TCY to TAD

Conversion starts

ADRES is loaded

GO bit is cleared

ADIF bit is set

Holding capacitor is connected to analog input

10-bit Result

ADRESH ADRESL

0000 00

ADFM = 0

2 1 0 77

10-bit Result

ADRESH ADRESL

10-bit Result

0000 00

70 7 6 5 0

ADFM = 1

Right Justified Left Justified

 2003 Microchip Technology Inc. DS30569B-page 85

PIC16F870/871

10.5 A/D Operation During SLEEP

The A/D module can operate during SLEEP mode. This

requires that the A/D clock source be set to RC

(ADCS1:ADCS0 = 11). When the RC clock source is

selected, the A/D module waits one instruction cycle

before starting the conversion. This allows the SLEEP

instruction to be executed, which eliminates all digital

switchi ng noise fro m the conv ersion. Whe n the conver-

sion i s comple ted, the GO /DONE bit will be cleared and

the result loaded into the ADRES register. If the A/D

interrupt is enabled, the device will wake-up from

SLEEP. If the A/D interrupt is not enabled, the A/ D mod-

ule will then be turned off, although the ADON bit will

remain set.

When the A/D clock sour ce is anoth er clock optio n (not

RC), a SLEEP instruction will cause the present conver-

sion t o be aborte d and the A/D mod ule to be turned of f,

though the ADON bit will remain set.

Turnin g off the A/D places the A/D mo du le in it s low es t

current consumption state.

10.6 Effects of a RESET

A device RESET forces all registers to their RESET

state. This forces the A/D module to be turned off, and

any conversion is aborted. All A/D input pins are

configured as analog inputs.

The value that is in the ADRESH:ADRESL registers is

not modified for a Power-on Reset. The

ADRESH:ADRESL registers w ill cont ain unkno wn data

after a Power-on Reset.

TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH A/D

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC

(ADCS1:ADCS0 = 11). To allow the con-

version to occur durin g SLEEP, ensure the

SLEEP instruction immediately follows the

instruction that sets the GO/DONE bit.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on

POR, BOR

Value on

MCLR,

WDT

0Bh,8Bh,

10Bh,18Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF(1) ADIF RCIF TXIF —CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000

8Ch PIE1 PSPIE(1) ADIE RCIE TXIE —CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000

1Eh ADRESH A/D Result Register High Byte xxxx xxxx uuuu uuuu

9Eh ADRESL A/D Result Register Low Byte xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE —ADON0000 00-0 0000 00-0

9Fh ADCON1 ADFM — — —PCFG3PCFG2PCFG1PCFG0--0- 0000 --0- 0000

85h TRISA —— PORTA Data Direction Register --11 1111 --11 1111

05h PORTA —— PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000

89h(1) TRISE IBF OBF IBOV PSPMODE — POR TE Dat a Direction bit s 0000 -111 0000 -111

09h(1) PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu

Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.

Note 1: These registers/bits are not available on the 28-pin devices.

PIC16F870/871

DS30569B-page 86  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 87

PIC16F870/871

11.0 SPECIAL FEATURES OF THE

CPU

The PIC16F870/871 devices have a host of features

intended to maximize system reliability, minimize cost

through elimination of external components, provide

Power Saving Operating modes and offer code

protect i on. Thes e are:

• Oscillator Selection

• RESET

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code Protection

• ID Locations

• In-Circuit Serial Programming

• Low Voltage In-Circuit Serial Programming

• In-Circuit Debugger

PIC16F870/871 devices have a Watchdog Timer,

which c an be s hu t-off only throug h configurat ion bi ts. It

runs off its own RC oscillator for added reliability.

There are two timers that offer necessary delays on

power-up. One is the Oscillator Start-up Timer (OST),

intended to keep the chip in RESET until the crystal

oscillator is stable. The other is the Power-up Timer

(PWRT), which provides a fixed delay of 72 ms (nomi-

nal) on pow er-up on ly. It is designed to keep th e par t in

RESET while the power supply stabilizes. With these

two tim ers on -ch ip, mo st applicati on s n eed no ext erna l

RESET circuitry.

SLEEP mode is designed to offer a very low current

Power-down mode. The user can wake-up from

SLEEP through external RESET, Watchdog Timer

Wake-up, or through an interrupt.

Several oscillator options are also made available to

allow the part to fit the application. The RC oscillator

option saves system cost while the LP crystal option

saves power. A set of configuration bits is used to

select various options.

Additional information on special features is available

in the PICmicro™ Mid-Range MCU Family Reference

Manual (DS33023).

11.1 Configurati on Bits

The configuration b its can be programmed (read as '0'),

or left unprogrammed (read as '1'), to select various

device configurations. The erased, or unprogrammed

value of the configuration word is 3FFFh. These bits

are mapped in program memory loc ati on 2007h.

It is impo rtant to n ote that addre ss 2007h is be yond the

user program memory space, which can be accessed

only during programming.

PIC16F870/871

DS30569B-page 88  2003 Microchip Technology Inc.

CP1 CP0 DEBUG — WRT CPD LVP BOREN CP1 CP0 PWRTEN WDTEN FOSC1 FOSC0

bit 13 bit 0

bit 13-1 2,

bit 5-4 CP1:CP0: FLASH Program Memory Code Protection bits(2)

11 = Code protection off

10 = Not supported

01 = Not supported

00 = Code protection on

bit 11 DEBUG: In-Circuit Debugger Mode

1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins

0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger

bit 10 Unimplemented: Read as ‘1’

bit 9 WRT: FLASH Program Memory Write Enable

1 = Unprotected program memory may be written to by EECON control

0 = Unprotected program memory may not be written to by EECON control

bit 8 CPD: Data EE Memory Code Protection

1 = Code protection off

0 = Data EEPROM memory code protected

bit 7 LVP: Low Voltage In-Circuit Serial Programming Enable bit

1 = RB3/PGM pin has PGM function, low voltage programming enabled

0 = RB3 is digital I/O, HV on MCLR must be used for programming

bit 6 BOREN: Brown-out Reset Enable bit(3)

1 = BOR enabled

0 = BOR disabled

bit 3 PWRTEN: Power-up Timer Enable bit(3)

1 = PWRT d i sabled

0 = PWRT enabled

bit 2 WDTEN: Watchdog Timer Enable bit

1 = WDT enab led

0 = WDT disabled

bit 1-0 FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator

10 = HS oscillator

01 = XT oscillator

00 = LP oscillator

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

3: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit

PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.

 2003 Microchip Technology Inc. DS30569B-page 89

PIC16F870/871

11.2 Oscillator Configurations

11.2.1 OSCILLATOR TYPES

The PIC16F870/871 can be operated in four different

Oscil lator modes. The user can p rogram two conf igura-

tion bits (FOSC1 and FOSC0) to select one of these

four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

11.2.2 CRYSTAL OSCILLATOR/CERAMIC

RESONATORS

In XT, LP or HS modes, a crystal or ceramic resonator

is connected to the OSC1/CLKI and OSC2/CLKO pins

to establish oscillation (Figure 11-1). The PIC16F870/

871 oscillator design requires the use of a parallel cut

crystal. Use of a series cut crystal may give a frequency

out of the crystal manufact urers specifications. Wh en in

XT, LP or HS modes, the device can have an external

clock s ourc e to dri ve th e O SC1 /C LKI pin (F igu re 11-2).

FIGU RE 11-1: CRYSTAL/CE R AMI C

RES ONAT OR OP ERA TIO N

(HS, XT OR LP

OSC CONFIGURATION)

FIGURE 11-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP

OSC CONFIGURATION)

TABLE 11-1: CERAMIC RESONATORS

Note 1: See Table 11-1 and Table 11-2 for

recommended values of C1 and C2.

2: A series resistor (Rs) may be required for

AT strip cut crys tals.

3: RF varies with the crystal chosen.

C1(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

SLEEP

Logic

PIC16F870/871

Rs(2)

Internal

Ranges Tested:

Mode Freq. OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF

15 - 68 pF

68 - 100 pF

15 - 68 pF

HS 8.0 MHz

16.0 MHz 10 - 68 pF

10 - 22 pF 10 - 68 pF

10 - 22 pF

These v alues are for design gu idance o nly.

See notes following Table 11-2.

Reson ators U sed :

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murat a Erie CSA 8.00 MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in ca pacitors.

OSC1

OSC2

Open

Clock from

Ext. Sy stem PIC16F870/871

PIC16F870/871

DS30569B-page 90  2003 Microchip Technology Inc.

TABLE 11-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR 11.2.3 RC OSCILLATOR

For timing insensitive applications, the “RC” device

option offers ad diti ona l cos t savings. The RC oscil lator

frequenc y is a fun ction of the sup pl y vo ltage, the re sis -

tor (REXT) and capacitor (CEXT) values, and the opera t-

ing temperature. In addition to this, the oscillator

frequency will vary from unit to unit due to normal pro-

cess parameter variation. Furthermore, the difference

in lead frame capacitance between package types will

also affect the oscillation frequency, especially for low

CEXT values. The user also needs to take into account

variation due to tolerance of external R and C

components used. Figure 11-3 shows how the R/C

combination is connected to the PIC16F870/871.

FIGU RE 11-3: RC O SCI LLAT OR M ODE

Osc Type Crystal

Freq. Cap. Range

C1 Cap. Range

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1 MHz 15 pF 15 pF

4 MHz 15 pF 15 pF

HS 4 MHz 15 pF 15 pF

8 MHz 15-33 pF 15-33 pF

20 MHz 15-33 pF 15-33 pF

These value s are for desi gn guidance only.

See notes following this table.

Crystals Used

32 kHz Epson C-001R32.768K-A ± 20 PPM

200 kHz STD XTL 200.000KHz ± 20 PPM

1 MHz ECS ECS-10-13-1 ± 50 PPM

4 MHz ECS ECS-40-20-1 ± 50 PPM

8 MHz EPSON CA-301 8.000M-C ± 30 PPM

20 MHz EPSON CA-301 20.000M-C ± 30 PPM

Note 1: Higher cap acita nce increase s the stabi lity

of oscillator, but also increases the

start - up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult

the resonator/crystal manufacturer for

appropriate values of external components.

3: Rs may be required in HS mode, as well

as XT mode, to av oid ov erdrivi ng crys tal s

with low drive level specification.

4: When migrating from other PICmicro®

devices, oscillator performance should be

verified.

OSC2/CLKO

CEXT

REXT

PIC16F870/871

OSC1

FOSC/4

Internal

Clock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

CEXT > 20pF

 2003 Microchip Technology Inc. DS30569B-page 91

PIC16F870/871

11.3 RESET

The PIC16F870/871 differentiates between various

kinds of RESET:

• Power-on Reset (POR )

•MCLR

Reset during normal operation

•MCLR

Reset during SLEEP

• WDT Reset (during normal operation)

• WDT Wake-up (during SLEEP)

• Brown-out Reset (BOR)

Some registers are not affected in any RESET condi-

tion. Their status is unknown on POR and unchanged

in any othe r RESET. Most other reg isters are reset to a

“RESET state” on Power-on Reset (POR), on the

MCLR and WDT Reset, on MCLR Reset during

SLEEP, and Brown-out Reset (BOR). They are not

affected by a WDT Wake-up, which is viewed as the

resumption of normal operation. The TO and PD bits

are set or cleared differently in different RESET situa-

tions, as indicated in Table 11-4. The se bits are used in

software to determine the nature of the RESET. See

Table 11-6 for a full description of RESET states of all

registers.

A simplif ied block diagra m of the On-Chip Rese t Circu it

is sh own in Figure 11-4.

These devices have a MCLR noise filter in the MCLR

Reset path. The filter will detect and ignore small

pulses.

It should be noted that a WDT Reset does not drive

MCLR pin low.

FIGURE 11-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

RESET

MCLR

VDD

OSC1

WDT

Module

VDD Rise

Detect

OST/PWRT

On-chip

RC OSC

WDT

Time-out

Power-on Reset

OST

10-bit Ripple Counter

PWRT

Chip_Reset

10-bit Ripple Counter

Reset

Enable OST

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.

Brown-out

Reset BOREN

(1)

PIC16F870/871

DS30569B-page 92  2003 Microchip Technology Inc.

11.4 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when

VDD rise is detected (in the range of 1.2V - 1.7V). To

take advantage of the POR, tie the MCLR pin direct ly

(or through a resistor) to VDD. This will eliminate

external RC components usually needed to create a

Power-on Reset. A maximum rise time for VDD is

specified. See Electrical Specifications for details.

When the device starts normal operation (exits the

RESET condition), device operating parameters (volt-

age, fre quency, temperature ,...) m ust be met to ensu re

operation. If these conditions are not met, the device

must be held in RESET until the operating conditions

are met. Brown-out Reset may be used to meet the

start-up conditions. For additional information, refer to

Applica tion Note, AN007, “P ower-up T roub le Shootin g”

(DS00007).

11.5 Power-up Ti me r (PWRT)

The Power-up Timer provides a fixed 72 ms nominal

time-out on power-up only from the POR. The Power-

up Timer operates on an internal RC oscillator. The

chip is kept in RESET as long as the PWRT is active.

The PWRT’s time delay allows VDD to rise to an

acceptable level. A configuration bit is provided to

enable/disable the PWRT.

The pow er-up time dela y will vary from chip to chip due

to VDD, temperature and process variation. See DC

parameters for details (TPWRT, parameter #33).

11.6 Oscillator Start-up Ti mer (OST)

The O scillator S ta rt-up T i mer (OST ) provide s a delay of

1024 oscillator cycles (from OSC1 input) after the

PWR T delay is over (if PWR T is enabled ). This helps to

ensure that the crystal oscillator or resonator has

started and stabilized.

The OST time-out is invoked only for XT, LP and HS

modes and only on Power-on Reset or Wake-up from

SLEEP.

11.7 Brown-out Reset (BOR)

The configuration bit, BOREN, can enable or disable

the Brown-out Reset circuit. If VDD falls below VBOR

(parameter D005, about 4V) for longer than TBOR

(param eter #35, about 100 µS), the brown- out situation

will reset the device. If VDD falls below VBOR for less

than TBOR, a RESET may not occur.

Once the brown-out occurs, the device will remain in

Brown-out Reset until VDD rises above VBOR. The

Power-up Timer then keeps the device in RESET for

TPWRT (par ameter #33, about 72 ms). If VDD sh ould fall

below VBOR during TPWRT, the Brown-out Reset pro-

cess will restart when VDD rises above VBOR with the

Power-up Timer Reset. The Power-up Timer is always

enabled when the Brown-out Reset circuit is enabled,

regardless of the state of the PWRT configuration bit.

11.8 Time- out Sequence

On power-up , the time-o ut seque nce is as follows: The

PWRT delay starts (if enabled) when a POR Reset

occurs. Then OST starts counting 1024 oscillator

cycles when PWRT ends (LP, XT, HS). When the OST

ends, the device comes out of RESET.

If MCLR is kept low long enough, the time-outs will

expire. Bring ing MCLR high will begin execution imme-

diately . This is useful for testing purposes or to synchro-

nize more than o ne PIC16F870/871 device operating in

parallel.

Table 11-5 shows the RESET conditions for the

STATUS, PCON and PC registers, while Table 11-6

shows the RESET conditions for all the registers.

11.9 Power Control/Status Register

(PCON)

The Power Control/Status Register, PCON, has up to

two bits depending upon the device.

Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is

unknown on a Power-on Reset. It must then be set by

the user and checked on subsequent RESETS to see if

bit BOR cleared, indicating a BOR occurred. When the

Brown-out Reset is disabled, the state of the BOR bit is

unpredictable and is, therefore, not valid at any time.

Bit1 is POR (Power-on Reset S tatus bit). It is cleared on

a Power-on Reset and unaffected otherwise. The user

must set this bit following a Power-on Reset.

TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS

Oscillator

Configuration

Power-up Brown-out Wake-up from SLEEP

PWRTEN = 0 PWRTEN = 1

XT, HS, LP 72 ms + 1024 TOSC 10 24 TOSC 72 ms + 1024 TOSC 1024 TOSC

RC 72 ms — 72 ms —

 2003 Microchip Technology Inc. DS30569B-page 93

PIC16F870/871

TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE

TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS

POR BOR TO PD

0x11Power-on Reset

0x0xIllegal, TO is set on POR

0xx0Illegal, PD is set on POR

1011Brown-out R ese t

1101WDT Reset

1100WDT Wake-up

11uuMCLR Reset during normal operation

1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP

Legend: x = don’t care, u = unchanged

Condition Program

Counter STATUS

Power-on Reset 000h 0001 1xxx ---- --0x

MCLR Reset during normal operation 000h 000u uuuu ---- --uu

MCLR Reset during SLEEP 000h 0001 0uuu ---- --uu

WDT Reset 000h 0000 1uuu ---- --uu

WDT Wake-up PC + 1 uuu0 0uuu ---- --uu

Brown-out Reset 000h 0001 1uuu ---- --u0

Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'

Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC i s loaded w ith th e interrupt vector (0004h).

TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS

Brown-out Reset MCLR Resets

WDT Reset Wake-up via WDT or

Interrupt

W PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

INDF PIC16F870 PIC16F871 N/A N/A N/A

TMR0 PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

PCL PIC16F870 PIC16F871 0000h 0000h PC + 1(2)

STATUS PIC16F870 PIC16F871 0001 1xxx 000q quuu(3) uuuq quuu(3)

FSR PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

PORTA PIC16F870 PIC16F871 --0x 0000 --0u 0000 --uu uuuu

PORTB PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

PORTC PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

PORTD PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

PORTE PIC16F870 PIC16F871 ---- -xxx ---- -uuu ---- -uuu

PCLATH PIC16F870 PIC16F871 ---0 0000 ---0 0000 ---u uuuu

INTCON PIC16F870 PIC16F871 0000 000x 0000 000u uuuu uuuu(1)

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,

r = reserved, maintain clear

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Ta ble 11-5 for RESET value for specific condition.

PIC16F870/871

DS30569B-page 94  2003 Microchip Technology Inc.

PIR1 PIC16F870 PIC16F871 r000 -000 r000 -000 ruuu -uuu(1)

PIC16F870 PIC16F871 0000 -000 0000 -000 uuuu -uuu(1)

PIR2 PIC16F870 PIC16F871 ---0 ---- ---0 ---- ---u ----(1)

TMR1L PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

TMR1H PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

T1CON PIC16F870 PIC16F871 --00 0000 --uu uuuu --uu uuuu

TMR2 PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu

T2CON PIC16F870 PIC16F871 -000 0000 -000 0000 -uuu uuuu

CCPR1L PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

CCPR1H PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

CCP1CON PIC16F870 PIC16F871 --00 0000 --00 0000 --uu uuuu

RCSTA PIC16F870 PIC16F871 0000 000x 0000 000x uuuu uuuu

TXREG PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu

RCREG PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu

ADRESH PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON0 PIC16F870 PIC16F871 0000 00-0 0000 00-0 uuuu uu-u

OPTION_REG PIC16F870 PIC16F871 1111 1111 1111 1111 uuuu uuuu

TRISA PIC16F870 PIC16F871 --11 1111 --11 1111 --uu uuuu

TRISB PIC16F870 PIC16F871 1111 1111 1111 1111 uuuu uuuu

TRISC PIC16F870 PIC16F871 1111 1111 1111 1111 uuuu uuuu

TRISD PIC16F870 PIC16F871 1111 1111 1111 1111 uuuu uuuu

TRISE PIC16F870 PIC16F871 0000 -111 0000 -111 uuuu -uuu

PIE1 PIC16F870 PIC16F871 r000 -000 r000 -000 ruuu -uuu

PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu

PIE2 PIC16F870 PIC16F871 ---0 ---- ---0 ---- ---u ----

PCON PIC16F870 PIC16F871 ---- --qq ---- --uu ---- --uu

PR2 PIC16F870 PIC16F871 1111 1111 1111 1111 1111 1111

TXSTA PIC16F870 PIC16F871 0000 -010 0000 -010 uuuu -uuu

SPBRG PIC16F870 PIC16F871 0000 0000 0000 0000 uuuu uuuu

ADRESL PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

ADCON1 PIC16F870 PIC16F871 0--- 0000 0--- 0000 u--- uuuu

EEDATA PIC16F870 PIC16F871 0--- 0000 0--- 0000 u--- uuuu

EEADR PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

EEDATH PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

EEADRH PIC16F870 PIC16F871 xxxx xxxx uuuu uuuu uuuu uuuu

EECON1 PIC16F870 PIC16F871 x--- x000 u--- u000 u--- uuuu

EECON2 PIC16F870 PIC16F871 ---- ---- ---- ---- ---- ----

TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Brown-out Reset MCLR Resets

WDT Reset Wake-up via WDT or

Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,

r = reserved, maintain clear

Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Ta ble 11-5 for RESET value for specific condition.

 2003 Microchip Technology Inc. DS30569B-page 95

PIC16F870/871

FIGURE 11-5: TIME-OUT SEQU ENCE ON POWER- UP (MCL R TIED TO VDD)

FIGURE 11-6: TIME-OUT SEQU ENCE ON POWER- UP (MCL R NOT T IED TO VDD): CASE 1

FIGURE 11-7: TIME-OUT SEQU ENCE ON POWER- UP (MCL R NOT T IED TO VDD): CASE 2

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

PIC16F870/871

DS30569B-page 96  2003 Microchip Technology Inc.

FIGURE 11-8: SLOW RISE TIME (MCLR TIED TO VDD)

11.10 Interrupts

The PIC16F870/871 family has up to 14 sources of

interrupt. The Interrupt Control register (INTCON)

records individual interrupt requests in flag bits. It also

has individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>),

enables (if set) all unmasked interrupts, or disables (if

cleared ) all i nterrupt s. W hen bit GIE i s enab led, a nd an

inter rupt’s flag bit and mask bi t are s et, the int errupt will

vector immediately. Individual interrupts can be dis-

abled through their corresponding enable bits in vari-

ous registers. Individual interrupt bits are set,

regardless of the status of the GIE bit. The GIE bit is

cleared on RESET.

The “return from interrupt” instruction, RETFIE, exits

the i nter rupt r out ine as well as sets the GIE b it, wh ich

re-enabl es inte rrupts.

The RB0/INT pin interrupt, the RB port change

interrupt, and the TMR0 overflow interrupt flags are

cont ained in the INTCON regist er.

The peripheral interrupt flags are contained in the spe-

cial function registers, PIR1 and PIR2. The correspond-

ing interrupt enable bits are contained in special

function registers, PIE1 and PIE2, and the peripheral

interrupt enable bit is contained in special function

When an interrupt is responded to, the GIE bit is

cleared to disable any further interrupt, the return

address is pu sh ed o nto the s t ac k a nd the PC is lo ade d

with 0004h. Once in the Interrupt Service Routine, the

source(s) of the interrupt can be determined by polling

the i nterr upt flag bits. T he inte rrupt flag bi t(s) mu st be

cleared in software before re-enabling interrupts to

avoid recursive interrupts.

For external interrupt events, such as the INT pin or

PORTB change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends when the interrupt event occurs. The latency

is the s ame for one or tw o-cy cle in str uction s. Indi vidua l

interrupt flag bits are set, regardless of the status of

their corresponding mask bit, PEIE bit, or GIE bit.

VDD

MCLR

INTERNAL POR

PWRT TIME-O UT

OST TIME-OUT

INTERNAL RESET

0V 1V

TPWRT

TOST

Note: Individual interrupt flag bits are set,

regardless of the status of their

corresponding mask bit, or the GIE bit.

 2003 Microchip Technology Inc. DS30569B-page 97

PIC16F870/871

FIGU RE 11-9 : INTERRU P T L O GI C

11.10.1 INT INTERRUPT

External in terrupt on the RB0/INT pin is edge trigg ered,

either rising, if bit INTEDG (OPTION_REG<6>) is set,

or fall ing , if th e IN TEDG bit i s cl ea r. When a valid edg e

appears on the RB0/INT pin, flag bit INTF

(INTCON<1>) is set. This interrupt can be disabled by

clearing enable bit INTE (INTCON<4>). Flag bit INTF

must be cleared in software in the Interrupt Service

Routin e before re-enablin g this interrupt. The INT int er-

rupt can wake-up the processor from SLEEP, if bit INTE

was set prior to going into SLEEP. The status of global

interrupt enable bit, GIE, decides whether or not the

processor branches to the interrupt vector following

wake-up. See Section 11.13 for details on SLEEP

mode.

11.10.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will set

flag bit T0IF (INTCON<2>). The interrupt can be

enabled/disabled by setting/clearing enable bit T0IE

(INTCON<5>) (Section 5.0).

11.10.3 PORTB INTCON CHANGE

An input change on PORTB<7:4> sets flag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled

by setting/clearing enable bit RBIE (INTCON<4>)

(Section 4.2).

PSPIF

PSPIE ADIF

ADIE

RCIF

RCIE

TXIF

TXIE

CCP1IF

CCP1IE

TMR2IF

TMR2IE

TMR1IF

TMR1IE

T0IF

T0IE

INTF

INTE

RBIF

RBIE

GIE

PEIE

Wake-up (If in SLEEP mode)

Interrupt to CPU

The following table shows which devices have which interrupts.

Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF CCP1IF TMR2IF TMR1IF EEIF

PIC18F870 Yes Yes Yes — Yes Yes Yes Yes Yes Yes Yes

PIC18F871 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

EEIF

EEIE

PIC16F870/871

DS30569B-page 98  2003 Microchip Technology Inc.

11.11 Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. T ypically , users may wish to save key reg-

isters d uri ng a n inte rrupt, (i.e., W reg ister a nd STATUS

For the PIC1 6F870/871 d evices, th e register W_TE MP

must be defined in both banks 0 and 1 and must be

defined at the same of fse t from the bank bas e addres s

(i.e., If W_TEMP is defined at 0x20 in bank 0, it must

also be defined at 0xA0 in bank 1). The registers,

PCLATH_TEMP and STATUS_TEMP, are only de fine d

in bank 0.

Since the upper 16 bytes of each bank are common in

the PIC16F870/871 devices, temporary holding regis-

ters W_TEMP, STATUS_TEMP, and PCLATH_TEMP

should be placed in here. These 16 locations don’t

require banking and therefore, make it easier for con-

text save and restore. The same code shown in

Example 11-1 can be used.

EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register

SWAPF STATUS,W ;Swap status to be saved into W

CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0

MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register

MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3

MOVWF PCLATH_TEMP ;Save PCLATH into W

CLRF PCLATH ;Page zero, regardless of current page

:(ISR) ;(Insert user code here)

MOVF PCLATH_TEMP, W ;Restore PCLATH

MOVWF PCLATH ;Move W into PCLATH

SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W

;(sets bank to original state)

MOVWF STATUS ;Move W into STATUS register

SWAPF W_TEMP,F ;Swap W_TEMP

SWAPF W_TEMP,W ;Swap W_TEMP into W

 2003 Microchip Technology Inc. DS30569B-page 99

PIC16F870/871

11.12 Watchdog Timer (WDT)

The W atchdog T imer is a free running on -chip RC oscil-

lator which does not require any external components.

This RC oscillator is separate from the RC oscillator of

the OSC 1 /CLKI pin . Th at me ans th at the WD T will ru n,

even if the clock on the OSC1/CLKI and OSC2/CLKO

pins of the device has been stopped, for example, by

execution of a SLEEP instruction.

During normal operation, a WDT time-out generates a

device RESET (W atchdog Timer Reset). If the device is

in SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation

(W a tchdo g T im er W a ke-up). The TO bi t in the STATUS

time-out.

The WDT can be permanently disabled by clearing

configuration bit WDTEN (Section 11.1).

WDT time-out period values may be found in the Elec-

trical Specifications section under parameter #31. Val-

ues for the WDT prescaler (actually a postscaler, but

shared with the Timer0 prescaler) may be assigned

using the OPTION_REG register.

FIGURE 1 1-10: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 11-7: SUMMARY OF WATCHDOG TIMER REGISTERS

Note 1: The CLRWDT and SLEEP instructions

clear the WDT and the postscaler, if

assigned to the WDT, and prevent it from

timing out and generating a device

RESET condition.

2: When a CLRWDT instruction is executed

and the pre scaler is assi gned to the WDT,

the prescaler count will be cleared, but

the pr es ca ler ass ig nm ent is no t c han ged.

From TMR0 Clock Source

(Figure 5-1)

To TMR0 (Figure 5-1)

Postscaler

WDT Timer

WDT

Enable Bit

PSA

8 - to - 1 MUX PS2:PS0

MUX PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION_REG register.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Config. bits (1) BOREN(1) CP1 CP0 PWRTEN(1) WDTEN FOSC1 FOSC0

81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cell s are not used by the Watchdog Time r.

Note 1: See Register 11-1 for operation of these bits .

PIC16F870/871

DS30569B-page 100  2003 Microchip Technology Inc.

11.13 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keep s runni ng, the PD bi t ( STATUS<3>) is c lea red , th e

TO (STATUS<4>) bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had

before the SLEEP instruction was executed (driving

high, low, or hi-impedance).

For lowest current consumption in this mode, place all

I/O pins at either VDD or VSS, ensure no external cir-

cuitr y is dr awing cu rrent from th e I/O pi n, powe r-down

the A/D and disable external clocks. Pull all I/O pins

that are hi-impedance inputs, high or low externally, to

avoid s witchi ng curre nts caus ed by fl oating input s. Th e

T0CKI input should also be at VDD or VSS for lowest

current consumption. The contribution from on-chip

pull-ups on PORTB should also be considered.

The MCLR pin must be at a logic high level (VIHMC).

11.13.1 WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

1. External RESET input on MCLR pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change or

peripheral interrupt.

External MCLR Reset will cause a device RESET. All

other events are considered a continuation of program

execut ion and c aus e a “wak e-u p”. The TO and PD bit s

in the STATUS register can be used to determine the

cause of device RESET. The PD bit, which is set on

power-up, is cleared when SLEEP is invoked. The TO

bit is cleared if a WDT time-out occurred and caused

wake-up.

The follo wing periph eral interrupt s can wake the device

from SLEEP:

1. PSP read or write (PIC16F874/877 only).

2. TMR1 interrup t. T imer1 m ust be ope rating as an

asynchronous counter.

3. CCP Capture mode interrupt.

4. Special event trigger (Timer1 in Asynchronous

mode using an external clock).

5. SSP (START/STOP) bit detect interrupt.

6. SSP transmit or receive in Slave mode

(SPI/I2C).

7. USART RX or TX (Synchronous Slave mode).

8. A/D conversion (when A/D clock source is RC).

9. EEPROM write operation completion

Other peripherals cannot generate interrupts, since

during SLEEP, no on-chip clocks are present.

When the SLEEP instruction is being e xecuted, the next

instruction (PC + 1) is pre-fetched. For the device to

wake-up thro ugh an interrupt eve nt, the co rres pon din g

interrupt enable bit must be set (enabled). Wake-up is

regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have a NOP after the SLEEP instruction.

11.13.2 WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit

and inte rrupt fla g bit s et, one of the fo llow ing wil l occur:

• If the interrupt occurs before the execution of a

SLEEP instr uct ion , the SLEEP instruction will com-

plete as a NOP. Therefore, the WDT and WDT

pos tscaler will not be cleared, the TO bit will not

be set and PD bits will not be cle are d.

• If the interrupt occurs during or after the

execution of a SLEEP ins truc tio n, the dev ic e wi ll

immediately wake-up from SLEEP. The SLEEP

instruction will be completely executed before the

wake-up. Therefore, the WDT and WDT

pos tscaler will be cleared, the TO bit will be set

and the PD bit will be cleared.

Even if the flag bits were checked before executing a

SLEEP instruction, it may be possible for flag bits to

become set before the SLEEP instruction completes. To

determine whether a SLEEP instruction executed, test

the PD bit. If the PD bit is set, the SLEEP instruction

was executed as a NOP.

To ensure that the WDT is cleared, a CLRWDT

instruction should be executed before a SLEEP

instruction.

 2003 Microchip Technology Inc. DS30569B-page 101

PIC16F870/871

FIGU RE 11-11: WAKE -U P FR O M SLEEP T H ROUG H I NT E R RU PT

11.14 In-Circuit Debugger

When the DEBUG bit in the configuration word is pro-

grammed to a '0', the In-Circuit Debugger functionality

is enabled. This function allows simple debugging func-

tions when used with MPLAB® ICD. When the micro-

controller has this feature enabled, some of the

resourc es a r e no t av ai lab le fo r ge nera l us e. Table 11-8

shows which features are consumed by the

background debugger.

TABLE 11-8: DEBUGGER RESOURCES

To use the In-Circuit Debugger function of the micro-

controller, the design must implement In-Circuit Serial

Programming connections to MCLR/VPP, VDD, GND,

RB7 and RB6. This will interface to the In-Circuit

Debugger module available from Microchip, or one of

the third party development tool companies.

11.15 Program Verification/Code

Protection

If the code protection bit(s) have not been pro-

grammed, the on-chip program memory can be read

out for verification purposes.

11.16 ID Locations

Four memo ry locations (2000h - 2003h) are designated

as ID locations, where the user can store checksum or

other code identification numbers. These locations are

not accessible during normal execution, but are read-

able and writable during program/verify. It is recom-

mended that only the 4 Least Significant bits of the ID

loc ation are used.

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKO(4)

INT pin

INTF Flag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

Fetched

Instruction

Executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency(2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h) Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

TOST(2)

PC+2

Note 1: XT, HS or LP Oscillator mode assumed.

2: TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Osc mode.

3: GIE = 1 assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.

4: CLKO is not available in these Osc modes, but shown here for timing reference.

I/O pins RB6, RB7

Stack 1 level

Program Memory Address 0000h mu st be NOP

Last 100h word s

Data Memory 0x070 (0x0F0, 0x170, 0x1F0)

0x1EB - 0x1EF

PIC16F870/871

DS30569B-page 102  2003 Microchip Technology Inc.

11.17 In-Circuit Serial Programming

PIC16F870/871 microcontrollers can be serially pro-

grammed while in the end application circuit. This is

simply done with tw o lines for cl ock and data and thre e

other lines for power, ground, and the programming

voltage. This allows customers to manufacture boards

with unprogrammed devices, and then program the

microcontroller just before shipping the product. This

also allows the most recent firmware, or a custom

firmware to be programmed.

When usin g IC SP, the part mu st be supp li ed at 4.5V to

5.5V, if a bulk erase will be executed. This includes

reprogramming of the code protect, both from an on-

state to off-state. For all other cases of ICSP, the part

may be programmed at the normal operating voltages.

This m eans c alibration values, unique u ser ID s, or us er

code can be reprogrammed or added.

For complete details of serial programming, please

refer to the EEPROM Memory Programming

Specific at ion for the PIC16F87X (DS39025) .

11.18 Low Voltage ICSP Programming

The LVP bit of the configu r ati on word ena bl es low volt-

age ICSP programming. This mode allows the micro-

controller to be programmed via ICSP, using a VDD

source i n the op erating vo ltage ra nge. This o nly means

that VPP does not have to be brought to VIHH, but can

instead be left at the normal operating voltage. In this

mode, the RB3/PGM pin is dedicated to the program-

ming function and ceases to be a general purpose I/O

pin. During programming, VDD is applied to the MCLR

pin. To ente r Programm ing mode , VDD mus t b e app lied

to the RB3/PGM pin, provided the LVP bit is set. The

LVP bit defaults to on (‘1’) from the factory.

If Low V ol tage Program ming mode is not us ed, the L V P

bit can be programmed to a '0' an d RB3/PGM beco mes

a digital I/O pin. Ho wev er, the LVP bit may o nly b e p ro-

grammed when programming is entered with VIHH on

MCLR. The LVP bit can only be charged when using

high voltage on MCLR.

It should be noted, that once the L VP bit is programmed

to 0, onl y the High Voltage Programming m ode is avai l-

able and onl y High Voltage Pro gramming mo de can b e

used to program the device.

When using low volt age ICSP, the part must be supplied

at 4.5V to 5.5V, if a bulk erase will be executed. This

includes reprogramming of the code protect bit s from an

on-state to off-state. For all other cases of low voltage

ICSP, the part may be programmed at the normal oper-

ating voltage. This means calibration values, unique

user IDs, or user code can be reprogram med or added .

Note 1: The High Voltage Programming mode is

always available, regardless of the state

of the LVP bit, by applying VIHH to the

MCLR pin.

2: While in Low Voltage ICSP mode, the

RB3 pin can no longer be used as a

general purpose I/O pin.

3: When using low voltage ICSP program-

ming (LVP) and the pull-ups on PORTB

are enabled, bit 3 in the TRISB register

must be cleared to disable the pull-up on

RB3 and ensure the proper operation of

the device.

4: RB3 should not be allowed to float if LVP

is enabled. An external pull-down device

should be used to default the device to

normal Operating mode. If RB3 floats

high, the PIC16F870/871 devices will

enter Programming mode.

5: LVP mode is enabled by default on all

device s shippe d from Microchi p. It can b e

disabled by clearing the LVP bit in the

CONFIG register.

6: Disabling LVP will provide maximum

compatibility to other PIC16CXXX

devices.

 2003 Microchip Technology Inc. DS30569B-page 103

PIC16F870/871

12.0 INSTRUCTION SET SUMMARY

Each PIC16F870/871 instruction is a 14-bit word,

divided into an OPCODE, which specifies the instruc-

tion type, and one or more operands, which further

specify the operation of the instruction. The

PIC16F870/871 instruction set summary in Table 12-2

lists byte-oriented, bit-oriented, and literal and con-

trol operations. Table 12-1 shows the opcode field

descriptions.

For byte-oriented instructio ns, 'f' rep res ents a file reg-

ister designator and 'd' represents a destination desig-

nator. The file register designator specifies which file

The desti nation designator specifies where the result of

the operation is to be placed. If 'd' is zero, the result is

placed in the W reg ister . If 'd' is one, the result is placed

in the file register specified in the instruction.

For bit-oriented instructions, 'b' represents a bit field

design ator which selec t s the nu mb er o f th e bi t a f fected

by the oper ation, w hile 'f' represent s the add ress of the

file in which the bit is located.

For literal and control operations, 'k' represents an

eight or eleven bit constant or literal value.

TABLE 12-1: OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped

into three basi c categories :

•Byte-oriented operations

•Bit-oriented operations

•Literal and cont rol operations

All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true, or the pro-

gram counter is changed as a result of an instruction.

In this c ase, the execu tion t a kes two i nstruc tio n cycles ,

with the second cycle executed as a NOP. One instru c-

tion cycle consists of four oscillator periods. Thus, for

an osc illator frequency of 4 M Hz, th e normal i nstructio n

executi on time is 1 µs . If a conditional test is true, or th e

program counter is changed as a result of an

instruction, the instruction execution time is 2 µs.

Table 12-2 lists the instructions recognized by the

MPASMTM assembler.

Figure 12-1 shows the general formats that the

instructions can have.

All examples use the following format to represent a

hexadecimal number:

0xhh

where h signifies a hexadecimal digit.

FIGU RE 12 - 1: GEN ERA L F O RM AT F O R

INSTRUCTIONS

A description of each instruction is available in the

PICmicro™ Mid-Range MCU Family Reference M anual

(DS33023).

Field Description

fRegister f ile address (0 x00 to 0x7F)

WWorking register (accumulator)

bBit address within an 8-bit file register

kLiteral field, constant data or label

xDon't care location (= 0 or 1).

The assembler will generate code with x = 0.

It is the recommended form of use for

compatibility with all Microchip sof tware tools.

dDestination select; d = 0: store resu lt in W,

d = 1: store result in file register f.

Default is d = 1.

PC Program Counter

TO Ti me -out bit

PD Power-down bit

Note: To maintain upward compatibility with

future PIC16F870/871 products, do not

use the OPTION and TRIS instructions.

Byte-oriented file register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f

f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT # ) f (FIL E #)

b = 3-bit bit address

f = 7-bit file register address

Literal and control operations

13 8 7 0

OPCODE k (literal )

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit imm ediate value

General

CALL and GOTO instructions only

PIC16F870/871

DS30569B-page 104  2003 Microchip Technology Inc.

TABLE 12-2: PIC16F870/871 INSTRUCTION SET

Mnemonic,

Operands Description Cycles 14-Bit Opcode Status

Affected Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS

ADDWF

ANDWF

CLRF

CLRW

COMF

DECF

DECFSZ

INCF

INCFSZ

IORWF

MOVF

MOVWF

NOP

RLF

RRF

SUBWF

SWAPF

XORWF

f, d

Add W and f

AND W with f

Clear f

Clear W

Complement f

Decrement f

Decrement f, Skip if 0

Increment f

Increment f, Skip if 0

Inclusive OR W with f

Move f

Move W to f

No Operation

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Swap nibbles in f

Exclusive OR W with f

1(2)

0111

0101

0001

1001

0011

1011

1010

1111

0100

1000

0000

1101

1100

0010

1110

0110

dfff

lfff

0xxx

dfff

lfff

0xx0

dfff

ffff

xxxx

ffff

0000

ffff

C,DC,Z

1,2

1,2,3

1,2

1,2,3

1,2

BIT-ORIENTED FILE REGISTER OPERATIONS

BCF

BSF

BTFSC

BTFSS

f, b

Bit Clear f

Bit Set f

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

1 (2)

00bb

01bb

10bb

11bb

bfff

ffff

1,2

LITERAL AND CONTROL OPERATIONS

ADDLW

ANDLW

CALL

CLRWDT

GOTO

IORLW

MOVLW

RETFIE

RETLW

RETURN

SLEEP

SUBLW

XORLW

Add literal and W

AND literal with W

Call subroutine

Clear Watchdog Timer

Go to address

Inclusive OR literal with W

Move litera l to W

Return from interrupt

Return with literal in W

Return from Subroutine

Go into Standby mode

Subtract W from literal

Exclusive OR literal with W

111x

1001

0kkk

0000

1kkk

1000

00xx

0000

01xx

0000

110x

1010

kkkk

0110

kkkk

0000

kkkk

0000

0110

kkkk

0100

kkkk

1001

kkkk

1000

0011

kkkk

C,DC,Z

TO,PD

C,DC,Z

Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins t hemselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external

device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if

assigned to the Timer0 module.

3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU

Family Reference Manual (DS33023).

 2003 Microchip Technology Inc. DS30569B-page 105

PIC16F870/871

12.1 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [ label ] ADDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) + k → (W)

Status Affected: C, DC, Z

Description: The contents of the W register

are ad ded to the eight-bi t literal 'k'

and the result is placed in the W

ADDWF Add W and f

Syntax: [ label ] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) + (f) → (destination)

Status Affected: C, DC, Z

Desc ription: Add the conten ts of the W regis ter

with register 'f'. If 'd' is 0, the result

is stored in the W register. If 'd' is

1, the result is stored back in

ANDLW AND Literal with W

Syntax: [ label ] ANDLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .AND. (k) → (W)

Status Affected: Z

Description: The contents of W register are

AND’ed with the eight-bit literal

'k'. The result is placed in the W

ANDWF AND W with f

Syntax: [ label ] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .AND. (f) → (destination)

Status Affected: Z

Description: AND the W register with register

'f'. If 'd' is 0, the result is stored in

the W regist er. If 'd' is 1, the re sult

is stored back in register 'f'.

BCF Bit Clear f

Syntax: [ label ] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 0 → (f<b>)

Status Affe cted: None

Description: Bit 'b' in register 'f' i s cleared.

BSF Bit Set f

Syntax: [ label ] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: 1 → (f<b>)

Status Affe cted: None

Description: Bit 'b' in register 'f' i s set.

BTFSS Bit Test f, Skip if Set

Syntax: [ label ] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7

Operation: skip if (f<b>) = 1

Status Affected: None

Descr ipti on : If bit 'b' in regi st er ' f' is '0 ', the nex t

instructi on is ex ecuted.

If bit 'b' is '1', then the next instruc-

tion is discarded and a NOP is

executed instead, making this a

CY instruction.

BTFSC Bit Test, Skip if Clear

Syntax: [ label ] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7

Operation: skip if (f<b>) = 0

Status Affected: None

Description: If bit 'b' in register 'f' is '1', the next

instruction is executed.

If bit 'b', in register 'f', is '0', the

next instru ction is discar de d, and

a NOP is executed instead, making

this a 2 TCY instruction.

PIC16F870/871

DS30569B-page 106  2003 Microchip Technology Inc.

CALL Call Subroutine

Syntax: [ label ] CALL k

Operands: 0 ≤ k ≤ 2047

Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11>

Status Affected: None

Description: Call Subroutine. First, return

address (PC+1) is pushed onto

the stack. The eleven-bit

immediate address is loaded into

PC bits <10:0>. The upper bits of

the PC are loa ded from PC LATH.

CALL is a two-cycle instruction.

CLRF Clear f

Syntax: [ label ] CLRF f

Operands: 0 ≤ f ≤ 127

Operation: 00h → (f)

1 → Z

Status Affected: Z

Desc ript ion : The content s of regi ste r 'f' are

cleared and the Z bit is set.

CLRW Clear W

Syntax: [ label ] CLRW

Operands: None

Operation: 00h → (W)

1 → Z

Status Affected: Z

Description: W register is cleared. Zero bit (Z)

is set.

CLRWDT Clear Watchdog Timer

Syntax: [ label ] CLRWDT

Operands: None

Operation: 00h → WDT

0 → WDT prescaler,

1 → TO

1 → PD

Status Affe cted: TO, PD

Description: CLRWDT instruction resets the

Watchdog Timer. It also resets

the prescaler of the WDT. Status

bits TO and PD are set.

COMF Complement f

Syntax: [ label ] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (destination)

Status Affe cted: Z

Description: The contents of register 'f' are

complemented. If 'd' is 0, the

result is s tored in W. If 'd' is 1, the

result is stored back in register 'f'.

DECF Decrement f

Syntax: [ label ] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination)

Status Affe cted: Z

Description: Decrement register 'f'. If 'd' is 0,

the result is stored in the W

stored back in register 'f'.

 2003 Microchip Technology Inc. DS30569B-page 107

PIC16F870/871

DECFSZ Decrement f, Skip if 0

Syntax: [ label ] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - 1 → (destination);

skip if result = 0

Status Affected: None

Description: The contents of register 'f' are

decremented. If 'd' is 0, the result

is placed in the W register. If 'd' is

1, the result is placed back in

If the result is 1, the next instruc-

tion is executed. If the result is 0,

then a NOP is executed instead

making it a 2 TCY instruction.

GOTO Unconditional Branch

Syntax: [ label ] GOTO k

Operands: 0 ≤ k ≤ 2047

Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11>

Status Affected: None

Description: GOTO is an unconditional branch.

The e le ven -bi t im me dia t e v al ue i s

loaded into PC bits <10:0>. The

upper bits of PC are loaded from

PCLATH<4:3>. GOTO is a

two-cycle instruction.

INCF Increment f

Syntax: [ label ] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination)

Status Affected: Z

Description: The contents of register 'f' are

incremented. If 'd' is 0, the result

is placed in the W regis ter. If 'd' is

1, the result is placed back in

INCFSZ Increment f, Skip if 0

Syntax: [ label ] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) + 1 → (destination),

skip if result = 0

Status Affected: None

Description: The contents of register 'f' are

incremen ted. If 'd' is 0, the result is

placed in the W register. If 'd' is 1,

the result is placed back in

regis te r 'f'.

If the result is 1, the next instruc-

tion is executed. If the result is 0,

a NOP is e xecuted i nstead, ma king

it a 2 TCY instruction.

IORLW Inclusive OR Literal with W

Syntax: [ label ] IORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .OR. k → (W)

Status Affe cted: Z

Descr iption: The con tents of t he W register a re

OR’ed with the eight bit literal 'k'.

The result is placed in the W

IORWF Inclusive OR W with f

Syntax: [ label ] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .OR. (f) → (dest ination)

Status Affe cted: Z

Description: Inclusive OR the W register with

placed in the W register. If 'd' is 1

the result is placed back in

PIC16F870/871

DS30569B-page 108  2003 Microchip Technology Inc.

MOVF Move f

Syntax: [ label ] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) → (destinati on )

Status Affected: Z

Description: The contents of register f are

moved to a destination dependant

upon the status of d. If d = 0,

destination is W register. If d = 1,

the destination is file register f itself.

d = 1 is useful to test a file register,

since status flag Z is affected.

MOVLW Move Literal to W

Syntax: [ label ] MOVLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W)

Status Affected: None

Description: The eight-bit literal 'k' is loaded

into W register. The don’t cares

will assemble as 0’s.

MOVWF Move W to f

Syntax: [ label ] MOVWF f

Operands: 0 ≤ f ≤ 127

Operation: (W) → (f)

Status Affected: None

Description: Move data from W register to

NOP No Operation

Syntax: [ label ] NOP

Operands: None

Operation: No operation

Status Affe cted: None

Description: No operation.

RETFIE Return from Interrupt

Syntax: [ label ] RETFIE

Operands: None

Operation: TOS → PC,

1 → GIE

Status Affe cted: None

RETLW Return with Literal in W

Syntax: [ label ] RETLW k

Operands: 0 ≤ k ≤ 255

Operation: k → (W);

TOS → PC

Status Affe cted: None

Description: The W register is loaded with the

eight-bit literal 'k'. The program

counter is loaded from the top of

the stack (the return address).

This is a two-cycle instruction.

 2003 Microchip Technology Inc. DS30569B-page 109

PIC16F870/871

RLF Rotate Left f through Carry

Syntax: [ label ] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Description: The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0, the result is placed in

the W register . If 'd' is 1, the result is

stored back in register 'f'.

RETURN Return from Subroutine

Syntax: [ label ] RETURN

Operands: None

Operation: TOS → PC

Status Affected: None

Description: Return from subroutine. The stack

is POPed an d t he top o f th e s t a ck

(TOS) is loaded into the program

counter. This is a two-cycle

instruction.

RRF Rotate Right f through Carry

Syntax: [ label ] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: See description below

Status Affected: C

Desc ript ion : The content s of regis te r 'f' are

rotat ed one bit to the r ight throug h

the C arry Flag. If 'd' is 0 , the result

is placed in the W register. If 'd' is

1, the result is placed back in

SLEEP

Syntax: [ label ] SLEEP

Operands: None

Operation: 00h → WDT,

0 → WDT prescaler,

1 → TO,

0 → PD

Status Affe cted: TO , PD

Descripti on: The pow er-down statu s bit, PD is

cleared. Time-out status bit, TO

is set. Watchdog Timer and its

prescaler are cleare d.

The proce ssor is put into SLEEP

mode with th e oscillator sto pped.

SUBLW Subtract W from Literal

Syntax: [ label ] SUBLW k

Operands: 0 ≤ k ≤ 255

Operation: k - (W) → (W)

Status Affected: C, DC, Z

Description: The W register is subtracted (2’s

complement method) from the

eight-bit literal 'k'. The result is

placed in the W register.

SUBWF Subtract W from f

Syntax: [ label ] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f) - (W) → (destination)

Status

Affected: C, DC, Z

Description: Subtract (2’s complement method)

W register from regi ster 'f'. If 'd' is 0,

the result is stored in the W

stored back in register 'f'.

PIC16F870/871

DS30569B-page 110  2003 Microchip Technology Inc.

SWAPF Swap Nibbles in f

Syntax: [ label ] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (destination<7:4>),

(f<7:4>) → (destination<3:0>)

Status Affected: None

Description: The upper and lower nibbles of

0, the result is placed in the W

placed in register 'f'.

XORLW Exclusive OR Literal with W

Syntax: [ label ]XORLW k

Operands: 0 ≤ k ≤ 255

Operation: (W) .XOR. k → (W)

Status Affected: Z

Description: The contents of the W register

are XOR’ed with the eight-bit

literal 'k'. The result is placed in

the W register.

XORWF Exclusive OR W with f

Syntax: [ label ] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (W) .XOR. (f) → (destination)

Status Affe cted: Z

Description: Exclusive OR the contents of the

W register with register 'f'. If 'd' is

0, the result is stored in the W

stored back in register 'f'.

 2003 Microchip Technology Inc. DS30569B-page 111

PIC16F870/871

13.0 DEVELOPMENT SUPPORT

The PICmicro® microcontrollers are supported with a

full ran ge of hardware a nd softwa re develo pment to ols:

• Integrated Development Environment

- MPLAB® IDE Software

• Assemblers/Compilers/Linkers

- MPASMTM Assembler

- MPLAB C17 and MPLAB C18 C Compilers

-MPLINK

TM Object Linker/

MPLIBTM Object Librarian

- MPLAB C30 C Compiler

- MPLAB ASM30 Assembler/Linker/Library

• Simulators

- MPLAB SIM Software Simulator

- MPLAB dsPIC30 Software Simulator

•Emulators

- MPLAB ICE 2000 In-Circuit Emulator

- MPLAB ICE 4000 In-Circuit Emulator

• In-Circuit Debugger

- MPLAB ICD 2

• Device Progra mmers

-PRO MATE

® II Universa l Devi ce Pr o gr a mm er

- PICSTART® Plus Development Programmer

• Low Cost Demonstration Boards

- PICDEMTM 1 Demonstration Board

- PICDEM.netTM De monstration Board

- PICDEM 2 Plus Demonstration Board

- PICDEM 3 Demonstration Board

- PICDEM 4 Demonstration Board

- PICDEM 17 Demonstration Board

- PICDEM 18R Demonstration Board

- PICDEM L IN Demo nstration Board

- PICDEM USB Demonstration Board

• Evaluation Kits

-K

EELOQ®

- P ICDEM MSC

-microID

-CAN

- PowerSmart®

-Analog

13.1 MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software

development previously unseen in the 8/16-bit micro-

controller market. The MPLAB IDE is a Windows®

based application that contains:

• An interface to deb ugging tools

- simulator

- programmer (sold separately)

- emulator (sold separately)

- in-circuit debugger (sold separately)

• A full-featured editor with color coded context

• A multiple project manager

• Customizable data windows with direct edit of

contents

• High level source code debugging

• Mouse over variable inspection

• Exten si ve on-l in e help

The MPLAB IDE allows you to:

• Edit your sour ce files (either assemb ly or C)

• One touch assemble (or compile) and download

to PICmicro emulator and simulator tools

(automatically updates all project information)

• Debug us ing :

- source files (as sembl y o r C)

- absolute listing file (mixed assembly and C)

- machine code

MPLAB IDE supports multiple debugging tools in a

single development paradigm, from the cost effective

simulators, through low cost in-circuit debuggers, to

full-featured emulators. This eliminates the learning

curve whe n upgrading to tools with increasin g flexibi lity

and power.

13.2 MPASM Assembler

The MPASM assembler is a full-featured, universal

macro assembler for all PICmicro MCUs.

The MPASM assembler generates relocatable object

files for the MPLINK object linker, Intel® standard HEX

files, M AP files to detail memory u sage and symbol re f-

erence, a bsolute LST files that contain source lines and

generated machine code and COFF files for

debugging.

The MPASM assembler features include:

• Integration into MPLAB IDE projects

• User de fined m acros to strea mline asse mbly cod e

• Condit ion al as sem bl y for mult i-p urpo se sourc e

files

• Directives that allow complete control over the

assembly p rocess

PIC16F870/871

DS30569B-page 112  2003 Microchip Technology Inc.

13.3 MPLAB C17 and MPLAB C18

C Compilers

The MPLAB C17 and MPLAB C18 Code Development

Systems are complete ANSI C compilers for

Microchip’s PIC17CXXX and PIC18CXXX family of

microcontrollers. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use not found with other compilers.

For easy source level debugging, the compilers provide

symbol info rmation tha t is optimized to the MPLAB IDE

debugger.

13.4 MPLINK Object Linker/

MPLIB Object Librari an

The MPLINK object linker combines relocatable

objects created by the MPASM assembler and the

MPLAB C17 and MPLAB C18 C compilers. It can link

relocatable objects from pre-compiled libraries, using

directives from a linker script.

The MPLIB object librarian manages the creation and

modific ation of li brary fil es of pre-co mpiled c ode. When

a routine from a library is called from a source file , only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement , deletion and extr action

13.5 MPLAB C30 C Compiler

The MPLAB C30 C compiler is a full-featured, ANSI

compliant, optimizing compiler that translates standard

ANSI C programs into dsPIC30F assembly language

source. The compiler also supports many command-

line options and language extensions to take full

adv antage of the dsPIC 30F dev ice ha rdwar e capab ili-

ties, and afford fine control of the compiler code

generator.

MPLAB C30 is distributed with a complete ANSI C

standard library. All library functions have been vali-

dated an d c on form to the ANSI C li brary standard . Th e

library includes functions for string manipulation,

dynamic memory allocation, data conversion, time-

keeping, and math functions (trigonometric, exponen-

tial and hyperbolic). The compiler provides symbolic

information for high level source debugging with the

MPLAB IDE.

13.6 MPLAB ASM30 Assembler , Linker ,

and Librarian

MPLAB ASM30 assembler produces relocatable

machine code from symbolic assembly language for

dsPIC30F devices. MPLAB C30 compiler uses the

assembler to produce it’s object file. The assembler

generates relocatable object files that can then be

archived or linked with other relocatabl e object files and

arch ives to c rea te an e xecu tabl e fil e. N otabl e fe atu res

of the assembler include:

• Support for the entire dsPIC30F instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich dire cti ve set

• Flexible macro language

• MPLAB IDE compatibility

13.7 MPLAB SIM Software Simulator

The MPLAB SIM sof tware simulat or allows code deve l-

opment in a PC hosted environment by simulating the

PICmicro series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or use r de fined key p ress, to any pin. The exec u-

tion can be performed in Single-Step, Execute Until

Break, or Trace mode.

The MPLAB SIM simulator fully supports symbolic

debugging using the MPLAB C17 and MPLAB C18

C Compilers, as well as the MPASM assembler. The

software simulator offers the flexibility to develop and

debug code outside of the laboratory environment,

making it an excellent, economical software

development tool .

13.8 MPLAB SIM30 Software Simulator

The MPLAB SIM30 software simulator allows code

develop ment in a PC hosted en vironment by simulating

the dsPIC30F series microcontrollers on an instruction

level. On any given instruction, the data areas can be

examined or modified and stimuli can be applied from

a file, or user defined key press, to any of the pins.

The MPLAB SIM30 simulator fully supports symbolic

debugging using the MPLAB C30 C Compiler and

MPLAB ASM30 assembler . The simulator runs in either

a Command Line mode for automated tasks, or from

MPLAB IDE. This high speed simulator is designed to

debug, analyze and optimize time intensive DSP

routines.

 2003 Microchip Technology Inc. DS30569B-page 113

PIC16F870/871

13.9 MPLAB ICE 2000

High Performance Universal

In-Circui t Emu lator

The MPLAB ICE 2000 universal in-circuit emulator is

intended to provide the product development engineer

with a complete microcontroller design tool set for

PICmicro microcontrollers. Software control of the

MPLAB ICE 2000 in-circuit emulator is advanced by

the MPLAB Integrated Development Environment,

which all ows ed iting, b uildin g, do wnlo ading and sourc e

debuggi ng from a singl e envi ronm en t.

The MPLAB ICE 2000 is a full-featured emulator sys-

tem with enhanced trace, trigger and data monitoring

featur es. Interchangea ble processo r modules al low the

system to be easi ly reconfi gured for emula tion of d iffer-

ent processors. The universal architecture of the

MPLAB ICE in-circuit emulator allows expansion to

support new PICmicro microcontrollers.

The MPLAB ICE 2000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Microsoft® Windows 32-bit operating system were

chosen to best make these features available in a

simple, unified application.

13.10 MPLAB ICE 4000

High Performance Universal

In-Circui t Emu lator

The MPLAB ICE 4000 universal in-circuit emulator is

intended to provide the product development engineer

with a co mplete micro controller de sign tool se t for high-

end PICmicro microcontrollers. Software control of the

MPLAB ICE in-circuit emulator is provided by the

MPLAB Integrated Development Environment, which

allows editing, building, downloading and source

debuggi ng from a singl e envi ronm en t.

The MPLAB ICD 4000 is a premium emulator system,

providing the features of MPLAB ICE 2000, but with

increased emulation memory and high speed perfor-

mance for dsPIC30F and PIC18XXXX devices. Its

advanc ed emulator fe atures inc lude complex t riggering

and timing, up to 2 Mb of emulation memory, and the

ability to view variables in real-time.

The MPLAB ICE 4000 in-circuit emulator system has

been designed as a real-time emulation system with

advanced features that are typically found on more

expensive development tools. The PC platform and

Micro soft W indow s 32- bit op erat ing sy stem were c ho-

sen to best make t hes e fe atur es av ail able i n a si mple ,

unified application.

13.11 MPLAB ICD 2 In-Circuit Debugger

Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a

powerful, low cost, run-time development tool,

connec ting to the h ost PC via an R S-232 or hig h speed

USB interface. This tool is based on the FLASH

PICmicro MCUs and can be used to develop for these

and other PICmicro microcontrollers. The MPLAB

ICD 2 utilizes the in-circuit debugging capability built

into the FLASH devices. This feature, along with

Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)

protocol, offers cost effective in-circuit FLASH debug-

ging from the graphical user interface of the MPLAB

Integrated Development Environment. This enables a

designer to develop and debug source code by setting

breakpoints, single-stepping and watching variables,

CPU status and peripheral registers. Running at full

speed enables testing hardware and applications in

real-tim e. MPLAB ICD 2 also serves as a de velopme nt

programmer for selected PICmicro devices.

13.12 PRO MATE II Universal Device

Programmer

The PRO MATE II is a universal, CE compliant device

programmer with programmable voltage verification at

VDDMIN and VDDMAX for maxi mum reli abili ty. It features

an LCD display for instructions and error messages

and a modular detachable socket assembly to support

various package types. In Stand-Alone mode, the

PRO MATE II dev ic e p rogra mmer ca n read, ve rify, and

program PICmicro devices without a PC connection. It

can also set code protection in this mode.

13.13 PICSTART Plus Development

Programmer

The PICSTART Plus development programmer is an

easy-to-use, low cost, prototype programmer. It con-

nects to the PC via a COM (RS-232) port. MPLAB

Inte grated Dev elopmen t En vironme nt so ftware makes

using the programmer simple and efficient. The

PICSTART Plus development programmer supports

most PICmicro devices up to 40 pins. Larger pin count

devices, such as the PIC16C92X and PIC17C76X,

may be supported with an adapter socket. The

PICSTART Plus development programmer is CE

compliant.

PIC16F870/871

DS30569B-page 114  2003 Microchip Technology Inc.

13.14 PICDEM 1 PICmicro

Demonstration Board

The PICDEM 1 demo nstrat ion boa rd demo nstrate s the

capabilities of the PIC16C5X (PIC16C54 to

PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,

PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All

necessary hardware and software is included to run

basic demo programs. The sample microcontrollers

provi d ed wi t h the P IC DE M 1 de mo ns t rat i on b oar d c an

be pro gramme d with a PRO MATE I I devi ce prog ram-

mer, or a PICSTART Plus development programmer.

The PICDE M 1 demonstrati on board can be conne cted

to the MPLAB ICE i n-circ uit emulato r for testi ng. A pro-

totype area extends the circuitry for additional applica-

tion components. Features include an RS-232

interface, a potentiometer for simulated analog input,

push button switches and eight LEDs.

13.15 PICDEM.net Internet/ E thernet

Demonstration Board

The PICDEM.net demonstration board is an Internet/

Ethernet demonstration board using the PIC18F452

microcontroller and TCP/IP firmware. The board

supports any 40-pin DIP device that conforms to the

standard pinout used by the PIC16F877 or

PIC18C452. This kit features a user friendly TCP/IP

stack, web server with HTML, a 24L256 Serial

EEPROM for Xmodem download to web pages into

Serial EEPROM, ICSP/MPLAB ICD 2 interface con-

nector, an Ethernet interface, RS-232 interface, and a

16 x 2 LCD display. Also included is the book and

CD-ROM “TCP/IP Lean, Web Servers for Embedded

Systems,” by Jeremy Bentham

13.16 PICDEM 2 Plus

Demonstration Board

The PICDEM 2 Plus demonstration board supports

many 18-, 28-, and 40-pin microcontrollers, including

PIC16F87X and PIC18FXX2 devices. All the neces-

sary ha rdware and s oftware is included to run the dem -

onstration programs. The sample microcontrollers

provi d ed wi t h the P IC DE M 2 de mo ns t rat i on b oar d c an

be pro gramme d with a PRO MATE I I devi ce prog ram-

mer, PICSTART Plus development programmer, or

MPLAB ICD 2 with a Universal Programmer Adapter.

The MPLAB I CD 2 and MPLAB I CE in-circuit emul ators

may also be used with the PICDEM 2 demonstration

board to test firmware. A prototype area extends the

circuitry for additional application components. Some

of the features include an RS-232 interface, a 2 x 16

LCD display , a piezo speaker , an on-board temperatu re

sensor, four LEDs, and sample PIC18F452 and

PIC16F8 77 FLASH microc on trol lers .

13.17 PICDEM 3 PIC16C92X

Demonstration Board

The PICDEM 3 demonstration board supports the

PIC16C923 and PIC16C924 in the PLCC package. All

the necessary hardware and software is included to run

the demonstration programs.

13.18 PICDEM 4 8/14/18-Pin

Demonstration Board

The PICDEM 4 can be used to demonstrate the capa-

bilities of the 8-, 14-, and 18-pin PIC16XXXX and

PIC18XXXX MCUs, including the PIC16F818/819,

PIC16F8 7/88, PIC16 F62 XA and th e PIC18 F132 0 fam -

ily of microcontrollers. PICDEM 4 is intended to show-

case the many features of these low pin count parts,

including LIN and Motor Control using ECCP. Special

provisions are made for low power operation with the

supercapacitor circuit, and jumpers allow on-board

hardware to be disabled to eliminate current draw in

this mode. Included on the demo board are provisions

for Crystal, RC or Canned Oscillator modes, a five volt

regulato r for use with a ni ne volt wall ad apter or battery,

DB-9 RS-232 interface, ICD connector for program-

ming via ICSP and development with MPLAB ICD 2,

2x16 liquid crystal display, PCB footprints for H-Bridge

motor driver, LIN transceiver and EEPROM. Also

included are: header for expansion, eight LEDs, four

potentiometers, three push buttons and a prototyping

area. Included with the kit is a PIC16F627A and a

PIC18F1320. Tutorial firmware is included along with

the User’s Guide.

13.19 PICDEM 17 Demonstration Board

The P ICDEM 17 de mo ns t rat i on bo a rd is an ev al u at i on

board that demonstrates the capabilities of several

Microchip microcontrollers, including PIC17C752,

PIC17C756A, PIC17C762 and PIC17C766. A pro-

grammed sample i s included. T he PRO MA TE II device

programmer, or the PICSTART Plus development pro-

grammer, can b e used to repro gram the d evice f or user

tailored application development. The PICDEM 17

demonstration board supports program download and

execution from external on-board FLASH memory. A

generous proto typ e area is av ailab le for user hardw are

expansion.

 2003 Microchip Technology Inc. DS30569B-page 115

PIC16F870/871

13.20 PICDEM 18R PIC18C601/801

Demonstration Board

The PICDEM 18R demonstration board serves to assist

development of the PIC18C601/801 family of Microchip

microcontrollers. It provides hardware implementation

of both 8-bit Multiplexed/De-multiplexed and 16-bit

Memory modes. The board includes 2 Mb external

FLASH memory and 128 Kb SRAM memory , as well as

serial EEPROM, allowing access to the wide range of

memory types supported by the PIC18C601/801.

13.21 PICDEM LIN PIC16C43X

Demonstration Board

The pow erfu l LI N hard w are a nd s of tw are kit includes a

series of boards and three PICmicro microcontrollers.

The small footprint PIC16C432 and PIC16C433 are

used as slaves in the LIN communication and feature

on-board LIN transceivers. A PIC16F874 FLASH

microcontroller serves as the master. All three micro-

controllers are programmed with firmware to provide

LIN b us communication.

13.22 PICkitTM 1 FLASH Starter Kit

A complete "development system in a box", the PICkit

FLASH Starter Kit includes a convenient multi-section

board for programming, evaluation, and development

of 8/14-pi n FLAS H PI C® microc ontro ll ers . Pow ere d vi a

USB, the board operates under a simple Windows GUI.

The PICkit 1 Starter Kit includes the user's guide (on

CD ROM), PICkit 1 tutorial software and code for vari-

ous applica tion s. Als o inc lu ded are MPLAB ® IDE (Inte-

grated Development Environment) software, software

and hardware "Tips 'n Tricks for 8-pin FLASH PIC®

Microcontrollers" Handbook and a USB Interface

Cable. Supports all current 8/14-pin FLASH PIC

microcontrollers, as well as many future planned

devices.

13.23 PICDEM USB PIC16C7X5

Demonstration Board

The PICDEM U SB Demo ns trati on Board sho w s o f f th e

capabilities of the PIC16C745 and PIC16C765 USB

microcontrollers. This board provides the basis for

future USB products.

13.24 Evaluation and

Programming Tools

In additio n to the PICDEM seri es of circuits, Microchip

has a line of evaluation kits and demonstration software

for the se products.

•K

EELOQ evaluation and prog ram mi ng too ls for

Microchip’s HCS Secure Data Products

• CAN developers kit for automotive network

applications

• Analog design boards and filter design software

• PowerS mart battery charging evaluation/

calibration kits

•IrDA

® development kit

• microID development and rfLabTM development

software

• SEEVAL® designer kit f or mem ory ev al uat ion an d

endurance calculations

• PICDEM MSC demo boards for Switching mode

power supply, high power IR driver, delta sigma

ADC, and flow rate sensor

Check the Microchip web page and the latest Product

Line Card for the complete list of demonstration and

evaluation kits.

PIC16F870/871

DS30569B-page 116  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 117

PIC16F870/871

14.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Ambient temperature under bias.................................................................................................................-55 to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) .........................................-0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V

Voltage on MC LR with respect to VSS (Note 2)............................................................................................0 to +13.25V

Voltage on RA4 with respect to Vss..................................................................................................................0 to +8.5V

Total power dissipation (Note 1) ...............................................................................................................................1.0W

Maximum curr ent out of VSS pin ...........................................................................................................................300 mA

Maximum curr ent into VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp cur rent, IOK (VO < 0 or VO > VDD).............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin....................................................................................................25 mA

Maximum curr ent sunk by PORTA, PORTB, and PORTE (combined) (Note 3)...................................................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (combined) (Note 3)..............................................200 mA

Maximum current sunk by PORTC and PORTD (combined) (Note 3) .................................................................200 mA

Maximum current sourced by PORTC and PORTD (combined) (Note 3) ............................................................200 mA

Note 1: Power diss ipation is calcul ate d as follows: Pd is = VDD x { IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)

2: Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up.

Thus, a s eries res istor o f 50-100 Ω shou ld be u sed whe n appl ying a “low” level to the MC LR pin, ra ther than

pulling this pin directly to VSS.

3: PORTD and PORTE are not implemented on the 28-pin devices.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16F870/871

DS30569B-page 118  2003 Microchip Technology Inc.

FIGURE 14-1: PIC16FXXX VOLTAGE-FREQUENCY GRAPH

FIGURE 14-2: PIC16LFXXX VOLT AGE-FREQUENCY GRAP H

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

20 MHz

5.0V

3.5V

3.0V

2.5V

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

5.0V

3.5V

3.0V

2.5V

Equation 1: FMAX = (6.0 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz; VDDAPPMIN = 2.0V - 3.0V

Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device i n the application.

4 MHz 10 MHz

Note 2: FMAX has a maximum frequency of 10 MHz.

20 MHz

Equation 1Equation 2

Equation 2: FMAX = (10.0 MHz/V) (VDDAPPMIN – 3.0V) + 10 MHz; VDDAPPMIN = 3.0V - 4.0V

 2003 Microchip Technology Inc. DS30569B-page 119

PIC16F870/871

14.1 DC Characteri stics: PIC16F870/871 (I ndustrial, Extended)

PIC16LF870/871 (Commercial , Industrial)

PIC16LF870/871

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature-40°C ≤ TA ≤ +85°C for Industrial

0°C ≤ TA ≤ +70°C for Commercial

PIC16F870/871

(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

VDD Supply Voltage

D001 PIC16LF870/871 2.0 — 5.5 V All configurations. See Figure 14-2 for

details.

D001

D001A PIC16F870/871 4.0

VBOR*

VBOR

—

5.5

All configurations.

BOR enabled, FMAX = 14 MHz (N ote 7),

-40°C to +85°C

BOR enabled, FMAX = 10 MHz (N ote 7),

-40°C to +125 °C

D002* VDR RAM Data Retention

Voltage(1) —1.5—V

D003 VPOR VDD Start Voltage to

ensure internal Power-on

Reset signal

— Vss — V See section on Power-on Reset for details

D004* SVDD VDD Rise Rate to ensure

internal Power-on Reset

signal

0.05 — — V/ms See section on Power-on Reset for details

D005 VBOR Brown-out Reset

Voltage 3.7 4.0 4.35 V BOREN bit in configuration word enabled

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disable d as s pecified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from

characterization and is for design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD meas urem en t.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

PIC16F870/871

DS30569B-page 120  2003 Microchip Technology Inc.

IDD Supply Current(2,5)

D010

D010A

PIC16LF870/871 —

—

0.6

2.0

µA

XT, RC osc configuration

FOSC = 4 MHz, VDD = 3.0V (Note 4)

LP osc configu ration

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

D010

D013

PIC16F870/871 —

—

1.6

XT, RC osc configuration

FOSC = 4 MHz, VDD = 5.5V (Note 4)

HS osc configuration

FOSC = 20 MHz , VDD = 5.5V, -40°C to +85°C

HS osc configuration

FOSC = 10 MH z, VDD = 5.5V, -40°C to +125°C

D015* ∆IBOR Brown-out Reset

Current(6) —85200µA BOR enabled, VDD = 5.0V

IPD Power-down Current(3,5)

D020

D021

D021A

PIC16LF870/871 —

—

7.5

0.8

0.9

4.5

µA

VDD = 3.0V, WDT enabled, -40°C to +85°C

VDD = 3.0V, WDT disabled, 0°C to +70°C

VDD = 3.0V, WDT disabled, -40°C to +85°C

D020

D20A

D021

D021A

D21B

PIC16F870/871 —

—

10.5

1.5

µA

VDD = 4.0V, WDT enabled, -40°C to +85°C

VDD = 4.0V, WDT enabled, -40°C to +125°C

VDD = 4.0V, WDT disabled, -0°C to +70°C

VDD = 4.0V, WDT disabled, -40°C to +85°C

VDD = 4.0V, WDT disabled, -40°C to +125°C

D023* ∆IBOR Brown-out Reset

Current(6) —85200µA BOR enabled, VDD = 5.0V

14.1 DC Characteri stics: PIC16F870/871 (I ndustrial, Extended)

PIC16LF870/871 (Commercial, Industrial) (Continued)

PIC16LF870/871

(Commercial, Industrial)

Standard Operating Conditions (unless otherwise stated)

Operating temperature-40°C ≤ TA ≤ +85°C for Industrial

0°C ≤ TA ≤ +70°C for Commercial

PIC16F870/871

(Industrial, Extended)

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

-40°C ≤ TA ≤ +125°C for Extended

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O

pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have

an impact on the current consumption.

The test conditions for all IDD measurements in active Operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD

MCLR = VDD; WDT enabled/disable d as s pecified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: For RC osc configuration, current through REXT is not included. The current through the resistor can be

estimated by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from

characterization and is for design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD meas urem en t.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

 2003 Microchip Technology Inc. DS30569B-page 121

PIC16F870/871

14.2 DC Characteristics: PIC16F870/871 (Industrial)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Operating voltage VDD range as described in DC spec Section 14.1

and Section 14.2.

Param

No. Sym Characteristic Min Typ† Max Units Conditions

VIL Input Low Voltage

I/O ports:

D030 with TTL buffer VSS — 0.15 VDD V For entire VDD range

D030A VSS —0.8V V4.5V ≤ VDD ≤ 5.5V

D031 with Schmitt Trigger buffer VSS —0.2 VDD V

D032 MCLR, OSC1 (in RC mode) VSS —0.2 VDD V

D033 OSC1 (in XT, HS and LP) VSS —0.3 VDD V(Note 1)

Ports RC3 and RC4:

D034 with Schmitt Trigger buffer VSS —0.3 VDD V For entire VDD range

D034A with SMBus -0.5 — 0.6 V For VDD = 4.5 to 5.5V

VIH Input High Voltage

I/O ports: —

D040 with TTL buffer 2.0 — VDD V4.5V ≤ VDD ≤ 5.5V

D04 0A 0 . 2 5 V DD +

0.8V —VDD V For entire VDD range

D041 with Schmitt Trigger buffer 0.8 VDD —VDD V For entire VDD range

D042 MCLR 0.8 VDD —VDD V

D042A OSC1 (XT, HS and LP) 0.7 VDD —VDD V(Note 1)

D043 OSC1 (in RC mode) 0.9 VDD —VDD V

Ports RC3 and RC4:

D044 with Schmitt Trigger buffer 0.7 VDD —VDD V For entire VDD range

D044A with SMBus 1.4 — 5.5 V for VDD = 4.5 to 5.5V

D070 IPURB PORTB Weak Pull-up

Current 50 250 400 µAVDD = 5V, VPIN = VSS

IIL Input Leakage Current

(No tes 2, 3)

D060 I/O ports — — ±1µAVss ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061 MCLR, RA4/T0CKI — — ±5µAVss ≤ VPIN ≤ VDD

D063 OSC1 — — ±5µAVss ≤ VPIN ≤ VDD, XT, HS and

LP osc configuration

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: In RC oscillat or confi guratio n, the OSC 1/CLKI pi n is a Sch mitt Trigger input. It is not recom mend ed that th e

PIC16F870/871 be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

PIC16F870/871

DS30569B-page 122  2003 Microchip Technology Inc.

VOL Output Low Voltage

D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

D083 OSC2/C LKO (R C o s c c onfig) — — 0.6 V IOL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

VOH Output High Voltage

D090 I/O ports (Note 3) VDD – 0.7 — — V IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

D092 OSC2/C LKO (R C o s c c onfig) V DD – 0.7 — — V IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

D150* VOD Open Drain High Voltage — — 8.5 V RA4 pin

Capacitive Loading Specs

on Output Pins

D100 COSC2 OSC2 pin — — 15 pF In XT, HS and LP modes when

external clock is used to drive

OSC1.

D101

D102

CIO

All I/O pins and OSC2

(in RC mode)

SCL, SDA in I2C mode

—

400

Data EEPROM Memory

D120 EDEndurance 100K — — E/W 25°C at 5V

D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/write

VMIN = min operating vol t ag e

D122 TDEW Erase/wr ite cycle time — 4 8 ms

Program FLASH Memory

D130 EPEndurance 1000 — — E/W 25°C at 5V

D131 VPR VDD for read VMIN —5.5 VVMIN = min operati ng vol t ag e

D132a VDD for erase/write VMIN — 5.5 V Using EECON to read/write,

VMIN = min operating vol t ag e

D133 TPEW Erase/Write cycle time — 4 8 ms

14.2 DC Characteristics: PIC16F870/871 (Industrial) (Continued)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +85°C for Industrial

Operating voltage VDD range as described in DC spec Section 14.1

and Section 14.2.

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: In RC oscillat or confi guratio n, the OSC 1/CLKI pi n is a Sch mitt Trigger input. It is not recom mend ed that th e

PIC16F870/871 be driven with external clock in RC mode.

2: The leakage current on the MCL R pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

 2003 Microchip Technology Inc. DS30569B-page 123

PIC16F870/871

14.3 DC Characteristics: PIC16F870/871 (Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Operating voltage VDD range as described in DC specification

(Section )

Param

No. Sym Characteristic Min Typ† Max Units Conditions

VIL Input Low Voltage

I/O ports:

D030 with TTL buffer VSS —0.15 VDD V For entire VDD range

D030A VSS —0.8V V4.5V ≤ VDD ≤ 5.5V

D031 with Schmitt Trigger buffer VSS —0.2 VDD V

D032 MCLR, OSC1 (in RC mode) VSS —0.2 VDD V

D033 OSC1 (in XT, HS and LP) VSS —0.3 VDD V(Note 1)

Ports RC3 and RC4:

D034 with Schmitt Trigger buffer VSS —0.3 VDD V For entire VDD range

D034A with SMBus -0.5 — 0.6 V For VDD = 4.5 to 5.5V

VIH Input High Volt age

I/O ports: —

D040 with TTL buffer 2.0 — VDD V4.5V ≤ VDD ≤ 5.5V

D040A 0.25 VDD

+ 0.8V —VDD V For entire VDD range

D041 with Schmitt Trigger buffer 0.8 VDD —VDD V For entire VDD range

D042 MCLR 0.8 VDD —VDD V

D042A OSC1 (XT, HS and LP) 0.7 VDD —VDD V(Note 1)

D043 OSC1 (in RC mode) 0.9 VDD —VDD V

Ports RC3 and RC4:

D044 with Schmitt Trigger buffer 0.7 VDD —VDD V For entire VDD range

D044A with SMBus 1.4 — 5.5 V For VDD = 4.5 to 5.5V

D070A IPURB PORTB Weak Pull-up Current 50 250 400 µAVDD = 5V, VPIN = VSS

IIL Input Leakag e Current(2,3)

D060 I/O ports — — ±1µAVss ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061 MCLR, RA4/T0CKI — — ±5µAVss ≤ VPIN ≤ VDD

D063 OSC1 — — ±5µAVss ≤ VPIN ≤ VDD, XT, HS

and LP osc configuration

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: In RC oscillato r configu ration, the OSC1 /CLKI pin is a Sch mitt Trigger input. It is not recomm ended tha t the

PIC16F87X be driven with external clock in RC mode.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

PIC16F870/871

DS30569B-page 124  2003 Microchip Technology Inc.

VOL Output Low Voltage

D080A I/O ports — — 0.6 V IOL = 7.0 mA, VDD = 4.5V

D083A OSC2/CLKO (RC osc config) — — 0.6 V IOL = 1.2 mA, VDD = 4.5V

VOH Output High Vo ltage

D090A I/O ports(3) VDD – 0.7 — — V IOH = -2.5 mA, VDD = 4.5V

D092A OSC2/CLKO (RC osc config) VDD – 0.7 — — V IOH = -1.0 mA, VDD = 4.5V

D150* VOD Open Drain High Voltage — — 8.5 V RA4 pin

Capacitive Loading Specs on

Output Pins

D100 COSC2 OSC2 pin — — 15 p F In XT, HS and LP modes when

external clock is used to drive

OSC1

D101

D102

CIO

All I/O pins and OSC2

(RC mode)

SCL, SDA (I2C mode)

—

400

Data EEPROM Memory

D120 EDEndurance 100K — — E/W 25°C at 5V

D121 VDRW VDD for read/write VMIN — 5.5 V Using EECON to read/ write,

VMIN = min. operating voltage

D122 TDEW Erase/write cycle time — 4 8 ms

Program FLASH Memory

D130 EPEndurance 1000 — — E/W 25°C at 5V

D131 VPR VDD for read VMIN —5.5 VVMIN = min operating voltage

D132A VDD for erase/write VMIN — 5 .5 V Using EECON to read/ wr ite,

VMIN = min. operating voltage

D133 TPEW Erase/Write cycle time — 4 8 ms

14.3 DC Characteristics: PIC16F870/871 (Extended) (Continued)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C ≤ TA ≤ +125°C

Operating voltage VDD range as described in DC specification

(Section )

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: In RC oscillato r configu ration, the OSC1 /CLKI pin is a Sch mitt Trigger input. It is not recomm ended tha t the

PIC16F87X be driven with external clock in RC mode.

2: The leakage current on the MCL R pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

 2003 Microchip Technology Inc. DS30569B-page 125

PIC16F870/871

14.4 Timing Parameter Symbology

The timing parameter symbols have been created

following one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

TF Frequency T Time

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKO rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppercase letters and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

I2C only

AA output access High High

BUF Bus free Low Low

TCC:ST (I2C specifications only)

HD Hold SU Setup

DAT DATA input hold STO STOP condition

STA START condition

PIC16F870/871

DS30569B-page 126  2003 Microchip Technology Inc.

FIGU RE 14- 3: LO AD C OND IT I ONS

FIGU RE 14- 4: EXT ER NA L C LOC K TIMI NG

VDD/2

Pin Pin

VSS VSS

RL= 464Ω

CL= 50 pF for all pins except OSC2, but including PORTD and PORTE outputs as ports

15 pF for OSC2 output

Note: PORTD and PORTE are not implemented on the PIC16F870.

Load condition 1 Load condition 2

OSC1

CLKO

Q4 Q1 Q2 Q3 Q4 Q1

23344

 2003 Microchip Technology Inc. DS30569B-page 127

PIC16F870/871

TABLE 14-1: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

FOSC External CLKI Frequency

(Note 1) DC — 4 MHz XT and RC Osc mode

DC — 4 MHz HS Osc mode (-04)

DC — 20 MHz HS Osc mode (-20)

DC — 200 kHz LP Osc mode

Oscillator Frequency

(Note 1) DC — 4 MHz RC Osc mode

0.1 — 4 MHz XT Osc mode

5—

—20

200 MHz

kHz HS Osc mode

LP Osc mode

1TOSC External CLKI Period

(Note 1) 250 — — ns XT and RC Osc mode

250 — — ns HS Osc mode (-04)

50 — — ns HS Osc mode ( -20)

5——µs LP Osc mode

Oscillator Period

(Note 1) 250 — — ns RC Osc mode

250 — 10,000 ns XT Osc mo de

250 — 250 ns HS Osc mode (-04)

50 — 250 ns HS Osc mode (-20)

5——µs LP Osc mode

2TCY Instruction Cy cle Time

(Note 1) 200 TCY DC ns TCY = 4/FOSC

3TosL,

TosH External Clock in (OSC1) High

or Low Time 100 — — ns XT oscillator

2.5 — — µs LP oscillator

15 — — ns HS oscillator

4TosR,

TosF External Clock in (OSC1) Rise

or Fall Time — — 25 ns XT oscillator

— — 50 ns LP oscillator

— — 15 ns HS oscil lator

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

Note 1: In struction cycle perio d (TCY) equals four times the input oscillator time base period. All specified values

are based on charac teri za tion data for that p art ic ula r osci lla tor type under st and ard ope rati ng con di t ion s

with the device executing code. Exceeding these specified limits may result in an unstable oscillator oper-

ation and/or higher than expected current consumption. All devices are tested to operate at "min." values

with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max."

cycle time limit is "DC" (no clock) for all devices.

PIC16F870/871

DS30569B-page 128  2003 Microchip Technology Inc.

FIGURE 14-5: CLKO AND I/O TIMING

TABLE 14-2: CLKO AND I/O TIMING REQUIREMENTS

Note: Refer to Figure 14-3 for load conditions.

OSC1

CLKO

I/O Pin

(Input)

I/O Pin

(Output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

12 16

Old Value New Value

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to C L KO↓ — 75 200 ns (Note 1)

11* TosH2ckH OSC1↑ to CL KO↑ — 75 200 ns (Note 1)

12* TckR CLKO rise time — 35 100 ns (Note 1)

13* TckF CLKO fall time — 3 5 100 ns (Note 1)

14* TckL2ioV CLKO↓ to Port out valid — — 0.5 TCY + 20 ns (Note 1)

15* TioV2ckH Port in valid before CLKO↑ T

OSC + 200 — — ns (Note 1)

16* TckH2ioI Port in hold after CLKO↑ 0——ns(Note 1)

17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 100 255 ns

18* TosH2ioI OSC1↑ (Q2 cycle) to Port input

invalid (I/O in hold time) Standard (F) 100 — — ns

Extended (LF) 200 — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns

20* TIOR Port output rise time S tandard (F) — 10 40 ns

Extended (LF) — — 145 ns

21* TIOF Port output fall time Standard (F) — 10 40 ns

Extended (LF) — — 145 ns

22††* TINP INT pin high or low time TCY ——ns

23††* TRBP RB7:RB4 change INT high or low time TCY ——ns

* Thes e parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC.

 2003 Microchip Technology Inc. DS30569B-page 129

PIC16F870/871

FIGURE 14-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP T IMER AND POWER -UP

TI MER TIMING

FIGURE 14-7: BROWN-OUT RESET TIMING

TABLE 14-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 — — µsVDD = 5V, -40°C to +85°C

31* TWDT Watchdog Timer Time-out Period

(No Prescaler) 71833msVDD = 5V, -40°C to +85°C

32 TOST Oscillation Start-up Timer Period — 1024 TOSC ——TOSC = OSC1 period

33* TPWRT Power up Timer Period 28 72 132 ms VDD = 5V, -40°C to +85°C

34 TIOZ I/O Hi-impedance from MCLR Low or

Watchdog Timer Reset ——2.1µs

35 TBOR Brown-out Reset pulse width 100 — — µsVDD ≤ VBOR (D005)

* These parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested .

VDD

MCLR

Internal

POR

PWRT

Time-out

Osc

Time-out

Internal

RESET

Watchdog

Timer

Reset

I/O Pins

Note: Refer to Figure 14-3 for load conditions.

VDD VBOR

PIC16F870/871

DS30569B-page 130  2003 Microchip Technology Inc.

FIGU RE 14-8: T I MER 0 AN D TIME R 1 E XTERNAL C L OCK TIMI NG S

TABLE 14-4: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T0CKI High Pulse Wid th No Prescaler 0.5 TCY + 20 — — ns Must als o meet

parameter 42

With Prescaler 10 — — ns

41* Tt0L T0CKI Low Pulse Wid th No Prescaler 0.5 TCY + 20 — — ns Must also meet

parameter 42

With Prescaler 10 — — ns

42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns

With Prescaler Greater of:

20 or TCY + 40

— — ns N = prescale value

(2, 4, ..., 256)

45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5 TCY + 20 — — ns Must also meet

parameter 47

Synchronous,

Prescaler = 2,4,8 Standard(F)15——ns

Extended(LF)25——ns

Asynchronous Standard(F)30——ns

Extended(LF)50——ns

46* Tt1L T1CKI Low Time Synchronous, Presc aler = 1 0.5 TCY + 20 — — ns Must also meet

parameter 47

Synchronous,

Prescaler = 2,4,8 Standard(F)15——ns

Extended(LF)25——ns

Asynchronous Standard(F)30——ns

Extended(LF)50——ns

47* Tt1P T1CKI inp ut period Synchro nous S t andard(F) Greater of:

30 or TCY + 40

— — ns N = prescale value

(1, 2, 4, 8)

Extended(LF) Greater of:

50 or TCY + 40

N = prescale value

(1, 2, 4, 8)

Asynchronous Standard(F)60——ns

Extended(LF) 100 — — ns

Ft1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz

48 TCKEZt mr1 Delay from external cloc k edge to timer inc rement 2 TOSC —7 TOSC —

* Thes e parameters are characterized but not tested.

† Data in "T yp" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note: Refer to Figure 14-3 for load conditions.

RA4/T0CKI

RC0/T1OSO/T1CKI

TMR0 o r

TMR1

 2003 Microchip Technology Inc. DS30569B-page 131

PIC16F870/871

FIGU RE 14- 9: CAPTURE/ CO MPARE/ PWM TIMINGS ( C CP1)

TABLE 14-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)

Note: Refer to Figure 14-3 for load conditions.

RC2/CCP1

(Capture Mode)

50 51

53 54

RC2/CCP1

(Compare or PWM Mode)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

50* TccL * CCP1

input low

time

No Prescaler 0.5 TCY + 20 — — ns

With Prescal er Standard(F)10——ns

Extended(LF)20——ns

51* TccH CCP1 input high time No Prescaler 0.5 TCY + 20 — — ns

With Prescal er Standard(F)10——ns

Extended(LF)20——ns

52* TccP CCP1 input period 3 TCY + 40

N— — ns N = prescale value

(1,4 or 16)

53* TccR CCP1 output rise time Standard(F) — 10 25 ns

Extended(LF) — 25 50 ns

54* TccF CCP1 output fall time Standard(F) — 10 25 ns

Extended(LF) — 25 45 ns

* Thes e parameters are characterized but not tested.

† Data in "T yp" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

PIC16F870/871

DS30569B-page 132  2003 Microchip Technology Inc.

FIGURE 14-10: PARALLEL SLAVE PORT TIMIN G (PIC16F871 ONLY)

TABLE 14-6: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F871 ONLY)

Note: Refer to Figure 14-3 for load conditions.

RE2/CS

RE0/RD

RE1/WR

RD7:RD0

Param

No. Sym Characteristic Min Typ† Max Units Conditions

62 TdtV2w rH Data in va l i d befor e W R ↑ or CS↑ (set up time) 20

25 —

——

—ns

ns Extended range only

63* TwrH2dtI WR↑ or C S↑ t o data–in invalid (hold ti me) St andard(F)20——ns

Extended(LF)35 — — ns

64 TrdL2dtV RD↓ and CS↓ to data–out valid —

——

—80

90 ns

ns Extended range only

65 TrdH2dtI RD↑ or CS↓ to data–out invalid 10 — 30 ns

* These parameters are charact erized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

 2003 Microchip Technology Inc. DS30569B-page 133

PIC16F870/871

FIGURE 14-11: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) T IMI NG

TABLE 14-7: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGU RE 14-12: USART SYN CH R ON OUS RE CEI V E ( M AST ER /SL A VE ) TIMING

TABLE 14-8: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Note: Refer to Figure 14-3 for load conditions.

121 121

122

RC6/TX/CK

RC7/RX/DT

120

Param

No. Sym Characteristic Min Typ† Max Units Conditions

120 TckH2dtV SYNC XMIT (MASTER & SLAVE)

Clock high to data out valid Standard(F)— — 80 ns

Extended(LF) — — 100 ns

121 Tckrf Clock out rise time and fall time

(Master mode) Standard(F)——45ns

Extended(LF)——50ns

122 Tdtrf Data out rise time and fall time Standard(F)——45ns

Extended(LF)——50ns

† Data in “Typ” column is at 5V, 25°C unless otherwise stated. T hese parameters are for design guidance only and are not

tested.

Note: Refer to Figure 14-3 for load conditions.

125

126

RC6/TX/CK

RC7/RX/DT

Param

No. Sym Characteristic Min Typ† Max Units Conditions

125 TdtV2ckL SYNC RCV (MA ST ER & SLAV E)

Data setup before CK ↓ (DT setup time) 15 — — ns

126 TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns

† Data in “T yp” column is at 5V, 25°C unless otherwise stated. These parameters are f or design guidance only and are not

tested.

PIC16F870/871

DS30569B-page 134  2003 Microchip Technology Inc.

TABLE 14-9: PIC16F870/871 (INDUSTRIAL)

PIC16LF870/871 (INDUSTRIAL)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRResolution — — 10-bits bit VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A03 EIL Integral linearity error — — < ± 1 LS b VREF = VDD = 5.12V,

VSS ≤ VAIN ≤ VREF

A04 EDL Differential linearity error — — < ± 1 LSb VREF = V DD = 5.12V,

VSS ≤ VAIN ≤ VREF

A06 EOFF Offset erro r — — < ± 1 LS b VREF = V DD = 5.12V,

VSS ≤ VAIN ≤ VREF

A07 EGN Gain e rror — — < ± 1 LSb VREF = V DD = 5.12V,

VSS ≤ VAIN ≤ VREF

A10 — Monotonicity(3) — guaranteed — — VSS ≤ VAIN ≤ VREF

A20 VREF Reference voltage (VREF+ – VREF-) 2.0V — VDD + 0.3 V

A21 VREF+ Reference voltage High VDD – 2. 5V VDD + 0.3V V Must meet spec. A20

A22 VREF- Reference voltage Low VSS – 0.3V V REF+ – 2.0V V Must meet spec. A20

A25 VAIN Analog input voltage VSS – 0.3 — VREF + 0.3 V

A30 ZAIN Recommended impedance of

analog voltage source ——10.0kΩ

A40 IAD A/D conversion

current (VDD)Standard(F) — 220 — µA Average current consump tion

when A/D is on (Not e 1).

Extended(LF)— 90 — µA

A50 IREF VREF input current (Note 2) 10

—

1000

µA

During VAIN acquisit ion.

Based on dif ferential of VHOLD

to VAIN to charge CHOLD, see

Section 10.1.

During A/D Con version cycl e

* Thes e parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes

any such leakage from the A/D module.

2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.

3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.

 2003 Microchip Technology Inc. DS30569B-page 135

PIC16F870/871

FIGURE 14-13: A/D CONVERSION TIMING

TABLE 14-10: A/D CONVERSION REQUIREMENTS

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPE D

DONE

NEW_DATA

(TOSC/2)(1)

987 210

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 TCY

. . . . . .

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period Standard(F)1.6 — — µsTOSC based, VREF ≥ 3.0V

Extended(LF)3.0——µsT

OSC based, VREF ≥ 2.0V

Standard(F) 2.0 4.0 6.0 µs A/D RC Mode

Extended(LF) 3.0 6.0 9.0 µs A/D RC Mode

131 TCNV Conversion time (not including S/H time)

(Note 1) —12TAD

132 TACQ Acquisition time (Note 2)

10*

—

µs

µs The minimum tim e is the ampli-

fier settling time. This may be

used if the "new" input voltage

has not changed by more than

1 LSb (i.e., 20.0 mV @ 5.12V)

from the last sampled voltage

(as stated on CHOLD).

134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is

selected as RC, a time of TCY is

added before the A/D clock

starts. This allows the SLEEP

instruction to be executed.

* Thes e parameters are characterized but not tested.

† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

§ T his spec ification ensured by design.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 10.1 for min conditions.

PIC16F870/871

DS30569B-page 136  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 137

PIC16F870/871

15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES

“T yp ical” represents the mean of the distribution at 25 °C. “Maximum” or “minimum” represen ts (mean + 3σ) or (mean - 3σ)

respectively, where σ is a standard deviation, ov er the whole temperature range.

FIGU RE 15- 1: TYPICA L I DD vs. F OSC OVER VDD (HS MODE)

FIGU RE 15- 2: MAXIMUM I DD v s . F OSC OVER VDD (HS MODE)

Note: The gra phs an d tables prov id ed fo ll ow in g thi s no te are a statistical summ ary bas ed on a li mi ted numbe r of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.

4 6 8 101214161820

FOSC (M H z)

IDD (mA)

2.5V

2.0V

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

Typical: statistical mean @ 25°C

Maximu m: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

4 6 8 101214161820

FOSC (MH z )

IDD (mA)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°C

Maximu m: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

PIC16F870/871

DS30569B-page 138  2003 Microchip Technology Inc.

FIGU RE 15- 3: TYPICA L I DD vs. F OSC OVER VDD (XT MODE)

FIGU RE 15- 4: MAXIMUM I DD v s . F OSC OVER VDD (LP MODE)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

0.00.51.01.52.02.53.03.54.0

FOSC (MHz)

IDD (mA)

5.5V

5.0V

4.5V

4.0V

3.5V

2.5V

2.0V

3.0V

Typical: statistical mean @ 25°C

Maxi mum: me an + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

FOSC (MHz)

IDD (mA)

5.5V

5.0V

4.5V

4.0V

3.5V

2.5V

2.0V

3.0V

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

 2003 Microchip Technology Inc. DS30569B-page 139

PIC16F870/871

FIGU RE 15- 5: TYPICA L I DD vs. F OSC OVER VDD (LP MODE)

FIGU RE 15- 6: MAXIMUM I DD v s . F OSC OVER VDD (XT MODE)

20 30 40 50 60 70 80 90 100

FOSC (kH z)

IDD

(uA)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

100

110

120

20 30 40 50 60 70 80 90 100

FOSC (kHz )

IDD (u A)

5.5V

5.0V

4.5V

4.0V

3.5V

3.0V

2.5V

2.0V

Typical: statistical mean @ 25°C

Maximu m: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

PIC16F870/871

DS30569B-page 140  2003 Microchip Technology Inc.

FIGURE 15-7: AVERAGE FOSC vs. VDD FOR VARIO US VALUES OF R (RC MOD E, C = 20 pF, 25°C)

FIGURE 15-8: AVERAGE FOSC vs. VDD FOR V ARIOUS V ALUES OF R (RC MODE, C = 100 pF, 25°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.02.53.03.54.04.55.05.5

VDD (V)

Freq (MHz)

3.3kΩ

5.1kΩ

10kΩ

100kΩ

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Freq (MHz)

3.3 k

Ω

5.1 kΩ

10 kΩ

100 kΩ

 2003 Microchip Technology Inc. DS30569B-page 141

PIC16F870/871

FIGURE 15-9: AVERAGE FOSC vs. VDD FOR V ARIOUS V ALUES OF R (RC MODE, C = 300 pF, 25°C)

FIGURE 15- 10: IPD vs. V DD (SLEEP M ODE, A LL PER IPHERALS D ISABLED)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

Freq (MHz)

3.3 kΩ

5.1 kΩ

10 kΩ

100 k Ω

0.01

0.10

1.00

10.00

100.00

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

IPD (µA)

Max (125C)

Max (85C)

Typ (25C)

Typical: statistical mean @ 25°C

Maxi mum: me an + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

PIC16F870/871

DS30569B-page 142  2003 Microchip Technology Inc.

FIGURE 15- 11: ∆IBOR vs. VDD OVER TEMPERATURE

FIGURE 15 - 12: TYPICAL AND MAXI MUM ∆ITMR1 vs. V DD OVER TEMPERATURE

(-10°C TO 70°C, T IMER1 WITH OSCILLATOR , XTAL=32 kHZ, C1 AND C2=50 pF)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

2.53.03.54.04.55.05.5

VDD (V)

∆I (mA)

Device in SL EEP

Device in RESET

Max RESET

Typ RESE T (25°C)

Max SLEEP

Typ SLEEP (25°C)

Indeterminate

State

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

Note: Device current in RESET

depends on Oscillator mode,

frequency and circ uit.

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

∆ITMR1 (uA)

Ty p (25C)

Max

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

 2003 Microchip Technology Inc. DS30569B-page 143

PIC16F870/871

FIGURE 15 - 13: TYPICAL AND MAXI MUM ∆IWDT vs . VDD OVER TEMPERATURE

FIGURE 15 - 14: TYPICAL, MINI MUM A ND M AXI MU M WDT PER IOD v s. V DD (-40°C T O 125°C)

2.02.53.03.54.04.55.05.5

VDD (V)

∆IWDT (uA)

Typ (2 5 C)

Max (85C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V )

WDT Period (ms)

M in (-40C)

Typ ( 2 5 C )

M ax (125 C)

Typical: statistical mean @ 25°C

Maxi mum: me an + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

PIC16F870/871

DS30569B-page 144  2003 Microchip Technology Inc.

FIGURE 15 - 15: AVER AG E WDT P ERI O D vs. V DD OVER TEMPERATURE (-40 °C TO 125°C)

FIGURE 15 - 16: TYPICAL, MI NI MUM AND M AXI MUM VOH vs. IOH (VDD = 5V, -40°C TO 125°C)

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V )

WDT Period (ms)

85C

125C

25C

-40C

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0 5 10 15 20 25

IOH (-m A)

VOH (V)

Max (-40C)

Typ (25C)

Min (125C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

 2003 Microchip Technology Inc. DS30569B-page 145

PIC16F870/871

FIGURE 15 - 17: TYPICAL, MI NI MUM AND M AXI MUM VOH vs. IOH (VDD = 3V, -40°C T O 125°C)

FIGURE 15 - 18: TYPICAL, MI NI MUM AND M AXI MUM VOL vs. IOL (VDD = 5V, -40°C TO 125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 5 10 15 20 25

IOH (-m A)

VOH (V)

M ax (-40C )

Typ ( 25 C)

Min (125C)

Typical: statistical mean @ 25°C

Maxi mum: me an + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 5 10 15 20 25

IOL (-m A )

VOL (V)

M ax (125C )

Typ ( 2 5 C)

Min (-40C)

Typical: statistical mean @ 25°C

Maximum: mean + 3σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

PIC16F870/871

DS30569B-page 146  2003 Microchip Technology Inc.

FIGURE 15 - 19: TYPICAL, MI NI MUM AND M AXI MUM VOL vs. IOL (VDD = 3V, -40°C TO 125°C)

FIGURE 15-20: MINIMUM AND MA XIMUM V IN vs. VDD, (TTL INPUT, -40°C T O 125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0 5 10 15 20 25

IOL (-mA)

VOL (V)

M ax (125C)

Typ (25C)

M in (-40C)

Typical: statistical mean @ 25°C

Maximum: mean + 3 σ (-40°C to 125°C)

Mini mum: me an – 3σ (-40°C to 125°C)

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V )

VIN (V)

M ax (-40 C)

Min (125C)

Typical: statistical mean @ 25°C

Maxi mum: me an + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

 2003 Microchip Technology Inc. DS30569B-page 147

PIC16F870/871

FIGURE 15-21: MINIMUM AND MA XIMUM V IN vs . VDD (ST INPUT, -40°C TO 125°C)

FIGURE 15-22: MINIMUM AND MA XIMUM V IN vs . VDD (I2C INPUT, -40°C TO 125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

2.02.53.03.54.04.55.05.5

VDD (V)

VIN (V)

M ax High (125C)

Max Low (125C)

M in Hi gh (-40C)

M in Low (-40C)

Typical: statistical mean @ 25°C

Maximu m: mean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

2.02.53.03.54.04.55.05.5

VDD (V )

VIN (V)

M ax Hi gh (125C)

Max Low (125C)

Min High (-40C)

M in Lo w (25C)

Typical: statistical mean @ 25°C

Maxi mum: m ean + 3σ (-40°C to 125°C)

Minimum: mean – 3σ (-40°C to 125°C)

PIC16F870/871

DS30569B-page 148  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 149

PIC16F870/871

16.0 PACKAGING INFORMATION

16.1 Package Marking Information

XXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead PDIP (Skinny DIP) Example

XXXXXXXXXXXXXXXXX

0317017

PIC16F870-I/SP

28-Lead SO IC

YYWWNNN

Example

XXXXXXXXXXXXXXXXX

XXXXXXXXXXXXXXXXX 0310017

PIC16F870-I/SO

28-Lead SSOP

YYWWNNN

XXXXXXXXXXXX

Example

0320017

PIC16F870-I/SS

Legend: XX...X Customer specific information*

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week c ode ( week o f January 1 is week ‘01’)

NNN Alphanumeric traceability code

Note: In the event the fu ll Micr ochip p art num ber cann ot be marked on one lin e, it wil l

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*Standard PICmicro device marking consists of Microchip part number, year code, week code, and

traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check

with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP

price.

PIC16F870/871

DS30569B-page 150  2003 Microchip Technology Inc.

Package Marking Information (Cont’d)

XXXXXXXXXXXXXXXXXX

YYWWNNN

40-Lead PDIP Example

XXXXXXXXXXXXXXXXXX

PIC16F871-I/P

0312017

44-Lead TQFP Example

XXXXXXXXXX

YYWWNNN

PIC16F871

-I/PT

0320017

44-Lead PLCC Example

XXXXXXXXXX

YYWWNNN

PIC16F871

-I/L

0320017

 2003 Microchip Technology Inc. DS30569B-page 151

PIC16F870/871

28-Lead Skinny Plasti c Dual In-line (SP) – 300 mil (PDIP)

1510515105

Mold Draft Angle Bottom 1510515105

Mold Draft Angle Top 10.928.898.13.430.350.320

Overall Row Spacing § 0.560.480.41.022.019.016BLower Lead Width 1.651.331.02.065.053.040B1Upper Lead Width 0.380.290.20.015.012.008

Lead Thickness 3.433.303.18.135.130.125LTip to Seating Plane 35.1834.6734.161.3851.3651.345DOverall Length 7.497.246.99.295.285.275E1Molded Package Width 8.267.877.62.325.310.300EShoulder to Shoulder Width 0.38.015A1Base to Seating Plane 3.433.303.18.135.130.125A2Molded Package Thickness 4.063.813.56.160.150.140ATop to Seating Plane 2.54.100

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERSINCHES*Units

Notes:

JEDEC Equivalent: MO-095

Drawing No. C04-070

* Controlling Parameter

Dimension D and E1 do not include mo ld flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0. 254 mm ) per si de.

§ Significant Characteristic

PIC16F870/871

DS30569B-page 152  2003 Microchip Technology Inc.

28-Lead Plasti c Small Outline (SO) – Wide, 300 mil (SOIC)

Foot Angle Top φ048048

1512015120

Mold Draft Angle Bottom 1512015120

Mold Draft Angle Top 0.510.420.36.020.017.014BLead Width 0.330.280.23.013.011.009

Lead Thickness

1.270.840.41.050.033.016LFoot Length 0.740.500.25.029.020.010hChamfer Distance 18.0817.8717.65.712.704.695DOverall Length 7.597.497.32.299.295.288E1Molded Package Width 10.6710.3410.01.420.407.394EOverall Width 0.300.200.10.012.008.004A1Standoff § 2.392.312.24.094.091.088A2Molded Package Thickness 2.642.502.36.104.099.093AOverall Height 1.27.050

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimensi on Lim its MILLIMETERSINCHES*Units

45°

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-013

Drawing No. C04-052

§ Significant Characteristic

 2003 Microchip Technology Inc. DS30569B-page 153

PIC16F870/871

28-Lead Plasti c Shrink Small Outl ine (SS) – 209 mil, 5.30 mm (SSOP)

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-150

Drawing No. C04-073

10501050Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.380.320.25.015.013.010BLead Width 203.20101.600.00840

Foot Angle 0.250.180.10.010.007.004

Lead Thickness 0.940.750.56.037.030.022LFoot Length 10.3410.2010.06.407.402.396DOvera ll Length 5.385.255.11.212.207.201E1Molded Package Width 8.107.857.59.319.309.299EOverall Width 0.250.150.05.010.006.002A1Standoff § 1.831.731.63.072.068.064A2Molded Package Thickness 1.981.851.73.078.073.068AOverall Height 0.65.026

Pitch 2828

Number of Pins MAXNOMMINMAXNOMMINDimen sion Li mits MILLIMETERS*INCHESUnits

§ Significant Characteristic

PIC16F870/871

DS30569B-page 154  2003 Microchip Technology Inc.

40-Lead Plastic Dual In-line (P) – 600 mil (PDIP)

1510515105

Mold Draft Angle Bottom 1510515105

Mold Draft Angle Top 17.2716.5115.75.680.650.620eBOverall Row Spacing § 0.560.460.36.022.018.014BLo w er Lea d Width 1.781.270.76.070.050.030B1Upp er Lea d Width 0.380.290.20.015.012.008

Lead Thic kness 3.433.303.05.135.130.120LTip to Seating Plane 52.4552.2651.942.0652.0582.045DOverall Lengt h 14.2213.8413.46.560.545.530E1Molded Package Width 15.8815.2415.11.625.600.595EShoulder to Shoulder Width 0.38.015

Base to Seating Plane 4.063.813.56.160.150.140A2Molded Package Thickness 4.834.454.06.190.175.160ATop to Seating Plane 2.54.100

Pitch 4040

Number of Pins MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-011

Drawing No. C04-016

§ Significant Characteristic

 2003 Microchip Technology Inc. DS30569B-page 155

PIC16F870/871

44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

* Controlling Parameter

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-076

1.140.890.64.045.035.025CHPin 1 Corner Chamfer

1.00.039

(F)

Footprint (Reference)

(F)

A1 A2

#leads=n1

D1 D

βL

Units INCHES MILLIMETERS*

Dim ension Limi ts MIN NOM MAX MIN NOM MAX

Numb er of Pin s n44 44

Pitch p.031 0.80

Overall Height A .039 .043 .047 1.00 1.10 1.20

Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05

Standoff § A1 .002 .004 .006 0.05 0.10 0.15

Foot Length L .018 .024 .030 0.45 0.60 0.75

Foot A ngle φ03.5 7 03.5 7

Overall Width E .463 .472 .482 11.75 12.00 12.25

Overall Length D .463 .472 .482 11.75 12.00 12.25

Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10

Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10

Pins per Side n1 11 11

Lead Thickness c.004 .006 .008 0.09 0.15 0.20

Lead Width B .012 .015 .017 0.30 0.38 0.44

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

CH x 45°

§ Significant Characteristic

PIC16F870/871

DS30569B-page 156  2003 Microchip Technology Inc.

44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC)

CH2 x 45°CH1 x 45°

10501050

Mold Draft Angle Bottom 10501050

Mold Draft Angle Top 0.530.510.33.021.020.013B0.810.740.66.032.029.026B1Upper Lead Width 0.330.270.20.013.011.008

Lead Thickness

1111n1Pins per Side

16.0015.7514.99.630.620.590

Footprint Length 16.0015.7514.99.630.620.590E2Footprint Width 16.6616.5916.51.656.653.650D1Molded Package Length 16.6616.5916.51.656.653.650E1Molded Package Width 17.6517.5317.40.695.690.685DOverall Length 17.6517.5317.40.695.690.685EOverall Width 0.250.130.00.010.005.000CH2Corner Chamfer (others) 1.271.141.02.050.045.040CH1Corner Chamfer 1 0.860.740.61.034.029.024

Side 1 Chamfer Height 0.51.020A1Standoff § A2

Molded Package Thickness 4.574.394.19.180.173.165AOverall Height

1.27.050

Pitch 4444

Number of Pins MAXNOMMINMAXNOMMINDime nsion Limits MILLIMETERSINCHES*Units

#leads=n1

35°

.145 .153 .160 3.68 3.87 4.06

.028 .035 0.71 0.89

Lower Lead Width

* Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-047

Drawing No. C04-048

§ Significant Characteristic

 2003 Microchip Technology Inc. DS30569B-page 157

PIC16F870/871

APPENDIX A: REVISION HISTORY

Revision A (December 1999)

Original data sheet for the PIC16F870/871 family.

Revision B (April 2003)

This revision includes the DC and AC Characteristics

Graphs and Tables. The Electrical Specifications in

Section 14.0 have been updated and there have been

minor corrections to the data sheet text.

APPENDIX B: DEVICE

DIFFERENCES

The differences between the devices listed in this data

sheet are shown in Table B-1.

TABLE B-1: DEVICE DIFFERENCES

Feature PIC16F870 PIC16F871

On-chip Program Memory (Kbytes) 2K 2K

Data Memory (bytes) 128 128

Boot Block (bytes) 2048 512

Timer1 Low Power Option Yes No

I/O Ports Ports A, B, C Ports A, B, C, D, E

A/D Channel s 5 8

External Me mo ry Interface No No

Package Types 28-pin DIP, SOIC, SSOP 40-pin PDIP, 44-pin PLCC, TQFP

PIC16F870/871

DS30569B-page 158  2003 Microchip Technology Inc.

APPENDIX C: CONVERSION

CONSIDERATIONS

This appendix discusses the considerations for con-

verting from previous versions of a device to the ones

listed in this data sheet. Typically, these changes are

due to the differences in the process technology used.

An example of this type of conversion is from a

PIC17C756 to a PIC18F8720.

Not Applicable

APPENDIX D: MIGRATION FROM

MID-RANGE TO

ENHANCED DEVICES

A detailed discussion of the differences between the

mid-range MCU devices (i.e., PIC16CXXX) and the

enhanced devices (i.e., PIC18FXXX) is provided in

AN716, “Migrating Designs from PIC16C74A/74B to

PIC18C442.” The changes discussed, while device

specific, are generally applicable to all mid-range to

enhanced device migrations.

This Ap plication Note is availab le as L iterature Nu mber

DS00716.

 2003 Microchip Technology Inc. DS30569B-page 159

PIC16F870/871

APPENDIX E: MIGRATION FROM

HIGH-END TO

ENHANCED DEVICES

A det a il ed dis cuss io n o f th e m ig ration p ath way an d d if-

ferences between the high-end MCU devices (i.e.,

PIC17CXXX) and the enhanced devices (i.e.,

PIC18FXXXX) is provided in AN726, “PIC17CXXX to

PIC18CXXX Migration.” This Application Note is

available as Literature Number DS00726.

PIC16F870/871

DS30569B-page 160  2003 Microchip Technology Inc.

NOTES:

 2003 Microchip Technology Inc. DS30569B-page 161
PIC16F870/871
INDEX
A
A/D......................................................................................79
Acquisition Requirements ............................ ......... .... ..82
ADCON0 Register.......................................................79
ADCON1 Register.......................................................79
ADIF Bi t............................. ................. ................. ........80
ADRESH Register.......................................................79
ADRESL Register.......................................................79
Analog Port Pins...................................................41, 42
Associated Registers and Bits................................ ....85
Calculating Acquisition Time.......................................82
Configuring Analog Port Pins......................................83
Configuring the Interrupt.............................................81
Configuring the Module...............................................81
Conversi o n  Clo ck...... ...... ...... ....... ...... ...... ....... ...... ......83
Conversions................................................................84
Delays.........................................................................82
Effects of a RESET.....................................................85
GO/DONE Bit ..............................................................80
Internal Sampling Switch (Rss) Impedance................82
Operation During SLEEP............................................85
Result Regi sters................ ...... ....... ...... ...... ....... ...... ....84
Source Impedance.................. ........... .... .... ......... .... ....82
Time Dela ys....... ....... ...... ...... ....... ................ ....... ...... ..82
Absolute Maximum Ratings ..............................................117
ADCON0 Register ...............................................................13
ADCON1 Register ...............................................................14
ADRESH Registers.............................................................13
ADRESL Register...............................................................14
Analog-to-Digital Converter. See A/D.
Application Notes
AN552 (Implementing Wake-up on Key Stroke).........35
AN556 (Implementing a Table Read) .........................24
Assembler
MPASM Assembler...................................................111
Asynchronous Reception
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....69
Asynchronous Reception (9-bit Mode)
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....71
B
Banking, Data Memory .......................................................11
Baud Rate Generator (BRG)
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....63
Block Diagrams
A/D..............................................................................81
Analog Input Model.....................................................82
Capture Mode Operation ......................... .. ....... .. .. .... ..56
Compare Mode Operation .................................. .. .. .. ..57
Inter rupt Logic......................... ....... ...... ................. ......97
On-Chip  RESET Circuit ................. ...... ...... .................91
PIC16F870....................................................................5
PIC16F871....................................................................6
PORTC (Peripheral Output Override). ........................37
PORTD (In I/O Port Mode)..........................................38
PORTD and PORTE (Parallel Slave Port)..................42
PORTE (In I/O Port Mode)..........................................39
PWM Mode........ ....... ...... ................. ...... ................. ....58
RA3:RA0 and RA5 Pins..............................................33
RA4/T0CKI Pin. ....... ...... ...... ....... ...... ...... ...... ....... ...... ..33
RB3:RB0 Pin s......................... ....... ...... ...... ....... ...... ....35
RB7:RB4 Pin s......................... ....... ...... ...... ....... ...... ....35
Timer0/WDT Prescaler ...............................................45
Timer1 ........................................................................ 50
Timer2 ........................................................................ 53
USART Asynchronous Receive.................................. 68
USART Asynchronous Receive (9-bit Mode) ............. 70
USART Transm i t .......... ....... ................ ....... ...... ...... .... 66
Watchdog Timer ........................ .. .... .. ....... .... .. .... .. .... .. 99
BOR. See Brown-out Reset.
BRGH Bit............................................................................ 63
Brown-out Reset (BOR) .................................... 87, 91, 92, 93
BOR Status  (BOR Bit)............. ...... ................. ...... ...... 23
C
C Compilers
MPLAB C17........ ................. ...... ................. ...... ...... .. 112
MPLAB C18........ ................. ...... ................. ...... ...... .. 112
MPLAB C30........ ................. ...... ................. ...... ...... .. 112
Capture/Compare /P WM ( CCP)....... ...... ...... ....... ...... ...... .... 55
Associated Registers
Capture, Compare and Timer 1....... ...... ...... ...... .. 59
PWM and Timer2................................................ 60
Capture Mod e................. ................. ....... ...... ...... ........ 56
CCP1IF............................................................... 56
Prescaler ............................................................ 56
CCP Timer Resou rce s................. ...... ....... ...... ...... ...... 55
Compare
Special Trigger Output of CCP1. ........................ 57
Compare Mode.................. ...... ...... ...... ....... ...... ...... .... 57
Softwar e  In terrupt Mode......................... ...... ...... 57
Special Event Trigger......................................... 57
PWM Mode..... ...... ...... ................. ...... ....... ................ .. 58
Duty Cycle...... ...... ....... ...... ...... ....... ................ .... 58
Example Frequencies/Resolutions (table).......... 59
PWM Period..... ................. ................. ................ 58
Setup for PWM Operation.................................. 59
Special Event Trigger and A/D Conversions. ............. 57
CCP. See Capture/Compare/PWM .
CCP1CON Regis te r................... ...... ...... ...... ....... ...... ...... .... 13
CCP1M0 Bit........................................................................ 55
CCP1M1 Bit........................................................................ 55
CCP1M2 Bit........................................................................ 55
CCP1M3 Bit........................................................................ 55
CCP1X Bit .......................................................................... 55
CCP1Y Bit .......................................................................... 55
CCPR1H Register................. ............. ...... ....... ............ .. 13, 55
CCPR1L Regist e r................. ....... ...... ...... ....... ...... ...... .. 13, 55
Code Examples
Changing Between Capture Prescalers ..................... 56
EEPROM Data Read...... ....... ...... ...... ....... ...... ...... ...... 29
EEPROM Data Write...... ....... ...... ................. ...... ...... .. 29
FLASH Program Read............... ................. ...... ...... .... 30
FLASH Program Write.... ....... ................. ...... .............. 31
Indirect Addressing..................................................... 24
Initializing PORTA ...................................................... 33
Saving STATUS, W and PCLATH Registers 
in RAM...... ...... ...... ....... ...... ...... ....... ...... ...... ...... .. 98
Code Protected Operation
Data EEPROM and FLASH Program Memory........... 31
Code Protection.......................................................... 87, 101
Computed GOTO................................................................ 24
Configuration Bits ............................................................... 87
Configuration Word............................................................. 88
Conversi on  Cons id e ration s. ....... ...... ...... ...... ....... ...... ...... .. 158

PIC16F870/871
DS30569B-page 162  2003 Microchip Technology Inc.
D
Data EEPROM....................................................................27
Associ a te d  Re g i st e rs .......... ...... ...... ....... ...... ...............32
Code Protection ..........................................................31
Reading.......................................................................29
Spuri o u s Wr ite  Protection ... ...... ................. .................31
Write Verify .................................................................31
Writing to.....................................................................29
Data Memory.......................................................................11
Bank Select (RP1:RP0 Bits) ......... ....... .......................11
General Purpose Registers.........................................11
Register File Map............ ...... ...... ....... ...... ...... ...... .......12
Special Function Registers.........................................13
DC and AC Characteristics Graphs and Tables................137
DC Characteristics
PIC16F870/871 (Extended) ......................................123
PIC16F870/871 (Industrial).......................................121
PIC16F870/871 (Industrial, Extended) and 
PIC16LF870/871 (Commercial, Industrial)........119
Demonstration Boards
PICDEM 1........ ...... ....... ...... ...... ...... ....... ...... ...... .......114
PICDEM 17............ ....... ...... ...... ...... ....... ...... ...... .......114
PICDEM 18R PIC18 C6 01/801...... ....... ...... ...... ....... ..115
PICDEM 2 Plus...... ................. ...... ....... ...... ...... ....... ..114
PICDEM 3 PIC16C92 X........................ ...... ............. ..114
PICDEM 4........ ...... ....... ...... ...... ...... ....... ...... ...... .......114
PICDEM LIN PIC16C43X . ................... ............ ....... ..115
PICDEM USB PIC16C7 X5........ ...... ....... ...... ...... .......115
PICDEM.net Internet/Ethernet..................................114
Development Support . ......................................................111
Device Differences............................................................157
Device Overview...................................................................5
Direct Add ressing........... ....... ...... ...... ...... ....... ...... ...... .........25
E
EEADR Register .................................................................15
EEADRH Register...............................................................15
EECON1 Regist e r................... ...... ...... ....... ...... ...... ...... .15, 27
EECON2 Regist e r................... ...... ...... ....... ...... ...... ...... .15, 27
EEDATA Register ...............................................................15
EEDATH Register...............................................................15
Electrical Characteristics...................................................117
Errata ....................................................................................4
Evalu a tion and Progr a mm i n g  To o l s............. ................ .....115
F
Firmware Instructions........................................................103
FLASH Program Memory............................. ...... .................27
Associ a te d  Re g i sters........ ...... ................. ...... ...... .......32
Code Protection ..........................................................31
Configuration Bits and Read/Write State....................32
Reading.......................................................................30
Spuri o u s Wr ite  Protection ... ...... ................. .................31
Write Protection ..........................................................32
Write Verify .................................................................31
Writing to.....................................................................30
FSR Register...........................................................13, 14, 15
I
I/O Ports.... ................. ...... ................. ................. ...... ...........33
ID Locations................................................................87, 101
In-Circuit Debugger.....................................................87, 101
In-Circuit Serial Programming (ICSP).........................87, 102
INDF Register .........................................................13, 14, 15
Indirect Addressing............................................................. 25
FSR Register........................................................ 11, 24
INDF Register............................................................. 24
Instruction Descriptions .................................................... 105
Instruction Format............................................................. 103
Instruction Set................................................................... 103
ADDLW..................................................................... 105
ADDWF..................................................................... 105
ANDLW..................................................................... 105
ANDWF..................................................................... 105
BCF .......................................................................... 105
BSF........................................................................... 105
BTFSC...................................................................... 105
BTFSS...................................................................... 105
CALL......................................................................... 106
CLRF ........................................................................ 106
CLRW....................................................................... 106
CLRWDT .................................................................. 106
COMF....................................................................... 106
DECF........................................................................ 106
DECFSZ ................................................................... 107
GOTO....................................................................... 107
INCF ......................................................................... 107
INCFSZ..................................................................... 107
IORLW...................................................................... 107
IORWF...................................................................... 107
MOVF ....................................................................... 108
MOVLW.................................................................... 108
MOVWF.................................................................... 108
NOP.......................................................................... 108
RETFIE..................................................................... 108
RETLW..................................................................... 108
RETURN................................................................... 109
RLF........................................................................... 109
RRF .......................................................................... 109
SLEEP...................................................................... 109
SUBLW..................................................................... 109
SUBWF..................................................................... 109
SWAPF..................................................................... 110
XORLW .................................................................... 110
XORWF .................................................................... 110
Summary Ta b l e...... ...... ...... ....... ...... ...... ................. .. 104
INT In t e rr up t (RB0/INT) .  See Interrupt Sources.
INTCON.............................................................................. 15
INTCON Register.......................................................... 13, 15
GIE Bi t...................... ........................... ....................... 18
INTE Bit ..... ...... ................. ................. ................. ........ 18
INTF Bit .................. ...... ...... ................. ...... ....... .......... 18
PEIE Bi t........... ................. ................. ...... ................. .. 18
RBIE Bit...................................................................... 18
RBIF Bit........... ....... ................ ....... ...... ................. 18, 35
T0IE Bi t.... ........................... ................. ................. ...... 18
Internal Sampling Switch (Rss) Impedance........................ 82
Interrupt Sources.......................................................... 87, 96
Interrupt-on-Change (RB7:RB4)................................. 35
RB0/INT Pin, External................................................. 97
TMR0 Overflow........................................................... 97
USART Receive/Transmit Complete.......................... 61
Interrupts, Context Saving During....................................... 98

 2003 Microchip Technology Inc. DS30569B-page 163
PIC16F870/871
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit)..........................18, 96
Interrupt-on-Change (RB7:RB4) Enable 
(RBIE Bit)......................................................18, 97
Peripheral Interrupt Enable (PEIE Bit)........................18
RB0/INT Enable (INTE Bit).........................................18
TMR0 Overflow Enable (T0IE Bit)...............................18
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) 
Flag (RBIF Bit)...... ................. .................18, 35, 97
RB0/INT Flag (INTF Bit)..............................................18
TMR0 Overflow Flag (T0IF  Bit).................. .................97
L
Loading of PC ....................... .. .. .. .. .. ....... .. .. .. .. .. .. .. ....... .. .. .. ..24
Low Voltage In-Circuit Serial Programming................87, 102
M
Master Clear (MCLR)
MCLR Reset, Normal Operation...........................91, 93
MCLR Reset, SLEEP....................... ...... ...............91, 93
MCLR/VPP/THV Pin..........................................................7, 8
Memory Organization
Data Memor y ................ ...... ....... ................ ....... ...... ....11
Program Memory........................................................11
Migration from High-End to Enhanced Devices.......... .. ....159
Migration from Mid-Range to Enhanced Devices .............158
MPLAB ASM30 Assembler, Linker, Librarian ...................112
MPLAB ICD 2 In-Circuit Debugger ............................. .... ..113
MPLAB ICE 2000 High Performance Univers al 
In-Circuit Emulator....................................................113
MPLAB ICE 4000 High Performance Univers al 
In-Circuit Emulator....................................................113
MPLAB Integrated Development 
Environ ment Softwa re.................. ...... ...... .................111
MPLINK Object Linker/ MPL IB Object Librar ia n............ ....112
O
OPCODE Fiel d  Descri p tions.................. ...... ...... ....... ........103
OPTION ..............................................................................15
OPTION Register................................................................15
OPTION_R EG Re g i ster........ ...... ....... ...... ...... ...... .........14, 17
INTEDG Bi t........ ....... ...... ...... ................. ...... ...............17
PSA Bit........................................................................17
RBPU Bit........ ....... ...... ...... ...... ................. ....... ...... ......17
T0CS Bit......................................................................17
T0SE Bit......................................................................17
OSC1/CLKI Pin............... ...... ...... ....... ...... ...... ...... .............7, 8
OSC2/CLKO Pin...............................................................7, 8
Oscillator Configuration .......................................................87
HS.........................................................................89, 92
LP..........................................................................89, 92
RC.............. ...... ................. ...... ....... ...... ...........89, 90, 92
XT .........................................................................89, 92
Oscillat o r, WDT.......... ....... ...... ............. ...... ...... ....... ...... ......99
Oscillators
Capacitor Selection................................................. ....90
Crystal and Ceramic Resonators................................89
RC...............................................................................90
P
Packaging......................................................................... 149
Marking In formation............. ...... ...... ....... ...... ...... ...... 149
Parallel Slave Port (PSP).......................................... 9, 38, 42
Associ a te d  Re g i sters......... ...... ...... ...... ....... ...... ...... .... 43
RE0/RD/AN5 Pin.................................................. 41, 42
RE1/WR/AN6 Pin ................................................. 41, 42
RE2/CS/AN7 Pi n ...... ...... ....... ................. ...... ........ 41, 42
Select (PSPMODE Bit)............................. 38, 39, 40, 42
PCL Register.................................................... 13, 14, 15, 24
PCLATH Register............. ...... ....... ...... ...... ....... 13, 14 , 15, 24
PCON Register....................................................... 14, 15, 92
BOR Bit....................................................................... 23
POR Bit....................................................................... 23
PICkit 1 FLASH Starter Kit................................................ 115
PICSTART Plus Development Programmer..................... 113
PIE1 Register ............................................................... 14, 15
PIE2 Register ............................................................... 14, 15
Pinout Descriptions
PIC16F870 ................................................................... 7
PIC16F871 ................................................................... 8
PIR1 Register ..................................................................... 13
PIR2 Register ..................................................................... 13
POP.................................................................................... 24
POR. See Power-on Reset.
PORTA............................................................................. 7, 8
Associ a te d  Re g i sters......... ...... ...... ...... ....... ...... ...... .... 34
PORTA Register......................................................... 33
RA0/AN0 Pin .. ...... ...... ....... ...... ...... ................. ...... .... 7, 8
RA1/AN1 Pin .. ...... ...... ....... ...... ...... ................. ...... .... 7, 8
RA2/AN2/VREF- Pin...................................................... 7
RA2/AN2/VREF- Pin...................................................... 8
RA3/AN3/VREF+ Pin..................................................... 7
RA3/AN3/VREF+ Pin..................................................... 8
RA4/T0CKI Pin. ...... ...... ....... ...... ...... ....... ...... ...... ...... 7,  8
RA5/AN4 Pin .. ...... ...... ....... ...... ................. ...... ...... .... 7, 8
TRISA Register........................................................... 33
PORTA Register................................................................. 13
PORTB............................................................................. 7, 8
PORTB Register......................................................... 35
Pull-up Enable (RBPU Bit).......................................... 17
RB0/INT Edge Select (INTEDG Bit) ........................... 17
RB0/INT Pin.............................................................. 7, 8
RB0/INT Pin, External ................................................ 97
RB1 Pin .................................................................... 7, 8
RB2 Pin .................................................................... 7, 8
RB3/PGM Pin............. ....... ................ ....... ...... ...... .... 7, 8
RB4 Pin .................................................................... 7, 8
RB5 Pin .................................................................... 7, 8
RB6/PGC Pin............................................................ 7, 8
RB7/PGD Pin............................................................ 7, 8
RB7:RB4 Interrupt-on-Change................................. .. 97
RB7:RB4 Interrupt-on-Change 
Enable (RBIE Bit) ......................................... 18, 97
RB7:RB4 Interrupt-on-Change 
Flag (RBIF Bit) ........................................ 18, 35, 97
TRISB Register........................................................... 35
PORTB Register........................................................... 13, 15

PIC16F870/871
DS30569B-page 164  2003 Microchip Technology Inc.
PORTC..............................................................................7, 8
Associ a te d  Re g i sters........ ...... ................. ...... ...... .......37
PORTC Register.........................................................37
RC0/T1OSO/T1CKI Pin................ ....... ................ .....7, 8
RC1/T1OSI Pin.........................................................7, 8
RC2/CCP1 Pin..........................................................7, 8
RC3 Pin.....................................................................7, 8
RC4 Pin.....................................................................7, 8
RC5 Pin.....................................................................7, 8
RC6/TX/CK Pin...................................................7, 8, 62
RC7/RX/DT Pin.............................................7, 8, 62, 63
TRISC Register...... ....... ...... ...... ...... ....... ...... ...... ...37, 61
PORTC Register.................................................................13
PORTD............................................................................9, 42
Associ a te d  Re g i st e rs .......... ...... ...... ....... ...... ...............38
Paral l e l  Sla ve Port (PSP)  Fu n ction........ ...... ...... .........38
PORTD Register.........................................................38
RD0/PSP0 Pin ....... ....... ...... ...... ...... ....... ...... ...... ....... ....9
RD1/PSP1 Pin ....... ....... ...... ...... ...... ....... ...... ...... ....... ....9
RD2/PSP2 Pin ....... ....... ...... ...... ...... ....... ...... ...... ....... ....9
RD3/PSP3 Pin ....... ....... ...... ...... ...... ....... ...... ...... ....... ....9
RD4/PSP4 Pin ....... ....... ...... ...... ...... ....... ...... ...... ....... ....9
RD5/PSP5 Pin ....... ....... ...... ...... ...... ....... ...... ...... ....... ....9
RD6/PSP6 Pin ....... ....... ...... ...... ...... ....... ...... ...... ....... ....9
RD7/PSP7 Pin ....... ....... ...... ...... ...... ....... ...... ...... ....... ....9
TRISD Register...... ....... ...... ...... ...... ....... ...... ...... ....... ..38
PORTD Register.................................................................13
PORTE..................................................................................9
Analog Port Pins...................................................41, 42
Associ a te d  Re g i sters........ ...... ................. ...... ...... .......41
Input Buffer Full Status (IBF Bit) .................................40
Input Buffer Overflow (IBOV Bit).................... .............40
Output Buffer Full Status (OBF Bit).............................40
PORTE Register.........................................................39
PSP Mode Select (PSPM ODE  Bit) ...........38, 39, 40, 42
RE0/RD/AN5 Pin...............................................9, 41, 42
RE1/WR/AN6 Pin..............................................9, 41, 42
RE2/CS/AN7 Pin...............................................9, 41, 42
TRISE Register...........................................................39
PORTE Register .................................................................13
Postscaler, WDT
Assignment (PSA Bit ) ... ................ ....... ...... .................17
Power-down Mode. See SLEEP.
Power-on Reset (POR).....................................87, 91, 92, 93
Oscillator Start-up Timer (OST)......................... ...87, 92
POR Status  (PO R  Bit)............. ...... ....... ................ .......23
Power Control (P CON)  Regis te r..... ....... ............ ....... ..92
Power-down (PD Bit) ..................................................91
Power-up  Tim e r ( PWRT) ........ ...... ....... ...... ...... .....87, 92
Time-out (TO  Bit) .......... ................ ....... ...... .................91
PR2.....................................................................................15
PR2 Register.................................................................14, 53
Prescaler, Timer0
Assignment (PSA Bit ) ... ................ ....... ...... .................17
PRO MATE II Universal Device Programmer ...................113
Product Identification System............................................169
Program Counter
RESET Conditions.................... .. .. ....... .... .. .. .... .. ....... ..93
Program Memory ................................................................11
Inter rupt Vecto r............... ................ ................. ...........11
Map and Stack............................................................11
Paging.........................................................................24
RESET Vec to r.......... ....... ...... ................. ................. ....11
Program Verification..........................................................101
Programming, Device Instructions....................................103
Pulse Width Modulation. 
See Capture/Compare/PW M , PWM  Mode.
PUSH.................................................................................. 24
R
RAM. See Data Me mory.
RCREG Register ................................................................ 13
RCSTA Regist e r............. ...... ...... ....... ................ ....... ...... .... 13
ADDEN Bit.................................................................. 62
CREN Bit....... ....... ...... ...... ................. ...... ....... ............ 62
FERR Bit..................................................................... 62
OERR Bit.................................................................... 62
RX9 Bit ....................................................................... 62
RX9D Bit.......... ....... ................ ....... ...... ................. ...... 62
SPEN Bit............................................................... 61, 62
SREN Bit ....... ....... ...... ...... ...... ....... ................. ...... ...... 62
Register File....... ............. ...... ...... ....... ...... ...... ................. .... 11
Register File Map.................. ...... ....... ...... ...... ...... ....... ...... .. 12
Registers
ADCON0 (A/D Contr o l 0 )........ ....... ...... ...... ....... .......... 79
ADCON1 (A/D Contr o l 1 )........ ....... ...... ...... ....... .......... 80
CCP1CON (CCP Control 1)........................................55
EECON1 (EEPROM Control 1) .................................. 28
INTCON...................................................................... 18
OPTION_REG...................................................... 17, 46
PCON (Power Control)............................................... 23
PIE1 (Peripheral Interrupt Enable 1)........................... 19
PIE2 (Peripheral Interrupt Enable 2)........................... 21
PIR1 (Peripheral Interrupt Request Flag 1)................ 20
PIR2 (Peripheral Interrupt Request Flag 2)................ 22
RCSTA (Receive Status and Control) ........................ 62
STATUS ..................................................................... 16
T1CON (Timer1 Con tr o l)...... ....... ...... ...... ....... ............ 49
T2CON (Timer 2 Cont rol) ............ ...... ...... ....... ............ 53
TRISE......................................................................... 40
TXSTA (Transmit Status and Control)........................ 61
Reset ............................................................................ 87, 91
MCLR Reset. See MCLR.
RESET Conditions for All Registers ........................... 93
RESET Conditions for PCON Register. ...................... 93
RESET Conditions for Program Counter.................... 93
RESET Conditions for STATUS Register................... 93
Reset
Brown-out Reset (BOR). See Brown-out Reset (BOR).
Power-on Reset (POR). See Power-on Reset  (POR ).
WDT Reset. See Watchdog Timer (WDT).
Revision History................................................................ 157
S
SCI. See USART
Serial Communication Interface. See USART.
SLEEP..... ................ ....... ................ ....... ............... 87, 91, 100
Softwar e  Simulator ( MP L AB SIM) .......................... ...... .... 112
Software Simulator (MPLAB SIM30) ................................ 112
SPBRG............................................................................... 15
SPBRG Register................................................................. 14
Special Features of the  CPU............... ...... ...... ....... ...... ...... 87
Special Function Registers................................................. 13
Special Function Register Summary .......................... 13
Speed, Operating.................................................................. 1
SSPADD Regist e r.... ....... ...... ...... ....... ...... ................. ...... .... 15
SSPSTAT Regi ster....... ...... ...... ...... ....... ...... ................. ......15
Stack................................................................................... 24
Overflows.................................................................... 24
Underflow ................................................................... 24

 2003 Microchip Technology Inc. DS30569B-page 165
PIC16F870/871
STATUS Regi ster ............... ................. ...... ...... ....... ......13, 15
PD Bit..........................................................................91
TO Bit..........................................................................91
Synchronous Master Reception
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....75
Synchronous Master Transmission
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....73
Synchronous Slave Reception
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....77
Synchronous Slave Transmission
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....76
T
T1CKPS0 Bit.......................................................................49
T1CKPS1 Bit.......................................................................49
T1CON Regis te r ................... ...... ....... ...... ...... ................. ....13
T1OSCEN Bit......................................................................49
T1SYNC Bit.......... ...... ................. ................. ................. ......49
T2CKPS0 Bit.......................................................................53
T2CKPS1 Bit.......................................................................53
T2CON Regis te r ................... ...... ....... ...... ...... ................. ....13
TAD......................................................................................83
Time-out Sequence................................ .... .. .... .... ....... .... ....92
Timer0.................................................................................45
Associ a te d  Re g i sters.... ................. ...... ...... ....... ..........47
Clock Source Edge Select (T0SE Bit) . ........................17
Cloc k So u rce Se l e ct (T0CS Bit)...... ...... ...... .. ..... .. ...... .1 7
External Clock.............................................................46
Interrupt.......................................................................45
Overflow Enable (T0IE Bit) .........................................18
Overflow Flag (T0IF Bit)............... ...... ...... ................. ..97
Overflow Interru p t ... ...... ...... ....... ...... ................. ...... ....97
Prescaler.....................................................................46
T0CKI..........................................................................46
Timer1.................................................................................49
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....52
Asynchronous Counter Mode
Reading and Writing to ........................ ..... .. .. .. .. ..51
Counter Operation .............. .. .. ....... .... .. .. .... .. ....... .... .. ..50
Incrementing Edge (figure) .........................................50
Operation in Asynchronous Counter Mode.... .............51
Operation in Synchronized Counter Mode................ ..50
Operation in Timer Mode........ ....... ...... ...... ....... ...... ....50
Oscillator.....................................................................51
Capacitor Selection.................... .... .... ........... .... ..51
Prescaler.....................................................................52
Resetting of Timer1 Register Pair 
(TMR1H, TMR1L)...............................................52
Resetting Timer1 Using a CCP Trigger Output...........51
TMR1H........................................................................51
TMR1L........................................................................51
Timer2.................................................................................53
Associ a te d  Re g i sters.... ...... ....... ................ ....... ...... ....54
Output.........................................................................54
Postscaler...................................................................53
Prescaler.....................................................................53
Prescaler and Postscaler. ...........................................54
Timing Diagrams
A/D Conversion..... ...... ...... ...... ....... ...... ...... ....... ...... ..135
Asynchronous Master Transmission...........................67
Asynchronous Master Transmission 
(Back to Back) ....................................................67
Asynchronous Reception with 
Address Byte First ..............................................71
Asynchronous Receptio n with 
Address Detect................................................... 71
Brown-o u t Re set..... ...... ....... ...... ...... ....... ...... ...... ...... 129
Capture/Compare/PWM (CCP1)....... ....... ...... ...... .... 131
CLKO and I/O........................................................... 128
External Clock .......................................................... 126
Parallel Slave Port (PSP) Read.................................. 43
Parallel Slave Port (PSP) Write.................................. 43
RESET, Watchdog Timer, Oscillator 
Start-up Timer and Power-up Timer............... .. 129
Slow Rise Time (MCLR Tied to VDD) ......................... 96
Time-out Sequence on Power-up 
(MCLR No t Ti e d  to  V DD)
Case 1................................................................ 95
Case 2................................................................ 95
Time-out Sequence on Power-up 
(MCLR Tied to VDD) ........................................... 95
Timer0 and Timer1 External Clock....................... .... 130
USART Asynchronous Reception .............................. 68
USART Synchronous Receive (Master/Slave)......... 133
USART Synchronous Reception 
(Master Mode, SREN)........................................ 75
USART Synchronous Transmission........................... 73
USART Synchronous Transmission 
(Master/Slave).................................................. 133
Wake-up from SLEEP via Interrupt .......................... 101
Timing Pa rameter Symbology......... ...... ................. .......... 125
TMR0 Register.............................................................. 13, 15
TMR1CS Bit.............. ...... ...... ................. ...... ....... ...... ...... .... 49
TMR1H Register................................................................. 13
TMR1L Register.................................................................. 13
TMR1ON Bit....................................................................... 49
TMR2 Register.................................................................... 13
TMR2ON Bit....................................................................... 53
TOUTPS0 Bit...................................................................... 53
TOUTPS1 Bit...................................................................... 53
TOUTPS2 Bit...................................................................... 53
TOUTPS3 Bit...................................................................... 53
TRISA................................................................................. 15
TRISA Register ................................................................... 14
TRISB................................................................................. 15
TRISB Register ............................................................. 14, 15
TRISC................................................................................. 15
TRISC Regist e r.. ....... ................. ...... ...... ...... ....... ...... ...... .... 14
TRISD................................................................................. 15
TRISD Regist e r.. ....... ................. ...... ...... ...... ....... ...... ...... .... 14
TRISE................................................................................. 15
TRISE Register ................................................................... 14
IBF Bit................. ................. ................ ................. ...... 40
IBOV Bit...................................................................... 40
OBF Bit............... ................. ...... ...... ................. ...... .... 40
PSPMODE Bit .......................................... 38 , 39, 40, 42
TXREG Register................................................................. 13
TXSTA................................................................................ 15
TXSTA Regi ster................ ...... ................. ................. ...... .... 14
BRGH Bit.................................................................... 61
CSRC Bit.............. ...... ................. ...... ................. ...... .. 61
TRMT Bit ............ ...... ...... ....... ...... ...... ................. ...... .. 61
TX9 Bit........................................................................ 61
TX9D Bit..................................................................... 61
TXEN Bit......... ................ ................. ....... ................ .... 61

PIC16F870/871
DS30569B-page 166  2003 Microchip Technology Inc.
U
Universal Synchronous Asynchronous Receiver Transmitter. 
See USART
USART................................................................................61
Address Detect Enable (ADDEN Bit)..........................62
Asynchronous Mode ...................................................66
Asynchronous Receive ...............................................68
Asynchronous Re ceive (9-bit Mode)...........................70
Asynchronous Re ceive with Address Detec t.
See Asynchronous Receive (9-bit  Mode).
Asynchronous Reception............................................69
Asynchronous Transmitter..........................................66
Baud Rate Generator (BRG).......................................63
Baud Rate Formula.............................................63
Baud Rates, Asynchronous Mode 
(BRGH = 0).................................................64
Baud Rates, Asynchronous Mode 
(BRGH = 1).................................................65
High Baud Rate Select (BRGH Bit).....................61
Sampling.............................................................63
Clock Source  Se le ct (CSRC Bit)..... ....... ...... ...... .........61
Continuous Receive Enable (CREN Bit).....................62
Framing  Error (FERR Bit) ............. ....... ...... ...... ....... ....62
Overrun Error (OERR Bit)...........................................62
Receive Data, 9th bit (RX9D Bit) ................................62
Receive Enable, 9-bit (RX9 Bit)..................................62
Serial Port Enable (SPEN Bit)...............................61, 62
Single Receive Enable (SREN Bit) .............................62
Synchronous Master Mode.........................................72
Synchronous Master Reception..................................74
Synchronous Master Transmission.............................72
Synchronous Slave Mode............... ......... .... .... .. .........76
Synchronous Slave Reception....................................77
Synchronous Slave Transmit....................... .... .... .......76
Transmit Data, 9th Bit (TX9D)......... ....... ...... ...... ....... ..61
Transmit Enable (TXEN Bit)............................. .. ....... ..61
Transmit Enable, Nine-bit (TX9 Bit) ............................61
Transmit Shift Reg i ster Statu s (T RMT Bit)..... ...... .......61
W
Wake-up from SLEEP................................................. 87, 100
Interrupts .................................................................... 93
MCLR Reset......... ...... ...... ...... ....... ...... ...... ................. 93
Timing Dia g ram ...................... ....... ...... ...... ....... ...... ..101
WDT Reset................... ...... ....... ...... ...... ...... ....... ...... ..93
Watchdog Timer
Register Summary.......... ...... ....... ................ ....... ........ 99
Watchdog Timer (WDT)................................. .... ....... .... 87, 99
Enable (WDTEN Bit)................................................... 99
Postscaler. See Postscaler, WDT.
Program ming  Co n side r a tions............ ...... ....... ............ 99
RC Oscillator............................................................... 99
Time-o u t Pe riod........ ................. ................ ................. 99
WDT Reset, Normal Operation............................. 91, 93
WDT Reset, SLE EP ...... ...... ....... ................ ....... .... 91, 93
Write Verify
Data EEPROM and FLASH Program Memory........... 31
WWW, On-Line Support....................................................... 4

 2003 Microchip Technology Inc. DS30569B-page 167

PIC16F870/871

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web site.

The web site is used b y Micr ochip as a me ans to mak e

files and information easily available to customers. To

view t he site, the user must have acce ss to the In ternet

and a web browser, such as Netscape® or Microsoft®

Internet Explorer. Files are also available for FTP

download from our FTP site.

Connecting to the Microchip Internet

Web S ite

The Microchip web site is available at the following

URL:

www.microchip.com

The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User's Guides, Articles and Sample Programs. A vari-

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

• Device Errat a

• Job Postin gs

• Mic rochip Consultant Pr ogram Member Listing

• Links to other useful web sites related to

Microchip Products

• Confere nces for prod ucts, Dev elopment Systems,

technical information and more

• Listing of seminars and events

SYSTEMS INFORMATION AND

UPGRADE HOT LINE

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip's development systems software products.

Plus, this line provides information on how customers

can rece ive the mo st current u pgrade kit s.The Hot Line

Numbe rs are:

1-800-755-2345 for U.S. and most of Canada, and

1-480-792-7302 for the rest of the world.

042003

PIC16F870/871

DS30569B-page 168  2003 Microchip Technology Inc.

READER RESPONSE

It is ou r intentio n to pro vi de you with the bes t do cu me ntation po ss ib le to ens ure suc c es sful use of your Mic roc hip pro d-

uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, subj ect matte r , a nd ways i n whic h our docum entat ion

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

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Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _________ - _________

DS30569BPIC16F870/871

1. What are the be st features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

 2003 Microchip Technology Inc. DS30569B-page 169

PIC16F870/871

PIC16F870/871 PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277

3. The Microchip Worldwide Site (www.microchip.c om)

Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.

New Customer Notification System

PART NO. -X /XX XXX

PatternPackageTemperature

Range

Device

Device PIC16F870, PIC16F870T; VDD range 4.0V to 5.5V

PIC16F871, PI C16F871T ; VDD range 4.0V to 5.5V

PIC16LF870X, PIC16LF870T; VDD range 2.0V to 5.5V

PIC16LF871X, PIC16LF871T; VDD range 2.0V to 5.5V

F= Normal V

DD limits

LP = Extended VDD limits

T = In Tape and Reel - SOIC, SSOP, TQFP and

PLCC packages only.

Tem per atu re Range blank( 3) = 0°C to +70°C (Com m erci a l)

I = -40°C to +85°C (Industrial)

Package PQ = MQFP (Metric PQFP)

PT = TQFP (Thin Quad Flatpack)

SO = SOIC

SP = Skinny Plastic Dip

SS = SSOP

P=PDIP

L=PLCC

Pattern QTP, Code or Special Requirements

(blank otherwise)

Examples:

a) PIC16F870-I/SP 301 = Industrial temp., PDIP

package, 20 MHz, normal VDD limits, QTP

pattern #301.

b) PIC16F871-I/PT = Industrial temp., TQFP

package, 20 MHz, Exten ded VDD limits.

c) PIC16F871-I/P = Industrial temp., PDIP

package, 20 MHz, norma l VDD limits.

d) PIC16LF870-I/SS = Industrial temp., SSOP

package, DC - 20 MHz, extende d VDD limits.

DS30569B-page 170  2003 Microchip Technology Inc.

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Austria

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

Denmark

Microchi p Technology Nordic ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45-4420-9895 Fax: 45-4420-9910

France

Microchip Technology SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - l er Etage

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Microchip Technology GmbH

Steinheilstrasse 10

D-85737 Ismaning, Germany

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy

Microchip Technology SRL

Via Quasimodo, 12

20025 Legnano (MI)

Milan, Italy

Tel: 39-0331-742611 Fax: 39-0331-466781

United Kingdom

Microchip Ltd.

505 Eskdale Road

Winnersh T riangle

Wokingham

Berk shire, England RG41 5TU

Tel: 44-118-921-5869 Fax: 44-118-921-5820

03/25/03

WORLDWIDE SALES AND SERVICE