Automotive Power
Data Sheet
Rev. 1.2, 2015-01-12
TLS203B0
Linear Voltage Post Regulator
Low Dropout, Low Noise, 3.3 V, Adjustable, 300 mA
TLS203B0EJV
TLS203B0EJV33
TLS203B0LDV
TLS203B0LDV33
Type Package Marking
TLS203B0EJV PG-DSO-8 Exposed Pad 203B0V
TLS203B0EJV33 PG-DSO-8 Exposed Pad 203B0V33
TLS203B0LDV PG-TSON-10 203B0V
TLS203B0LDV33 PG-TSON-10 203B0V3
PG-DSO-8 Exposed Pad
PG-TSON-10
Data Sheet 2 Rev. 1.2, 2015-01-12
Linear Voltage Post Regulator
Low Dropout, Low Noise, 3.3 V, Adjustable, 300 mA
TLS203B0
1Overview
Features
• Low Noise down to 24 µVRMS (BW = 10 Hz to 100 kHz)
• 300 mA Current Capability
• Low Quiescent Current: 30 µA
• Wide Input Voltage Range up to 20 V
• Internal circuitry working down to 2.3 V
• 2.5% Output Voltage Accuracy (over full temperature and load range)
• Low Dropout Voltage: 270 mV
• Very low Shutdown Current: < 1 µA
• No Protection Diodes Needed
• Fixed Output Voltage: 3.3 V
• Adjustable Version with Output from 1.22 V to 20 V
• Stable with 3.3 µF Output Capacitor
• Stable with Aluminium, Tantalum or Ceramic Output Capacitors
• Reverse Polarity Protection
• No Reverse Current
• Overcurrent and Overtemperature Protected
• PG-DSO-8 Exposed Pad and PG-TSON-10 Exposed Pad Package
• Suitable for Use in Automotive Electronics as Post Regulator
• Green Product (RoHS compliant)
• AEC Qualified
The TLS203B0 is a micropower, low noise, low dropout voltage regulator. The device is capable of supplying an
output current of 300 mA with a dropout voltage of 270 mV. Designed for use in battery-powered systems, the low
quiescent current of 30 µA makes it an ideal choice.
A key feature of the TLS203B0 is its low output noise. By adding an external 10 nF bypass capacitor output noise
values down to 24 µVRMS over a 10 Hz to 100 kHz bandwidth can be reached. The TLS203B0 voltage regulator
TLS203B0
Overview
Data Sheet 3 Rev. 1.2, 2015-01-12
is stable with output capacitors as small as 3.3 µF. Small ceramic capacitors can be used without the series
resistance required by many other linear voltage regulators.
Internal protection circuitry includes reverse battery protection, current limiting and reverse current protection. The
TLS203B0 comes as fixed output voltage variant 3.3 V as well as adjustable device with a 1.22 V reference
voltage. It is available in a PG-DSO-8 Exposed Pad and as well as in a PG-TSON-10 Exposed Pad package.
Data Sheet 4 Rev. 1.2, 2015-01-12
TLS203B0
Block Diagram
2 Block Diagram
Note: Pin numbers in block diagrams refer to the PG-DSO-8 Exposed Pad package type.
Figure 1 Block Diagram TLS203B0 V33 fixed voltage version
Figure 2 Block Diagram TLS203B0 V adjustable version
Bias
Voltage
reference
Saturation
Control
Temperature
Protection
Over Current
Protection
TLS203B0
I
EN
GND
BYP
Q
SENSE
Error
Amplifier
1
2
4
5
8
6
Bias
Voltage
reference
Saturation
Control
Temperature
Protection
Over Current
Protection
TLS203B0 (ADJ)
I
EN
GND
BYP
Q
ADJ
Error
Amplifier
1
2
4
5
8
6
TLS203B0
Pin Configuration
Data Sheet 5 Rev. 1.2, 2015-01-12
3 Pin Configuration
3.1 Pin Assignment
Figure 3 Pin Configuration of TLS203B0 in PG-DSO-8 Exposed Pad for fixed voltage and adjustable
version
Figure 4 Pin Configuration of TLS203B0 in PG-TSON-10 for fixed voltage and adjustable version.
I
NC
GND
Q
ADJ
NC
BYP EN
1
3
2
8
7
6
45
I
NC
GND
Q
SENSE
NC
BYP EN
1
3
2
8
7
6
45
TLS203B0EJV33 TLS203B0EJV
99
1
2
3
4
5
10
9
8
7
6
Q
Q
NC
SENSE
BYP
I
I
NC
EN
GND
1
2
3
4
5
10
9
8
7
6
Q
Q
NC
ADJ
BYP
I
I
NC
EN
GND
TLS205B0LDV33 TLS205B0LDV
Data Sheet 6 Rev. 1.2, 2015-01-12
TLS203B0
Pin Configuration
3.2 Pin Definitions and Functions
Pin Symbol Function
1 (DSO-8 EP)
1,2 (TSON-10)
QOutput. Supplies power to the load. For this pin a minimum output capacitor of
3.3 µF is required to prevent oscillations. Larger output capacitors may be
required for applications with large transient loads in order to limit peak voltage
transients or when the regulator is applied in conjunction with a bypass capacitor.
For more details please refer to “Application Information” on Page 24.
2 (DSO-8 EP)
4 (TSON-10)
SENSE
(fix voltage
version)
Output Sense. For the fixed voltage version the SENSE pin is the input to the
error amplifier. This allows to achieve an optimized regulation performance in
case of small voltage drops Rp that occur between regulator and load. In
applications where such drops are relevant they can be eliminated by connecting
the SENSE pin directly at the load. In standard configuration the SENSE pin can
be directly connected to Q. For further details please refer to the section “Kelvin
Sense Connection” on Page 25.
2 (DSO-8 EP)
4 (TSON-10)
ADJ
(adjustable
version)
Adjust. For the adjustable version the ADJ pin is the input to the error amplifier.
The ADJ pin voltage is 1.22 V referenced to ground and allows a output voltage
range from 1.22 V to 20 V- VDR. The ADJ pin is internally clamped to ±7 V. Please
note that the bias current of the ADJ pin is flowing into the pin. Its typical value of
60 nA shows a good stability with temperature. For further details please refer to
Typical Performance Graph “Adjust Pin Bias Current versus Junction
Temperature TJ” on Page 20.
3, 7 (DSO-8 EP)
3, 8 (TSON-10)
NC No Connect. The NC Pins have no connection to any internal circuitry. Connect
either to GND or leave open.
4 (DSO-8 EP)
5 (TSON-10)
BYP Bypass. The BYP pin is used to bypass the reference of the TLS203B0 to
achieve low noise performance. The BYP-pin is clamped internally to ±0.6 V (i.e.
one VBE). A small capacitor from the output Q to the BYP pin will bypass the
reference to lower the output voltage noise 1). If not used this pin must be left
unconnected.
5 (DSO-8 EP)
7 (TSON-10)
EN Enable. With the EN pin the TLS203B0 can be put into a low power shutdown
state. The output will be off when the EN is pulled low. The EN pin can be driven
either by 3.3 V or 5 V logic or as well by open-collector logic with pull-up resistor.
The pull-up resistor is required to supply the pull-up current of the open-collector
gate 2) and the EN pin current 3). Please note that if the EN pin is not used it must
be connected to VI. It must not be left floating.
6 (DSO-8 EP)
6,(TSON-10)
GND Ground. For the ADJ version connect the bottom of the output voltage setting
resistor divider directly to the GND pin for optimum load regulation performance.
TLS203B0
Pin Configuration
Data Sheet 7 Rev. 1.2, 2015-01-12
8 (DSO-8 EP)
9, 10 (TSON-10)
IInput. The device is supplied by the input pin I. A capacitor at the input pin is
required if the device is more than 6 inches away from the main input filter
capacitor or if a non-negligible inductance is present at the input I 4). The
TLS203B0 is designed to withstand reverse voltages on the input pin I with
respect to GND and output Q. In the case of reverse input (e.g. due to a wrongly
attached battery) the device will act as if there is a diode in series with its input. In
this way there will be no reverse current flowing into the regulator and no reverse
voltage will appear at the load. Hence, the device will protect both - the device
itself and the load.
9 (DSO-8 EP)
11 (TSON-10)
Tab Exposed Pad. To ensure proper thermal performance, solder Pin 11 of TSON-10
to the PCB ground and tie directly to Pin 6. In the case of DSO-8 EP as well solder
Pin 9 to the PCB ground and tie directly to Pin 6 (GND).
1) A maximum value of 10 nF can be used for reducing output voltage noise over the bandwidth from 10 Hz to 100 kHz.
2) Normally several microamperes.
3) Typical value is 1 µA.
4) In general the output impedance of a battery rises with frequency, so it is advisable to include a bypass capacitor in battery-
powered circuits. Depending on actual conditions an input capacitor in the range of 1 to 10 µF is sufficient.
Pin Symbol Function
Data Sheet 8 Rev. 1.2, 2015-01-12
TLS203B0
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Notes
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not
designed for continuous repetitive operation.
Table 1 Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise
specified)
1) Not subject to production testing, specified by design.
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
Input Voltage
Voltage VI-20 – 20 V – P_4.1.1
Output Voltage
Voltage VQ-20 – 20 V – P_4.1.2
Input to Output Differential Voltage VI-V
Q-20 – 20 V – P_4.1.3
Sense Pin
Voltage VSENSE -20 – 20 V – P_4.1.4
ADJ Pin
Voltage VADJ -7 – 7 V – P_4.1.5
BYP Pin
Voltage VBYP -0.6 – 0.6 V P_4.1.6
Enable Pin
Voltage VEN -20 – 20 V – P_4.1.7
Temperatures
Junction Temperature Tj-40 – 150 °C – P_4.1.8
Storage Temperature Tstg -55 – 150 °C – P_4.1.9
ESD Susceptibility
All Pins VESD -2 – 2 kV HBM 2)
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 k, 100 pF)
P_4.1.10
All Pins VESD -1 – 1 kV CDM 3)
3) ESD susceptibility, Charged Device Model “CDM” according JEDEC JESD22-C101
P_4.1.11
TLS203B0
General Product Characteristics
Data Sheet 9 Rev. 1.2, 2015-01-12
4.2 Functional Range
Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the Electrical Characteristics table.
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go
to www.jedec.org.
Table 2 Functional Range
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
Input Voltage Range
(fix voltage version)
VI3.8 – 20 V – P_4.2.1
Input Voltage Range
(adjustable voltage version)
VI2.3 – 20 V – 1)
1) For the TLS203B0 adjustable version the minimum limit of the functional range VI is tested and specified with the ADJ pin
connected to the Q pin.
P_4.2.2
Output Capacitor’s Requirements
for Stability
CQ3.3 – – µF CBYP =0nF2)
2) for further details see corresponding graph.
P_4.2.3
Output Capacitor’s Requirements
for Stability
CQ6.8 – – µF 0<C
BYP 10 nF 2) P_4.2.4
ESR ESR –3)
3) CBYP =0nF, CQ3.3 µF; please note that for cases where a bypass capacitor at BYP is used – depending on the actual
applied capacitance of CQ and CBYP a minimum requirement for ESR of CQ may apply.
–3–2) P_4.2.5
Operating Junction Temperature Tj-40 – 125 °C – P_4.2.6
Table 3 Thermal Resistance 1)
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLS203B0EJ (PG-DSO-8 Exposed Pad)
Junction to Case RthJC – 7.0 – K/W – P_4.3.1
Junction to Ambient RthJA –39–K/W–
2) P_4.3.2
Junction to Ambient RthJA – 155 – K/W Footprint only 3) P_4.3.3
Junction to Ambient RthJA – 66 – K/W 300 mm2 heatsink
area on PCB 3)
P_4.3.4
Junction to Ambient RthJA – 52 – K/W 600 mm2 heatsink
area on PCB 3)
P_4.3.5
TLS203B0LD (PG-TSON-10)
Junction to Case RthJC – 6.4 – K/W – P_4.3.6
Junction to Ambient RthJA –53–K/W–
2) P_4.3.7
Junction to Ambient RthJA – 183 – K/W Footprint only 3) P_4.3.8
Data Sheet 10 Rev. 1.2, 2015-01-12
TLS203B0
General Product Characteristics
Junction to Ambient RthJA – 69 – K/W 300 mm2 heatsink
area on PCB 3)
P_4.3.9
Junction to Ambient RthJA – 57 – K/W 600 mm2 heatsink
area on PCB 3)
P_4.3.10
1) Not subject to production test, specified by design.
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 µm Cu, 2 x 35 µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70 µm Cu).
Table 3 Thermal Resistance 1)
Parameter Symbol Values Unit Note /
Test Condition
Number
Min. Typ. Max.
TLS203B0
Electrical Characteristics
Data Sheet 11 Rev. 1.2, 2015-01-12
5 Electrical Characteristics
Table 4 Electrical Characteristics
-40 °C < Tj< 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Minimum Operating Voltage 1)
Minimum Operating Voltage VI,min –1.82.3VIQ=300mA2) 3) P_5.0.1
Output Voltage 4)
TLS203B0EJV33
TLS203B0LDV33
VQ3.220 3.30 3.380 V 1 mA < IQ<300mA;
4.3 V < VI<20V
P_5.0.2
TLS203B0EJV
TLS203B0LDV
VQ1.190 1.220 1.250 V 1 mA < IQ<300mA;
2.3V < VI<20V3)
P_5.0.3
Line Regulation
TLS203B0EJV33
TLS203B0LDV33
VQ–120mVVI= 3.8 V to 20 V ;
IQ=1mA
P_5.0.4
TLS203B0EJV
TLS203B0LDV
VQ–120mVVI= 2.0 V to 20 V ;
IQ=1mA3)
P_5.0.5
Load Regulation
TLS203B0EJV33
TLS203B0LDV33
VQ–615mVTJ=25°C;VI=4.3V;
IQ= 1 to 300 mA
P_5.0.6
TLS203B0EJV33
TLS203B0LDV33
VQ––28mVVI=4.3V;
IQ=1to300mA
P_5.0.7
TLS203B0EJV
TLS203B0LDV
VQ–38mVTJ=25°C; VI=2.3V;
IQ= 1 to 300 mA 3)
P_5.0.8
TLS203B0EJV
TLS203B0LDV
VQ––12mVVI=2.3V;
IQ= 1 to 300 mA 3)
P_5.0.9
Dropout Voltage 2) 5) 6)
Dropout Voltage VDR – 130 190 mV IQ=10mA; VI=VQ,nom ;
TJ=25°C
P_5.0.10
Dropout Voltage VDR – – 250 mV IQ=10mA; VI=VQ,nom P_5.0.11
Dropout Voltage VDR – 170 220 mV IQ=50mA; VI=VQ,nom ;
TJ=25°C
P_5.0.12
Dropout Voltage VDR – – 320 mV IQ=50mA; VI=VQ,nom P_5.0.13
Dropout Voltage VDR – 200 240 mV IQ=100mA;
VI=VQ,nom ; TJ=25°C
P_5.0.14
Dropout Voltage VDR – – 340 mV IQ=100mA; VI=VQ,nom P_5.0.15
Dropout Voltage VDR – 270 300 mV IQ=300mA;
VI=VQ,nom ; TJ=25°C
P_5.0.16
Dropout Voltage VDR – – 400 mV IQ=300mA; VI=VQ,nom P_5.0.17
Quiescent Current
Quiescent Current 7)
(Active-Mode, EN-pin high)
Iq–3060µAVI=VQ,nom ;
IQ=0mA
P_5.0.18
Data Sheet 12 Rev. 1.2, 2015-01-12
TLS203B0
Electrical Characteristics
Quiescent Current
(Off-Mode, EN-pin low)
Iq–0.11µAVI=6V; VEN =0V;
TJ=25°C
P_5.0.19
GND Pin Current 5) 7)
GND Pin Current IGND – 50 100 µA VI=VQ,nom;
IQ=1mA
P_5.0.20
GND Pin Current IGND – 300 850 µA VI=VQ,nom ;
IQ=50mA
P_5.0.21
GND Pin Current IGND –0.72.2mAVI=VQ,nom ;
IQ=100mA
P_5.0.22
GND Pin Current IGND –412mAVI=VQ,nom ;
IQ=300mA
P_5.0.23
Enable
Enable Threshold High Vth,EN –0.82.0VVQ= Off to On P_5.0.24
Enable Threshold Low Vtl,EN 0.25 0.65 – V VQ= On to Off P_5.0.25
EN Pin Current 8) IEN –0.01–µAVEN =0V; TJ= 25 °C P_5.0.26
EN Pin Current 8) IEN –1–µAVEN =20V; TJ= 25 °C P_5.0.27
Adjust Pin Bias Current 9) 10)
ADJ Pin Bias Current Ibias,ADJ –60–nATJ= 25 °C P_5.0.28
Output Voltage Noise 10)
Output Voltage Noise
TLS203B0EJV 11)
TLS203B0LDV 11)
eno –41–µVRMS CQ=10µF;
CBYP =10nF;
IQ=300mA;
BW=10Hzto100kHz
P_5.0.29
Output Voltage Noise
TLS203B0EJV 11)
TLS203B0LDV 11)
eno –28–µVRMS CQ=10µF
+250m resistor in series;
CBYP =10nF;
IQ=300mA;
BW=10Hzto100kHz
P_5.0.30
Output Voltage Noise
TLS203B0EJV 11)
TLS203B0LDV 11)
eno –29–µVRMS CQ=22µF
CBYP =10nF;
IQ=300mA;
BW=10Hzto100kHz
P_5.0.31
Output Voltage Noise
TLS203B0EJV 11)
TLS203B0LDV 11)
eno –24–µVRMS CQ=22µF
+250m resistor in series;
CBYP =10nF;
IQ=300mA;
BW=10Hzto100kHz
P_5.0.32
Output Voltage Noise
TLS203B0EJV33
TLS203B0LDV33
eno –45–µVRMS CQ=10µF;
CBYP =10nF;
IQ=300mA;
BW=10Hzto100kHz
P_5.0.33
Table 4 Electrical Characteristics (cont’d)
-40 °C < Tj< 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
TLS203B0
Electrical Characteristics
Data Sheet 13 Rev. 1.2, 2015-01-12
Output Voltage Noise
TLS203B0EJV33
TLS203B0LDV33
eno –35–µVRMS CQ=10µF
+250m resistor in series;
CBYP =10nF;
IQ=300mA;
BW=10Hzto100kHz
P_5.0.34
Output Voltage Noise
TLS203B0EJV33
TLS203B0LDV33
eno –33–µVRMS CQ=22µF
CBYP =10nF;
IQ=300mA;
BW=10Hzto100kHz
P_5.0.35
Output Voltage Noise
TLS203B0EJV33
TLS203B0LDV33
eno –30–µVRMS CQ=22µF
+250m resistor in series;
CBYP =10nF;
IQ=300mA;
BW=10Hzto100kHz
P_5.0.36
Power Supply Ripple Rejection 10)
Power Supply Ripple Rejection PSRR –65–dBVI-VQ= 1.5 V (avg) ;
VRIPPLE =0.5Vpp;
fr= 120 Hz ; IQ=300mA
P_5.0.37
Output Current Limitation
Output Current Limit IQ,limit 320 – – mA VI=7V; VQ= 0 V P_5.0.38
Output Current Limit IQ,limit 320 – – mA VI=VQ,nom +1V or
2.3 V 12) ; VQ=-0.1V
P_5.0.39
Input Reverse Leakage Current
Input Reverse Leakage Ileak,rev ––1mAVI=-20V; VQ= 0 V P_5.0.40
Reverse Output Current 13)
Fixed Voltage Versions IReverse –1020µAVQ =VQ,nom ; VI<VQ,nom ;
TJ=25°C
P_5.0.41
Adjustable Voltage Version IReverse –510µAVQ=1.22V; VI< 1.22 V ;
TJ=25°C3)
P_5.0.42
1) This parameter defines the minimum input voltage for which the device is powered up and provides the maximum nominal
output current of 300 mA. The output voltage of the adjustable version in this condition depends on the chosen setting of
the external voltage divider as well as on the applied conditions – thus the device is either regulating its nominal output
voltage or is in tracking mode.The 3.3 V fixed voltage version is by definition in tracking mode for such low input voltages.
2) For the adjustable version of the TLS203B0 the dropout voltage for certain output voltage / load conditions will be restricted
by the minimum input voltage specification.
3) The adjustable version of the TLS203B0 is tested / specified for these conditions with the ADJ pin connected to the Q pin.
4) The operation conditions are limited by the maximum junction temperature. The regulated output voltage specification will
only apply for conditions where the limit of the maximum junction temperature is fulfilled. It will therefore not apply for all
possible combinations of input voltage and output current at a given output voltage. When operating at maximum input
voltage, the output current must be limited for thermal reasons. The same holds true when operating at maximum output
current where the input voltage range must be limited for thermal reasons.
5) To satisfy requirements for minimum input voltage, the TLS203B0 adjustable version is tested and specified for these
conditions with an external resistor divider (two 250 k resistors) for an output voltage of 2.44 V. The external resistors will
add a 5 µA DC load on the output.
Table 4 Electrical Characteristics (cont’d)
-40 °C < Tj< 125 °C; all voltages with respect to ground; positive current defined flowing out of pin; unless
otherwise specified.
Parameter Symbol Values Unit Note / Test Condition Number
Min. Typ. Max.
Data Sheet 14 Rev. 1.2, 2015-01-12
TLS203B0
Electrical Characteristics
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specified mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at TA=25°C and the given supply voltage.
6) The dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a specified output
current. In dropout, the output voltage will be equal to VI-VDR
7) GND-pin current is tested with VI=VQ,nom and a current source load. This means that this parameter is tested while being
in the dropout region. The GND pin current will in most cases decrease slightly at higher input voltages - please also refer
to the corresponding typical performance graphs.
8) The EN pin current flows into EN pin.
9) The ADJ pin current flows into ADJ pin.
10) Not subject to production test, specified by design.
11) ADJ pin connected to output pin Q.
12) Whichever of the two values of VI is greater in order to also satisfy the requirements for VI,min.
13) Reverse output current is tested with the I pin grounded and the Q pin forced to the rated output voltage. This current flows
into the Q pin and out of the GND pin.
TLS203B0
Electrical Characteristics
Data Sheet 15 Rev. 1.2, 2015-01-12
5.1 Typical Performance Characteristics
Dropout Voltage VDR versus
Output Current IQ
Guaranteed Dropout Voltage VDR versus
Output Current IQ
Dropout Voltage VDR versus
Junction Temperature Tj
Quiescent Current versus
Junction Temperature Tj
0 50 100 150 200 250 300
0
50
100
150
200
250
300
350
400
450
500
IQ [A]
VDR [mV]
Tj = −40 °C
Tj = 25 °C
Tj = 125 °C
0 50 100 150 200 250 300
0
50
100
150
200
250
300
350
400
450
500
IQ [A]
VDR [mV]
Δ = Guaranteed Limits
Tj ≤ 25 °C
Tj ≤ 125 °C
−50 0 50 100
0
50
100
150
200
250
300
350
400
450
500
Tj [°C]
VDR [mV]
IQ = 10 mA
IQ = 50 mA
IQ = 100 mA
IQ = 300 mA
−50 0 50 100
0
5
10
15
20
25
30
35
40
45
50
Tj [°C]
Iq [µA]
VI = 6 V
IQ = 0 mA .
VEN = VI
Data Sheet 16 Rev. 1.2, 2015-01-12
TLS203B0
Electrical Characteristics
Output Voltage VQ versus
Junction Temperature TJ (TLS203B0EJV33)
Output Voltage VQ versus
Junction Temperature TJ (TLS203B0EJV)
Quiescent Current Iq versus
Input Voltage VI (TLS203B0EJV33)
Quiescent Current Iq versus
Input Voltage VI (TLS203B0EJV)
−50 0 50 100
3.24
3.26
3.28
3.3
3.32
3.34
3.36
Tj [°C]
VQ [V]
IQ = 1 mA
−50 0 50 100
1.2
1.205
1.21
1.215
1.22
1.225
1.23
1.235
1.24
Tj [°C]
VQ [V]
IQ = 1 mA
0 2 4 6 8 10
0
100
200
300
400
500
600
700
800
VI [V]
Iq [µA]
VQ,nom = 3.3 V
IQ,nom = 0 mA
VEN = VI
Tj = 25 °C
0 5 10 15 20
0
5
10
15
20
25
30
35
40
VI [V]
Iq [µA]
VQ,nom = 1.22 V
RLoad = 250 kΩ
VEN = VI
Tj = 25 °C
TLS203B0
Electrical Characteristics
Data Sheet 17 Rev. 1.2, 2015-01-12
GND Pin Current IGND versus
Input Voltage VI (TLS203B0EJV33)
GND Pin Current IGND versus
Input Voltage VI (TLS203B0EJV)
GND Pin Current IGND versus
Input Voltage VI (TLS203B0EJV33)
GND Pin Current IGND versus
Input Voltage VI (TLS203B0EJV)
0 2 4 6 8 10
0
200
400
600
800
1000
1200
VI [V]
IGND [µA]
[* for VQ = 3.3 V]
Tj = 25°C
RLoad = 3.3 kΩ / IQ = 1 mA*
RLoad = 330 Ω / IQ = 10 mA*
RLoad = 66 Ω / IQ = 50 mA*
0 2 4 6 8 10
0
50
100
150
200
250
300
350
400
VI [V]
IGND [µA]
[* for VQ = 1.22 V]
Tj = 25°C
RLoad = 1.22 kΩ / IQ = 1 mA*
RLoad = 122 Ω / IQ = 10 mA*
RLoad = 24.4 Ω / IQ = 50 mA*
0 2 4 6 8 10
0
1
2
3
4
5
6
7
8
VI [V]
IGND [mA]
[* for VQ = 3.3 V]
Tj = 25°C
RLoad = 33.0 Ω / IQ = 100 mA*
RLoad = 11.0 Ω / IQ = 300 mA* .
0 2 4 6 8 10
0
1
2
3
4
5
6
7
8
VI [V]
IGND [mA]
[* for VQ = 1.22 V]
Tj = 25°C
RLoad = 12.2 Ω / IQ = 100 mA*
RLoad = 4.07 Ω / IQ = 300 mA* .
Data Sheet 18 Rev. 1.2, 2015-01-12
TLS203B0
Electrical Characteristics
GND Pin Current IGND versus
Output Current IQ
EN Pin Threshold (On-to-Off) versus
Junction Temperature TJ
EN Pin Threshold (Off-to-On) versus
Junction temperature TJ
EN Pin Input Current (On-to-Off) versus
EN Pin Voltage VEN
0 50 100 150 200 250 300
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IQ [mA]
IGND [mA]
VI = VQ,nom + 1 V
Tj = 25 ° C
−50 0 50 100
0
0.2
0.4
0.6
0.8
1
1.2
Tj [°C]
VEN,th [V]
1 mA
300 mA
−50 0 50 100
0
0.2
0.4
0.6
0.8
1
1.2
Tj [°C]
VEN,th [V]
1 mA
300 mA
0 5 10 15 20
0
0.2
0.4
0.6
0.8
1
1.2
1.4
VEN [V]
IEN [µA]
Tj = 25 °C
VI = 20 V
TLS203B0
Electrical Characteristics
Data Sheet 19 Rev. 1.2, 2015-01-12
EN Pin Current versus
Junction Temperature TJ
Current Limit versus
Input Voltage VI
Current Limit versus
Junction Temperature TJ
Reverse Output Current versus
Output Voltage VQ
−50 0 50 100
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Tj [°C]
IEN [µA]
VEN = 20 V
0 1 2 3 4 5 6 7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VI [V]
IQ,max [A]
VQ = 0 V
Tj = 25 ° C
−50 0 50 100
0
0.2
0.4
0.6
0.8
1
1.2
Tj [°C]
IQ,max [A]
VI = 7 V
VQ = 0 V
0 2 4 6 8 10
0
10
20
30
40
50
60
70
80
90
VQ [V]
IQ,rev [µA]
VI = 0 V
Tj = 25 °C
VQ.nom = 1.22 V (ADJ)
VQ.nom = 3.3 V (V33)
Data Sheet 20 Rev. 1.2, 2015-01-12
TLS203B0
Electrical Characteristics
Reverse Output Current versus
Junction Temperature TJ
Minimum Input Voltage 1) versus
Junction Temperature TJ
1) VI,min is referred here as the minimum input voltage for which the requested current is provided and VQ reaches 1 V.
Load Regulation versus
Junction Temperature TJ
Adjust Pin Bias Current versus
Junction Temperature TJ
−50 0 50 100
0
2
4
6
8
10
12
14
16
18
20
Tj [°C]
IQ,rev [µA]
VI = 0 V
VQ.nom = 1.22 V (ADJ)
VQ.nom = 3.3 V (V33)
−50 0 50 100
0
0.5
1
1.5
2
2.5
Tj [°C]
VI,min [V]
IQ = 1 mA
IQ = 300 mA
−50 0 50 100
−25
−20
−15
−10
−5
0
5
Tj [°C]
ΔVQ [mV]
ΔIQ = 1 mA to 300 mA
V33: VI = 4.3 V VQ.nom = 3.3 V
ADJ: V
I = 2.3 V VQ.nom = 1.22 V
−50 0 50 100
0
20
40
60
80
100
120
140
Tj [°C]
IADJ [nA]
TLS203B0
Electrical Characteristics
Data Sheet 21 Rev. 1.2, 2015-01-12
ESR Stability versus
Output Current IQ (for CQ=3.3µF)
ESR(CQ) with CBYP =10nF versus
Output Capacitance CQ
Input Ripple Rejection PSRR versus
Frequency f
Input Ripple Rejection PSRR versus
Junction Temperature TJ
ESRmax CByp = 0 nF
ESRmin CByp = 0 nF
ESRmax CByp = 10 nF
ESRmin CByp = 10 nF
0 50 100 150 200 250 300
10−1
100
101
IQ [mA]
ESR(CQ) [Ω]
CQ = 3.3 µF
(0.06 Ω is measurement limit)
2 3 4 5 6 7
0
0.5
1
1.5
2
2.5
3
CQ [µF]
ESR(CQ) [Ω]
stable region above blue line
CByp = 10 nF
measurement limit
IQ = 300mA; CBYP = 0 nF
IQ = 300mA; CBYP = 10nF
IQ = 50mA; CBYP = 0 nF
IQ = 50mA; CBYP = 10nF
10 100 1k 10k 100k
0
10
20
30
40
50
60
70
80
90
100
f [Hz]
PSRR [dB]
VI = VQnom + 1.5 V
Vripple = 0.5 Vpp
CQ = 10 µF
−50 0 50 100
56
58
60
62
64
66
68
70
72
Tj [°C]
PSRR [dB]
VI = VQnom + 1.5 V
Vripple = 0.5 Vpp
fripple = 120 Hz
CQ = 10 µF
IQ = 300mA; CBYP = 0 nF
IQ = 300mA; CBYP = 10nF
Data Sheet 22 Rev. 1.2, 2015-01-12
TLS203B0
Electrical Characteristics
Output Noise Spectral Density (ADJ) versus
Frequency f (CQ = 10 µF, IQ = 50 mA)
Output Noise Spectral Density (ADJ) versus
Frequency f (CQ = 22 µF, IQ = 50 mA)
Output Noise Spectral Density (3.3V) versus
Frequency f (CQ = 10 µF, IQ = 50 mA)
Output Noise Spectral Density (3.3V) versus
Frequency f (CQ = 22 µF, IQ = 50 mA)
CByp = 0 nF; ESR(CQ)=0
CByp = 10 nF; ESR(CQ)=0
CByp = 10 nF; ESR(CQ)=250mΩ
101102103104105
10−2
10−1
100
101
f [Hz]
Output Spectral Noise Density μV/√Hz
CQ = 10 µF
IQ = 50 mA
CByp = 0 nF; ESR(CQ)=0
CByp = 10 nF; ESR(CQ)=0
CByp = 10 nF; ESR(CQ)=250mΩ
101102103104105
10−2
10−1
100
101
f [Hz]
Output Spectral Noise Density μV/√Hz
CQ = 22 µF
IQ = 50 mA
CByp = 0 nF; ESR(CQ)=0
CByp = 10 nF; ESR(CQ)=0
CByp = 10 nF; ESR(CQ)=250mΩ
101102103104105
10−2
10−1
100
101
f [Hz]
Output Spectral Noise Density μV/√Hz
CQ = 10 µF
IQ = 50 mA
CByp = 0 nF; ESR(CQ)=0
CByp = 10 nF; ESR(CQ)=0
CByp = 10 nF; ESR(CQ)=250mΩ
101102103104105
10−2
10−1
100
101
f [Hz]
Output Spectral Noise Density μV/√Hz
CQ = 22 µF
IQ = 50 mA
TLS203B0
Electrical Characteristics
Data Sheet 23 Rev. 1.2, 2015-01-12
Transient Response CBYP= 0 nF (TLS203B0EJV33) Transient Response CBYP= 10 nF (TLS203B0EJV33)
-0,3
-0,2
-0,1
0
0,1
0,2
0,3
0 100 200 300 400 500 600 700 800 900 1000
V
Q
Deviation / [V]
Time (μs)
C
Q
= 10 µF
C
BYP
= 0 nF
V
I
= 6 V
0
50
100
150
200
250
300
350
400
0 100 200 300 400 500 600 700 800 900 1000
Load Step / [mA]
Time (μs)
I
Q
: 100 to 300 mA
-0,15
-0,1
-0,05
0
0,05
0,1
0,15
0 20406080100120140160180200
VQDeviation / [V]
Time / [μs]
CQ= 10 µF
CBYP = 10 nF
VI= 6V
0
50
100
150
200
250
300
350
400
0 20 40 60 80 100 120 140 160 180 200
Load Step / [mA]
Time / [μs]
I
Q
: 100 to 300 mA
Data Sheet 24 Rev. 1.2, 2015-01-12
TLS203B0
Application Information
6 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 5 Typical Application Circuit TLS203B0 (fixed voltage version)
Figure 6 Typical Application Circuit TLS203B0 (adjustable version)
Note: This is a very simplified example of an application circuit. The function must be verified in the real
application. 1) 2)
1) Please note that in case a non-negligible inductance at the input pin I is present, e.g. due to long cables, traces, parasitics,
etc, a bigger input capacitor CI may be required to filter its influence. As a rule of thumb if the I pin is more than six inches
away from the main input filter capacitor an input capacitor value of CI= 10 µF is recommended.
2) For specific needs a small optional resistor may be placed in series to very low ESR output capacitors CQ for enhanced
noise performance (for details please see “Bypass Capacitance and Low Noise Performance” on Page 25).
RLoad
CBYP CQ
CI
I
GND
Q
EN
SENSE
BYP
TLS203B0
VI
GND
10nF 10µF
1µF
VQ
Calculation of V
Q
: V
Q
= 1.22V x (1 + R
2
/ R
1
) + (I
ADJ
x R
2
)
RLoad
CBYP
CI
I
GND
Q
EN
ADJ
BYP
TLS203B0 (ADJ)
VI
GND
10nF 10µF
1µF CQ
VQ
R2
R1
TLS203B0
Application Information
Data Sheet 25 Rev. 1.2, 2015-01-12
The TLS203B0 is a 300 mA low dropout regulator with very low quiescent current and Enable-functionality. The
device is capable of supplying 300 mA at a dropout voltage of 270 mV. Output voltage noise numbers down to
24 µVRMS can be achieved over a 10 Hz to 100 kHz bandwidth with the addition of a 10 nF reference bypass
capacitor. The usage of a reference bypass capacitor will additionally improve transient response of the regulator,
lowering the settling time for transient load conditions. The device has a low operating quiescent current of typical
30 µA that drops to less than 1 µA in shutdown (EN-pin pulled to low level). The device also incorporates several
protection features which makes it ideal for battery-powered systems. It is protected against both reverse input
and reverse output voltages.
6.1 Adjustable Operation
The adjustable version of the TLS203B0 has an output voltage range of 1.22 V to 20 V - VDR. The output voltage
is set by the ratio of two external resistors, as it can be seen in Figure 6. The device controls the output to maintain
the ADJ pin at 1.22 V referenced to ground. The current in R1 is then equal 1.22 V / R1 and the current in R2
equals the current in R1 plus the ADJ pin bias current. The ADJ pin bias current, which is ~60 nA @ 25 °C, flows
through R2 into the ADJ pin. The value of R1 should be not greater than 250 k in order to minimize errors in the
output voltage caused by the ADJ pin bias current. Note that when the device is shutdown (i.e. low level applied
to EN pin) the output is turned off and consequently the divider current will be zero. For details of the ADJ Pin Bias
current see also the corresponding typical performance graph “Adjust Pin Bias Current versus Junction
Temperature TJ” on Page 20.
6.2 Kelvin Sense Connection
For the fixed voltage version of the TLS203B0 the SENSE pin is the input to the error amplifier. An optimum
regulation will be obtained at the point where the SENSE pin is connected to the output pin Q of the regulator. In
critical applications however small voltage drops may be caused by the resistance Rp of the PC-traces and thus
may lower the resulting voltage at the load. This effect may be eliminated by connecting the SENSE pin to the
output as close as possible at the load (see Figure 7). Please note that the voltage drop across the external PC
trace will add up to the dropout voltage of the regulator.
Figure 7 Kelvin Sense Connection
6.3 Bypass Capacitance and Low Noise Performance
The TLS203B0 regulator may be used in combination with a bypass capacitor connecting the output pin Q to the
BYP pin in order to minimize output voltage noise 1). This capacitor will bypass the reference of the regulator,
1) a good quality low leakage capacitor is recommended.
CI
I
GND
Q
EN
SENSE
BYP
TLS203B0
VIRLoad
CQ
RP
RP
Data Sheet 26 Rev. 1.2, 2015-01-12
TLS203B0
Application Information
providing a low frequency noise pole. The noise pole provided by such a bypass capacitor will lower the output
voltage noise in the considered bandwidth. For a given output voltage actual numbers of the output voltage noise
will - next to the bypass capacitor itself - be dependent on the capacitance of the applied output capacitor CQ and
its ESR: In case of the TLS203B0EJV / TLS203B0LDV applied with unity gain (i.e. VQ= 1.22V) the usage of a
bypass capacitor of 10 nF in combination with a (low ESR) ceramic CQ of 10 µF will result in output voltage noise
numbers of typical 41 µVRMS. This Output Noise level can be reduced to typical 28 µVRMS under the same
conditions by adding a small resistor of ~250 m in series to the 10 µF ceramic output capacitor acting as
additional ESR. A reduction of the output voltage noise can also be achieved by increasing capacitance of the
output capacitor. For CQ= 22 µF (ceramic low ESR) the output voltage noise will be typically around 29 µVRMS and
can again be further lowered to 24 µVRMS by adding a small resistance of ~250 m in series to CQ. In case of the
fix voltage version TLS203B0EJV33 / TLS203B0LDV33 the output voltage noise for the described cases vary from
45 µVRMS down to 30 µVRMS. For further details please also see “Output Voltage Noise 10)” on Page 12,, of the
Electrical Characteristics. Please note that next to reducing the output voltage noise level the usage of a bypass
capacitor has the additional benefit of improving transient response which will be also explained in the next
chapter. However one needs to take into consideration that on the other hand the regulator start-up time is
proportional to the size of the bypass capacitor and slows down to values around 15 ms when using a 10 nF
bypass capacitor in combination with a 10 µF CQ output capacitor.
6.4 Output Capacitance and Transient Response
The TLS203B0 is designed to be stable with a wide range of output capacitors. The ESR of the output capacitor
is an essential parameter with regard to stability, most notably with small capacitors. A minimum output capacitor
of 3.3 µF with an ESR of 3 or less is recommended to prevent oscillations. Like in general for LDO’s the output
transient response of the TLS203B0 will be a function of the output capacitance. Larger values of output
capacitance decrease peak deviations and thus improve transient response for larger load current changes.
Bypass capacitors, used to decouple individual components powered by the TLS203B0 will increase the effective
output capacitor value. Please note that with the usage of bypass capacitors for low noise operation either larger
values of output capacitors may be needed or a minimum ESR requirement of CQ may have to be considered (see
also typical performance graph “ESR(CQ) with CBYP = 10 nF versus Output Capacitance CQ” on Page 21 as
example). In conjunction with the usage of a 10 nF bypass capacitor an output capacitor CQ 6.8 µF is
recommended. The benefit of a bypass capacitor to the transient response performance is impressive and
illustrated as one example in Figure 8 where the transient response of the TLS203B0EJV33 to one and the same
load step from 100 mA to 300 mA is shown with and without a 10 nF bypass capacitor: for the given configuration
of CQ = 10 µF with no bypass capacitor the load step will settle in the range of less than 100 µs while for
CQ= 10 µF in conjunction with a 10 nF bypass capacitor the same load step will settle in the range of 10 µs. Due
to the shorter reaction time of the regulator by adding the bypass capacitor not only the settling time improves but
also output voltage deviations due to load steps are sharply reduced.
Figure 8 Influence of CBYP: example of transient response to one and the same load step with and
without CBYP of 10 nF (IQ: 100 mA to 300 mA, TLS203B0EJV33)
-0,3
-0,2
-0,1
0
0,1
0,2
0,3
0 100 200 300 400 500 600 700 800 900 1000
V
Q
Deviation / [V]
Time (μs)
C_BYP = 0nF
C_BYP = 10nF
C
Q
= 10 µF
C
BYP
= 0 vs 10nF
V
I
= 6 V
TLS203B0
Application Information
Data Sheet 27 Rev. 1.2, 2015-01-12
6.5 Protection Features
The TLS203B0 regulators incorporate several protection features which make them ideal for use in battery-
powered circuits. In addition to normal protection features associated with monolithic regulators like current limiting
and thermal limiting the device is protected against reverse input voltage, reverse output voltage and reverse
voltages from output to input.
Current limit protection and thermal overload protection are intended to protect the device against current overload
conditions at the output of the device. For normal operation the junction temperature must not exceed 125 °C.
The input of the device will withstand reverse voltages of 20 V. Current flowing into the device will be limited to
less than 1 mA (typically less than 100 µA) and no negative voltage will appear at the output. The device will
protect both itself and the load. This provides protection against batteries being plugged backwards.
The output of the TLS203B0 can be pulled below ground without damaging the device. If the input is left open-
circuit or grounded, the output can be pulled below ground by 20 V. Under such conditions the output of the device
by itself behaves like an open circuit with practically no current flowing out of the pin 1). In more application relevant
cases however where the output is either connected to the SENSE pin (fix voltage variant) or tied either via an
external voltage divider or directly to the ADJ pin (adjustable variant) a small current will be present from this origin.
In the case of the fixed voltage version this current will typically be below 100 µA while for the adjustable version
it depends on the magnitude of the top resistor of the external voltage divider 2). If the input is powered by a voltage
source the output will source the short circuit current of the device and will protect itself by thermal limiting. In this
case grounding the EN pin will turn off the device and stop the output from sourcing the short-circuit current.
The ADJ pin of the adjustable device can be pulled above or below ground by as much as 7 V without damaging
the device. If the input is grounded or left open-circuit, the ADJ pin will act inside this voltage range like a large
resistor (typically 100 k) when being pulled above ground and like a resistor (typically 5 k) in series with a diode
when being pulled below ground. In situations where the ADJ pin is at risk of being pulled outside its absolute
maximum ratings ±7 V the ADJ pin current must be limited to 1 mA (e.g. in cases where the ADJ pin is connected
to a resistor divider that would pull the ADJ pin above its 7 V clamp voltage). Let’s consider for example the case
where a resistor divider is used to provide a 1.5 V output from the 1.22 V reference and the output is forced to
20 V. The top resistor of the resistor divider must then be chosen to limit the current into the ADJ pin to 1 mA or
less when the ADJ pin is at 7 V. The 13 V difference between output and ADJ pin divided by the 1 mA maximum
current into the ADJ pin requires a minimum resistor value of 13 k.
In circuits where a backup battery is required, several different input/output conditions can occur. The output
voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left
open-circuit. Current flow back into the output will follow the curve as shown in Figure 9 below.
1) typically < 1 µA for the mentioned conditions, VQ being pulled below ground with other pins either grounded or open.
2) In case there is no external voltage divider applied i.e. the ADJ pin is directly connected to the output Q and the output is
pulled below ground by 20 V the current flowing out of the ADJ pin will be typically ~ 4 mA. Please ensure in such cases
that the absolute maximum ratings of the ADJ pin are respected.
Data Sheet 28 Rev. 1.2, 2015-01-12
TLS203B0
Application Information
Figure 9 Reverse Output Current
0 2 4 6 8 10
0
10
20
30
40
50
60
70
80
90
V
Q
[V]
I
Q,rev
[µA]
V
I
= 0 V
T
j
= 25 °C
V
Q.nom
= 1.22 V (ADJ)
V
Q.nom
= 3.3 V (V33)
TLS203B0
Package Outlines
Data Sheet 29 Rev. 1.2, 2015-01-12
7 Package Outlines
Figure 10 PG-DSO-8 Exposed Pad package outlines
Figure 11 PG-TSON-10 Package Outlines
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
PG-DSO-8-27-PO V01
14
85
8
14
5
8x
0.41
±0.092)
M
0.2 DC A-B
1.27 C
Stand Off
+0
-0.1
0.1
(1.45)
1.7 MAX.
0.08
Seating Plane
C
A
B
4.9
±0.11)
A-BC0.1 2x
3
)
JEDEC reference MS-012 variation BA
1) Does not include plastic or metal protrusion of 0.15 max. per side
2) Dambar protrusion shall be maximum 0.1 mm total in excess of lead width
Bottom View
±0.2
3
±0.2
2.65
0.2
±0.2
D6
M
D 8x
0.64
±0.25
3.9
±0.11)
0.1
0.35 x 45˚
CD2x
+0.06
0.19
8
˚
MAX.
Index Marking
Pin 1 Marking Pin 1 Marking
PG-TSON-10-2-PO V02
±0.1
0.2
±0.1
0.25
±0.1
0.55
0.96
±0.1
2.58
±0.1
0
+0.05
0.1
±0.1
0.36
±0.1
0.53
±0.1
±0.1
0.25
0.5
±0.1
3.3
±0.1
3.3
±0.1
1
±0.1
0.71
±0.1
1.63
±0.1
1.48
±0.1
Z
0.05
0.07 MIN.
Z (4:1)
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
Data Sheet 30 Rev. 1.2, 2015-01-12
TLS203B0
Revision History
8 Revision History
Revision Date Changes
1.2 2015-01-12 Data Sheet - Revision 1.2:
• PG - TSON - 10 package variants added: Product Overview, Pin Configura-
tion, Thermal Resistance, etc - wording and description added or updated
accordingly.
• Editorial changes.
1.1 2014-06-03 Data Sheet - Revision 1.1:
• Order of footnotes in Table 3 “Thermal Resistance” on Page 9 corrected.
• Application Information Chapter 6.5 updated: Clarification and correction of
wording. Typical values updated and footnotes added.
• Editorial changes.
1.0 2014-02-28 Data Sheet - Initial Release
Edition 2015-01-12
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
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