SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 D D D D D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Bidirectional Interface Between GTL+ Signal Levels and LVTTL Logic Levels Equivalent to '16245 Function LVTTL Interfaces Are 5-V Tolerant High-Drive GTL+ Outputs (100 mA) LVTTL Outputs (-24 mA/24 mA) Variable Edge-Rate Control (ERC) Input Selects GTL+ Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion Bus Hold on A-Port Data Inputs Distributed VCC and GND-Pin Configuration Minimizes High-Speed Switching Noise Package Options Include Plastic Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV), and Shrink Small-Outline (DL) Packages 1DIR 1A1 1A2 GND 1A3 1A4 VCC GND 1A5 1A6 GND 1A7 1A8 GND ERC 2A1 2A2 GND 2A3 2A4 GND VCC 2A5 2A6 GND 2A7 2A8 2DIR description The SN74GTLPH1645 is a high-drive 16-bit bus transceiver that provides LVTTL-to-GTL+ and GTL+-to-LVTTL signal-level translation. It is partitioned as two 8-bit transceivers and is equivalent to the '16245 function. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL+ signal levels. High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output edge control (OEC). Improved GTLP OEC circuits minimize bus settling time and have been designed and tested using several backplane models. The high drive is suitable for driving double-terminated low-impedance backplanes using incident-wave switching. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 1OE 1B1 1B2 GND 1B3 1B4 VCC GND 1B5 1B6 GND 1B7 1B8 BIAS VCC VREF 2B1 2B2 GND 2B3 2B4 GND VCC 2B5 2B6 GND 2B7 2B8 2OE PRODUCT PREVIEW D GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The AC specification of the SN74GTLPH1645 is given only at the preferred higher noise margin GTL+, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V and VREF = 1 V) signal levels. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OEC is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 description (continued) Normally, the B port operates at GTL or GTL+ levels, while the A port and control inputs are compatible with LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port. This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability. High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load. PRODUCT PREVIEW Active bus-hold circuitry holds unused or undriven LVTTL inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74GTLPH1645 is characterized for operation from -40C to 85C. functional description The SN74GTLPH1645 is a high-drive (100 mA) 16-bit bus transceiver providing standard '16245 functionality, and is designed for asynchronous communication between data buses. The device transmits data from the A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR) input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting. For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When OE is high, the outputs are in the high-impedance state. Data flow for B to A is similar to that for A to B, but OE is low and DIR is low. Function Tables OUTPUT CONTROL INPUTS OUTPUT MODE L B data to A port Transparent L H A data to B port Transparent H X Z Isolation OE DIR L B-PORT EDGE-RATE CONTROL (ERC) INPUT ERC 2 LOGIC LEVEL NOMINAL VOLTAGE OUTPUT B-PORT EDGE RATE L GND Slow H VCC Fast POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 logic diagram (positive logic) 1 1DIR 56 ERC 1A1 15 1OE 55 2 1B1 42 VREF To Seven Other Channels 28 2DIR PRODUCT PREVIEW 29 2OE 2A1 41 16 2B1 To Seven Other Channels POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 PRODUCT PREVIEW absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, VCC and BIAS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Input voltage range, VI (see Note 1): A-port and control inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V B port, ERC, and VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 7 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Voltage range applied to any output in the high or low state, VO (see Note 1): A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 4.6 V Current into any output in the low state, IO: A port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA Current into any A-port output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA Continuous current through each VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -50 mA Package thermal impedance, JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 recommended operating conditions (see Notes 4 through 6) Supply voltage VTT Termination voltage VREF Supply voltage VI Input voltage VIH High-level input voltage MIN NOM MAX UNIT 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 GTL+ 1.35 1.5 1.65 GTL 0.74 0.8 0.87 GTL+ 0.87 1 1.1 B port VTT VCC Except B port B port ERC Except B port and ERC VREF+0.05 VCC-0.6 Low-level input voltage ERC Except B port and ERC IIK IOH Input clamp current IOL Low level output current Low-level High-level output current A port V V V VCC 2 B port VIL V GND VREF-0.05 0.6 V 0.8 -18 mA -24 mA A port 24 B port 100 mA TA Operating free-air temperature -40 85 C NOTES: 4. All unused control and B-port inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 5. Normal connection sequence is GND first, BIAS VCC = 3.3 V second, and VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. However, if the B-port I/O precharge is not required, the acceptable connection sequence is GND first and VCC = 3.3 V, BIAS VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. When VCC is connected, the BIAS VCC circuitry is disabled. 6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings. Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 PRODUCT PREVIEW VCC, BIAS VCC SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 electrical characteristics over recommended operating free-air temperature range for GTL+ (unless otherwise noted) PARAMETER VIK VOH A port TEST CONDITIONS VCC = 3.15 V, VCC = 3.15 V to 3.45 V, II = -18 mA IOH = -100 A VCC = 3 3.15 15 V IOH = -12 mA IOH = -24 mA VCC = 3.15 V to 3.45 V, A port VCC = 3 3.15 15 V VOL B port PRODUCT PREVIEW II VCC = 3.45 V, A-port and control inputs VCC = 3 3.45 45 V A port IBHLO# IBHHO|| A port ICC A or B port A port A port Ciio TYP IOL = 100 A IOL = 12 mA 0.2 IOL = 24 mA IOL = 10 mA 0.5 0.4 0.2 VI = 2 V VI = 0 to VCC Control inputs A port VI = 3.15 V or 0 VO = 3.15 V or 0 B port VO = 1.5 V or 0 V 0.4 0.55 10 10 A 20 VI = 5.5 V VI = 0.8 V VCC = 3.45 V, IO = 0, VI (A-port or control input) = VCC or GND VI (B port) = VTT or GND V V VI = 0 to 1.5 V VI = 0 or VCC VCC = 3.45 V, VCC = 3.45 V, UNIT -1.2 2 IOL = 64 mA IOL = 100 mA VCC = 3.15 V, VCC = 3.15 V, MAX VCC-0.2 2.4 A 75 A -75 VI = 0 to VCC Outputs high 500 A -500 A 40 Outputs low 40 Outputs disabled 40 VCC = 3.45 V, One A-port or control input at VCC - 0.6 V, Other A-port or control inputs at VCC or GND ICCk Ci VCC = 3.15 V B port IBHL IBHH MIN 1.5 mA mA pF pF All typical values are at VCC = 3.3 V, TA = 25C. For I/O ports, the parameter II includes the off-state output leakage current. The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and then raising it to VILmax. The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and then lowering it to VIHmin. # An external driver must source at least IBHLO to switch this node from low to high. || An external driver must sink at least IBHHO to switch this node from high to low. k This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. live-insertion specifications for A port over recommended operating free-air temperature range PARAMETER 6 TEST CONDITIONS MIN MAX UNIT Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, BIAS VCC = 0, VI or VO = 0 to 5.5 V OE = 0 100 A VO = 0.5 V to 3 V, 100 A IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = 0 100 A POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 live-insertion specifications for B port over recommended operating free-air temperature range PARAMETER TEST CONDITIONS Ioff IOZPU VCC = 0, VCC = 0 to 1.5 V, IOZPD VCC = 1.5 V to 0, VCC = 0 to 3.15 V ICC (BIAS VCC) VO IO BIAS VCC = 0, VO = 0.5 V to 1.5 V, VO = 0.5 V to 1.5 V, VCC = 3.15 V to 3.45 V VCC = 0, VCC = 0, BIAS VCC = 3 3.15 15 V to 3 3.45 45 V V, MIN VI or VO = 0 to 1.5 V OE = 0 OE = 0 VO (B port) = 0 to 1.5 15V BIAS VCC = 3.3 V 0.95 BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V MAX UNIT 100 A 100 A 100 A 5 mA 10 A 1.05 V A -1 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd d A B ten tdis OE B Slow ns ten tdis OE B Fast ns Slow Fast tr Rise time,, B outputs (0.6 V to 1.3 V) Slow tf Fall time,, B outputs (1.3 V to 0.6 V) Slow tpd ten tdis Fast Fast MIN TYP MAX UNIT ns PRODUCT PREVIEW EDGE RATE ns ns B A ns OE A ns Slow (ERC = GND) and Fast (ERC = VCC) All typical values are at VCC = 3.3 V, TA = 25C. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 PARAMETER MEASUREMENT INFORMATION 1.5 V 6V 500 From Output Under Test S1 Open 12.5 From Output Under Test CL = 30 pF (see Note A) GND CL = 50 pF (see Note A) TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 S1 Open 6V GND LOAD CIRCUIT FOR A OUTPUTS Test Point LOAD CIRCUIT FOR B OUTPUTS 3V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1V Output 1V PRODUCT PREVIEW VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (A port to B port) 1V 0V tPLH 1.5 V 1.5 V 0V Output Waveform 1 S1 at 6 V (see Note B) tPHL tPLZ 3V 1.5 V VOL + 0.3 V VOL tPHZ tPZH VOH Output 1.5 V tPZL 1.5 V 1V Input 3V Output Control 1.5 V VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (B port to A port) 1.5 V VOH VOH - 0.3 V 0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES (A port) NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , slew rate 1 V/ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SN74GTLPH1645 16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER SCES290 - OCTOBER 1999 DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS This data sheet is specified for and tested to the lump load shown in Figure 1. However, the designer probably uses this GTLP device in a distributed load like that shown in Figure 2, in which actual B-port backplane switching characteristics are different. Therefore, the device is modeled as shown in Figure 3, which very closely matches the results obtained using Figure 2. Switching characteristics based on Figure 3 more closely match actual backplane design requirements. RTT .25" .875" .625" .875" .625" .625" RTT VTT VTT .25" .625" 1.5 V 1" Conn. 1" Conn. Conn. 1" Rcvr 1" Rcvr From Output Under Test Rcvr LL = 21 nH Test Point CL = 13 pF Drvr Slot 1 14 Slot 2 Slot 15 Slot 16 Figure 2. Test Backplane Model Figure 3. Distributed-Load Circuit for B Outputs switching characteristics over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 3) PARAMETER FROM (INPUT) TO (OUTPUT) tpd d A B ten tdis OE B Slow ns ten tdis OE B Fast ns EDGE RATE Slow Fast tr Rise time,, B outputs (0.6 V to 1.3 V) Slow tf Fall time, B outputs (1.3 V to 0.6 V) Slow Fast Fast MIN TYP MAX UNIT ns ns ns Slow (ERC = GND) and Fast (ERC = VCC) All typical values are at VCC = 3.3 V, TA = 25C. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 PRODUCT PREVIEW Conn. IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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