SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
D
Equivalent to ’16245 Function
D
LVTTL Interfaces Are 5-V Tolerant
D
High-Drive GTL+ Outputs (100 mA)
D
LVTTL Outputs (–24 mA/24 mA)
D
Variable Edge-Rate Control (ERC) Input
Selects GTL+ Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity
D
Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
D
Bus Hold on A-Port Data Inputs
D
Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and Shrink
Small-Outline (DL) Packages
description
The SN74GTLPH1645 is a high-drive 16-bit bus
transceiver that provides LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. It is
partitioned as two 8-bit transceivers and is
equivalent to the ’16245 function. The device
provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane
operating at GTL+ signal levels. High-speed
(about two times faster than standard LVTTL or
TTL) backplane operation is a direct result of
GTLP’s reduced output swing (<1 V), reduced
input threshold levels, improved differential input,
and output edge control (OEC). Improved GTLP
OEC circuits minimize bus settling time and have
been designed and tested using several
backplane models. The high drive is suitable for
driving double-terminated low-impedance
backplanes using incident-wave switching.
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLPH1645 is given only at the preferred higher noise margin GTL+, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V
and VREF = 1 V) signal levels.
PRODUCT PREVIEW
Copyright 1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC is a trademark of Texas Instruments Incorporated.
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
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1DIR
1A1
1A2
GND
1A3
1A4
VCC
GND
1A5
1A6
GND
1A7
1A8
GND
ERC
2A1
2A2
GND
2A3
2A4
GND
VCC
2A5
2A6
GND
2A7
2A8
2DIR
1OE
1B1
1B2
GND
1B3
1B4
VCC
GND
1B5
1B6
GND
1B7
1B8
BIAS VCC
VREF
2B1
2B2
GND
2B3
2B4
GND
VCC
2B5
2B6
GND
2B7
2B8
2OE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Normally, the B port operates at GTL or GTL+ levels, while the A port and control inputs are compatible with
LVTTL logic levels and are 5-V tolerant. VREF is the reference input voltage for the B port.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS V CC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between GND and VCC adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
Active bus-hold circuitry holds unused or undriven L VTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
The SN74GTLPH1645 is characterized for operation from –40°C to 85°C.
functional description
The SN74GTLPH1645 is a high-drive (100 mA) 16-bit bus transceiver providing standard ’16245 functionality,
and is designed for asynchronous communication between data buses. The device transmits data from the
A port to the B port or from the B port to the A port, depending on the logic level at the direction-control (DIR)
input. OE can be used to disable the device so the buses are effectively isolated. Data polarity is noninverting.
For A-to-B data flow, when OE is low and DIR is high, the B outputs take on the logic value of the A inputs. When
OE is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that for A to B, but OE is low and DIR is low.
Function Tables
OUTPUT CONTROL
INPUTS
OUTPUT
MODE
OE DIR
OUTPUT
MODE
L L B data to A port T ransparent
LH A data to B port T ransparent
H X Z Isolation
B-PORT EDGE-RATE CONTROL (ERC)
INPUT ERC OUTPUT
LOGIC
LEVEL NOMINAL
VOLTAGE B-PORT
EDGE RATE
L GND Slow
HVCC Fast
PRODUCT PREVIEW
SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1DIR
1OE
1A1 1B1
1
2
56
55
VREF
42
2DIR
2OE
2A1 2B1
To Seven Other Channels
28
16
29
41
ERC 15
To Seven Other Channels
PRODUCT PREVIEW
SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC and BIAS VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): A-port and control inputs –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
B port, ERC, and VREF –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1):A port –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Note 1):A port –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any A-port output in the high state, IO (see Note 2) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 48°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 56°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
PRODUCT PREVIEW
SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Notes 4 through 6)
MIN NOM MAX UNIT
VCC,
BIAS VCC Supply voltage 3.15 3.3 3.45 V
VTT
Termination voltage
GTL 1.14 1.2 1.26
V
V
TT
Termination
v
oltage
GTL+ 1.35 1.5 1.65
V
VREF
Su
pp
ly voltage
GTL 0.74 0.8 0.87
V
V
REF
S
u
ppl
y v
oltage
GTL+ 0.87 1 1.1
V
VI
In
p
ut voltage
B port VTT
V
V
I
Inp
u
t
v
oltage
Except B port VCC
V
B port VREF+0.05
VIH High-level input voltage ERC VCC–0.6 VCC V
Except B port and ERC 2
B port VREF–0.05
VIL Low-level input voltage ERC GND 0.6 V
Except B port and ERC 0.8
IIK Input clamp current –18 mA
IOH High-level output current A port –24 mA
IOL
Low level out
p
ut current
A port 24
mA
I
OL
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
B port 100
mA
TAOperating free-air temperature –40 85 °C
NOTES: 4. All unused control and B-port inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI
application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
5. Normal connection sequence is GND first, BIAS VCC = 3.3 V second, and VCC = 3.3 V , I/O, control inputs, VTT and VREF (any order)
last. However , if the B-port I/O precharge is not required, the acceptable connection sequence is GND first and VCC = 3.3 V, BIAS
VCC = 3.3 V, I/O, control inputs, VTT and VREF (any order) last. When VCC is connected, the BIAS VCC circuitry is disabled.
6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings.
Similarly, VREF can be adjusted to optimize noise margins, but normally is 2/3 VTT.
PRODUCT PREVIEW
SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range for GTL+
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 3.15 V, II = –18 mA –1.2 V
VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC–0.2
VOH A port
VCC = 3 15 V
IOH = –12 mA 2.4 V
V
CC =
3
.
15
V
IOH = –24 mA 2
VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2
A port
VCC = 3 15 V
IOL = 12 mA 0.4
VOL
V
CC =
3
.
15
V
IOL = 24 mA 0.5
V
V
OL IOL = 10 mA 0.2
V
B port VCC = 3.15 V IOL = 64 mA 0.4
IOL = 100 mA 0.55
‡
B port VCC = 3.45 V, VI = 0 to 1.5 V ±10
II
‡
A-port and
VCC = 3 45 V
VI = 0 or VCC ±10 µA
control inputs
V
CC =
3
.
45
V
VI = 5.5 V ±20
IBHL§A port VCC = 3.15 V, VI = 0.8 V 75 µA
IBHHA port VCC = 3.15 V, VI = 2 V –75 µA
IBHLO#A port VCC = 3.45 V, VI = 0 to VCC 500 µA
IBHHO|| A port VCC = 3.45 V, VI = 0 to VCC –500 µA
VCC
=
3.45 V, IO
=
0,
Outputs high 40
ICC A or B port
VCC
=
3
.
45
V
,
IO
=
0
,
VI (A-port or control input) = VCC or GND Outputs low 40 mA
VI (B port) = VTT or GND Outputs disabled 40
∆ICC
k
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND 1.5 mA
CiControl inputs VI = 3.15 V or 0 pF
Ci
A port VO = 3.15 V or 0 p
F
C
io B port VO = 1.5 V or 0
pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡For I/O ports, the parameter II includes the off-state output leakage current.
§The bus-hold circuit can sink at least the minimum low sustaining current at VILmax. IBHL should be measured after lowering VIN to GND and
then raising it to VILmax.
The bus-hold circuit can source at least the minimum high sustaining current at VIHmin. IBHH should be measured after raising VIN to VCC and
then lowering it to VIHmin.
#An external driver must source at least IBHLO to switch this node from low to high.
|| An external driver must sink at least IBHHO to switch this node from high to low.
k
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
live-insertion specifications for A port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 5.5 V 100 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = 0 ±100 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = 0 ±100 µA
PRODUCT PREVIEW
SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
live-insertion specifications for B port over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
Ioff VCC = 0, BIAS VCC = 0, VI or VO = 0 to 1.5 V 100 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 1.5 V, OE = 0 ±100 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 1.5 V, OE = 0 ±100 µA
VCC = 0 to 3.15 V
BIAS VCC =315Vto345V
VO(B
p
ort)=0to15V
5 mA
CC
CC
VCC = 3.15 V to 3.45 V
BIAS
V
CC =
3
.
15
V
to
3
.
45
V
,
V
O
(B
port)
=
0
to
1
.
5
V
10 µA
VOVCC = 0, BIAS VCC = 3.3 V 0.95 1.05 V
IOVCC = 0, BIAS VCC = 3.15 V to 3.45 V, VO (B port) = 0.6 V –1 µA
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 1)
PARAMETER FROM
(INPUT) TO
(OUTPUT) EDGE RATE†MIN TYP‡MAX UNIT
td
A
B
Slow
ns
t
pd
A
B
Fast
ns
ten
OE
B
Slow
ns
tdis
OE
B
Slo
w
ns
ten
OE
B
Fast
ns
tdis
OE
B
Fast
ns
t
Rise time, B outputs Slow
ns
t
r
,
(0.6 V to 1.3 V) Fast
ns
tf
Fall time, B outputs Slow
ns
t
f
,
(1.3 V to 0.6 V) Fast
ns
tpd B A ns
ten
OE
A
ns
tdis
OE
A
ns
†Slow (ERC = GND) and Fast (ERC = VCC)
‡All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW
SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
S1 Open
GND
500 Ω
500 Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
6 V
GND
tPLH tPHL
Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
Input
3 V
3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A port to B port)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A port)
Output
1.5 V
Test
Point
CL = 30 pF
(see Note A)
From Output
Under Test
12.5 Ω
LOAD CIRCUIT FOR B OUTPUTS
0 V
VOH
VOL
Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to A port)
Output
1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≤ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
tPLH tPHL
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1 V 1 V
1 V 1 V
Figure 1. Load Circuits and Voltage Waveforms
PRODUCT PREVIEW
SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
This data sheet is specified for and tested to the lump load shown in Figure 1. However , the designer probably uses
this GTLP device in a distributed load like that shown in Figure 2, in which actual B-port backplane switching
characteristics are different. Therefore, the device is modeled as shown in Figure 3, which very closely matches the
results obtained using Figure 2. Switching characteristics based on Figure 3 more closely match actual backplane
design requirements.
Drvr
VTT
.25” .875”
.625” .625”
1” 1”
VTT
.625”.625”
1”1”
.875” .25”
RTT
Rcvr Rcvr Rcvr
Figure 2. Test Backplane Model
RTT
Slot 1 Slot 2 Slot 15 Slot 16
Conn. Conn. Conn. Conn.
From Output
Under Test Test
Point
1.5 V
CL = 13 pF
14 Ω
LL = 21 nH
Figure 3. Distributed-Load Circuit for B Outputs
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, VTT = 1.5 V and VREF = 1 V for GTL+ (see Figure 3)
PARAMETER FROM
(INPUT) TO
(OUTPUT) EDGE RATE†MIN TYP‡MAX UNIT
td
A
B
Slow
ns
t
pd
A
B
Fast
ns
ten
OE
B
Slow
ns
tdis
OE
B
Slo
w
ns
ten
OE
B
Fast
ns
tdis
OE
B
Fast
ns
t
Rise time, B outputs Slow
ns
t
r
,
(0.6 V to 1.3 V) Fast
ns
tf
Fall time, B outputs Slow
ns
t
f(1.3 V to 0.6 V) Fast
ns
†Slow (ERC = GND) and Fast (ERC = VCC)
‡All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW
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Copyright 1999, Texas Instruments Incorporated