SN74GTLPH1645
16-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER
SCES290 – OCT OBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Bidirectional Interface Between GTL+
Signal Levels and LVTTL Logic Levels
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Equivalent to ’16245 Function
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LVTTL Interfaces Are 5-V Tolerant
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High-Drive GTL+ Outputs (100 mA)
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LVTTL Outputs (–24 mA/24 mA)
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Variable Edge-Rate Control (ERC) Input
Selects GTL+ Rise and Fall Times for
Optimal Data-Transfer Rate and Signal
Integrity
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Ioff, Power-Up 3-State, and BIAS VCC
Support Live Insertion
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Bus Hold on A-Port Data Inputs
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Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Switching Noise
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and Shrink
Small-Outline (DL) Packages
description
The SN74GTLPH1645 is a high-drive 16-bit bus
transceiver that provides LVTTL-to-GTL+ and
GTL+-to-LVTTL signal-level translation. It is
partitioned as two 8-bit transceivers and is
equivalent to the ’16245 function. The device
provides a high-speed interface between cards
operating at LVTTL logic levels and a backplane
operating at GTL+ signal levels. High-speed
(about two times faster than standard LVTTL or
TTL) backplane operation is a direct result of
GTLP’s reduced output swing (<1 V), reduced
input threshold levels, improved differential input,
and output edge control (OEC). Improved GTLP
OEC circuits minimize bus settling time and have
been designed and tested using several
backplane models. The high drive is suitable for
driving double-terminated low-impedance
backplanes using incident-wave switching.
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.
The AC specification of the SN74GTLPH1645 is given only at the preferred higher noise margin GTL+, but the
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTL+ (VTT = 1.5 V
and VREF = 1 V) signal levels.
PRODUCT PREVIEW
Copyright 1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC is a trademark of Texas Instruments Incorporated.
DGG, DGV, OR DL PACKAGE
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1DIR
1A1
1A2
GND
1A3
1A4
VCC
GND
1A5
1A6
GND
1A7
1A8
GND
ERC
2A1
2A2
GND
2A3
2A4
GND
VCC
2A5
2A6
GND
2A7
2A8
2DIR
1OE
1B1
1B2
GND
1B3
1B4
VCC
GND
1B5
1B6
GND
1B7
1B8
BIAS VCC
VREF
2B1
2B2
GND
2B3
2B4
GND
VCC
2B5
2B6
GND
2B7
2B8
2OE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.