TMP100 TMP101 SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 Digital Temperature Sensor with I2Ct Interface FEATURES DESCRIPTION D DIGITAL OUTPUT: I2C Serial 2-Wire D RESOLUTION: 9- to 12-Bits, User-Selectable D ACCURACY: The TMP100 and TMP101 are two-wire, serial output temperature sensors available in SOT23-6 packages. Requiring no external components, the TMP100 and TMP101 are capable of reading temperatures with a resolution of 0.0625C. D The TMP100 and TMP101 feature SMBus and I2C interface compatibility, with the TMP100 allowing up to eight devices on one bus. The TMP101 offers SMBus alert function with up to three devices per bus. D D 2.0C from -25C to +85C (max) 3.0C from -55C to +125C (max) LOW QUIESCENT CURRENT: 45A, 0.1A Standby WIDE SUPPLY RANGE: 2.7V to 5.5V TINY SOT23-6 PACKAGE The TMP100 and TMP101 are ideal for extended temperature measurement in a variety of communication, computer, consumer, environmental, industrial, and instrumentation applications. APPLICATIONS D POWER-SUPPLY TEMPERATURE MONITORING The TMP100 and TMP101 are specified for operation over a temperature range of -55C to +125C. D COMPUTER PERIPHERAL THERMAL D D D D D D D PROTECTION NOTEBOOK COMPUTERS CELL PHONES BATTERY MANAGEMENT OFFICE MACHINES THERMOSTAT CONTROLS ENVIRONMENTAL MONITORING AND HVAC ELECTROMECHANICAL DEVICE TEMPERATURE Temperature SCL GND ADD1 Temperature 1 2 3 Diode Temp. Sensor Control Logic 6 A/D Converter Serial Interface 5 OSC Config and Temp Register 4 SDA SCL ADD0 GND V+ ALERT TMP100 1 2 3 Diode Temp. Sensor Control Logic 6 A/D Converter Serial Interface 5 OSC Config and Temp Register 4 SDA ADD0 V+ TMP101 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. Copyright 2002-2007, Texas Instruments Incorporated ! ! www.ti.com "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 ABSOLUTE MAXIMUM RATINGS(1) Power Supply, V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5V Input Voltage(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7.5V Operating Temperature Range . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . . . . . -60C to +150C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . . . . +150C ESD Rating, Human Body Model . . . . . . . . . . . . . . . . . . . . . 2000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . 200V (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input voltage rating applies to all TMP100 and TMP101 input This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. voltages. ORDERING INFORMATION(1) PRODUCT PACKAGE-LEAD PACKAGE DESIGNATOR PACKAGE MARKING TMP100 SOT23-6 DBV T100 TMP101 SOT23-6 DBV T101 (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATION Top View SOT23 GND 2 ADD1 3 TMP100 2 SOT23 6 SDA SCL 1 5 ADD0 GND 2 4 V+ ALERT 3 T101 1 T100 SCL Top View TMP101 6 SDA 5 ADD0 4 V+ "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 ELECTRICAL CHARACTERISTICS At TA = -55C to +125C and V+ = 2.7V to 5.5V, unless otherwise noted. TMP100, TMP101 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEMPERATURE INPUT +125 C -25C to +85C 0.5 2.0 C -55C to +125C 1.0 3.0 C Selectable 0.0625 Range -55 Accuracy (temperature error) Resolution C DIGITAL INPUT/OUTPUT Input Logic Levels: VIH VIL 0.7(V+) 6.0 -0.5 0.3(V+) V 1 A V 0V VIN 6V Input Current, IIN V Output Logic Levels: VOL SDA IOL = 3mA 0 0.15 0.4 VOL ALERT IOL = 4mA 0 0.15 0.4 Resolution Conversion Time Conversion Rate Selectable 9 to 12 V Bits 9-Bit 40 75 ms 10-Bit 80 150 ms 11-Bit 160 300 ms 12-Bit 320 600 ms 9-Bit 25 s/s 10-Bit 12 s/s 11-Bit 6 s/s 12-Bit 3 s/s POWER SUPPLY Operating Range Quiescent Current Shutdown Current 2.7 IQ ISD Serial Bus Inactive 45 5.5 V 75 A A Serial Bus Active, SCL Frequency = 400kHz 70 Serial Bus Active, SCL Frequency = 3.4MHz 150 Serial Bus Inactive 0.1 Serial Bus Active, SCL Frequency = 400kHz 20 A Serial Bus Active, SCL Frequency = 3.4MHz 100 A A 1 A TEMPERATURE RANGE Specified Range -55 +125 Storage Range -60 +150 Thermal Resistance qJA SOT23-6 Surface-Mount 200 C C C/W 3 "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 TYPICAL CHARACTERISTICS At TA = +25C and V+ = 5.0V, unless otherwise noted. SHUTDOWN CURRENT vs TEMPERATURE QUIESCENT CURRENT vs TEMPERATURE 70 1.0 0.9 0.8 60 0.7 0.6 ISD (A) I Q (A) V+ = 5V 50 0.5 0.4 0.3 V+ = 2.7V 0.2 40 0.1 0.0 Serial Bus Inactive -0.1 -60 -40 -20 30 -60 -40 -20 0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 Temperature (_ C) Temperature (_ C) CONVERSION TIME vs TEMPERATURE TEMPERATURE ACCURACY vs TEMPERATURE 2.0 400 350 Temperature Error (_C) Conversion Time (ms) 1.5 V+ = 5V 300 V+ = 2.7V 1.0 0.5 0.0 -0.5 -1.0 -1.5 NOTE: 12-bit resolution. -60 -40 -20 0 20 40 60 80 100 NOTE: 12-bit resolution. 3 Typical Units -2.0 -60 -40 -20 0 250 120 140 Temperature (_ C) 20 QUIESCENT CURRENT WITH BUS ACTIVITY vs TEMPERATURE 180 160 125_C 140 25_ C I Q (A) 120 100 125_ C 80 25_C -55_ C 60 40 20 -55_ C FAST MODE Hs MODE 0 10k 100k 1M SCL Frequency (Hz) 4 40 60 Temperature (_ C) 10M 80 100 120 140 "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 APPLICATIONS INFORMATION The TMP100 and TMP101 are digital temperature sensors optimal for thermal management and thermal protection applications. The TMP100 and TMP101 are I2C and SMBus interface-compatible and are specified over a temperature range of -55C to +125C. The TMP100 and TMP101 require no external components for operation except for pull-up resistors on SCL, SDA, and ALERT, although a 0.1F bypass capacitor is recommended, as shown in Figure 1 and Figure 2. V+ To maintain the accuracy in applications requiring air or surface temperature measurement, care should be taken to isolate the package and leads from ambient air temperature. A thermally-conductive adhesive will assist in achieving accurate surface temperature measurement. POINTER REGISTER Figure 3 shows the internal register structure of the TMP100 and TMP101. The 8-bit Pointer Register of the TMP100 and TMP101 is used to address a given data register. The Pointer Register uses the two LSBs to identify which of the data registers should respond to a read or write command. Table 1 identifies the bits of the Pointer Register byte. Table 2 describes the pointer address of the registers available in the TMP100 and TMP101. Power-up Reset value of P1/P0 is 00. 0.1F 4 To I2C Controller SCL 1 SDA 6 3 ALERT (Output) 5 ADD0 (Input) Pointer Register TMP101 Temperature Register 2 NOTE: (1) SCL, SDA and ALERT require pull-up resistors for I2C bus applications. SCL Configuration Register I/O Control Interface GND Figure 1. Typical Connections of the TMP101 TLOW Register V+ THIGH Register 0.1F 4 To I 2C Controller SCL 1 SDA 6 SDA 3 ADD1 (Input) 5 ADD0 (Input) Figure 3. Internal Register Structure of the TMP100 and TMP101 Table 1. Pointer Register Type TMP100 2 NOTE: (1) SCL and SDA require pull-up resistors for I2C bus applications. GND Figure 2. Typical Connections of the TMP100 The die flag of the lead frame is connected to pin 2. The sensing device of the TMP100 and TMP101 is the chip itself. Thermal paths run through the package leads as well as the plastic package. The lower thermal resistance of metal causes the leads to provide the primary thermal path. The GND pin of the TMP100 or TMP101 is directly connected to the metal lead frame, and is the best choice for thermal input. P7 P6 P5 P4 P3 P2 0 0 0 0 0 0 P1 P0 Register Bits Table 2. Pointer Addresses of the TMP100 and TMP101 Registers P1 P0 0 0 1 1 0 1 0 1 REGISTER Temperature Register (READ Only) Configuration Register (READ/WRITE) TLOW Register (READ/WRITE) THIGH Register (READ/WRITE) TEMPERATURE REGISTER The Temperature Register of the TMP100 or TMP101 is a 12-bit read-only register that stores the output of the most recent conversion. Two bytes must be read to obtain data and are described in Table 3 and Table 4. The first 12 bits are used to indicate temperature with all remaining bits 5 "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 equal to zero. Data format for temperature is summarized in Table 5. Following power-up or reset, the Temperature Register will read 0C until the first conversion is complete. THERMOSTAT MODE (TM) Table 3. Byte 1 of Temperature Register D7 D6 D5 D4 D3 D2 D1 D0 T11 T10 T9 T8 T7 T6 T5 T4 Table 4. Byte 2 of Temperature Register D7 D6 D5 D4 D3 D2 D1 D0 T3 T2 T1 T0 0 0 0 0 Table 5. Temperature Data Format TEMPERATURE (C) DIGITAL OUTPUT (BINARY) HEX 128 127.9375 100 80 75 50 25 0.25 0.0 -0.25 -25 -55 -128 0111 1111 1111 0111 1111 1111 0110 0100 0000 0101 0000 0000 0100 1011 0000 0011 0010 0000 0001 1001 0000 0000 0000 0100 0000 0000 0000 1111 1111 1100 1110 0111 0000 1100 1001 0000 1000 0000 0000 7FF 7FF 640 500 4B0 320 190 004 000 FFC E70 C90 800 The user can obtain 9, 10, 11, or 12 bits of resolution by addressing the Configuration Register and setting the resolution bits accordingly. For 9-, 10-, or 11-bit resolution, the most significant bits in the Temperature Register are used with the unused LSBs set to zero. The Thermostat Mode bit of the TMP101 indicates to the device whether to operate in Comparator Mode (TM = 0) or Interrupt Mode (TM = 1). For more information on comparator and interrupt modes, see the HIGH and LOW Limit Registers section. POLARITY (POL) The Polarity Bit of the TMP101 allows the user to adjust the polarity of the ALERT pin output. If POL = 0, the ALERT pin will be active LOW, as shown in Figure 4. For POL = 1 the ALERT pin will be active HIGH, and the state of the ALERT pin is inverted. THIGH Measured Temperature TLOW TMP101 ALERT PIN (Comparator Mode) POL = 0 TMP101 ALERT PIN (Interrupt Mode) POL = 0 TMP101 ALERT PIN (Comparator Mode) POL = 1 TMP101 ALERT PIN (Interrupt Mode) POL = 1 CONFIGURATION REGISTER The Configuration Register is an 8-bit read/write register used to store bits that control the operational modes of the temperature sensor. Read/write operations are performed MSB first. The format of the Configuration Register for the TMP100 and TMP101 is shown in Table 6, followed by a breakdown of the register bits. The power-up/reset value of the Configuration Register is all bits equal to 0. The OS/ALERT bit will read as 1 after power-up/reset. Table 6. Configuration Register Format BYTE D7 D6 D5 D4 D3 D2 D1 D0 1 OS/ALERT R1 R0 F1 F0 POL TM SD SHUTDOWN MODE (SD) The Shutdown Mode of the TMP100 and TMP101 allows the user to save maximum power by shutting down all device circuitry other than the serial interface, which reduces current consumption to less than 1A. For the TMP100 and TMP101, Shutdown Mode is enabled when 6 the SD bit is 1. The device will shutdown once the current conversion is completed. For SD equal to 0, the device will maintain continuous conversion. Read Read Read Time Figure 4. Output Transfer Function Diagrams FAULT QUEUE (F1/F0) A fault condition occurs when the measured temperature exceeds the user-defined limits set in the THIGH and TLOW Registers. Additionally, the number of fault conditions required to generate an alert may be programmed using the Fault Queue. The Fault Queue is provided to prevent a false alert due to environmental noise. The Fault Queue requires consecutive fault measurements in order to trigger the alert function. If the temperature falls below TLOW, prior to reaching the number of programmed consecutive faults limit, the count is reset to 0. Table 7 defines the number of measured faults that may be programmed to trigger an alert condition in the device. "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 Table 7. Fault Settings of the TMP100 and TMP101 F1 F0 CONSECUTIVE FAULTS 0 0 1 1 0 1 0 1 1 2 4 6 CONVERTER RESOLUTION (R1/R0) The Converter Resolution Bits control the resolution of the internal Analog-to-Digital (A/D) converter. This allows the user to maximize efficiency by programming for higher resolution or faster conversion time. Table 8 identifies the Resolution Bits and relationship between resolution and conversion time. Table 8. Resolution of the TMP100 and TMP101 R1 R0 RESOLUTION CONVERSION TIME (typical) 0 0 9 Bits (0.5C) 40ms 0 1 10 Bits (0.25C) 80ms 1 0 11 Bits (0.125C) 160ms 1 1 12 Bits (0.0625C) 320ms OS/ALERT (OS) The TMP100 and TMP101 feature a One-Shot Temperature Measurement Mode. When the device is in Shutdown Mode, writing a 1 to the OS/ALERT bit will start a single temperature conversion. The device will return to the shutdown state at the completion of the single conversion. This is useful to reduce power consumption in the TMP100 and TMP101 when continuous monitoring of temperature is not required. Reading the OS/ALERT bit will provide information about the Comparator Mode status. The state of the POL bit will invert the polarity of data returned from the OS/ALERT bit. For POL = 0, the OS/ALERT will read as 1 until the temperature equals or exceeds THIGH for the programmed number of consecutive faults, causing the OS/ALERT bit to read as 0. The OS/ALERT bit will continue to read as 0 until the temperature falls below TLOW for the programmed number of consecutive faults when it will again read as 1. The status of the TM bit does not affect the status of the OS/ALERT bit. In Interrupt Mode (TM = 1) the ALERT Pin becomes active when the temperature equals or exceeds THIGH for a consecutive number of fault conditions. The ALERT pin remains active until a read operation of any register occurs or the device successfully responds to the SMBus Alert Response Address. The ALERT pin will also be cleared if the device is placed in Shutdown Mode. Once the ALERT pin is cleared, it will only become active again by the temperature falling below TLOW. When the temperature falls below TLOW, the ALERT pin will become active and remain active until cleared by a read operation of any register or a successful response to the SMBus Alert Response Address. Once the ALERT pin is cleared, the above cycle will repeat with the ALERT pin becoming active when the temperature equals or exceeds THIGH. The ALERT pin can also be cleared by resetting the device with the General Call Reset command. This will also clear the state of the internal registers in the device returning the device to Comparator Mode (TM = 0). Both operational modes are represented in Figure 4. Table 9 and Table 10 describe the format for the THIGH and TLOW registers. Power-up Reset values for THIGH and TLOW are: THIGH = 80C and TLOW = 75C. The format of the data for THIGH and TLOW is the same as for the Temperature Register. Table 9. Bytes 1 and 2 of THIGH Register BYTE D7 D6 D5 D4 D3 D2 D1 D0 1 H11 H10 H9 H8 H7 H6 H5 H4 BYTE D7 D6 D5 D4 D3 D2 D1 D0 2 H3 H2 H1 H0 0 0 0 0 Table 10. Bytes 1 and 2 of TLOW Register BYTE D7 D6 D5 D4 D3 D2 D1 D0 1 L11 L10 L9 L8 L7 L6 L5 L4 BYTE D7 D6 D5 D4 D3 D2 D1 D0 2 L3 L2 L1 L0 0 0 0 0 All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is configured for 9-bit resolution. SERIAL INTERFACE HIGH AND LOW LIMIT REGISTERS In Comparator Mode (TM = 0), the ALERT pin of the TMP101 becomes active when the temperature equals or exceeds the value in THIGH and generates a consecutive number of faults according to fault bits F1 and F0. The ALERT pin will remain active until the temperature falls below the indicated TLOW value for the same number of faults. The TMP100 and TMP101 operate only as slave devices on the I2C bus and SMBus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The TMP100 and TMP101 support the transmission protocol for fast (up to 400kHz) and high-speed (up to 3.4MHz) modes. All data bytes are transmitted most significant bit first. 7 "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 SERIAL BUS ADDRESS To program the TMP100 and TMP101, the master must first address slave devices via a slave address byte. The slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or write operation. The TMP100 features two address pins to allow up to eight devices to be addressed on a single I2C interface. Table 11 describes the pin logic levels used to properly connect up to eight devices. Float indicates the pin is left unconnected. The state of pins ADD0 and ADD1 is sampled on the first I2C bus communication and should be set prior to any activity on the interface. Table 11. Address Pins and Slave Addresses for the TMP100 ADD1 ADD0 SLAVE ADDRESS 0 0 0 1 1 1 Float Float 0 Float 1 0 Float 1 0 1 1001000 1001001 1001010 1001100 1001101 1001110 1001011 1001111 The TMP101 features one address pin and an ALERT pin, allowing up to three devices to be connected per bus. Pin logic levels are described in Table 12. The address pins of the TMP100 and TMP101 are read after reset or in response to an I2C address acquire request. Following reading, the state of the address pins is latched to minimize power dissipation associated with detection. Table 12. Address Pins and Slave Addresses for the TMP101 ADD0 SLAVE ADDRESS 0 Float 1 1001000 1001001 1001010 BUS OVERVIEW The device that initiates the transfer is called a master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. To address a specific device, a START condition is initiated, indicated by pulling the data-line (SDA) from a HIGH to LOW logic level while SCL is HIGH. All slaves on the bus shift in the slave address byte, with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being addressed responds to the master by generating an Acknowledge and pulling SDA LOW. 8 Data transfer is then initiated and sent over eight clock pulses followed by an Acknowledge Bit. During data transfer SDA must remain stable while SCL is HIGH, as any change in SDA while SCL is HIGH will be interpreted as a control signal. Once all data have been transferred, the master generates a STOP condition indicated by pulling SDA from LOW to HIGH, while SCL is HIGH. WRITING/READING TO THE TMP100 AND TMP101 Accessing a particular register on the TMP100 and TMP101 is accomplished by writing the appropriate value to the Pointer Register. The value for the Pointer Register is the first byte transferred after the I2C slave address byte with the R/W bit LOW. Every write operation to the TMP100 and TMP101 requires a value for the Pointer Register. (Refer to Figure 6.) When reading from the TMP100 and TMP101, the last value stored in the Pointer Register by a write operation is used to determine which register is read by a read operation. To change the register pointer for a read operation, a new value must be written to the Pointer Register. This is accomplished by issuing an I2C slave address byte with the R/W bit LOW, followed by the Pointer Register Byte. No additional data are required. The master can then generate a START condition and send the I2C slave address byte with the R/W bit HIGH to initiate the read command. See Figure 7 for details of this sequence. If repeated reads from the same register are desired, it is not necessary to continually send the Pointer Register bytes as the TMP100 and TMP101 will remember the Pointer Register value until it is changed by the next write operation. SLAVE MODE OPERATIONS The TMP100 and TMP101 can operate as slave receivers or slave transmitters. Slave Receiver Mode: The first byte transmitted by the master is the slave address, with the R/W bit LOW. The TMP100 or TMP101 then acknowledges reception of a valid address. The next byte transmitted by the master is the Pointer Register. The TMP100 or TMP101 then acknowledges reception of the Pointer Register byte. The next byte or bytes are written to the register addressed by the Pointer Register. The TMP100 and TMP101 will acknowledge reception of each data byte. The master may terminate data transfer by generating a START or STOP condition. Slave Transmitter Mode: The first byte is transmitted by the master and is the slave address, with the R/W bit HIGH. The slave acknowledges reception of a valid slave address. The next byte is transmitted by the slave and is the most significant byte of the register indicated by the Pointer Register. The master "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 acknowledges reception of the data byte. The next byte transmitted by the slave is the least significant byte. The master acknowledges reception of the data byte. The master may terminate data transfer by generating a Not-Acknowledge on reception of any data byte, or generating a START or STOP condition. SMBus ALERT FUNCTION The TMP101 supports the SMBus Alert function. When the TMP101 is operating in Interrupt Mode (TM = 1), the ALERT pin of the TMP101 may be connected as an SMBus Alert signal. When a master senses that an ALERT condition is present on the ALERT line, the master sends an SMBus Alert command (00011001) on the bus. If the ALERT pin of the TMP101 is active, the TMP101 will acknowledge the SMBus Alert command and respond by returning its slave address on the SDA line. The eighth bit (LSB) of the slave address byte will indicate if the temperature exceeding THIGH or falling below TLOW caused the ALERT condition. For POL = 0, this bit will be LOW if the temperature is greater than or equal to THIGH. This bit will be HIGH if the temperature is less than TLOW. The polarity of this bit will be inverted if POL = 1. Refer to Figure 8 for details of this sequence. If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion of the SMBus alert command will determine which device will clear its ALERT status. If the TMP101 wins the arbitration, its ALERT pin will become inactive at the completion of the SMBus Alert command. If the TMP101 loses the arbitration, its ALERT pin will remain active. The TMP100 will also respond to the SMBus ALERT command if its TM bit is set to 1. Since it does not have an ALERT pin, the master needs to periodically poll the device by issuing an SMBus Alert command. If the TMP100 has generated an ALERT, it will acknowledge the SMBus Alert command and return its slave address in the next byte. GENERAL CALL The TMP100 and TMP101 respond to the I2C General Call address (0000000) if the eighth bit is 0. The device will acknowledge the General Call address and respond to commands in the second byte. If the second byte is 00000100, the TMP100 and TMP101 will latch the status of their address pins, but will not reset. If the second byte is 00000110, the TMP100 and TMP101 will latch the status of their address pins and reset their internal registers. POR (POWER-ON RESET) The TMP100 and TMP101 both have on-chip power-on reset circuits that reset the device to default settings when the device is powered on. This circuit activates when the power supply is less than 0.3V for more than 100ms. If the TMP100 and TMP101 are powered down by removing supply voltage from the device, but the supply voltage is not assured to be less than 0.3V, it is recommended to issue a General Call reset command on the I2C interface bus to ensure that the TMP100 and TMP101 are completely reset. HIGH-SPEED MODE In order for the I2C bus to operate at frequencies above 400kHz, the master device must issue an Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed operation. The TMP100 and TMP101 will not acknowledge this byte as required by the I2C specification, but will switch their input filters on SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 3.4MHz. After the Hs-mode master code has been issued, the master will transmit an I2C slave address to initiate a data transfer operation. The bus will continue to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving the STOP condition, the TMP100 and TMP101 will switch their input and output filters back to fast-mode operation. 9 "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 TIMING DIAGRAMS Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and is determined by the master device. The receiver acknowledges the transfer of data. The TMP100 and TMP101 are I2C and SMBus compatible. Figure 5 to Figure 8 describe the various operations on the TMP100 and TMP101. Bus definitions are given below. Parameters for Figure 5 are defined in Table 13. Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the Acknowledge clock pulse. Setup and hold times must be taken into account. On a master receive, the termination of the data transfer can be signaled by the master generating a Not-Acknowledge on the last byte that has been transmitted by the slave. Bus Idle: Both SDA and SCL lines remain HIGH. Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCL line is HIGH, defines a START condition. Each data transfer is initiated with a START condition. Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCL line is HIGH defines a STOP condition. Each data transfer is terminated with a repeated START or STOP condition. Table 13. Timing Diagram Definitions FAST MODE PARAMETER SCLK Operating Frequency Bus Free TIme Between STOP and START Conditions Hold time after repeated START condition. After this period, the first clock is generated. Repeated START Condition Setup Time STOP Condition Setup Time Data HOLD Time Data Setup Time SCLK Clock LOW Period SCLK Clock HIGH Period Clock/Data Fall Time Clock/Data Rise Time for SCLK 100kHz 10 MIN MAX HIGH-SPEED MODE MIN 3.4 UNITS f(SCLK) t(BUF) 600 160 ns t(HDSTA) 600 160 ns t(SUSTA) t(SUSTO) 600 160 ns 600 160 ns t(HDDAT) t(SUDAT) 0 0 ns 100 10 ns 1300 160 ns 600 60 t(LOW) t(HIGH) 0.4 MAX MHz ns tF tR 300 160 ns 300 160 ns tR 1000 ns "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 I2C TIMING DIAGRAMS t(LOW) tF tR t (HDSTA) SCL t (HDSTA) t(HIGH) t (SUSTO) t (SUSTA) t(HDDAT) t (SUDAT) SDA t(BUF ) P S S P Figure 5. I2C Timing Diagram 1 9 1 9 ... SCL 1 SDA 0 0 1 A2 A1 A0 Start By Master R/W 0 0 0 0 0 0 P1 ACK By TMP100 or TMP101 ... P0 ACK By TMP100 or TMP101 Frame 1 I2C Slave Address Byte Frame 2 Pointer Register Byte 1 9 1 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 ACK By TMP100 or TMP101 Frame 3 Data Byte 1 D2 D1 D0 ACK By Stop By TMP100 or TMP101 Master Frame 4 Data Byte 2 Figure 6. I2C Timing Diagram for Write Word Format 11 "#$$ "#$# www.ti.com SBOS231G - JANUARY 2002 - REVISED NOVEMBER 2007 1 9 1 9 ... SCL 1 SDA 0 0 1 A2 A1 A0 R/W Start By Master 0 0 0 0 0 0 P1 ACK By TMP100 or TMP101 ... P0 ACK By TMP100 or TMP101 Frame 1 I2C Slave Address Byte Frame 2 Pointer Register Byte 1 9 1 9 ... SCL (Continued) SDA (Continued) 1 0 0 1 A2 A1 A0 D7 R/W Start By Master D6 D5 D4 D3 ACK By TMP100 or TMP101 D1 ... D0 From TMP100 or TMP101 Frame 3 I2C Slave Address Byte 1 D2 ACK By Master Frame 4 Data Byte 1 Read Register 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 From TMP100 or TMP101 ACK By Master Stop By Master Frame 5 Data Byte 2 Read Register Figure 7. I2C Timing Diagram for Read Word Format ALERT 1 9 1 9 SCL SDA Start By Master 0 0 0 1 1 0 0 R/W 1 ACK By TMP100 or TMP101 Frame 1 SMBus ALERT Response Address Byte 0 0 1 A2 A0 S ta tu s From NACK By TMP100 or TMP101 Master Frame 2 Slave Address From TMP100 Figure 8. Timing Diagram for SMBus ALERT 12 A1 Stop By Master PACKAGE OPTION ADDENDUM www.ti.com 13-Apr-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) SN0312100DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP100NA/250 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP100NA/250G4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP100NA/3K ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP100NA/3KG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP101NA/250 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP101NA/250G4 ACTIVE SOT-23 DBV 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP101NA/3K ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMP101NA/3KG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com (3) 13-Apr-2012 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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OTHER QUALIFIED VERSIONS OF TMP100, TMP101 : * Automotive: TMP101-Q1 * Enhanced Product: TMP100-EP NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects * Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TMP100NA/250 SOT-23 DBV 6 250 178.0 9.0 TMP100NA/3K SOT-23 DBV 6 3000 178.0 9.0 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.23 3.17 1.37 4.0 8.0 Q3 3.23 3.17 1.37 4.0 8.0 Q3 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TMP100NA/250 SOT-23 DBV TMP100NA/3K SOT-23 DBV 6 250 180.0 180.0 18.0 6 3000 180.0 180.0 18.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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