PRELIMINARY
2-Mbit (128K x 18) Flow-Through SRAM
with NoBL™ Architecture
CY7C1231H
Cypress Semiconductor Corporation • 3901 North First Street • San Jose,CA 95134 • 408-943-2600
Document #: 001-00207 Rev. ** Revised April 11, 2005
Features
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 128K x 18 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
— 8.0 ns (for 100-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchr onous Output Enable
• Offered in JEDEC-standard Lead-Free 100 TQFP
package
• Burst Capability—linear or interle aved burst order
• Low standby power
Functional Description[1]
The CY7C1231H is a 3.3V, 128K x 18 Synchronous
Flow-through Burst SRAM designed specifically to support
unlimited true back-to-back Read/Write operations without the
insertion of wait states. The CY7C1231H is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to
enable consecutive Read/Write operations with data being
transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of th e clock. The clo ck input is qual ified b y
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay fr om the clock rise is 6.5 ns (133-M Hz
device).
Write operations are controlled by the two Byte Write Select
(BW[A:B]) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoi d bu s
contention, the output drivers are synchronously three- stated
during the data portion of a write sequence.
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
C
MODE
BW
A
BW
B
WE
CE
1
CE
2
CE
3
OE READ LOGIC
DQs
DQP
A
DQP
B
MEMORY
ARRAY
E
INPUT
REGISTER
ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BURST
LOGIC
A0'
A1'
D1
D0 Q1
Q0
A0
A1
ADV/LD
CE ADV/LD
C
CLK
CEN
WRITE
DRIVERS
D
A
T
A
S
T
E
E
R
I
N
G
S
E
N
S
E
A
M
P
S
WRITE ADDRESS
REGISTER
A0, A1, A
O
U
T
P
U
T
B
U
F
F
E
R
SE
ZZ SLEEP
CONTROL
Logic Block Diagram
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 2 of 12
Selection Guide
CY7C1231H-133 CY7C1231H-100 Unit
Maximum Access T i me 6.5 8.0 ns
Maximum Operating Current 225 205 mA
Maximum CMOS Standby Current 40 40 mA
Shaded areas conta i n advance information. Please contact your local CYpress sales representative for availability of this part.
Pin Configuration
100-lead TQFP
A
A
A
A
A1
A0
NC/288M
NC/144M
VSS
VDD
NC(36M)
A
A
A
A
A
NC/4M
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
WE
CEN
OE
NC(18M)
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
ANC(9M)
ADV/LD
ZZ
MODE
NC(72M)
CY7C1231H
BYTE A
BYTE B
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 3 of 12
Pin Definitions (100-pin TQFP Package)
Name I/O Description
A0, A1, A Input-
Synchronous Address Inputs used to select one of the 128K address locations. Sampled at the rising edge of
the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:B] Input-
Synchronous Byte Write Input s, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the
rising edge of CLK.
WE Input-
Synchronous Write Enab le Inpu t, ac tive LOW. Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence .
ADV/LD Input-
Synchronous Advance/Load Input. Used to advance the on-chip address counter or load a new address. When
HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address
can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW
in order to load a new address.
CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK
is only recognized if CEN is active LOW .
CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE2, and CE3 to select/deselect the device.
CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE2 to select/deselect the device.
OE Input-
Asynchronous Output Enable, asynchro no us input, active LOW. Combin ed with the synchronous logic block
inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave
as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is
masked during the data portion of a write sequence, during the first clock when emerging from a
deselected state, when the device has been deselected.
CEN Input-
Synchronous Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the SRAM.
When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the
device, CEN can be used to extend the previous cycle when required.
ZZ Input-
Asynchronous ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
with data integrity preserved. During normal operation, this pin can be conne cted to VSS or left
floating.
DQsI/O-
Synchronous Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by address during the clock rise of the read cycle. The direction of the pins is controlled by OE and
the internal control logic. When OE is asserted LOW , the pins can behave as outputs. When HIGH,
DQs and DQP[A:B] are placed in a three-state condition. The outputs are automatically three-stated
during the data portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE.
DQP[A:B] I/O-
Synchronous Bidirectional Data Parity I/O Lines. Fu nctionally, these signals are identical to DQs. During write
sequences, DQP[A:B] is controlled by BWx correspondingly.
Mode Input
Strap Pin Mode Input. Selects the burst order of the device. When tied to Gnd selects linear burst sequence. When
tied to VDD or left floating selects interleaved burst sequence.
VDD Power Supply Power supply inputs to the core of the device.
VDDQ I/O Power
Supply Power supply for the I/O circuitry.
VSS Ground Ground for the device.
NC –No Connects. Not Internally connected to the die.4M, 9M,18M,36M, 72M, 144M, 288M, 576M and
1G are address expansion pins and are not internally connected to the die.
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 4 of 12
Functional Overview
The CY7C1231H is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous op erations
are qualified with CEN. Maximum access delay from the clock
rise (tCDV) is 6.5 ns (133-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE1, CE2, CE3) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, dep ending on
the status of the Write Enable (WE). BW[A:B] can be used to
conduct Byte Write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enab le (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the ou tput buffers are controlled b y
OE and the internal con trol logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1231H has an on-chip burst counter that allows the
user the ability to supply a si ngle address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address in to the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of Chip Enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write accesses are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW , (2) CE1, CE2,
and CE3 are ALL asserted active, and (3) the Write signal WE
is asserted LOW. The address presented to the addre ss bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically three-stated regardless of the state of the OE
input signal. This allows the external logic to present the data
on DQs and DQP[A:B].
On the next clock rise the data presented to DQs and DQP[A:B]
(or a subset for Byte Write operations, see Truth Table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW[A:B] signals. The CY7C1231H provides Byte Write
capability that is described in the Truth Table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input will selective ly write to only the desired bytes. Bytes not
selected during a Byte Write operation will remain unalte red.
A synchronous self-timed write mechanism has been provided
to simplify the Write operations. Byte Write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1231H is a common I/O device, data
should not be driven into the device while the outputs are
active. The Output Enable (OE) can be deasserted HIGH
before presenting data to the DQs and DQP[A:B] inputs. Doing
so will three-state the o utput drivers. As a safety precaution,
DQs and DQP[A:B].are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1231H has an on-chip burst counter that allows the
user the ability to supply a singl e address and conduct up to
four Write operations without reasserting the address inpu ts.
ADV/LD must be driven LOW in order to load the initial
address, as described in the Single Write Access section
above. When ADV/LD is driven HIGH on the subsequent clock
rise, the Chip Enables (CE1, CE2, and CE3) and WE inputs are
ignored and the burst counter is incremented. The correct
BW[A:B] inputs must be driven in each cycle of the burst write,
in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected p rior to entering
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 5 of 12
the “sleep” mode. CE1, CE2, and CE3, must remain inactive for
the duration of tZZREC after the ZZ input returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
Second
Address
A1, A0
Third
Address
A1, A0
Fourth
Address
A1, A0
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
Interleaved Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
A1, A0 A1, A0 A1, A0 A1, A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Sleep mode standby current ZZ > VDD − 0.2V 40 mA
tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
tZZI ZZ Active to sleep current This parameter is sampled 2tCYC ns
tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 ns
Truth Table[2, 3, 4, 5, 6, 7, 8]
Operation Address
Used CE1CE2 CE3ZZ ADV/LD WE BWXOE CEN CLK DQ
Deselect Cycle None H X X L L X X X L L->H Three-State
Deselect Cycle None X X H L L X X X L L->H Three-St ate
Deselect Cycle None X L X L L X X X L L->H Three-State
Continue Deselect Cycle None X X X L H X X X L L->H Three-State
READ Cycle (Begin Burst) External L H L L L H X L L L->H Data Out (Q)
READ Cycle (Continue Burst) Next X X X L H X X L L L->H Data Out (Q)
NOP/DUMMY READ (Begin Burst) External L H L L L H X H L L->H Three-State
DUMMY READ (Continue Burst) Next X X X L H X X H L L->H Three-State
WRITE Cycle (Begin Burst) External L H L L L L L X L L->H Data In (D)
WRITE Cycle (Continue Burst) Next X X X L H X L X L L->H Data In (D)
NOP/WRITE ABORT (Begin Burst) None L H L L L L H X L L->H Three-State
WRITE ABORT (Continue Burst) Next X X X L H X H X L L->H Three-State
IGNORE CLOCK EDGE (Stall) Current X X X L X X X X H L->H –
Sleep MODE None X X X H X X X X X X Three-State
Notes:
2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = 0 signifies at least one Byte Writ e Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see Truth Table for details.
3. Write is defined by BW[A:B], and WE. See Truth Table for Read/Write.
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. The DQs and DQP[A:B] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE.
8. OE is asynchronous and is not sampled wit h the clock rise. It is masked int ernally during write cycles. Duri ng a read cycle DQs and DQ P[A:B] = Three-state when
OE is inactive or when the device is deselecte d, and DQs and DQP[A:B] = data when OE is active .
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 6 of 12
Truth Table for Read/Write [2, 3]
Function WE BWABWB
Read HXX
Write – No bytes written L H H
Write Byte A – (DQA and DQPA)LHH
Write Byte B – (DQB and DQPB)LHH
Write All Bytes L L L
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 7 of 12
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Supply Voltage on VDD Relative to GND ......–0.5V to +4.6V
DC Voltage Applied to Outputs
in Three-State ... .................................. –0.5V to VDDQ + 0.5V
DC Input Voltage....................................–0.5V to VDD + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current............... ... ... ............................... > 200 mA
Operating Range
Range Ambient
Temperature (TA)V
DD VDDQ
Com’l 0°C to +70°C 3.3V –
5%/+10% 3.3V – 5% to
VDD
Ind’l -40°C to +85°C
Electrical Characteristics Over the Operating Range [9,10]
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.135 3.6 V
VDDQ I/O Supply Vo ltage for 3.3V I/O 3.135 VDD V
VOH Output HIGH Voltage for 3.3V I/O, IOH = –4.0 mA 2.4 V
VOL Output LOW Voltage for 3.3V I/O, IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage for 3.3V I/O 2.0 VDD + 0.3V V
VIL Input LOW Voltage[9] for 3.3V I/O –0.3 0.8 V
IXInput Load Current
(except ZZ and MODE) GND ≤ VI ≤ VDDQ –5 5 µA
Input Current of MODE Input = VSS –30 µA
Input = VDD 5µA
Input Current of ZZ Input = VSS –5 µA
Input = VDD 30 µA
IOZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled –5 5 µA
IDD VDD Operating Supply
Current VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC 7.5-ns cycle, 133 MHz 225 mA
10-ns cycle, 100 MHz 205 mA
ISB1 Automatic CE Power-down
Current—TTL Inputs VDD = M a x , Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
7.5-ns cycle, 133 MHz 90 mA
10-ns cycle, 100 MHz 80 mA
ISB2 Automatic CE Power-down
Current—CMOS Inputs VDD = M a x , Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0. 3V,
f = 0, inputs static
All speeds 40 mA
ISB3 Automatic CE Power-down
Current—CMOS Inputs VDD = M a x , Device Deselected,
VIN ≥ VDDQ – 0. 3V or V IN ≤ 0.3V,
f = fMAX, inputs switching
7.5-ns cycle, 133 MHz 75 mA
10-ns cycle, 100 MHz 65 mA
ISB4 Automatic CE Power-down
Current—TTL Inputs VDD = M a x , Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V , f =
0, inputs static
All speeds 45 mA
Thermal Resistance[11]
Parameters Description Test Conditions 100 TQFP
Package Unit
ΘJA Thermal Resistance
(Junction to Ambient) T est conditions follow standard test methods and
procedures for measuring thermal impedance,
per EIA/JESD51
30.32 °C/W
ΘJC Thermal Resistance
(Junction to Case) 6.85 °C/W
Notes:
9. Overshoot: VIH(AC) < VDD +1.5V (Pulse wid th less than tCYC/2), undershoot: VIL(AC)> –2V (Pulse width less than tCYC/2).
10.TPower-up: Assumes a linear ramp from 0V to VDD (min. ) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
11.Tested initially and after any design or process change s that may affect these paramet ers.
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 8 of 12
Capacitance[11]
Parameter Description Test Conditions 100 TQFP Package Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V
VDDQ=3.3V
5pF
CCLOCK Clock Input Capacitance 5 pF
CI/O I/O Capacit ance 5 pF
AC Test Loads and Waveforms
Switching Characteristics Over the Operating Range [12, 13 ]
Parameter Description 133 MHz 100 MHz UnitMin. Max. Min. Max.
tPOWER VDD(Typical) to the first Access[14] 1 1 ms
Clock
tCYC Clock Cycle Time 7.5 10 ns
tCH Clock HIGH 2.5 4.0 ns
tCL Clock LOW 2.5 4.0 ns
Output Times
tCDV Data Output Valid after CLK Rise 6.5 8.0 ns
tDOH Data Output Hold after CLK Rise 2.0 2.0 ns
tCLZ Clock to Low-Z[15, 16, 17] 0 0 ns
tCHZ Clock to High-Z[15, 16, 17] 3.5 3.5 ns
tOEV OE LOW to Output Valid 3.5 3.5 ns
tOELZ OE LOW to Output Low-Z[15, 16, 17] 0 0 ns
tOEHZ OE HIGH to Output High-Z[15, 16, 17] 3.5 3.5 ns
Set-up Times
tAS Address Set-up before CLK Rise 1.5 2.0 ns
tALS ADV/LD Set-up before CLK Rise 1.5 2.0 ns
tWES WE, BW[A:B] Set-up before CLK Rise 1.5 2.0 ns
tCENS CEN Set-up before CLK Rise 1.5 2.0 ns
tDS Data Input Set-up before CLK Rise 1.5 2.0 ns
tCES Chip Enable Set-up before CLK Rise 1.5 2.0 ns
Notes:
12.Timing reference level is 1.5V when VDDQ = 3.3V.
13.Test conditions shown in (a) of AC Test Loads, unless otherwise noted.
14.This part has a voltage regulator int ernally; tPOWER is the time that the power ne eds to be supplied above VDD minimum i nitially bef ore a read or wr ite op eration
can be initiated.
15.tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
16.At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same
data bus. The se specif icatio ns do n ot i mply a bus con tenti on cond iti on, but reflect parameters guaranteed over worst case user conditions. Device is design ed
to achieve Three-state prior to Low-Z under the same system conditions.
17.This parameter is sampled and not 100% tested.
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
V
L
= 1.5V
3.3V ALL INPUT PULSES
VDDQ
GND
90%
10% 90%
10%
≤1ns ≤1ns
(c)
3.3V I/O Test Load
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 9 of 12
Hold Times
tAH Address Hold after CLK Rise 0.5 0.5 ns
tALH ADV/LD Hold after CLK Rise 0.5 0.5 ns
tWEH WE, BW[A:B] Hold after CLK Rise 0.5 0.5 ns
tCENH CEN Hold after CLK Rise 0.5 0.5 ns
tDH Data Input Hold after CLK Rise 0.5 0.5 ns
tCEH Chip Enable Hold after CLK Rise 0.5 0.5 ns
Switching Waveforms
Read/Write Waveforms[18, 19, 20]
Notes:
18.For this waveform ZZ is tied LOW.
19.When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20.Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Switching Characteristics Over the Operating Range (continued)[12, 13 ]
Parameter Description 133 MHz 100 MHz UnitMin. Max. Min. Max.
WRITE
D(A1)
123456789
CLK
tCYC
tCL
tCH
10
CE
tCEH
tCES
WE
CEN
tCENH
tCENS
BW
[A:B]
ADV/LD
tAH
tAS
ADDRESS A1 A2 A3 A4 A5 A6 A7
tDH
tDS
DQ
C
OMMAND
tCLZ
D(A1) D(A2) Q(A4)Q(A3)
D(A2+1)
tDOH tCHZ
tCDV
WRITE
D(A2) BURST
WRITE
D(A2+1)
READ
Q(A3) READ
Q(A4) BURST
READ
Q(A4+1)
WRITE
D(A5) READ
Q(A6) WRITE
D(A7) DESELECT
OE
tOEV
tOELZ
tOEHZ
DON’T CARE UNDEFINED
D(A5)
tDOH
Q(A4+1)
D(A7)Q(A6)
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 10 of 12
NOP, STALL and Deselect Cycles[18, 19, 21]
ZZ Mode Timing[22, 23]
Switching Waveforms
READ
Q(A3)
45678910
A3 A4 A5
D(A4)
123
CLK
CE
WE
CEN
BW[A:B]
ADV/LD
ADDRESS
DQ
C
OMMAND WRITE
D(A4) STALLWRITE
D(A1) READ
Q(A2) STALL NOP READ
Q(A5) DESELECT CONTINUE
DESELECT
DON’T CARE UNDEFINED
tCHZ
A1 A2
Q(A2)D(A1) Q(A3) tDOHQ(A5)
tZZ
I
SUPPLY
CLK
ZZ
tZZREC
A
LL INPUTS
(except ZZ)
DON’T CARE
IDDZZ
tZZI
tRZZI
Outputs (Q)
High-Z
DESELECT or READ Only
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
133 CY7C1231H-133AXC A101 Lead-Free 100-lead Thin Quad Flat Pack (14 x 20 x 1.4 mm) Commercial
CY7C1231H-133AXI A101 Lead-Fre e 100-le ad Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial
100 CY7C1231H-100AXC A101 Lead-Free 100-lead T hin Quad F lat Pack (14 x 20 x 1.4 mm) Commercial
CY7C1231H-100AXI A101 Lead-Fre e 100-le ad Thin Quad Flat Pack (14 x 20 x 1.4 mm) Industrial
Shaded areas conta i n advance information. Please contact your local CYpress sales representative for availability of this part.
Notes:
21.The IG NORE CLOCK EDGE or STALL cycle (Clock 3) illustrated CEN being used to create a pause. A write is not performed during this cycle.
22.Device must be deselected when entering ZZ mode. See Truth Table for all possible signal conditions to deselect the device.
23.I/Os are in three-state when exiting ZZ sleep mode.
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 11 of 12
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device
Technology. All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagram
100-lead Thin Plas tic Quad Flatpack (14 x 20 x 1.4 mm) A 10 1
51-85050-*A
PRELIMINARY CY7C1231H
Document #: 001-00207 Rev. ** Page 12 of 12
Document History Page
Document Title: CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM
with NoBL™ Architecture
Document Number: 001-00207
REV. ECN NO. Issue Date Orig. of
Change Description of Cha ng e
** 347377 See ECN PCI New Datasheet
