November 2011 Doc ID 17448 Rev 5 1/15
15
STL16N65M5
N-channel 650 V, 0.270 Ω, 12 A PowerFLAT™ 8x8 HV
MDmesh™ V Power MOSFET
Features
■100% avalanche tested
■Low input capacitance and gate charge
■Low gate input resistance
Applications
■Switching applications
Description
This device is an N-channel MDmesh™ V Power
MOSFET based on an innovative proprietary
vertical process technology, which is combined
with STMicroelectronics’ well-known
PowerMESH™ horizontal layout structure. The
resulting product has extremely low on-
resistance, which is unmatched among silicon-
based Power MOSFETs, making it especially
suitable for applications which require superior
power density and outstanding efficiency.
Figure 1. Internal schematic diagram
Order code VDSS @
TJmax
RDS(on)
max ID
STL16N65M5 710 V < 0.299 Ω12 A (1)
1. The value is rated according to Rthj-case
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Table 1. Device summary
Order code Marking Package Packaging
STL16N65M5 16N65M5 PowerFLAT™ 8x8 HV Tape and reel
www.st.com
Contents STL16N65M5
2/15 Doc ID 17448 Rev 5
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STL16N65M5 Electrical ratings
Doc ID 17448 Rev 5 3/15
1 Electrical ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage (VGS = 0) 650 V
VGS Gate-source voltage ± 25 V
ID (1)
1. The value is rated according to Rthj-case
Drain current (continuous) at TC = 25 °C 12 A
ID (1) Drain current (continuous) at TC = 100 °C 7.4 A
IDM (1),(2)
2. Pulse width limited by safe operating area
Drain current (pulsed) 48 A
ID(3)
3. When mounted on FR-4 board of inch², 2oz Cu
Drain current (continuous) at Tamb = 25 °C 2 A
ID(3) Drain current (continuous) at Tamb = 100 °C 1.3 A
IDM(2),(3) Drain current (pulsed) 8 A
PTOT (3) Total dissipation at Tamb = 25 °C 3 W
PTOT(1) Total dissipation at TC = 25 °C 90 W
IAR
Avalanche current, repetitive or not-
repetitive (pulse width limited by Tj max) 4A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V) 200 mJ
dv/dt (4)
4. ISD ≤ 12 A, di/dt ≤ 400 A/µs, VPeak < V(BR)DSS, VDD = 400 V
Peak diode recovery voltage slope 15 V/ns
Tstg Storage temperature - 55 to 150 °C
TjMax. operating junction temperature 150 °C
Table 3. Thermal data
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case max 1.38 °C/W
Rthj-amb(1)
1. When mounted on 1inch² FR-4 board, 2 oz Cu
Thermal resistance junction-amb max 45 °C/W
Electrical characteristics STL16N65M5
4/15 Doc ID 17448 Rev 5
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4. On /off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS
Drain-source
breakdown voltage
(VGS = 0)
ID = 1 mA 650 V
IDSS
Zero gate voltage
drain current (VGS = 0)
VDS = 650 V
VDS = 650 V, TC=125 °C
1
100
µA
µA
IGSS
Gate-body leakage
current (VDS = 0) VGS = ± 25 V 100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 5 V
RDS(on)
Static drain-source on
resistance VGS = 10 V, ID = 6 A 0.270 0.299 Ω
Table 5. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss
Coss
Crss
Input capacitance
Output capacitance
Reverse transfer
capacitance
VDS = 100 V, f = 1 MHz,
VGS = 0 -
1250
30
3
-
pF
pF
pF
Co(tr)(1)
1. Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss
when VDS increases from 0 to 80% VDSS
Equivalent
capacitance time
related VDS = 0 to 520 V, VGS = 0
-100-pF
Co(er)(2)
2. Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as
Coss when VDS increases from 0 to 80% VDSS
Equivalent
capacitance energy
related
-30-pF
RG
Intrinsic gate
resistance f = 1 MHz open drain - 2 - Ω
Qg
Qgs
Qgd
Total gate charge
Gate-source charge
Gate-drain charge
VDD = 520 V, ID = 6 A,
VGS = 10 V
(see Figure 16)
-
31
8
12
-
nC
nC
nC
STL16N65M5 Electrical characteristics
Doc ID 17448 Rev 5 5/15
Table 6. Switching times
Symbol Parameter Test conditions Min. Typ. Max Unit
td (v)
tr (v)
tf (i)
tc(off)
Voltage delay time
Voltage rise time
Current fall time
Crossing time
VDD = 400 V, ID = 8 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 17),
(see Figure 20)
-
25
7
6
8
-
ns
ns
ns
ns
Table 7. Source drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
ISD
ISDM (1)
1. Pulse width limited by safe operating area
Source-drain current
Source-drain current (pulsed) -12
48
A
A
VSD (2)
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
Forward on voltage ISD = 12 A, VGS = 0 - 1.5 V
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 12 A, di/dt = 100 A/µs
VDD = 100 V (see Figure 17)-
300
3.5
23
ns
µC
A
trr
Qrr
IRRM
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 12 A, di/dt = 100 A/µs
VDD = 100 V, Tj = 150 °C
(see Figure 17)
-
350
4
24
ns
µC
A
Electrical characteristics STL16N65M5
6/15 Doc ID 17448 Rev 5
2.1 Electrical characteristics (curves)
Figure 2. Safe operating area Figure 3. Thermal impedance
Figure 4. Output characteristics Figure 5. Transfer characteristics
Figure 6. Normalized BVDSS vs temperature Figure 7. Static drain-source on resistance
I
D
10
1
0.1
0.01
0.1 1100 V
DS
(V)
10
(A)
Operation in this area is
Limited by max R
DS(on)
10µs
100µs
1ms
10ms
Tj=150°C
Tc=25°C
Single pulse
AM10357v1
10
-5
10
-4
10
-3
10
-2
t
p
(s)
10
-2
10
-1
K
0.2
0.05
0.02
0.01
0.1
Single pulse
δ=0.5
Zth PowerFLAT 8x8 HV
I
D
15
10
5
00V
DS
(V)
(A)
2
20
6.5V
6V
7V
V
GS
=10V 7.5V
46810 12 14 16 18
5.5V
AM03178v1
ID
15
10
5
0
35VGS(V)
(A)
467
20
VDS=10V
89
AM03179v1
BV
DSS
-50 0T
J
(°C)
(norm)
-25 75
25 50 100
0.93
0.95
0.97
0.99
1.01
1.03
1.05
1.07
I
D
=1mA
AM03187v1
R
DS(on)
0.26
0.25
04I
D
(A)
(Ω)
26
0.27
V
GS
=10V
10
812
0.24
0.29
0.28
AM10358v1
STL16N65M5 Electrical characteristics
Doc ID 17448 Rev 5 7/15
Figure 8. Output capacitance stored energy Figure 9. Capacitance variations
Figure 10. Gate charge vs gate-source voltage Figure 11. Normalized on resistance vs
temperature
Figure 12. Normalized gate threshold voltage
vs temperature
Figure 13. Source-drain diode forward
characteristics
Eoss
6
4
2
0
0100 VDS(V)
(µJ)
400
200 300 500 600
1
3
5
7
AM03312v1
C
1000
100
10
1
0.1 10 VDS(V)
(pF)
1
10000
100
Ciss
Coss
Crss
AM03183v1
V
GS
6
4
2
0010 Q
g
(nC)
(V)
8
25
10
V
DD
=520V
V
GS
=10V
I
D
=6A
12
515 20 3035
100
200
300
400
500
V
DS
AM03182v1
R
DS(on)
1.7
1.5
1.3
0.5
-50 0T
J
(°C)
(norm)
50 100
0.7
0.9
1.1
2.1
1.9
V
GS
=10V
I
D
=6.5V
AM03185v1
VGS(th)
1.00
0.90
0.80
0.70
-50 0TJ(°C)
(norm)
1.10
50 100
ID=250µA
AM03184v1
V
SD
05I
SD
(A)
(V)
10
0.4
0.5
0.6
0.7
0.8
0.9
1.0
T
J
=25°C T
J
=150°C
T
J
=-25°C
AM03186v1
Electrical characteristics STL16N65M5
8/15 Doc ID 17448 Rev 5
Figure 14. Switching losses vs gate resistance
(1)
1. Eon including reverse recovery of a SiC diode
E
60
40
20
0
020 RG(Ω)
(μJ)
10 30
80
100
40
Eon
Eoff
ID=18A
VDD=400V
L=50µH
AM10359v1
STL16N65M5 Test circuits
Doc ID 17448 Rev 5 9/15
3 Test circuits
Figure 15. Switching times test circuit for
resistive load
Figure 16. Gate charge test circuit
Figure 17. Test circuit for inductive load
switching and diode recovery times
Figure 18. Unclamped inductive load test
circuit
Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform
AM01468v1
VGS
PW
VD
RG
RL
D.U.T.
2200
μF
3.3
μFVDD
AM01469v1
VDD
47kΩ1kΩ
47kΩ
2.7kΩ
1kΩ
12V
Vi=20V=VGMAX
2200
μF
PW
IG=CONST
100Ω
100nF
D.U.T.
VG
AM01470v1
A
D
D.U.T.
S
B
G
25 Ω
AA
BB
RG
G
FAST
DIODE
D
S
L=100μH
μF
3.31000
μFVDD
AM01471v1
Vi
Pw
VD
ID
D.U.T.
L
2200
μF
3.3
μFVDD
AM01472v1
V(BR)DSS
VDD
VDD
VD
IDM
ID
AM05540v1
Id
Vgs
Vds
90%Vds
10%Id
90%Vgson
Tdelay-off
Tfall
Trise
Tcross -over
10%Vds
90%Id
Vgs(I(t))
on
-off
Tfall
Trise
-
))
Concept waveform for Inductive Load Turn-off
Package mechanical data STL16N65M5
10/15 Doc ID 17448 Rev 5
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com. ECOPACK
is an ST trademark.
STL16N65M5 Package mechanical data
Doc ID 17448 Rev 5 11/15
Table 8. PowerFLAT™ 8x8 HV mechanical data
Dim.
mm
Min. Typ. Max.
A 0.80 0.90 1.00
A1 0.00 0.02 0.05
b 0.95 1.00 1.05
D8.00
E8.00
D2 7.05 7.20 7.30
E2 4.15 4.30 4.40
e2.00
L 0.40 0.50 0.60
aaa 0.10
bbb 0.10
ccc 0.10
Package mechanical data STL16N65M5
12/15 Doc ID 17448 Rev 5
Figure 21. PowerFLAT™ 8x8 HV drawing mechanical data
INDEX AREA
TOP VIEW
PLANE
SEATING
0.08 C
BOTTOM VIEW
SIDE VIEW
PIN#1 ID
D
E
b
A
E2
D2
L
0.40
0.20
±0.008
C
bbb C A B
B
A
aaa C
aaa C
A1
ccc C
8222871_Rev_B
STL16N65M5 Package mechanical data
Doc ID 17448 Rev 5 13/15
Figure 22. PowerFLAT™ 8x8 HV recommended footprint
7.30
1.05
2.00
7.70
4.40
0.60
Footprint
Revision history STL16N65M5
14/15 Doc ID 17448 Rev 5
5 Revision history
Table 9. Document revision history
Date Revision Changes
30-Apr-2010 1 First release
08-Jun-2010 2 VGS value has been changed in Ta b l e 4
10-Feb-2011 3 Modified RDS(on) value
28-Jul-2011 4
Document status promoted from preliminary data to datasheet
Added Section 2.1: Electrical characteristics (curves)
Minor text changes
03-Nov-2011 5 Section 4: Package mechanical data has been modified.
STL16N65M5
Doc ID 17448 Rev 5 15/15
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