FL7740 Constant-Voltage Primary-SideRegulation PWM Controller for Power Factor Correction The FL7740 provides accurate CV regulation in the steady state with differentiated dynamic function to minimize overshoot and undershoot of output voltage in line and load transient condition. Standby power is less than 0.3 W for smart lighting application and power factor is higher than 0.9 even at half load condition when enabling PF optimizer for wide output power scalability. Startup time is less than 0.2 sec with built-in high voltage startup circuit and output voltage quickly reaches to the target CV level by loop gain transition technique during startup. Various protections such as over load, output diode short, sensing resistor short, output short and output over voltage protection guarantee high system reliability. www.onsemi.com SO 10L NB MARKING DIAGRAM ZXYKK FL7740 MA Features * * * * * * * * * * * * Wide universal input range (90 VAC ~ 305 VAC) Precise CV regulation in the steady state : < 3 % CV regulation in the load transient : < 10 % Overshoot-less fast HV start up time ( < 0.2 sec ) Low standby power PF higher than 0.9 at high-line and half load by PF optimizer Pulse-by-pulse current limit Output short protection Output over voltage protection Output diode short protection Sensing resistor short & open protection Over load protection Typical Applications * * * LED Lighting System AC-DC Adapters, TVs, Monitors Off Line Appliances Requiring Power Factor Correction Z X Y KK M A = Plant code = 1 digit year code = 1 digit week code = 2 digit lot traceability code = Package code = Product version PIN CONNECTIONS VDD HV GND NC GATE COMV CS BIAS VS PF ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 13 of this data sheet. (c) Semiconductor Components Industries, LLC, 2016 February 2018 - Rev. 3 1 Publication Order Number: FL7740 FL7740 VOUT.MAIN Secondary DC-DC Converter VAC Dimming Signal FL7740 VDD HV GND NC GATE VOUT.BIAS Dimming Control Module COMV CS BIAS VS PF 0-10, DALI, Wireless, etc. Figure 1. Application Schematic Dynamic control GND VDYN-REF1,2,3 VREF VS HV GM amp. VEAV S/H NC JFET VDD COMV Gain control at startup Digital Duty Control BIAS GATE 5V regulator Protection VIN.PK PF Driver Digital PF optimizer CPF detector VDYN-REF control VOUT open/short protection RCS open/short protection Over current protection Over load protection Thermal shutdown Figure 2. Simplified Block Diagram www.onsemi.com 2 Shutdown CS VDD EAV FL7740 PIN FUNCTION DESCRIPTION Pin No. Pin Name Function Description 1 VDD IC Supply 2 GND Ground 3 GATE PWM Driver Output 4 CS Current Sense 5 VS Voltage Sense 6 PF Power Factor 7 BIAS Internal Circuit BIAS Bypass pin for the internal supply, which powers all control circuitry on the IC. 8 COMV Loop Compensation This pin is connected to a capacitor between COMV and GND for compensation. 9 NC No Connection 10 HV High Voltage IC operating current and MOSFET driving current are supplied using this pin. Controller ground pin. This pin uses the internal totem-pole output driver to drive the power MOSFET. Connected to a current sense resistor to detect the MOSFET current for pulse-bypulse current limit. This pin is connected to the auxiliary winding of the transformer via a resistor divider to detect the output voltage. This pin is connected to a resistor to optimize power factor. This pin is connected to the rectified input voltage via a resistor for fast startup. www.onsemi.com 3 FL7740 MAXIMUM RATINGS (Note 1) Rating Symbol VHV(MAX) Value HV Pin Voltage Range 560 V VDD, GATE Pin Voltage Range VMV(MAX) -0.3 to 30 V COMV, PF, BIAS, VS, CS Pin Voltage Range Unit VLV(MAX) -0.3 to 6 V VLV(PULSE) -1.5 V PD(MAX) TJ(max) 663 mW 150 C -55 to 150 C Junction-to-Ambient Thermal Impedance TSTG RJA 158 C/W Junction-to-Case Thermal Impedance RJC 39 C/W ESDHBM 2 kV VS, CS Pin Negative Pulse Voltage at ILV < 0.2 A and tPULSE < 300 ns Maximum Power Dissipation (TA < 50C) Maximum Junction Temperature Storage Temperature Range ESD Capability, Human Body Model (Note 3) ESDCDM 2 kV ESD Capability, Charged Device Model (Note 3) 1. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 3. This device series incorporates ESD protection and is tested by the following methods: ESD Human Body Model tested per AEC-Q100-002 (EIA/JESD22-A114) ESD Machine Model tested per AEC-Q100-003 (EIA/JESD22-A115) Latchup Current Maximum Rating: 150 mA per JEDEC standard: JESD78 RECOMMENDED OPERATING RANGES (Note 4) Rating Symbol Min Max Unit Ambient Temperature TA -40 125 C 4. Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 4 FL7740 ELECTRICAL CHARACTERISTICS VDD = 18 V and TJ = -40 ~ 125C unless otherwise specified Parameter Test Conditions Symbol Min Typ Max Unit Turn-On Threshold Voltage VDD-ON 14.5 16.0 17.5 V Turn-Off Threshold Voltage VDD-OFF 6.75 7.75 8.75 V IDD-OP 3 5 6.5 mA IDD-AR 0.3 1 mA VDD Section Operating Current CLOAD = 1 nF, VDD = 18V Operating Current during Auto Restart VDD Over-Voltage-Protection VBIAS Voltage VDD-OVP 24 25 26 V VBIAS 4.85 5.00 5.15 V 0.2 V GATE Section Output Voltage Low VOL Output Voltage High VDD = 18 V VOH Peak Sourcing Current Design guaranteed CLOAD = 1 nF, VDD = 20 V CLOAD = 1 nF, VDD = 23 V Isource Design guaranteed CLOAD = 1 nF, VDD = 20 V CLOAD = 1 nF, VDD = 23 V Isink Peak Sinking Current 17.8 V mA 180 210 mA 385 435 Rising Time CLOAD = 1 nF tr 110 150 190 ns Falling Time CLOAD = 1 nF tf 40 60 80 ns IHV 3 9 mA 1 10 A HV Section Supply Current From HV Pin VHV = 560 V, VDD = 0 V Leakage Current after Startup JFET Regulation Time at Startup IHV-LC Design guaranteed tR-JFET 400 500 600 ms VDD High Limit during JFET Regulation VDD-JFET-HL 17.5 19.0 20.5 V VDD Low Limit during JFET Regulation VDD-JFET-LL 15.5 17.0 18.5 V PWM Section s Min. Turn-on Time Min. Limit Design guaranteed TON-MIN-MIN 0.40 Min. Turn-on Time Max. Limit Design guaranteed TON-MIN-MAX 2.0 s Max. Turn-on Time Design guaranteed TON-MAX 23.3 s Oscillator Section Max. Frequency fMAX 60 65 70 kHz Min. Frequency fMIN 0.72 0.80 0.88 kHz Current Sense Section Leading-Edge Blanking Time Design guaranteed tLEB 300 ns Propagation Delay to GATE Design guaranteed tPD 50 100 150 ns tDIS-BNK 0.95 1.00 1.05 s Voltage Sense Section tDIS Blanking Time at VS Sampling Design guaranteed VS Clamping Voltage V VVS-CLAMP IVS=1 mA IVS=10 A -0.1 0.35 Feedback Section Reference voltage VREF www.onsemi.com 5 3.465 3.5 3.535 V FL7740 ELECTRICAL CHARACTERISTICS (CONTINUED) VDD = 18 V and TJ = -40 ~ 125C unless otherwise specified Parameter Test Conditions CV Regulation Tolerance Symbol Min Typ Max % CVREGULATION -0.7 -1.2 VVS = 3.5 V, TJ = 25 C VVS = 3.5 V, TJ = -40~125 C Transconductance Unit +0.7 +1.2 gM 16 20 24 mho COMV Sink Current VVS = 4 V ICOMV-SINK 8 10 12 A COMV Source Current VVS = 3 V ICOMV-SOURCE 8 10 12 A COMV High Voltage VCOMV-HGH 4.7 COMV Low Voltage VCOMV-LOW V 0.1 V Start Sequence Section Soft Start Time Design guaranteed tSOFT-START 25.6 ms SS1 Minimum Time Design guaranteed tSS1-MIN 2 ms SS1 Maximum Time Design guaranteed tSS1-MAX 100 ms SS21 Time Design guaranteed tSS21 45 ms SS22 Maximum Time Design guaranteed tSS22 30 ms Dynamic Section DYN Reference Set Threshold VDYN-REF-SET 0.72 0.80 0.88 V DYN Reference Set Time Design guaranteed tDYN-REF-SET 5 s OV Reference 5 Design guaranteed VOV-REF5 +20 % OV Reference 4 VOV-REF4 +14 +15 +16 % OV Reference 3 VOV-REF3 +9 +10 +11 % OV Reference 2 VOV-REF2 +4.7 +5.7 +6.7 % OV Reference 1 VOV-REF1 +1.86 +2.86 +3.86 % UV Reference 1 VUV-REF1 -3.86 -2.86 -1.86 % UV Reference 2 VUV-REF2 -6.7 -5.7 -4.7 % UV Reference 3 Design guaranteed VUV-REF3 -10 % Design guaranteed tAR 3 s Protection Section Auto Restart Delay Time VS Ouptut Short Hys. Voltage 'H' VVS-OS-H 0.85 0.90 0.95 V VS Ouptut Short Hys. Voltage 'L' VVS-OS-L 0.65 0.70 0.75 V OSP Delay Time Design guaranteed tOSP-DELAY 35 ms High Current Limit Threshold VCS-HIGH-CL 1.13 1.20 1.27 V Low Current Limit Threshold VCS-LOW-CL 0.15 0.20 0.25 V Over Current Protection Voltage VCS-OCP CS Threshold Voltage for SRSP VCS-SRSP Max. Turn-on Time for SRSP 1.8 V 0.040 0.075 0.125 7.5 1.3 10.0 1.6 12.5 1.9 s tTON-MAX-SRSP IVS = 100 uA IVS = 700 uA V Threshold Temperature for OTP Design guaranteed TOTP 150 o Junction Temperature Hysteresis Design guaranteed TOTP-HYS 30 o www.onsemi.com 6 C C FL7740 T Y P I C A L C H A R A T -40 -20 E 5.8 18 5.6 16 15 S T I C S 5.2 5.0 4.8 4.6 4.4 13 4.2 12 -40 -20 0 20 40 60 80 100 120 4.0 140 0 TJ, JUNCTION TEMPERATURE (C) Figure 3 V vs. Temperature D D - O N Figure 60 80 100 120 140 4 V vs. B I A S Temperature 1.35 8.50 1.30 VCS-HIGH-CL (V) 8.25 8.00 7.75 7.50 7.25 1.25 1.20 1.15 1.10 7.00 1.05 6.75 -40 -20 0 20 40 60 80 100 120 1.00 140 -40 -20 TJ, JUNCTION TEMPERATURE (C) Figure 5 V D D - O F F 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) vs. Temperature Figure 6 VCS-HIGH-CL vs. Temperature 3.60 2.00 3.58 1.95 3.56 1.90 VCS-OCP (V) 3.54 3.52 3.50 3.48 3.46 1.85 1.80 1.75 1.70 3.44 1.65 3.42 3.40 40 1.40 8.75 6.50 20 TJ, JUNCTION TEMPERATURE (C) 9.00 VDD-OFF (V) I 5.4 17 14 VREF (V) R 6.0 19 VBIAS (V) VDD-ON (V) 20 C -40 -20 0 20 40 60 80 100 120 140 1.60 -40 TJ, JUNCTION TEMPERATURE (C) F i g u re 7 V R E F vs . -20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) T e mp e ra t u re Figure 8 V www.onsemi.com 7 C S - O C P vs. Temperature FL7740 Y P I C A L C H A R A C 1.0 10.5 0.8 10.4 0.6 10.3 0.4 10.2 VOV-REF3 (%) CVREGULATION (%) T 0.2 0.0 -0.2 -0.4 20 40 60 80 100 120 -40 S -20 0 20 40 60 80 100 120 140 -2.10 -2.25 3.45 -2.40 3.30 3.15 VUV-REF1 (%) VOV-REF1 (%) C Figure 10 VOV-REF3 vs. Temperature 3.60 3.00 2.85 2.70 -2.55 -2.70 -2.85 -3.00 2.55 -3.15 2.40 -3.30 2.25 -3.45 -3.60 -40 -20 0 20 40 60 80 100 120 140 -40 -20 Figure 11 VOV-REF1 vs. Temperature -5.3 6.0 -5.4 5.9 -5.5 VUV-REF2 (%) -5.2 6.1 5.8 5.7 5.6 5.5 -6.2 60 80 100 100 120 140 -5.9 -6.1 40 80 -5.8 -6.0 20 60 -5.7 5.3 0 40 -5.6 5.4 -20 20 Figure 12 VUV-REF1 vs. Temperature 6.2 -40 0 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) VOV-REF2 (%) I TJ, JUNCTION TEMPERATURE (C) Figure 9 CVREGULATION vs. Temperature 5.2 T 9.5 140 TJ, JUNCTION TEMPERATURE (C) 2.10 S 9.8 9.6 0 I 9.9 9.7 -20 R 10.0 -0.8 -40 E 10.1 -0.6 -1.0 T 120 140 -40 -20 0 20 40 60 80 100 120 140 TJ, JUNCTION TEMPERATURE (C) TJ, JUNCTION TEMPERATURE (C) Figure 13 VOV-REF2 vs. Temperature Figure 14 VUV-REF2 vs. Temperature www.onsemi.com 8 FL7740 APPLICATION INFORMATION General FL7740 is high power factor flyback controller with accurate primary side constant voltage regulation for smart LED lighting and AC-DC adapter, TV & monitors application. Precise output voltage detection and dynamic function manage good CV regulation. Startup is fast with internal HV biasing circuit with overshoot-less gain control. It guarantees high system reliable protection functions such as output over voltage, output short, over load, over current and thermal shut down protections. Output Over Voltage Protection When VEAV is higher than VVS-OVP threshold or VDD is higher than VDD-OVP, output over voltage protection is triggered. Output Diode Short Protection Once output diode is short circuited, high di/dt in the primary winding is occurred by leakage inductance. Once CS pin voltage reaches to 1.7 V, switching is shut down. Constant Voltage Regulation Sensing Resistor Short Protection VS pin detects output voltage information (=VEAV) during secondary side diode conduction time and internal gm amplifier regulates the detected voltage at 3.5 V. At first switching, sensing resistor short condition is monitored by detecting CS pin voltage. If CS is less than 75 mV during first GATE turn-on time, sensing resistor short protection is triggered. Dynamic Response at Load Transient Over Load Protection At load transient condition, VEAV is shortly out of regulation due to the narrow PFC loop bandwidth. When VEAV is far from 3.5 V regulation reference, duty is quickly changed to bring the VEAV back to 3.5 V by dynamic control function. When output is over loaded, pulse-by-pulse current limit event is occurred. If this event lasts for 60 half line cycles, over load protection is triggered. Thermal Shut Down If internal junction temperature is higher than 150C, protection is triggered and released with 30C hysteresis. HV biasing at startup Internal HV biasing circuit quickly charges external VDD capacitor to begin IC operation at plug-in. After 500 ms initial time, HV biasing stops for low standby power. Overshoot-less gain control at startup Once IC operation starts, feedback loop is dominantly controlled in proportional gain to speed up the output capacitor charging. Once output voltage is settled down close to the regulation target, gain control is smoothly changed to integration gain with no output voltage overshoot. Digital PF optimizer FL7740 compensates input current phase shift caused by EMI filter capacitor current in a half line period. With sophisticated digital PF optimizer, FL7740 significantly improves power factor in the wide load range. Pulse-by-pulse current limit When CS pin voltage reaches to 1.2 V current limit reference, GATE turn-on is terminated to limit primary peak current. Auto Restart at Protection Once protection is triggered, IC operation stops for 3 sec and begin the operation for auto restart. Output Short Protection When VEAV is less than 0.7 V continuously for 35 ms, output short protection is triggered. www.onsemi.com 9 FL7740 Primary Side Constant Voltage Regulation FL7740 utilizes auxiliary winding to detect output voltage during secondary side diode conduction time (=TDIS). The true output voltage level without secondary diode forward voltage drop is at the end of secondary diode conduction time. In order to detect the right output voltage, 85% of TDIS at previous switching cycle is sampling time for VEAV detection at current switching cycle. TDIS detection VS NAUX Error Amp. VREF S/H VEAV COMV Duty Control VIN.PK during startup sequence (SS1 + SS2) by using internal resistive load at the output of the error amplifier. In SS1, CCM prevent operation is enabled for the initial 2 ms. When output voltage is 0 V, deep CCM could be entered at initial startup and CS could touch OCP level with startup failure. So, pulse-by-pulse current limit is 0.2 V and switching frequency is 22 kHz during the 2 ms CCM prevent time. Also, duty is gradually increased for 26 ms for soft startup. Once 5 V pulled-up COMV voltage drops less than 4.5 V as VEAV is close to VREF, SS1 is ended. Maximum SS1 time is limited up to 100 ms. In SS2, VCOMV drops from 5 V and goes into p-gain steady state in which VEAV is little bit lower than VREF due to the error amplifier input error in p-gain. Once pgain steady state is settled down in 45 ms, SS2 is finished at min. VCOMV range not to make overshoot when transitioning to i-gain after SS2. FL7740 ends SS2 by monitoring VIN 1.5 ms after VIN.PK detection moment where VCOMV is generally in the min. range. VIN.PK Figure 15. Primary Side Regulation VIN 1.5 ms VCOMV GATE 5.0 V 4.5 V 26 ms soft start Duty VEAV sampling VS 2 ms CCM prevent VEAV VREF 85% TDIS at previous switching 45 ms SS2 SS1 Startup time by P-gain I-gain TDIS Figure 17. Startup Sequence Figure 16. VEAV Detection The sampled VEAV is compared with 3.5 V VREF at the input of the error amplifier. Several hundreds nF capacitor is connected to the output of the error amplifier at COMV pin to keep feedback loop slow in PFC control. COMV voltage controls duty to regulate VEAV same as VREF in the system. Turn-on time is controlled by both COMV voltage and VIN.PK information in line feedforward operation in order to keep the constant COMV voltage in the wide input voltage range. So, turn-on time is proportional to COMV voltage and inversely proportional to VIN.PK. Startup After plug-in, external VDD capacitor is quickly charged by internal HV biasing supply. Even after VDD is higher than 16 V VDD-ON, internal HV biasing is still enabled for 500 ms, so HV biasing can relieve VDD capacitor discharging until auxiliary winding builds up VDD voltage. In order to speed up large output capacitor charging without overshoot, FL7740 starts with proportional gain Dynamic CV Regulation Due to the narrow loop bandwidth, PFC controller generally does not guarantee good CV regulation at load transient. Especially in secondary side regulation, primary side controller does not know the output voltage level and it only monitors the output of feedback signal through opto-coupler. Therefore, output voltage undershoot is severely happened at no to full load transient in the conventional SSR PFC control. In order to overcome this, FL7740 utilizes the benefit of PSR with ON semiconductor's proprietary dynamic duty control by monitoring the output voltage. For example, when VEAV is less than VUVD.EN (Under Voltage Dynamic Enable threshold), duty is quickly increased not to allow undershoot anymore. Once VEAV rises higher than VUVD.DIS (Under Voltage Dynamic Disable threshold), duty quickly drops and follows COMV voltage. During the VEAV hiccup operation, COMV voltage slowly increases and dynamic operation is terminated when COMV voltage is close to steady state level. www.onsemi.com 10 FL7740 COMV VREF Duty Generator VEAV GM amp. VOVD.EN2 VOVD.EN1 Over Voltage Dynamic (OVD) VOVD.DIS VUVD.EN VUVD.DIS Under Voltage Dynamic (UVD) GATE In case of OVD (Over Voltage Dynamic) function, it has two enable levels (VOVD.EN1 and VOVD.EN2). If output voltage overshoot at load transient is too high, VEAV increases to VOVD.EN2 passing by VOVD.EN1. Duty quickly drops when reaching VOVD.EN1 and drops to min. level at once not to allow severe output over voltage when VEAV increases higher than VOVD.EN2. FL7740 provides two sets of dynamic triggering threshold. When user prefers narrow output voltage variation at load transient with large output capacitor, SET0 can be selected without capacitor at PF pin. If wider output voltage variation is allowed and output capacitor should be small due to system size, SET1 can be selected with connection of capacitor around 0.5 nF at PF pin. FL7740 detects capacitance at PF pin at the beginning of switching startup and maintains the SET# until UVLO is triggered. During the 1st switching, PF pin is pulled down to 0 V. In the 2nd switching, PF pull down is disabled and PF voltage is monitored 5 us after 2nd switching period begins. If the PF voltage is higher than 0.8 V VDYN-REF-SET, SET0 is decided. If not, SET1 is determined. Figure 18. Dynamic Function Block Dynamic Threshold at SET0 and SET1 VVS.OVP VEAV VREF VOV-REF5 +20%VREF VUVD.DIS VOV-REF4 +15%VREF VOVD.EN2 VOVD.EN1 VOVD.DIS VUVD.DIS VUVD.EN SET1 SET0 SET1 VUVD.EN VOV-REF3 +10%VREF VCOMV SET0 VOV-REF2 +5.7%VREF VOV-REF1 +2.9%VREF Duty VUV-REF1 -2.9%VREF VUV-REF2 Figure 19. No to full load transient -5.7%VREF SET1 SET0 SET1 SET0 SET0 SET1 VUV-REF3 -10%VREF VEAV VOVD.EN2 Digital PF Optimizer VOVD.EN1 VOVD.DIS VREF VCOMV Duty Figure 20. Full to no load transient As line voltage increases and output load decreases, PF is degraded due to the effect of EMI filter capacitor charging/discharging current. Input current is the sum of EMI Filter capacitor current and flyback input current. Whether the flyback input current is exactly in-phase sinusoidal current with line voltage, 90 phase shifted EMI filter cap current worsens displacement factor of the overall system input current. The ON semiconductor's proprietary PF optimizer accurately compensates the EMI filter capacitor current and improves PF more than 0.1 at high line and half load condition. The calculation coefficient in the PF optimizer is externally programmable by supplying a certain level of voltage at PF pin with external resistive divider from 5 V www.onsemi.com 11 SET0 SET1 FL7740 BIAS pin. Before 1st switching, FL7740 converts the PF voltage into digital value without switching noise and keeps the digital value for the coefficient until UVLO is triggered. Recommended VPF is in Equation 1, where LM is magnetizing inductance and CEMI is total EMI filter capacitance. VPF = 5 x 10 9 x LM x C EMI + 1.5 VIN IFLYBACK IIN IEMI.CAP GATE TON Figure 21. With PF Optimizer VIN IFLYBACK (=Ideal IIN) IIN Leading phase IEMI.CAP VDD regulation for 3 sec VDD 19 V 17 V 16 V 7.75 V (eq. 1) As VPF increases, the coefficient in the PF optimizer calculation is larger with better PF, but THD is worse due to the input current distortion at input voltage zero cross. Therefore, VPF adjustment by changing PF resistors is recommended to bring the best PF and THD performance to meet user's target. When VPF is lower than 1.5 V, PF optimizer is disabled. Ideal IIN with released protection. When VDD voltage is up again to 16 V VDD-ON, FL7740 begins startup sequence. GATE IC restart IC reset Protection triggered Figure 23. Auto Restart * Output Over Voltage Protection Output over voltage is hardly triggered due to the powering limit by dynamic function. But, in the abnormal condition, output OVP is triggered when VEAV is higher than 4.0 V @ SET0 / 4.2 V @ SET1 for 4 switching cycles or VDD voltage is higher than 25 V for 10 us delay. * Output Short Protection At output short condition, VEAV is less than 0.7 V. If this condition lasts for continuous 35 ms switching time, OSP is triggered. * Over Current Protection When CS voltage is higher than 1.8 V over the 1.2 V pulse-by-pulse current limit, protection is immediately triggered. OCP protects output diode short, sensing resistor open and transformer saturation condition. * Sensing Resistor Short Protection 1st switching is 0.2 V current mode. If CS doesn't reach over 75 mV threshold during 1st turn-on time, SRSP is triggered. Max. turn-on time at 1st switching is inversely proportional to input voltage to limit the primary peak current. * Over Load Protection At over load condition, CS reaches to 1.2 V pulse-bypulse current limit. FL7740 generates internal ZC (Zero Cross) signal and OLP is triggered if the event (1.2V current limit event between the two close ZC signals) is occurred for consecutive 60 ZC signals. VIN GATE TON 1.2 V current limit event CS Figure 22. Without PF Optimizer ZC OLP Count 0 0 1 2 3 57 58 59 Protection 60 OLP * Auto-restart Once protection is triggered, FL7740 terminates switching and internal 3 sec counter makes delay time. In 3 sec, VDD voltage is regulated between 17 V and 19 V by internal HV biasing not to fall in UVLO. After 3 sec, VDD falls down to 7.75 V VDD-OFF and IC is reset * Figure 24. Over Load Protection Thermal Shut Down When internal junction temperature is higher than 150C, TSD is triggered and protection is released when the junction temperature drops under 120C. www.onsemi.com 12 FL7740 Single layer PCB layout guidance AC Input Bridge diode Secondary DC-DC Converter Dimming Signal RHV1 PG (Power GND) PG line goes under RHV1 RHV2 SG (Signal GND) 5 MCU module VDD line goes under RHV2 RHV3 SG line goes under RHV3 FL7740 HV NC 4 VDD 3 COMV 2 GND 1 GATE 1 G-GATE and S-GND distance should be short. 2 SG and PG are connected close at GND pin. RGATE CS PF VS CS line goes under RGATE G D S BIAS 3 4 5 COMV,BIAS,PF,VS circuit ground and aux. winding VDD circuit ground are connected close at GND pin. SMD filter cap is connected close at VDD and GND pin. Powering lines (Drain and PG) are closely placed and away from FL7740 control circuits. ORDERING INFORMATION Device Package Shipping FL7740MX 10 Lead SOIC, JDEC MS-012, 150" Narrow Body Tape and Reel www.onsemi.com 13 FL7740 PACKAGE DIMENSIONS ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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