FL7740
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10
Primary Side Constant Voltage Regulation
FL7740 utilizes auxiliary winding to detect output
voltage during secondary side diode conduction time
(=TDIS). The true output voltage le vel wi t hout secondary
diode forward voltage drop is at the end of secondary
diode c onduction time. In order to detect the right outp ut
voltage, 85% of TDIS at pre vious switching c ycle is
sampling ti me for VEAV detection at current switc hing
cycle.
S/H
VS V
REF
Error
Amp.
V
EAV
COMV
T
DIS
detection
Duty
Control
N
AUX
V
IN.PK
Figure 15. Primary Side Regulation
VS
GATE
85% TDIS
at previous
switching
TDIS
VEAV sampling
Figure 16. VEAV Detection
The sampled VEAV is compared with 3.5 V VREF at the
input of the erro r amplifier. Several hundreds nF
capacitor is connected to the output of the error amplifier
at COMV pin to keep feedback loop slow in PFC control.
COMV voltage controls duty to regulate VEAV same as
VREF in the system.
Turn-on time is controlled by both COMV voltage and
VIN.PK information in line feedforward operation in order
to keep the constant COMV v oltage in the wide inp ut
voltage range. So, turn-on time is proportional to COMV
voltage and inversely proportional to VIN.PK.
Startup
After plug-in, e xter nal VDD capacitor is quickly
char ged by inter nal HV b iasing sup ply. Even after VDD
is higher t han 16 V VDD-ON, inte rnal HV biasing is still
enabled for 500 ms, so HV biasing can relieve VDD
capacito r discharging until auxiliary winding b ui ld s up
VDD voltage.
In order to speed up large output capacitor charging
without overshoot, FL7740 starts with proportional gain
duri ng star tup seque nce (SS1 + SS2) by using int erna l
resistive load at the output of the e r ror amplifier.
In SS1, CCM prevent operation is enabled for the initial
2 ms. When output voltage is 0 V, deep CCM could be
entered at initial startup and C S c ould touch OCP level
with startup failur e. So, pulse-by-pulse current limit is
0.2 V and switching fre quency is 2 2 kHz d uring the 2 ms
CCM prevent time. Also, duty is gradually increased for
26 ms for soft startup. Once 5 V pulled-up COMV
voltage drops less than 4.5 V as VEAV is close to V REF,
SS1 is ended. Maximum SS1 time is limited up to 100
ms.
In SS2, VCOMV drops from 5 V and goe s into p-gain
steady state in which VEAV is little bit lower than VREF
due to the error amplifier inpu t e rror in p-gain. Once p-
gain stead y state is settled down in 45 ms, SS2 is
finished at min. VCOMV range not to make oversho ot
when transitio ning to i-gain after SS2. FL7740 ends SS2
by moni toring VIN 1.5 ms after VIN.PK detection moment
where VCOMV is general ly in the min. range.
V
COMV
Duty
V
EAV
V
IN
V
REF
Startup time by P-gain I-gain
45 ms
4.5 V
26 ms soft start
2 ms CCM prevent
5.0 V
V
IN.PK
1.5 ms
SS1 SS2
Figure 17. Startup Sequence
Dynamic CV Regulation
Due to the narrow loop bandwidth, PFC controller
gener ally does not guarantee good CV regulation at load
transient. Espe c ia lly in second a ry side regulation,
primary side controller does not know the output voltage
level and it only monitors the output of feedback signal
through opto-coupler. The refore, out put voltage
undershoot is severely happened at no to full load
transient in the co nventional S SR PFC control.
In order to overcome this, FL7740 utilizes the benefit of
P S R wit h ON semiconductor’s proprietary dynamic duty
control by monitoring the output voltage. For example,
when V EAV i s l ess tha n VUVD.EN (Under Volta ge Dynamic
Enable threshold), duty is quickly increa sed not to allo w
undershoot anymore. Once VEAV rises hig her than
VUVD.DIS (Under Voltage Dynamic Disable threshold),
duty quickly drops and follows COMV voltage . During
the VEAV hi ccup o peration, COMV voltage slowly
increases and dynamic operation is terminated when
COMV voltage is close to stea dy state level.