74LVC74A Dual D-type flip-flop with set and reset; positive-edge trigger Rev. 06 -- 4 June 2007 Product data sheet 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. 2. Features n n n n n n 5 V tolerant inputs for interlacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard JESD8-B/JESD36 ESD protection: u HBM JESD22-A114D exceeds 2000 V u CDM JESD22-C101C exceeds 1000 V n Specified from -40 C to +85 C and -40 C to 125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC74AD -40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LVC74ADB -40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LVC74APW -40 C to +125 C 74LVC74ABQ -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1 quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 4. Functional diagram 4 2 3 1SD 1D 1CP SD Q D Q 4 10 3 1SD 2SD 2 2 12 3 11 SD 1Q 1D Q D 2D 2Q 1CP CP 2CP FF 1Q Q 2Q RD 1 5 9 10 6 8 11 12 13 1RD 2RD 1 13 Fig 1. Logic symbol 1Q 6 RD S 5 1 C1 1D 6 10 1RD 2SD R 12 S 9 11 C1 2D 2CP SD Q D 2Q 9 CP FF 1D Q 8 2Q 8 RD R 13 mna419 mna418 5 CP FF 4 1Q Fig 2. IEC logic symbol 2RD mna420 Fig 3. Functional diagram Q C C C C C C D Q C C RD SD CP mna421 C C Fig 4. Logic diagram for one flip-flop 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 2 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 5. Pinning information 14 VCC 1D 2 13 2RD terminal 1 index area 1Q 5 74 11 2CP 12 2D 1SD 4 74 11 2CP 1Q 5 GND(1) 10 2SD 1Q 6 10 2SD 9 1Q 6 9 2Q 8 4 13 2RD 3 GND 7 8 2Q 2Q 1SD 12 2D 2 7 3 1D 1CP GND 1CP 14 VCC 1 1 1RD 1RD 5.1 Pinning 001aad106 2Q 001aad107 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration for SO14 and (T)SSOP14 Fig 6. Pin configuration for DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1RD 1 asynchronous reset-direct input (active LOW) 1D 2 data input 1CP 3 clock input (LOW-to-HIGH, edge-triggered) 1SD 4 asynchronous set-direct input (active LOW) 1Q 5 true output 1Q 6 complement output GND 7 ground (0 V) 2Q 8 complement output 2Q 9 true output 2SD 10 asynchronous set-direct input (active LOW) 2CP 11 clock input (LOW-to-HIGH, edge-triggered) 2D 12 data input 2RD 13 asynchronous reset-direct input (active LOW) VCC 14 supply voltage 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 3 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 6. Functional description Table 3. Function table[1] Input Output nSD nRD nCP nD nQ nQ L H X X H L H L X X L H L L X X H H [1] H = HIGH voltage level L = LOW voltage level X = don't care Table 4. Function table[1] Input Output nSD nRD nCP nD nQn+1 nQn+1 H H L L H H H H H L [1] H = HIGH voltage level L = LOW voltage level = LOW-to-HIGH transition Qn+1 = state after the next LOW-to-HIGH CP transition X = don't care 7. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions VI < 0 V [1] VO > VCC or VO < 0 V [2] Min Max Unit -0.5 +6.5 V -50 - mA -0.5 +6.5 V - 50 mA -0.5 VCC + 0.5 V - 50 mA VO output voltage IO output current ICC supply current - 100 mA IGND ground current -100 - mA Tstg storage temperature -65 +150 C - 500 mW total power dissipation Ptot VO = 0 V to VCC Tamb = -40 C to +125 C [3] [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO14 packages: above 70 C the value of Ptot derates linearly with 8 mW/K. For (T)SSOP14 packages: above 60 C the value of Ptot derates linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 C the value of Ptot derates linearly with 4.5 mW/K. 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 4 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 8. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC supply voltage for maximum speed performance 2.7 - 3.6 V for low-voltage applications 1.2 - 3.6 V VI input voltage 0 - 5.5 V Vo output voltage 0 - VCC V Tamb ambient temperature -40 - +125 C t/V input transition rise and fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V 9. Static characteristics Table 7. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter -40 C to +85 C Conditions -40 C to +125 C Min Typ[1] Max Min Max - - VCC - Unit VIH HIGH-level input voltage VCC = 1.2 V VCC VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VIL LOW-level input voltage VCC = 1.2 V - - 0 - 0 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V HIGH-level output voltage VI = VIH or VIL - VCC - 0.3 - V VOH LOW-level output voltage VOL IO = -100 A; VCC = 2.7 V to 3.6 V VCC - 0.2 V IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 A; VCC = 2.7 V to 3.6 V - - 0.2 - 0.3 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V VI = VIH or VIL II input leakage VCC = 3.6 V; VI = 5.5 V or GND current - 0.1 5 - 20 A ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 A ICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 5 500 - 5000 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 4.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 C. 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 5 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 10. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9. Symbol Parameter propagation delay tpd -40 C to +85 C Conditions -40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V - 15 - - - ns VCC = 2.7 V 1.0 2.7 6.0 1.0 7.5 ns VCC = 3.0 V to 3.6 V 1.0 2.5 5.2 1.0 6.5 ns VCC = 1.2 V - 15 - - - ns VCC = 2.7 V 1.0 3.2 6.4 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.5 5.4 1.0 7.0 ns VCC = 1.2 V - 15 - - - ns VCC = 2.7 V 1.0 3.2 6.4 1.0 8.0 ns VCC = 3.0 V to 3.6 V 1.0 2.5 5.4 1.0 7.0 ns VCC = 2.7 V 3.3 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns nCP to nQ, nQ; see Figure 7 [2] nSD to nQ, nQ; see Figure 8 nRD to nQ, nQ; see Figure 8 pulse width tW clock HIGH or LOW; see Figure 7 set or reset LOW; see Figure 8 recovery time trec set-up time tsu hold time th maximum frequency fmax tsk(o) CPD VCC = 2.7 V 3.3 - - 4.5 - ns VCC = 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns VCC = 2.7 V 1.5 - - 1.0 - ns VCC = 3.0 V to 3.6 V +1.0 -3.0 - 1.0 - ns VCC = 2.7 V 2.2 - - 2.2 - ns VCC = 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns VCC = 2.7 V 1.0 - - 1.0 - ns VCC = 3.0 V to 3.6 V +1.0 -0.2 - 1.0 - ns - set or reset; see Figure 8 nD to nCP; see Figure 7 nD to nCP; see Figure 7 nCP; see Figure 7 VCC = 2.7 V 83 - VCC = 3.0 V to 3.6 V 150 250 - - - 15 output skew time VCC = 3.0 V to 3.6 V [3] power dissipation capacitance [4] per flip-flop; VI = GND to VCC VCC = 3.3 V 66 - MHz 120 - MHz 1.0 - 1.5 ns - - - pF [1] Typical values are measured at Tamb = 25 C. For VCC = 3.0 V to 3.6 V range, typical values are measured at 3.3 V. [2] tpd is the same as tPLH and tPHL. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 6 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching (CL x VCC2 x fo) = sum of the outputs 11. AC waveforms VI VM nD input GND th th t su t su 1/fmax VI VM nCP input GND tW t PHL t PLH VOH VM nQ output VOL VOH nQ output VM VOL t PLH t PHL mna422 The shaded areas indicate when the input is permitted to change for predictable output performance. VM = 1.5 V at VCC 2.7 V; VM = 0.5 x VCC at VCC < 2.7 V; VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, and the maximum frequency 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 7 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger VI VM nCP input GND t rec VI VM nSD input GND tW tW VI VM nRD input GND t PLH t PHL VOH nQ output VM VOL VOH VM nQ output VOL t PHL t PLH mna423 VM = 1.5 V at VCC 2.7 V; VM = 0.5 x VCC at VCC < 2.7 V; VOL and VOH are typical output voltage levels that occur with the output load. Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths, and the nRD to nCP recovery time 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 8 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC PULSE GENERATOR VI VO DUT RT CL RL 001aaf615 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 9. Load circuitry for switching times Table 9. Test data Supply voltage Input Load VI tr, tf CL RL 1.2 V VCC 2.5 ns 50 pF 500 2.7 V 2.7 V 2.5 ns 50 pF 500 3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 9 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.05 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 10. Package outline SOT108-1 (SO14) 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 10 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 o 0 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 11. Package outline SOT337-1 (SSOP14) 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 11 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 o 0 o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 12. Package outline SOT402-1 (TSSOP14) 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 12 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 e 0.5 e1 L v w y y1 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT762-1 (DHVQFN14) 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 13 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC74A_6 20070604 Product data sheet - 74LVC74A_5 Modifications: * Change of hold time in Table 8 "Dynamic characteristics". Minimum values changed to 1.0 ns. 74LVC74A_5 20070525 Product data sheet - 74LVC74A_4 74LVC74A_4 20030526 Product specification - 74LVC74A_3 74LVC74A_3 20020618 Product specification - 74LVC74A_2 74LVC74A_2 19980617 Product specification - 74LVC74A_1 74LVC74A_1 19980617 Product specification - - 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 14 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com 74LVC74A_6 Product data sheet (c) NXP B.V. 2007. All rights reserved. Rev. 06 -- 4 June 2007 15 of 16 74LVC74A NXP Semiconductors Dual D-type flip-flop with set and reset; positive-edge trigger 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 June 2007 Document identifier: 74LVC74A_6