(R) PRELIMINARY SP3508 Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver with Programmable DCE/DTE and Termination Resistors FEATURES Fast 20Mbps Differential Transmission Rates Internal Transceiver Termination Resistors for V.11 & V.35 Interface Modes: RS-232 (V.28) X.21 (V.11) RS-449/V.36 (V.10 & V.11) Now Available in Lead Free Packaging Refer to page 9 for pinout EIA-530 (V.10 & V.11) EIA-530A (V.10 & V.11) V.35 (V.35 & V.28) Protocols are Software Selectable with 3-Bit Word Eight (8) Drivers and Eight (8) Receivers Termination Network Disable Option Internal Line or Digital Loopback for Diagnostic Testing Certified conformance to NET1/NET2 and TBR-1 TBR-2 by TUV Rheinland (TBR2/30451940.001/04) Easy Flow-Through Pinout +3.3V Only Operation Individual Driver and Receiver Enable/Disable Controls Operates in either DTE or DCE Mode APPLICATIONS Router Frame Relay CSU DSU PBX Secure Communication Terminals DESCRIPTION The SP3508 is a monolithic device that supports eight (8) popular serial interface standards for Wide Area Network (WAN) connectivity. The SP3508 is fabricated using a low power BiCMOS process technology, and incorporates a Sipex regulated charge pump allowing +3.3V only operation. Sipex's patented charge pump provides a regulated output of +5.5V, which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and eight (8) receivers can be configured via software for any of the above interface modes at any time. The SP3508 requires no additional external components for compliant operation for all of the eight (8) modes of operation other than six capacitors used for the internal charge pump. All necessary termination is integrated within the SP3508 and is switchable when V.35 drivers and V.35 receivers, or when V.11 receivers are used. The SP3508 provides the controls and transceiver availability for operating as either a DTE or DCE. Additional features with the SP3508 include internal loopback that can be initiated in any of the operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are internally connected to driver inputs creating an internal signal path bypassing the serial communications controller for diagnostic testing. The SP3508 also includes a latch enable pin with the driver and receiver address decoder. The internal V.11 or V.35 termination can be switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and receivers in the SP3508 include separate enable pins for added convenience. The SP3508 is ideal for WAN serial ports in networking equipment such as routers, access concentrators, network muxes, DSU/CSU's, networking test equipment, and other access devices. Applicable U.S. Patents-5,306,954; and others patents pending Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 1 (c) Copyright 2004 Sipex Corporation ABSOLUTE MAXIMUM RATINGS VCC ................................................................................................ +7V Input Voltages: Logic ................................................ -0.3V to (VCC+0.5V) Drivers ............................................. -0.3V to (VCC+0.5V) Receivers ........................................................... 15.5V Output Voltages: Logic ................................................ -0.3V to (VCC+0.5V) Drivers ................................................................... 12V Receivers ........................................ -0.3V to (VCC+0.5V) Storage Temperature ................................................ -65C to +150C Power Dissipation ................................................................. 1520mW (derate 19.0mW/C above +70C) Package Derating: oJA ................................................................................................................. 36.9 C/W oJC .................................................................................................................... 6.5 C/W These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. STORAGE CONSIDERATIONS 48 hours or stored in an environment at or below 20%RH. If the above conditions cannot be followed, the parts should be baked for four hours at 125C in order to remove moisture prior to soldering. Sipex ships the 100-pin LQFP in Dry Vapor Barrier Bags with a humidity indicator card and desiccant pack. The humidity indicator should be below 30%RH. Due to the relatively large package size of the 100-pin quad flatpack, storage in a low humidity environment is preferred. Large high density plastic packages are moisture sensitive and should be stored in Dry Vapor Barrier Bags. Prior to usage, the parts should remain bagged and stored below 40C and 60%RH. If the parts are removed from the bag, they should be used within ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS LOGIC INPUTS VIH V V V V 15 V per Figure 1 15 V per Figure 2 100 mA per Figure 4 per Figure 5 0.8 VIL 2.0 LOGIC OUTPUTS 0.4 VOL VOH VCC 0.6 VCC 0.3 IOUT= - 3.2mA IOUT= 1.0mA V.28 DRIVER DC Parameters (Outputs) Outputs Open Circuit Voltage Loaded Voltage 5.0 Short-Circuit Current Power-Off Impedance 300 VCC = +3.3V for AC parameters V.28 DRIVER AC Parameters (Outputs) Transition Time 1.5 Instantaneous Slew Rate 30 s V/s Propagation Delay: tPHL 0.5 1.0 3.0 s Propagation Delay: tPLH 0.5 1.0 3.0 s Max.Transmission Rate 120 230 kbps Date: 10/12/04 per Figure 6, +3V to -3V per Figure 3 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 2 (c) Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.28 RECEIVER DC Parameters (Inputs) Input Impedance 3 Open-Circuit Bias HIGH Threshold 1.7 LOW Threshold 0.8 7 k per Figure 7 +2.0 V per Figure 8 3.0 V V 1.2 VCC = +3.3V for AC parameters V.28 RECEIVER AC Parameters Propagation Delay: tPHL 100 500 ns Propagation Delay: tPLH 100 500 ns Max Transmission Rate 120 235 kbps V.10 DRIVER DC Parameters (Outputs) Open Circuit Voltage Test-Terminated Voltage 4.0 6.0 0.9VOC Short-Circuit Current 150 Power-Off Current 100 V per Figure 9 V per Figure 10 mA per Figure 11 A per Figure 12 VCC = +3.3V for AC parameters V.10 DRIVER AC Parameters (Outputs) Transition Time 200 ns Propagation Delay: tPHL 100 500 ns Propagation Delay: tPLH 100 500 ns kbps Max Transmission Rate 120 per Figure 13; 10% to 90% V.10 RECEIVER DC Parameters (Inputs) Input Current -3.25 Input Impedance +3.25 4 Sensitivity 0.3 mA k V VCC = +3.3V for AC parameters V.10 RECEIVER AC Parameters Propagation Delay: tPHL 120 250 ns Propagation Delay: tPLH 120 250 ns kbps Max Transmission Rate Date: 10/12/04 per Figures 14 and 15 120 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 3 (c) Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS V.11 DRIVER DC Parameters (Outputs) V per Figure 16 2.0 V per Figure 17 0.5(VOC) V Open Circuit Voltage (VOC) 6.0 Test Terminated Voltage Balance 0.4 V per Figure 17 Offset +3.0 V per Figure 17 Short-Circuit Current 150 mA per Figure 18 Power-Off Current 100 A per Figure 19 VCC = +3.3V for AC parameters V.11 DRIVER AC Parameters (Outputs) Transition Time 10 ns per Figures 21 and 35; 10% to 90% Using CL = 50pF; Propagation Delay: tPHL 30 60 ns per Figures 32 and 35 Propagation Delay: tPLH 30 60 ns per Figures 32 and 35 Differential Skew 5 10 ns per Figures 32 and 35 Mbps +7 V 0.2 V Max.Transmission Rate 20 V.11 RECEIVER DC Parameters (Inputs) Common Mode Range -7 Sensitivity Input Current -3.25 3.25 Current w/ 100 Termination Input Impedance mA 60.75 mA 4 per Figure 20 and 22; power on or off per Figure 23 and 24 k VCC = +3.3V for AC parameters Using CL = 50pF V.11 RECEIVER AC Parameters Propagation Delay: tPHL 30 60 ns per Figures 32 and 37 Propagation Delay: tPLH 30 60 ns per Figures 32 and 37 Skew 5 10 ns per Figure 32 Max Transmission Rate Date: 10/12/04 20 Mbps SP3508 Enhanced WAN Multi-Mode Serial Transceiver 4 (c) Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS 1.20 V per Figure 16 0.66 V per Figure 25 V.35 DRIVER DC Parameters (Outputs) Open Circuit Voltage Test Terminated Voltage 0.44 0.6 V per Figure 25 +0.2VST V ST per Figure 25; VST = Steady state value Source Impedance 50 150 per Figure 26; ZS = V2/V1 x 50 Short-Circuit Impedance 135 165 per Figure 27 Offset Output Overshoot -0.2V- VCC = +3.3V for AC parameters V.35 DRIVER AC Parameters (Outputs) Transition Time 20 ns Propagation Delay: tPHL 30 60 ns per Figures 32 and 35; CL = 20pF Propagation Delay: tPLH 30 60 ns per Figures 32 and 35; CL = 20pF 5 ns per Figures 32 and 35; CL = 20pF Mbps mV Differential Skew Max.Transmission Rate 20 V.35 RECEIVER DC Parameters (Inputs) Sensitivity 50 200 Source Impedance 90 110 per Figure 29; ZS = V2/V1 x 50 Short-Circuit Impedance 135 165 per Figure 30 VCC = +5V for AC parameters V.35 RECEIVER AC Parameters Propagation Delay: tPHL 30 60 ns per Figures 32 and 37; CL = 20pF Propagation Delay: tPLH 30 60 ns per Figures 32 and 37; CL = 20pF Skew 5 10 ns per Figures 32; CL = 20pF Max.Transmission Rate 20 Mbps TRANSCEIVER LEAKAGE CURRENTS Driver Output 3-State Current Receiver Output 3-State Current Date: 10/12/04 200 1 10 A per Figure 31; Drivers disabled A DX = 111 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 5 (c) Copyright 2004 Sipex Corporation ELECTRICAL SPECIFICATIONS TA = 0 to 70C and VCC = 3.3V 5% unless otherwise noted. The denotes the specifications which apply over the full operating temperature range (-40C to +85C), unless otherwise specified. PARAMETER MIN. TYP. MAX. UNITS 3.15 3.3 3.45 V CONDITIONS POWER REQUIREMENTS VCC 1 A All ICC values are with VCC = +3.3V V.28/RS-232) 95 mA fIN = 230kbps; Drivers active & loaded (V.11/RS-422) 230 mA fIN = 20Mbps; Drivers active & loaded (EIA-530 & RS-449) 270 mA fIN = 20Mbps; Drivers active & loaded (V.35) 170 mA V.35 @ fIN = 20Mbps, V.28 @ 230kbps ICC (No Mode Selected) Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 6 (c) Copyright 2004 Sipex Corporation OTHER AC CHARACTERISTICS TA = 0 to 70C and VCC = +3.3V unless otherwise noted. PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state 0.70 0.40 0.20 0.40 5.0 2.0 2.0 2.0 s s s s CL = 100pF, Fig. 33 & 39; S1 closed CL = 100pF, Fig. 33 & 39; S2 closed CL = 100pF, Fig. 33 & 39; S1 closed CL = 100pF, Fig. 33 & 39; S2 closed RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state 0.15 0.20 0.20 0.15 2.0 2.0 2.0 2.0 s s s s CL = 100pF, Fig. 33 & 39; S1 closed CL = 100pF, Fig. 33 & 39; S2 closed CL = 100pF, Fig. 33 & 39; S1 closed CL = 100pF, Fig. 33 & 39; S2 closed RS-422/V.11 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state 2.80 0.10 0.10 0.10 10.0 2.0 2.0 2.0 s s s s CL = 100pF, Fig. 33 & 36; S1 closed CL = 100pF, Fig. 33 & 36; S2 closed CL = 15pF, Fig. 33 & 36; S1 closed CL = 15pF, Fig. 33 & 36; S2 closed V.35 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state 2.60 0.10 0.10 0.15 10.0 2.0 2.0 2.0 s s s s CL = 100pF, Fig. 33 & 36; S1 closed CL = 100pF, Fig. 33 & 36; S2 closed CL = 15pF, Fig. 33 & 36; S1 closed CL = 15pF, Fig. 33 & 36; S2 closed RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE RS-232/V.28 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state 0.12 0.10 0.10 0.10 2.0 2.0 2.0 2.0 s s s s CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed RS-423/V.10 tPZL; Tri-state to Output LOW tPZH; Tri-state to Output HIGH tPLZ; Output LOW to Tri-state tPHZ; Output HIGH to Tri-state 0.10 0.10 0.10 0.10 2.0 2.0 2.0 2.0 s s s s CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed CL = 100pF, Fig. 34 & 37; S1 closed CL = 100pF, Fig. 34 & 37; S2 closed Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 7 (c) Copyright 2004 Sipex Corporation OTHER AC CHARACTERISTICS: Continued TA = 0 to 70C and VCC = +3.3V unless otherwise noted. PARAMETER RS-422/V.11 tPZL; Tri-state to Output LOW MIN. TYP. MAX. UNITS 0.10 2.0 s tPZH; Tri-state to Output HIGH 0.10 2.0 s tPLZ; Output LOW to Tri-state 0.10 2.0 s tPHZ; Output HIGH to Tri-state 0.10 2.0 s V.35 tPZL; Tri-state to Output LOW 0.10 2.0 s tPZH; Tri-state to Output HIGH 0.10 2.0 s tPLZ; Output LOW to Tri-state 0.10 2.0 s tPHZ; Output HIGH to Tri-state 0.10 2.0 s CONDITIONS CL = 100pF, Fig. 34 & 38; S1 closed CL = 100pF, Fig. 34 & 38; S2 closed CL = 15pF, Fig. 34 & 38; S1 closed CL = 15pF, Fig. 34 & 38; S2 closed CL = 100pF, Fig. 34 & 38; S1 closed CL = 100pF, Fig. 34 & 38; S2 closed CL = 15pF, Fig. 34 & 38; S1 closed CL = 15pF, Fig. 34 & 38; S2 closed TRANSCEIVER TO TRANSCEIVER SKEW RS-232 Driver 100 100 RS-232 Receiver 20 20 RS-422 Driver 2 2 RS-422 Receiver 3 3 RS-423 Driver 5 5 RS-423 Receiver 5 5 (per Figures 32, 35, 37) ns [ (tphl )Tx1 - (tphl )Txn ] ns [ (tplh )Tx1 - (tplh )Txn] ns [ (tphl )Rx1 - (tphl )Rxn ] ns [ (tphl )Rx1 - (tphl )Rxn ] ns [ (tphl )Tx1 - (tphl )Txn ] ns [ (tplh )Tx1 - (tplh )Txn ] ns [ (tphl )Rx1 - (tphl )Rxn ] ns [ (tphl )Rx1 - (tphl )Rxn ] ns [ (tphl )Tx2 - (tphl )Txn ] ns [ (tplh )Tx2 - (tplh )Txn ] ns [ (tphl )Rx2 - (tphl )Rxn ] ns [ (tphl )Rx2 - (tphl )Rxn ] V.35 Driver ns ns ns ns V.35 Receiver Date: 10/12/04 4 4 6 6 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 8 [ (tphl )Tx1 - (tphl )Txn ] [ (tplh )Tx1 - (tplh )Txn ] [ (tphl )Rx1 - (tphl )Rxn ] [ (tphl )Rx1 - (tphl )Rxn] (c) Copyright 2004 Sipex Corporation 76 VDD 77 RCC(b) 78 VCC 79 RRC(a) 80 GND 81 RS(a) 82 VCC 83 RS(b) 84 GND 85 TR(a) 86 VCC 87 TR(b) 88 GND 89 ST(a) 90 VCC 91 ST(b) 92 GND 93 TT(a) 94 VCC 95 TT(b) 96 GND 97 SD(a) 98 VCC 99 SD(b) 100 VCC PINOUT GND 1 75 GND SDEN 2 74 C1P TTEN 3 73 VCC STEN 4 72 C2P RSEN 5 71 GND TREN 6 70 C1N RRCEN 7 69 C2N (R) RLEN 8 68 VSS1 LLEN 9 67 RL(a) RDEN 10 66 VCC RTEN 11 65 LL(a) TXCEN 12 64 TM(a) CSEN13 63 IC DMEN 14 62 RRT(a) RRTEN 15 61 RRT(b) SP3508 ICEN 16 TMEN 17 D0 18 D1 19 60 GNDV10 59 DM(a) 58 DM(b) 57 CS(a) D2 20 56 CS(b) D_LATCH 21 55 TXC(a) TERM_OFF 22 54 GND Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 9 RD(a) 50 RD(b) 49 VCC 48 GND 47 TM 46 RI 45 DCD_DTE 44 DSR 43 CTS 42 TXC 41 RXC 40 RXD 39 LL 38 RL 37 DCD_DCE 36 DTR 35 RTS 34 ST 33 TXCE 32 LOOPBACK 30 TXD 31 AVCC 29 51 RT(b) AGND 28 52 RT(a) GND 25 C3N 26 53 TXC(b) C3P 24 VSS2 27 VCC 23 (c) Copyright 2004 Sipex Corporation SP3508 Pin Designation Pin Number Pin Name Pin Number Pin Name 1 GND Signal Ground Description 51 RT(B) RxC Non-Inverting Input Description 2 SDEN TxD Driver Enable Input 52 RT(A) RxC Inverting Input 3 TTEN TxCE Driver Enable Input 53 TxC(B) TxC Non-Inverting Input 4 STEN ST Driver Enable Input 54 GND 5 RSEN RTS Driver Enable Input 55 TxC(A) 6 TREN DTR Driver Enable Input 56 CS(B) CTS Non-Inverting Input 7 RRCEN DCD Driver Enable Input 57 CS(A) CTS Inverting Input 8 RLEN RL Driver Enable Input 58 DM(B) DSR Non-Inverting Input 9 LLEN LL Driver Enable Input 59 DM(A) DSR Inverting Input 10 RDEN RxD Receiver Enable Input 60 GNDV10 11 RTEN RxC Receiver Enable Input 61 RRT(B) DCDDTE Non-Inverting Input 12 TxCEN TxC Receiver Enable Input 62 RRT(A) DCDDTE Inverting Input 13 CSEN CTS Receiver Enable Input 63 IC 14 DMEN DSR Receiver Enable Input 64 TM(A) TM Receiver Input 15 RRTEN DCDDTE Receiver Enable Input 65 LL(A) LL Driver Output Power Supply Input Signal Ground TxC Inverting Input V.10 Rx Reference Node RI Receiver Input 16 ICEN RI Receiver Enable Input 66 VCC 17 TMEN TM Receiver Enable Input 67 RL(A) RL Driver Output 18 D0 Mode Select Input 68 VSS1 -2xVCC Charge Pump Output 19 D1 Mode Select Input 69 C2N Charge Pump Capacitor 20 D2 Mode Select Input 70 C1N Charge Pump Capacitor 21 D_LATCH Decoder Latch Input 71 GND Signal Ground 72 C2P Charge Pump Capacitor 22 TERM_OFF Termination Disable Input 23 VCC Power Supply Input 73 VCC Power Supply Input 24 C3P Charge Pump Capacitor 74 C1P Charge Pump Capacitor 25 GND Signal Ground 75 GND Signal Ground 26 C3N Charge Pump Capacitor 76 VDD 2xVCC Charge Pump Output 27 VSS2 Minus VCC 77 RRC(B) DCDDCE Non-Inverting Output 28 AGND Signal Ground 78 VCC 29 AVCC Power Supply Input 79 RRC(A) 30 LOOPBACK Loopback Mode Enable Input 31 TxD 32 TxCE 33 ST Power Supply Input DCDDCE Inverting Output 80 GND Signal Ground TxD Driver TTL Input 81 RS(A) RTS Inverting Output TxCE Driver TTL Input 82 VCC Power Supply Input ST Driver TTL Input 83 RS(B) RTS Non-Inverting Output 34 RTS RTS Driver TTL Input 84 GND Signal Ground 35 DTR DTR Driver TTL Input 85 TR(A) DTR Inverting Output 36 DCD_DCE DCDDCE Driver TTL Input 86 VCC Power Supply Input 37 RL RL Driver TTL Input 87 TR(B) DTR Non-Inverting Output 38 LL LL Driver TTL Input 88 GND Signal Ground 39 RxD RxD Receiver TTL Output 89 ST(A) ST Inverting Output 40 RxC RxC Receiver TTLOutput 90 VCC Power Supply Input 41 TxC TxC Receiver TTL Output 91 ST(B) ST Non-Inverting Output 42 CTS CTS Receiver TTL Output 92 GND Signal Ground 43 DSR DSR Receiver TTL Output 93 TT(A) TxCE Inverting Output 44 DCD_DTE DCDDTE Receiver TTL Output 94 VCC Power Supply Input 45 RI RI Receiver TTL Output 95 TT(B) TxCE Non-Inverting Output 46 TM TM Receiver TTL Output 96 GND Signal Ground 47 GND Signal Ground 97 SD(A) TxD Inverting Output 48 VCC Power Supply Input 98 VCC 49 RD(B) RXD Non-Inverting Input 99 SD(B) 50 RD(A) RXD Inverting Input 100 VCC Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 10 Power Supply Input TxD Non-Inverting Output Power Supply Input (c) Copyright 2004 Sipex Corporation SP3508 Driver Table Driver Output Pin V.35 Mode EIA-530 Mode RS-232 Mode (V.28) EIA-530A Mode RS-449 Mode (V.36) X.21 Mode (V.11) Shutdown MODE (D0, D1, D2) 001 010 011 100 101 110 111 T1OUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxD(a) T1OUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxD(b) T2OUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxCE(a) T2OUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxCE(b) T3OUT(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxC_DCE(a) T3OUT(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxC_DCE(b) T4OUT(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z RTS(a) T4OUT(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z RTS(b) T5OUT(a) V.28 V.11 V.28 V.10 V.11 V.11 High-Z DTR(a) T5OUT(b) High-Z V.11 High-Z High-Z V.11 V.11 High-Z DTR(b) T6OUT(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z DCD_DCE(a) T6OUT(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z DCD_DCE(b) T7OUT(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z RL T8OUT(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z LL X.21 Mode (V.11) Shutdown Suggested Signal Suggested Signal Table 1. Driver Mode Selection SP3508 Receiver Table Receiver Input Pin V.35 Mode EIA-530 Mode RS-232 Mode (V.28) EIA-530A Mode RS-449 Mode (V.36) MODE (D0, D1, D2) 001 010 011 100 101 110 111 R1IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z RxD(a) R1IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z RxD(b) R2IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z RxC(a) R2IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z RxC(b) R3IN(a) V.35 V.11 V.28 V.11 V.11 V.11 High-Z TxC_DTE(a) R3IN(b) V.35 V.11 High-Z V.11 V.11 V.11 High-Z TxC_DTE(b) R4IN(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z CTS(a) R4IN(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z CTS(b) R5IN(a) V.28 V.11 V.28 V.10 V.11 V.11 High-Z DSR(a) R5IN(b) High-Z V.11 High-Z High-Z V.11 V.11 High-Z DSR(b) R6IN(a) V.28 V.11 V.28 V.11 V.11 V.11 High-Z DCD_DTE(a) R6IN(b) High-Z V.11 High-Z V.11 V.11 V.11 High-Z DCD_DTE(b) R7IN(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z RI R8IN(a) V.28 V.10 V.28 V.10 V.10 High-Z High-Z TM Table 2. Receiver Mode Selection Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 11 (c) Copyright 2004 Sipex Corporation TEST CIRCUITS A A VT 3k VOC C C Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage A A VT 7k Oscilloscope Isc C C Scope used for slew rate measurement. Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current VCC = 0V A A Ix 2V 3k Oscilloscope C C Figure 6. V.28 Driver Output Rise/Fall Times Figure 5. V.28 Driver Output Power-Off Impedance Date: 10/12/04 2500pF SP3508 Enhanced WAN Multi-Mode Serial Transceiver 12 (c) Copyright 2004 Sipex Corporation A A Iia 15V voc C C Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias A A 3.9k Vt 450 VOC C C Figure 9. V.10 Driver Output Open-Circuit Voltage Figure 10. V.10 Driver Output Test Terminated Voltage VCC = 0V A A Ix 0.25V Isc C C Figure 11. V.10 Driver Output Short-Circuit Current Date: 10/12/04 Figure 12. V.10 Driver Output Power-Off Current SP3508 Enhanced WAN Multi-Mode Serial Transceiver 13 (c) Copyright 2004 Sipex Corporation A A Iia 10V Oscilloscope 450 C C Figure 13. V.10 Driver Output Transition Time Figure 14. V.10 Receiver Input Current A V.10 RECEIVER +3.25mA VOCA 3.9k VOC VOCB -10V -3V B +3V +10V Maximum Input Current Versus Voltage C -3.25mA Figure 15. V.10 Receiver Input IV Graph Figure 16. V.11 Driver Output Open-Circuit Voltage A A Isa 50 VT 50 Isb B B V OS C C Figure 17. V.11 Driver Output Test Terminated Voltage Date: 10/12/04 Figure 18. V.11 Driver Output Short-Circuit Current SP3508 Enhanced WAN Multi-Mode Serial Transceiver 14 (c) Copyright 2004 Sipex Corporation VCC = 0V A Iia A Ixa 10V 0.25V B B C C VCC = 0V A A 0.25V 10V Ixb B Iib B C C Figure 19. V.11 Driver Output Power-Off Current Figure 20. V.11 Receiver Input Current A V.11 RECEIVER +3.25mA 50 Oscilloscope 50 -10V B 50 -3V VE +3V +10V Maximum Input Current Versus Voltage C -3.25mA Figure 22. V.11 Receiver Input IV Graph Figure 21. V.11 Driver Output Rise/Fall Time Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 15 (c) Copyright 2004 Sipex Corporation A V.11 RECEIVER Iia w/ Optional Cable Termination (100 to 150) i [mA] = V [V] / 0.1 6V 100 to 150 i [mA] = V [V] - 3) / 4.0 -6V -3V +3V B +6V i [mA] = V [V] - 3) / 4.0 C Maximum Input Current versus Voltage i [mA] = V [V] / 0.1 Figure 24. V.11 Receiver Input Graph with Termination A 6V A 100 to 150 50 VT Iib B 50 VOS B C C Figure 23. V.11 Receiver Input Current w/ Termination Figure 25. V.35 Driver Output Test Terminated Voltage V1 A A 50 24kHz, 550mVp-p Sine Wave V2 B ISC B 2V C C Figure 27. V.35 Driver Output Short-Circuit Impedance Figure 26. V.35 Driver Output Source Impedance Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 16 (c) Copyright 2004 Sipex Corporation V1 A A 50 50 24kHz, 550mVp-p Sine Wave Oscilloscope V2 50 B B 50 C C Figure 29. V.35 Receiver Input Source Impedance Figure 28. V.35 Driver Output Rise/Fall Time Any one of the three conditions for disabling the driver. A VCC = 0V 1 1 1 D2 D1 D0 VCC A IZSC 10V IZSC 10V Isc B Logic "1" B 2V C Figure 30. V.35 Receiver Input Short-Circuit Impedance Figure 31. Driver Output Leakage Current Test CL1 TIN B B A A ROUT CL2 15pF fIN (50% Duty Cycle, 2.5VP-P) Figure 32. Driver/Receiver Timing Test Circuit Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 17 (c) Copyright 2004 Sipex Corporation Output Under Test VCC S1 500 VCC S1 CRL CL 1K Test Point Receiver Output 1K S2 S2 Figure 34. Receiver Timing Test Load Circuit Figure 33. Driver Timing Test Load Circuit f > 10MHz; tR < 5ns; tF < 5ns DRIVER INPUT +3V 1.5V A DRIVER OUTPUT DIFFERENTIAL OUTPUT VB - VA 1.5V 0V tPLH tPHL VO 1/2VO 1/2VO B tDPLH VO+ 0V VO- tDPHL tR tF tSKEW = | tDPLH - tDPHL | Figure 35. Driver Propagation Delays Mx or Tx_Enable f = 1MHz; tR 10ns; tF 10ns +3V 1.5V 0V 1.5V tZL 5V 2.3V A, B VOL VOH A, B 2.3V 0V tLZ Output normally LOW 0.5V Output normally HIGH 0.5V tZH tHZ Figure 36. Driver Enable and Disable Times A-B f > 10MHz; tR < 5ns; tF < 5ns V0D2+ 0V 0V INPUT V0D2- OUTPUT VOH (VOH - VOL)/2 (VOH - VOL)/2 RECEIVER OUT VOL tPLH tPHL tSKEW = | tPHL - tPLH | Figure 37. Receiver Propagation Delays Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 18 (c) Copyright 2004 Sipex Corporation f = 1MHz; tR < 10ns; tF < 10ns DECx +3V 1.5V RxENABLE 0V 1.5V tZL +3.3V RECEIVER OUT VIL 1.5V tLZ Output normally LOW 0.5V Output normally HIGH 0.5V VIH RECEIVER OUT 1.5V 0V tZH tHZ Figure 38. Receiver Enable and Disable Times +3V f = 60kHz; tR < 10ns; tF < 10ns 1.5V 1.5V Tx_Enable 0V 0V TOUT VOL +3V Tx_Enable TOUT tLZ tZL VOL - 0.5V VOL - 0.5V Output LOW f = 60kHz; tR < 10ns; tF < 10ns 1.5V 1.5V 0V VOH tZH Output HIGH tHZ VOH - 0.5V 0V Figure 39. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 19 (c) Copyright 2004 Sipex Corporation Figure 40. Typical V.10 Driver Output Waveform. Figure 41. Typical V.11 Driver Output Waveform. Figure 42. Typical V.28 Driver Output Waveform. Figure 43. Typical V.35 Driver Output Waveform. Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 20 (c) Copyright 2004 Sipex Corporation (See pinout assignments for +3.3V (decoupling capacitor not shown) GND and VCC pins) C1 C2 1F 1F CVDD VCC C1+ 72 70 74 1F +3.3V C1- C2+ 69 C2- C3+ 24 1F 76 VDD Regulated Charge Pump C3- 26 VSS1 68 1F 29 AVCC Inverter VSS2 CVSS1 27 1F CVSS2 31 50 RD(a) C3 TxD 97 RxD RDEN SD(a) 39 10 99 RD(b) 49 2 SDEN RT(a) 52 32 TxCE SD(b) 93 RxC RTEN TT(a) 40 11 95 RT(b) 51 3 TxC(a) 55 33 TT(b) TTEN ST 89 TxC TxCEN TxC(b) CS(a) ST(a) 41 12 91 53 4 57 34 ST(b) STEN RTS 81 CTS CSEN RS(a) 42 13 83 CS(b) 56 5 DM(a) 59 35 RS(b) RSEN DTR 85 DSR DMEN TR(a) 43 14 87 DM(b) 58 6 RRT(a) 62 36 TR(b) TREN DCD_DCE 79 DCD_DTE RRTEN 15 77 61 RRT(b) RI ICEN RRC(b) 7 63 IC RRC(a) 44 RRCEN 37 45 RL 67 16 RL(a) 8 64 TM(a) TM TMEN RLEN 38 46 LL 65 LL(a) 17 9 18 19 20 21 22 RECEIVER TERMINATION NETWORK 30 V.35 MODE V.11 MODE LLEN D0 D1 SP3508 D2 V.10-GND AGND 60 28 D-LATCH TERM-OFF V.35 DRIVER TERMINATION NETWORK LOOPBACK GND 51ohms 124ohms 51ohms RX ENABLE V.35 MODE 51ohms 124ohms TX ENABLE 51ohms Figure 44. Functional Diagram Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 21 (c) Copyright 2004 Sipex Corporation FEATURES The SP3508 contains highly integrated serial transceivers that offer programmability between interface modes through software control. The SP3508 offers the hardware interface modes for RS-232 (V.28), RS-449/V.36 (V.11 and V.10), EIA-530 (V.11 and V.10), EIA-530A (V.11 and V.10), V.35 (V.35 and V.28) and X.21(V.11). The interface mode selection is done via three control pins, which can be latched via microprocessor control. There are four basic types of driver circuits - ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423), ITU-T-V.11 (RS-422), and CCITT-V.35. The V.28 (RS-232) drivers output single-ended signals with a minimum of +5V (with 3k & 2500pF loading), and can operate over 120kbps. Since the SP3508 uses a charge pump to generate the RS-232 output rails, the driver outputs will never exceed +10V. The V.28 driver architecture is similar to Sipex's standard line of RS232 transceivers. The SP3508 has eight drivers, eight receivers, and Sipex's patented on-board charge pump (5,306,954) that is ideally suited for wide area network connectivity and other multi-protocol applications. Other features include digital and line loopback modes, individual enable/disable control lines for each driver and receiver, failsafe when inputs are either open or shorted. The RS-423 (V.10) drivers are also single-ended signals which produce open circuit VOL and VOH measurements of +4.0V to +6.0V. When terminated with a 450 load to ground, the driver output will not deviate more than 10% of the open circuit value. This is in compliance of the ITU V.10 specification. The V.10 (RS-423) drivers are used in RS-449/V.36, EIA-530, and EIA-530A modes as Category II signals from each of their corresponding specifications. The V.10 driver can transmit over 120Kbps if necessary. THEORY OF OPERATION The SP3508 device is made up of 1) the drivers 2) the receivers 3) charge pumps 4) DTE/DCE switching algorithm The third type of drivers are V.11 (RS-422) differential drivers. Due to the nature of differential signaling, the drivers are more immune to noise as opposed to single-ended transmission methods. The advantage is evident over high speeds and long transmission lines. The strength of the driver outputs can produce differential signals that can maintain +2V differential output levels with a load of 100. The strength allows the SP3508 differential driver to drive over long cable lengths with minimal signal degradation. The V.11 drivers are used in RS449, EIA-530, EIA-530A and V.36 modes as Category I signals which are used for clock and data. Sipex's new driver design over its predecessors allow the SP3508 to operate over 20Mbps for differential transmission. 5) control logic. Drivers The SP3508 has eight enhanced independent drivers. Control for the mode selection is done via a three-bit control word into D0, D1, and D2. The drivers are prearranged such that for each mode of operation, the relative position and functionality of the drivers are set up to accommodate the selected interface mode. As the mode of the drivers is changed, the electrical characteristics will change to support the required signal levels. The mode of each driver in the different interface modes that can be selected is shown in Table 1. Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 22 (c) Copyright 2004 Sipex Corporation FEATURES will change to support the required serial interface protocols of the receivers. Table 1 shows the mode of each receiver in the different interface modes that can be selected. There are two basic types of receiver circuits--ITU-T-V .28 (RS-232) and ITU-T-V.11, (RS-422). The fourth type of drivers are V.35 differential drivers. There are only three available on the SP3508 for data and clock (TxD, TxCE, and TxC in DCE mode). These drivers are current sources that drive loop current through a differential pair resulting in a 550mV differential voltage at the receiver. These drivers also incorporate fixed termination networks for each driver in order to set the VOH and VOL depending on load conditions. This termination network is basically a "Y" configuration consisting of two 51 resistors connected in series and a 124 resistor connected between the two 50 resistors to GND. Filtering can be done on these pins to reduce common mode noise transmitted over the transmission line by connecting a capacitor to ground. The RS-232 (V.28) receiver is single-ended and accepts RS-232 signals from the RS-232 driver. The RS-232 receiver has an operating input voltage range of +15V and can receive signals downs to +3V. The input sensitivity complies with RS-232 and V.28 at +3V. The input impedance is 3k to 7k in accordance to RS232 and V.28. The receiver output produces a TTL/CMOS signal with a +2.4V minimum for a logic "1" and a +0.4V maximum for a logic "0". The RS-232 (V.28) protocol uses these receivers for all data, clock and control signals. They are also used in V.35 mode for control line signals: CTS, DSR, LL, and RL. The RS-232 receivers can operate over 120kbps. The drivers also have separate enable pins which simplifies half-duplex configurations for some applications, especially programmable DTE/DCE. The enable pins will either enable or disable the output of the drivers according to the appropriate active logic illustrated on Figure 44. The enable pins have internal pull-up and pulldown devices, depending on the active polarity of the receiver, that enable the driver upon poweron if the enable lines are left floating. During disabled conditions, the driver outputs will be at a high impedance 3-state. The second type of receiver is a differential type that can be configured internally to support ITU-T-V.10 and CCITT-V.35 depending on its input conditions. This receiver has a typical input impedance of 10k and a differential threshold of less than +200mV, which complies with the ITU-T-V.11 (RS-422) specifications. V.11 receivers are used in RS-449/V.36, EIA-530, EIA-530A and X.21 as Category I signals for receiving clock, data, and some control line signals not covered by Category II V.10 circuits. The differential V.11 transceiver has improved architecture that allows over 20Mbps transmission rates. The driver inputs are both TTL or CMOS compatible. All driver inputs have an internal pull-up resistor so that the output will be at a defined state at logic LOW ("0"). Unused driver inputs can be left floating. The internal pull-up resistor value is approximately 500k. Receivers The SP3508 has eight enhanced independent receivers. Control for the mode selection is done via a three-bit control word that is the same as the driver control word. Therefore, the modes for the drivers and receivers are identical in the application. Receivers dedicated for data and clock (RxD, RxC, TxC) incorporate internal termination for V.11. The termination resistor is typically 120 connected between the A and B inputs. The termination is essential for minimizing crosstalk and signal reflection over the transmission line . The minimum value is guaranteed to exceed 100, thus complying with the V.11 and RS-422 specifications. This resistor is invoked when the receiver is operating as a V.11 receiver, in modes EIA-530, EIA-530A, RS-449/V.36, and X.21. Like the drivers, the receivers are prearranged for the specific requirements of the synchronous serial interface. As the operating mode of the receivers is changed, the electrical characteristics Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 23 (c) Copyright 2004 Sipex Corporation FEATURES The same receivers also incorporate a termination network internally for V.35 applications. For V.35, the receiver input termination is a "Y" termination consisting of two 51 resistors connected in series and a 124 resistor connected between the two 50 resistors and GND. The receiver itself is identical to the V.11 receiver. All receivers include a fail-safe feature that outputs a logic high when the receiver inputs are open, terminated but open, or shorted together. For single-ended V.28 and V.10 receivers, there are internal 5k pull-down resistors on the inputs which produces a logic high ("1") at the receiver outputs. The differential receivers have a proprietary circuit that detect open or shorted inputs and if so, will produce a logic HIGH ("1") at the receiver output. The differential receivers can be configured to be ITU-T-V.10 single-ended receivers by internally connecting the non-inverting input to ground. This is internally done by default from the decoder. The non-inverting input is rerouted to V10GND and can be grounded separately. The ITU-T-V.10 receivers can operate over 120Kbps and are used in RS-449/V.36, E1A530, E1A-530A and X.21 modes as Category II signals as indicated by their corresponding specifications. All receivers include an enable/ disable line for disabling the receiver output allowing convenient half-duplex configurations. The enable pins will either enable or disable the output of the receivers according to the appropriate active logic illustrated on Figure 44. The receiver's enable lines include an internal pull-up or pull-down device, depending on the active polarity of the receiver, that enables the receiver upon power up if the enable lines are left floating. During disabled conditions, the receiver outputs will be at a high impedance state. If the receiver is disabled any associated termination is also disconnected from the inputs. CHARGE PUMP SP3508 uses an internal capacitive charge pump to generate Vdd and Vss. The design is Sipex patented (5,306,954) four-phased voltage shifting charge pump converters that converts the input voltage of 3.3V to nominal output voltages of +/-6V (Vdd & Vss1). SP3508 also includes an inverter block that inverts Vcc to -Vcc (Vss2). There is a free-running oscillator that controls the four phases of the voltage shifting. A description of each phase follows. 4-phased doubler pump Phase 1 -VSS1 charge storage -During this phase of the clock cycle, the positive side of capacitors C1 and C2 are initially charged to VCC. C1+ is then switched to ground and the charge in C1- is transferred to C2-. Since C2+ is connected to VCC, the voltage potential across capacitor C2 is now 2xVCC. VCC = +3V CVDD +3V + C1 - -3V C2 + - - + + - -3V VDD Storage Capacitor VSS1 Storage Capacitor CVSS1 Figure 45. Charge Pump - Phase 1. Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 24 (c) Copyright 2004 Sipex Corporation FEATURES Phase 2 -VSS1 transfer -Phase two of the clock connects the negative terminal of C2 to the VSS1 storage capacitor and the positive terminal of C2 to ground, and transfers the negative generated voltage to CVSS1. This generated voltage is regulated to -5.5V. Simultaneously, the positive side of the capacitor C1 is switched to VCC and the negative side is connected to ground. VCC = +3V CVDD C1 + - - + + C2 - + - -6V VDD Storage Capacitor VSS Storage Capacitor CVSS1 Figure 46. Charge Pump - Phase 2. Phase 3 -VDD charge storage -The third phase of the clock is identical to the first phase-the charge transferred in C1 produces -VCC in the negative terminal of C1 which is applied to the negative side of the capacitor C2. Since C2+ is at VCC, the voltage potential across C2 is 2xVCC. VCC = +3V +3V C1 + C2 - -3V CVDD + - - + + - -3V VDD Storage Capacitor VSS1 Storage Capacitor CVSS1 Figure 47.Charge Pump - Phase 3. Phase 4 -VDD transfer -The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers the generated 5.5V across C2 to CVDD, the VDD storage capacitor. This voltage is regulated to +5.5V. At the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of capacitor C1 is switched to VCC and the negative side is connected to ground, and the cycle begins again. The charge pump cycle will continue as long as the operational conditions for the internal oscillator are present. Since both V+ and V- are separately generated from VCC; in a no-load condition V+ and V- will be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the magnitude of V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump typically operates at 250kHz. The external capacitors can be as low as 1F with a 16V breakdown voltage rating. Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 25 (c) Copyright 2004 Sipex Corporation FEATURES VCC = +3V CVDD +6V C1 + C2 - + - - + + - VDD Storage Capacitor VSS1 Storage Capacitor CVSS1 Figure 48. Charge Pump - Phase 4. 2-phased inverter pump Phase 1 Please refer to figure below: In the first phase of the clock cycle, switches S2 and S4 are opened and S1 and S3 closed. This connects the flying capacitor, C3, from Vin to ground. C3 charge up to the input voltage applied at Vcc. Phase 2 In the second phase of the clock cycle, switches S2 and S4 are closed and S1 and S3 are opened. This connects the flying capacitor, C3, in parallel with the output capacitor, CVSS2. The Charge stored in C3 is now transferred to CVSS2. Simultaneously, the negative side of CVSS2 is connected to VSS2 and the positive side is connected to ground. With the voltage across CVSS2 smaller than the voltage across C3, the charge flows from C3 to CVSS2 until the voltage at the VSS2 equals -VCC. VSS2 = -VCC VCC S1 S2 C3 + + CVSS2 S4 S3 VSS2 Figure 49. Circuit for an Ideal Voltage Inverter. Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 26 (c) Copyright 2004 Sipex Corporation Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations RS-232 or V.24 EIA-530 RS-449 V.35 X.21 Signal Mnemo DB-25 Signal Mnemo DB-25 Signal Mnemo DB-37 Signal Mnemo M34 Signal Mnemo DB-15 Type nic Pin(F) Type nic Pin(F) Type Pin(F) Type nic nic Pin(F) Type nic Pin(F) V.28 BB 3 V.11 BB(A) 3 V.11 RD(A) 6 V.35 104 R V.11 R(A) 4 V.11 BB(B) 16 V.11 RD(B) 24 V.35 104 T V.11 R(B) 11 V.28 DD 17 V.11 DD(A) 17 V.11 RT(A) 8 V.35 115 V V.11 B(A) 7** V.11 DD(B) 9 V.11 RT(B) 26 V.35 115 X V.11 B(B) 14** V.28 DB 15 V.11 DB(A) 15 V.11 ST(A) 5 V.35 114 Y V.11 S(A) 6 V.11 DB(B) 12 V.11 ST(B) 23 V.35 114 AA V.11 S(B) 13 V.28 CB 5 V.11 CB(A) 5 V.11 CS(A) 9 V.28 106 D V.11 I(A) 5 V.11 CB(B) 13 V.11 CS(B) 27 V.11 I(B) 12 V.28 CC 6 V.11 CC(A) 6 V.11 DM(A) 11 V.28 107 E V.11 CC(B) 22 V.11 DM(B) 29 V.28 CF 8 V.11 CF(A) 8 V.11 RR(A) 13 V.28 109 F V.11 CF(B) 10 V.11 RR(B) 31 V.28 CE 22 V.28 125 J V.28 TM 25 V.10 TM 25 V.10 TM 18 V.28 142 NN V.11 V.11 V.11 V.11 BA(A) BA(B) DA(A) DA(B) 2 12 24 11 V.11 V.11 V.11 V.11 SD(A) SD(B) TT(A) TT(B) 4 22 17 35 V.35 V.35 V.35 V.35 103 103 113 113 P S U W V.11 V.11 V.11 V.11 T(A) T(B) X(A) X(B) 2 9 7** 14** V.11 V.11 V.11 V.11 CA(A) CA(B) CD(A) CD(B) 4 19 20 23 V.11 V.11 V.11 V.11 RS(A) RS(B) TR(A) TR(B) 7 25 12 30 V.28 105 C V.11 V.11 C(A) C(B) 3 10 V.28 108 H V.28 BA 2 V.28 DA 24 V.28 CA 4 V.28 CD 20 V.28 RL 21 V.10 RL 21 V.10 RL 14 V.28 140 N V.28 LL 18 V.10 LL 18 V.10 LL 10 V.28 141 L Date: 10/12/04 ** X.21 use either B() or X(), not both Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 27 (c) Copyright 2004 Sipex Corporation 27 Recommended Signals and Port Pin Assignments (c) Copyright 2004 Sipex Corporation SP3508 Multiprotocol Configured as DCE Interface to PortInterface to System Logic Connector Pin Pin Number Pin Mnemonic Circuit Pin Mnemonic Number 31 TxD Driver_1 SD(A) 97 2 SDEN SD(B) 99 32 TxCE Driver_2 TT(A) 93 3 TTEN TT(B) 95 33 ST Driver_3 ST(A) 89 4 STEN ST(B) 91 34 RTS Driver_4 RS(A) 81 5 RSEN RS(B) 83 35 DTR TR(A) Driver_5 85 6 TREN TR(B) 87 36 DCD_DCE RRC(A) Driver_6 79 7 RRCEN RRC(B) 77 37 RL RL(A) Driver_7 67 8 RLEN 38 LL LL(A) Driver_8 65 9 LLEN# 39 RxD RD(A) 50 Receiver_1 10 RDEN# RD(B) 49 40 RxC RT(A) 52 Receiver_2 11 RTEN# RT(B) 51 41 TxC TxC(A) 55 Receiver_3 12 TxCEN# TxC(B) 53 42 CTS CS(A) 57 Receiver_4 13 CSEN# CS(B) 56 43 DSR DM(A) 59 Receiver_5 14 DMEN# DM(B) 58 44 DCD_DTE RRT(A) 62 Receiver_6 15 RRTEN# RRT(B) 61 45 RI IC 63 Receiver_7 16 ICEN# 46 TM TM(A) 64 Receiver_8 17 TMEN SP3508 Enhanced WAN Multi-Mode Serial Transceiver DCE CONFIGURATION Driver_7 Pin Mnemonic SD(A) SD(B) TT(A) TT(B) ST(A) ST(B) RS(A) RS(B) TR(A) TR(B) RRC(A) RRC(B) RL(A) Driver_8 LL(A) 65 Receiver_1 Receiver_7 RD(A) RD(B) RT(A) RT(B) TxC(A) TxC(B) CS(A) CS(B) DM(A) DM(B) RRT(A) RRT(B) IC Receiver_8 TM(A) Circuit Driver_1 Driver_2 Driver_3 Driver_4 Driver_5 Driver_6 Receiver_2 Receiver_3 Receiver_4 Receiver_5 Receiver_6 V.28 105 C V.28 108 H 14 V.28 140 N 10 V.28 141 L 6 24 8 26 5 23 9 27 11 29 13 31 V.35 V.35 V.35 V.35 V.35 V.35 V.28 104 104 115 115 114 114 106 R T V X Y AA D V.28 107 E V.28 109 F V.28 125 J V.28 142 NN V.11 V.11 V.11 V.11 CA(A) CA(B) CD(A) CD(B) 4 19 20 23 V.11 V.11 V.11 V.11 RS(A) RS(B) TR(A) TR(B) 7 25 12 30 21 V.10 RL 21 V.10 RL 18 V.10 LL 18 V.10 LL BB 3 V.28 DD 17 V.28 DB 15 V.28 CB 5 V.28 CC 6 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 BB(A) BB(B) DD(A) DD(B) DB(A) DB(B) CB(A) CB(B) CC(A) CC(B) CF(A) CF(B) 3 16 17 9 15 12 5 13 6 22 8 10 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 RD(A) RD(B) RT(A) RT(B) ST(A) ST(B) CS(A) CS(B) DM(A) DM(B) RR(A) RR(B) V.28 CA 4 V.28 CD 20 V.28 RL V.28 LL 50 49 52 51 55 53 57 56 59 58 62 61 63 V.28 64 V.28 CF 8 V.28 CE 22 V.28 TM 25 V.10 TM 25 V.10 TM 18 Pin assignments and signal functions are subject to national or regional variation and proprietary / non-standard implementations V.11 V.11 C(A) C(B) 3 10 V.11 V.11 V.11 V.11 V.11 V.11 V.11 V.11 R(A) R(B) B(A) B(B) S(A) S(B) I(A) I(B) 4 11 7** 14** 6 13 5 12 ** X.21 use either B() or X(), not both Date: 10/12/04 Spare drivers and receivers may be used for optional signals (Signal Quality, Rate Detect, Standby) or may be disabled using individual enable pins for each driver and receiver X.21 V.35 RS-449 EIA-530 RS-232 or V.24 Signal Mnemo DB-25 Signal Mnemo DB-25 Signal Mnemo DB-37 Signal Mnemo M34 Signal Mnemo DB-15 Pin(M) nic Pin(M) Type nic Pin(M) Type nic Pin(M) Type nic Pin(M) Type nic Type 2 T(A) V.11 P 103 V.35 4 V.11 SD(A) 2 V.11 BA(A) 2 BA V.28 9 T(B) V.11 S 103 V.35 22 V.11 SD(B) 12 V.11 BA(B) 7** X(A) V.11 U 113 V.35 17 TT(A) V.11 24 V.11 DA(A) 24 DA V.28 14** X(B) V.11 W 113 V.35 35 TT(B) V.11 11 V.11 DA(B) Date: 06/14/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 28 (c) Copyright 2004 Sipex Corporation 28 Pin Mnemonic TxD SDEN TxCE TTEN ST STEN RTS RSEN DTR TREN DCD_DCE RRCEN RL RLEN LL LLEN# RxD RDEN# RxC RTEN# TxC TxCEN# CTS CSEN# DSR DMEN# DCD_DTE RRTEN# RI ICEN# TM TMEN Pin Number 97 99 93 95 89 91 81 83 85 87 79 77 67 (c) Copyright 2004 Sipex Corporation Pin Number 31 2 32 3 33 4 34 5 35 6 36 7 37 8 38 9 39 10 40 11 41 12 42 13 43 14 44 15 45 16 46 17 Recommended Signals and Port Pin Assignments SP3508 Enhanced WAN Multi-Mode Serial Transceiver DTE CONFIGURATION SP3508 Multiprotocol Configured as DTE Interface to PortConnector Interface to System Logic FEATURES TERM_OFF FUNCTION There are internal pull-up devices on D0, D1 and The SP3508 contains a TERM_OFF pin that disables all three receiver input termination networks regardless of mode. This allows the device to be used in monitor mode applications typically found in networking test equipment. D2, which allow the device to be in SHUTDOWN mode ("111") upon power up. However, if the device is powered-up with the D_LATCH at a logic HIGH, the decoder state of the SP3508 will be undefined. The TERM_OFF pin internally contains a pulldown device with an impedance of over 500k, which will default in a "ON" condition during power-up if V.35 receivers enable line and the SHUTDOWN mode from the decoder will disable the termination regardless of TERM_OFF. CTR1/CTR2 EUROPEAN COMPLIANCY As with all of Sipex's previous multi-protocol serial transceiver IC's the drivers and receivers have been designed to meet all the requirements to NET1/NET2 and TBR2 in order to meet CTR1/ CTR2 compliancy. The SP3508 is also tested inhouse at Sipex and adheres to all the NET1/2 physical layer testing and the ITU Series V specifications before shipment. Please note that although the SP3508, as with its predecessors, adhere to CRT1/CTR2 compliancy testing, any complex or usual configuration should be doublechecked to ensure CTR1/CTR2 compliance. Consult the factory for details. LOOPBACK FUNCTION The SP3508 contains a LOOPBACK pin that invokes a loopback path. This loopback path is illustrated in Figure 50. LOOPBACK has an internal pull-up resistor that defaults to normal mode during power up or if the pin is left floating. During loopback, the driver output and receiver input characteristics will still adhere to its appropriate specifications. DECODER AND D_LATCH FUNCTION The SP3508 contains a D_LATCH pin that latches the data into the D0, D1 and D2 decoder inputs. If tied to a logic LOW ("0"), the latch is transparent, allowing the data at the decoder inputs to propagate through and program the SP3508 accordingly. If tied to a logic HIGH ("1"), the latch locks out the data and prevents the mode from changing until this pin is brought to a logic LOW. Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 29 (c) Copyright 2004 Sipex Corporation 97 TxD 99 50 RxD 93 95 89 91 81 83 85 87 79 62 44 61 RL RI LL TM TxC(b) RS(a) RS(b) CS(a) CS(b) TR(a) TR(b) DM(a) DM(b) RRC(a) 36 77 DCD_DTE TxC(a) 43 58 DCD_DCE ST(b) 35 59 DSR RT(b) ST(a) 42 56 DTR RT(a) 34 57 CTS TT(b) 41 53 RTS TT(a) 33 55 TxC RD(b) 40 51 ST RD(a) 32 52 RxC SD(b) 39 49 TxCE SD(a) 31 37 67 45 63 38 65 46 64 RRC(b) RRT(a) RRT(b) RL(a) IC LL(a) TM(a) Figure 50. Loopback Path Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 30 (c) Copyright 2004 Sipex Corporation CVDD C1 C2 1F 1F 1F +3.3V 10F 76 VDD 74 C1+ 70 72 69 C1- C2+ C2- C3+ 24 C3- 26 VCC VSS1 +3.3V Charge Pump Section 29 AV CC 31 +3.3V DCE/DTE VSS2 CVSS1 27 SD(a) 97 TxD SD(b) 99 TxCE 33 ST 34 RTS TT(a) 93 TT(b) 95 RS(a) 81 RS(b) 83 TR(a) 85 DTR 36 DCD_DCE 37 RL RL(a) 67 38 LL LL(a) 65 39 RxD 40 RxC RT(a) 52 RT(b) 51 41 TxC TxC(a) 55 TxC(b) 53 42 CTS CS(a) 57 CS(b) 56 43 DSR DM(a) 59 DM(b) 58 44 DCD_DTE RRT(a) 62 RRT(b) 61 45 RI IC 63 46 TM TM(a) 64 11 12 13 14 15 16 17 TR(b) 87 RRC(a) 79 TXD_RXD_A TXD_RXD_B TXCE_TXC_A TXCE_TXC_B 4 (V.11, V.28) 19 (V.11) 20 (V.11, V.28) 23 (V.11) RTS_CTS_A RTS_CTS_B DTR_DSR_A DTR_DSR_B 21 (V.10, V.28) RL_RI 18 (V.10, V.28) LL_TM 3 (V.11, V.35, V.28) 16 (V.11, V.35) 17 (V.11, V.35, V.28) 9 (V.11, V.35) 15 (V.11, V.35, V.28) 12 (V.11, V.35) 5 (V.11, V.28) 13 (V.11) 6 (V.11, V.28) 22 (V.11) 8 (V.11, V.28) 10 (V.11) RXD_TXD_A RXD_TXD_B RXC_TXCE_A RXC_TXCE_B *TXC_RXC_A *TXC_RXC_B CTS_RTS_A CTS_RTS_B DSR_DTR_A DSR_DTR_B DCD_DCD_A DCD_DCD_B 22 (V.10, V.28) RI_RL 25 (V.10, V.28) LL_TM RRC(b) 77 RD(a) 50 RD(b) 49 SDEN TTEN STEN RSEN TREN RRCEN RLEN LLEN Signal (DTE_DCE) 2 (V.11, V.35, V.28) 14 (V.11, V.35) 24 (V.11, V.35, V.28) 11 (V.11, V.35) ST(a) 89 ST(b) 91 35 10 DB-26 Serial Port Connector Pins CVSS2 Transceiver Section 32 2 3 4 5 6 7 8 9 1F C3 68 Logic Section D0 SP3508CF D1 D2 D_LATCH TERM_OFF LOOPBACK RDEN RTEN TxCEN CSEN DMEN RRTEN ICEN TMEN AGND 18 19 20 21 22 30 28 +3.3V * - Driver applies for DCE only on pins 15 and 12. Receiver applies for DTE only on pins 15 and 12. Driver applies for DCE only on pins 8 and 10. Receiver applies for DTE only on pins 8 and 10. GND Input Line Output Line I/O Lines represented by double arrowhead signifies a bi-directional bus. Figure 51. SP3508 Typical Operating Configuration to Serial Port Connector with DCE/DTE programmability Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 31 (c) Copyright 2004 Sipex Corporation PACKAGE: 100 PIN LQFP D D1 0.2 RAD MAX. c 0.08 RAD MIN. PIN 1 11-13 0MIN E1 CL E 0-7 11-13 L L1 CL A2 A b DIMENSIONS Minimum/Maximum (mm) SYMBOL A1 e 100-PIN LQFP JEDEC MS-026 (BED) Variation MIN NOM COMMON DIMENSIONS SYMBL MIN NOM MAX 1.60 A A1 0.05 A2 1.35 1.40 1.45 b 0.17 0.22 0.27 16.00 BSC D1 14.00 BSC e 0.50 BSC E 16.00 BSC E1 14.00 BSC N 100 c 0.09 L 0.45 L1 0.15 D Seating Plane MAX 0.20 0.60 0.75 1.00 REF 100 PIN LQFP Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 32 (c) Copyright 2004 Sipex Corporation ORDERING INFORMATION Part Number Temperature Range Package Types SP3508CF ............................................. 0C to +70C ................................................. 100-pin JEDEC LQFP SP3508EF ......................................... -40C to +85C ................................................. 100-pin JEDEC LQFP Available in lead free packaging. To order add "-L" suffix to part number. Example: SP3508EF = standard; SP3508EF-L = lead free REVISION HISTORY DATE 1/12/04 2/27/04 REVISION A B 3/31/04 6/3/04 10/12/04 C D E DESCRIPTION Implemented tracking revision. Included Diamond column in spec table indicating which specs apply over full operating temp. range. In figure 51, fixed typo on pin 61 and 62 from an input line to a bidirectional bus. Corrected max dimension for symbol c on LQFP package. Added tables to page 27 and 28. Certified conformance to NET1/NET2 and TBR-1 TBR-2 BY TUV Rheinland (Test Report # TBR2/30451940.001/04) Corporation ANALOG EXCELLENCE Sipex Corporation Headquarters and Sales Office 233 South Hillview Drive Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600 Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Date: 10/12/04 SP3508 Enhanced WAN Multi-Mode Serial Transceiver 33 (c) Copyright 2004 Sipex Corporation