1
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
FEATURES
■ Fast 20Mbps Differential Transmission Rates
■ Internal Transceiver Termination Resistors
for V.11 & V.35
■ Interface Modes:
✓ RS-232 (V.28) ✓ EIA-530 (V.10 & V.11)
✓ X.21 (V.11) ✓ EIA-530A (V.10 & V.11)
✓ RS-449/V.36 ✓ V.35 (V.35 & V.28)
(V.10 & V.11)
■ Protocols are Software Selectable with 3-Bit Word
■ Eight (8) Drivers and Eight (8) Receivers
■ Termination Network Disable Option
■ Internal Line or Digital Loopback for Diagnostic Testing
■ Certified conformance to NET1/NET2 and TBR-1
TBR-2 by TUV Rheinland (TBR2/30451940.001/04)
■ Easy Flow-Through Pinout
■ +3.3V Only Operation
■ Individual Driver and Receiver Enable/Disable Controls
■ Operates in either DTE or DCE Mode
SP3508
Rugged 3.3V, 20Mbps, 8 Channel Multiprotocol Transceiver
with Programmable DCE/DTE and Termination Resistors
DESCRIPTION
The SP3508 is a monolithic device that supports eight (8) popular serial interface standards
for Wide Area Network (WAN) connectivity. The SP3508 is fabricated using a low power
BiCMOS process technology, and incorporates a Sipex regulated charge pump allowing
+3.3V only operation. Sipex's patented charge pump provides a regulated output of +5.5V,
which will provide enough voltage for compliant operation in all modes. Eight (8) drivers and
eight (8) receivers can be configured via software for any of the above interface modes at any
time. The SP3508 requires no additional external components for compliant operation for all
of the eight (8) modes of operation other than six capacitors used for the internal charge pump.
All necessary termination is integrated within the SP3508 and is switchable when V.35 drivers
and V.35 receivers, or when V.11 receivers are used. The SP3508 provides the controls and
transceiver availability for operating as either a DTE or DCE.
Additional features with the SP3508 include internal loopback that can be initiated in any of the
operating modes by use of the LOOPBACK pin. While in loopback mode, receiver outputs are
internally connected to driver inputs creating an internal signal path bypassing the serial
communications controller for diagnostic testing. The SP3508 also includes a latch enable pin
with the driver and receiver address decoder. The internal V.11 or V.35 termination can be
switched off using a control pin (TERM_OFF) for monitoring applications. All eight (8) drivers and
receivers in the SP3508 include separate enable pins for added convenience. The SP3508 is
ideal for WAN serial ports in networking equipment such as routers, access concentrators,
network muxes, DSU/CSU's, networking test equipment, and other access devices.
Applicable U.S. Patents-5,306,954; and others patents pending
®
PRELIMINARY
APPLICATIONS
■ Router
■ Frame Relay
■ CSU
■ DSU
■ PBX
■ Secure Communication Terminals
Now Available in Lead Free Packaging
Refer to page 9 for pinout
2
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating
temperature range (-40°C to +85°C), unless otherwise specified.
VCC ................................................................................................ +7V
Input Voltages:
Logic ................................................ -0.3V to (VCC+0.5V)
Drivers ............................................. -0.3V to (VCC+0.5V)
Receivers ........................................................... ±15.5V
Output Voltages:
Logic ................................................ -0.3V to (VCC+0.5V)
Drivers ................................................................... ±12V
Receivers ........................................ -0.3V to (VCC+0.5V)
Storage Temperature ................................................ -65°C to +150°C
Power Dissipation ................................................................. 1520mW
(derate 19.0mW/°C above +70°C)
Due to the relatively large package size of the 100-pin quad flat-
pack, storage in a low humidity environment is preferred. Large
high density plastic packages are moisture sensitive and should
be stored in Dry Vapor Barrier Bags. Prior to usage, the parts
should remain bagged and stored below 40°C and 60%RH. If
the parts are removed from the bag, they should be used within
Package Derating:
øJA ................................................................................................................. 36.9 °C/W
øJC .................................................................................................................... 6.5 °C/W
These are stress ratings only and functional operation of the
device at these ratings or any other above those indicated in the
operation sections of the specifications below is not implied.
Exposure to absolute maximum rating conditions for extended
periods of time may affect reliability.
ABSOLUTE MAXIMUM RATINGS
48 hours or stored in an environment at or below 20%RH. If the
above conditions cannot be followed, the parts should be
baked for four hours at 125°C in order to remove moisture prior
to soldering. Sipex ships the 100-pin LQFP in Dry Vapor
Barrier Bags with a humidity indicator card and desiccant pack.
The humidity indicator should be below 30%RH.
STORAGE CONSIDERATIONS
RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC
STUPNICIGOL
V
LI
8.0 ♦♦
♦
♦♦ V
V
HI
0.2 ♦♦
♦
♦♦ V
STUPTUOCIGOL
V
LO
4.0 ♦♦
♦
♦♦ VAm2.3–=TUOI
V
HO
V
CC
-
6.0
V
CC
-
3.0 ♦♦
♦
♦♦ VAm0.1=TUOI
)stuptuO(sretemaraPCDREVIRD82.V
stuptuO
egatloVtiucriCnepO51± ♦♦
♦
♦♦ V1erugiFrep
egatloVdedaoL0.5±51± ♦♦
♦
♦♦ V2erugiFrep
tnerruCtiucriC-trohS001± ♦♦
♦
♦♦ Am4erugiFrep
ecnadepmIffO-rewoP003 ♦♦
♦
♦♦Ω 5erugiFrep
)stuptuO(sretemaraPCAREVIRD82.V V
CC
sretemarapCArofV3.3+=
emiTnoitisnarT5.1 ♦♦
♦
♦♦ sµV3-otV3+,6erugiFrep
etaRwelSsuoenatnatsnI03sµ/V3erugiFrep
t:yaleDnoitagaporP
LHP
5.00.10.3 ♦♦
♦
♦♦ sµ
t:yaleDnoitagaporP
HLP
5.00.10.3 ♦♦
♦
♦♦ sµ
etaRnoissimsnarT.xaM021032 ♦♦
♦
♦♦ spbk
3
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating
temperature range (-40°C to +85°C), unless otherwise specified.
RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC
)stupnI(sretemaraPCDREVIECER82.V
ecnadepmItupnI37
♦♦
♦
♦♦ kΩ7erugiFrep
saiBtiucriC-nepO0.2+ ♦♦
♦
♦♦ V8erugiFrep
dlohserhTHGIH7.10.3 ♦♦
♦
♦♦ V
dlohserhTWOL8.02.1 ♦♦
♦
♦♦ V
sretemaraPCAREVIECER82.V V
CC
sretemarapCArofV3.3+=
t:yaleDnoitagaporP
LHP
001005sn
t:yaleDnoitagaporP
HLP
001005sn
etaRnoissimsnarTxaM021532spbk
)stuptuO(sretemaraPCDREVIRD01.V
egatloVtiucriCnepO0.4±0.6± ♦♦
♦
♦♦ V9erugiFrep
egatloVdetanimreT-tseTV9.0
CO
V01erugiFrep
tnerruCtiucriC-trohS051±Am11erugiFrep
tnerruCffO-rewoP001± ♦♦
♦
♦♦ Aµ21erugiFrep
)stuptuO(sretemaraPCAREVIRD01.V V
CC
sretemarapCArofV3.3+=
emiTnoitisnarT002 ♦♦
♦
♦♦ sn%09ot%01;31erugiFrep
t:yaleDnoitagaporP
LHP
001005 ♦♦
♦
♦♦ sn
t:yaleDnoitagaporP
HLP
001005 ♦♦
♦
♦♦ sn
etaRnoissimsnarTxaM021 ♦♦
♦
♦♦ spbk
)stupnI(sretemaraPCDREVIECER01.V
tnerruCtupnI52.3-52.3+Am51dna41serugiFrep
ecnadepmItupnI4
♦♦
♦
♦♦ kΩ
ytivitisneS3.0± ♦♦
♦
♦♦ V
sretemaraPCAREVIECER01.V V
CC
sretemarapCArofV3.3+=
t:yaleDnoitagaporP
LHP
021052 ♦♦
♦
♦♦ sn
t:yaleDnoitagaporP
HLP
021052 ♦♦
♦
♦♦ sn
etaRnoissimsnarTxaM021 ♦♦
♦
♦♦ spbk
4
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating
temperature range (-40°C to +85°C), unless otherwise specified.
RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC
)stuptuO(sretemaraPCDREVIRD11.V
V(egatloVtiucriCnepO
CO
)0.6± ♦♦
♦
♦♦ V61erugiFrep
egatloVdetanimreTtseT0.2± ♦♦
♦
♦♦ V71erugiFrep
5.0V(
CO
)♦♦
♦
♦♦ V
ecnalaB4.0±V 71erugiFrep
tesffO0.3+ ♦♦
♦
♦♦ V71erugiFrep
tnerruCtiucriC-trohS051± ♦♦
♦
♦♦ Am81erugiFrep
tnerruCffO-rewoP001± ♦♦
♦
♦♦ Aµ91erugiFrep
)stuptuO(sretemaraPCAREVIRD11.V V
CC
sretemarapCArofV3.3+=
emiTnoitisnarT01♦♦
♦
♦♦ sn ot%01;53dna12serugiFrep
;Fp05=LCgnisU%09
t:yaleDnoitagaporP
LHP
0306♦♦
♦
♦♦ sn53dna23serugiFrep
t:yaleDnoitagaporP
HLP
0306♦♦
♦
♦♦ sn53dna23serugiFrep
wekSlaitnereffiD501♦♦
♦
♦♦ sn53dna23serugiFrep
etaRnoissimsnarT.xaM02♦♦
♦
♦♦ spbM
)stupnI(sretemaraPCDREVIECER11.V
egnaRedoMnommoC7-7+♦♦
♦
♦♦ V
ytivitisneS2.0± ♦♦
♦
♦♦ V
tnerruCtupnI52.3-52.3± Am ronorewop;22dna02erugiFrep
ffo
Ω001/wtnerruC
noitanimreT
-7.06±
5Am 42dna32erugiFrep
ecnadepmItupnI4
♦♦
♦
♦♦ kΩ
sretemaraPCAREVIECER11.V V
CC
sretemarapCArofV3.3+=
Fp05=LCgnisU
t:yaleDnoitagaporP
LHP
0306sn73dna23serugiFrep
t:yaleDnoitagaporP
HLP
0306sn73dna23serugiFrep
wekS501sn23erugiFrep
etaRnoissimsnarTxaM02spbM
5
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating
temperature range (-40°C to +85°C), unless otherwise specified.
RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC
)stuptuO(sretemaraPCDREVIRD53.V
egatloVtiucriCnepO02.1±V 61erugiFrep
egatloVdetanimreTtseT44.0±66.0±V 52erugiFrep
tesffO6.0± ♦♦
♦
♦♦ V52erugiFrep
toohsrevOtuptuO-V2.0-
TS
-2.0+
V
TS
♦♦
♦
♦♦ VV;52erugiFrep
TS
etatsydaetS=
eulav
ecnadepmIecruoS05051 ♦♦
♦
♦♦Ω Z;62erugiFrep
S
V=
2
V/
1
05x
ecnadepmItiucriC-trohS531561 Ω72erugiFrep
)stuptuO(sretemaraPCAREVIRD53.V V
CC
sretemarapCArofV3.3+=
emiTnoitisnarT02♦♦
♦
♦♦ sn
t:yaleDnoitagaporP
LHP
0306♦♦
♦
♦♦ snC;53dna23serugiFrep
L
Fp02=
t:yaleDnoitagaporP
HLP
0306♦♦
♦
♦♦ snC;53dna23serugiFrep
L
Fp02=
wekSlaitnereffiD5
♦♦
♦
♦♦ snC;53dna23serugiFrep
L
Fp02=
etaRnoissimsnarT.xaM02♦♦
♦
♦♦ spbM
)stupnI(sretemaraPCDREVIECER53.V
ytivitisneS05±002± ♦♦
♦
♦♦ Vm
ecnadepmIecruoS09011 ΩZ;92erugiFrep
S
V=
2
V/
1
05x Ω
ecnadepmItiucriC-trohS531561 Ω03erugiFrep
sretemaraPCAREVIECER53.V V
CC
sretemarapCArofV5+=
t:yaleDnoitagaporP
LHP
0306snC;73dna23serugiFrep
L
Fp02=
t:yaleDnoitagaporP
HLP
0306snC;73dna23serugiFrep
L
Fp02=
wekS501snC;23serugiFrep
L
Fp02=
etaRnoissimsnarT.xaM02spbM
STNERRUCEGAKAELREVIECSNART
tnerruCetatS-3tuptuOrevirD002AµdelbasidsrevirD;13erugiFrep
etatS-3tuptuOrevieceR
tnerruC
101Aµ D
X
111=
6
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
ELECTRICAL SPECIFICATIONS
TA = 0 to 70°C and VCC = 3.3V ± 5% unless otherwise noted. The ♦ denotes the specifications which apply over the full operating
temperature range (-40°C to +85°C), unless otherwise specified.
RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC
STNEMERIUQERREWOP
V
CC
51.33.354.3V
I
CC
)detceleSedoMoN(1
♦♦
♦
♦♦ AµIllA
CC
Vhtiweraseulav
CC
V3.3+=
)232-SR/82.V59♦♦
♦
♦♦ Am f
NI
&evitcasrevirD;spbk032=
dedaol
)224-SR/11.V(032 ♦♦
♦
♦♦ Amf
NI
dedaol&evitcasrevirD;spbM02=
)944-SR&035-AIE(072 ♦♦
♦
♦♦ Amf
NI
dedaol&evitcasrevirD;spbM02=
)53.V(071 ♦♦
♦
♦♦ Am If@53.V
N
@82.V,spbM02=
spbk032
7
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
OTHER AC CHARACTERISTICS
TA = 0 to 70°C and VCC = +3.3V unless otherwise noted.
PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
DRIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW 0.70 5.0 µsC
L = 100pF, Fig. 33 & 39; S1 closed
tPZH; Tri-state to Output HIGH 0.40 2.0 µsC
L = 100pF, Fig. 33 & 39; S2 closed
tPLZ; Output LOW to Tri-state 0.20 2.0 µsC
L = 100pF, Fig. 33 & 39; S1 closed
tPHZ; Output HIGH to Tri-state 0.40 2.0 µsC
L = 100pF, Fig. 33 & 39; S2 closed
RS-423/V.10
tPZL; Tri-state to Output LOW 0.15 2.0 µsC
L = 100pF, Fig. 33 & 39; S1 closed
tPZH; Tri-state to Output HIGH 0.20 2.0 µsC
L = 100pF, Fig. 33 & 39; S2 closed
tPLZ; Output LOW to Tri-state 0.20 2.0 µsC
L = 100pF, Fig. 33 & 39; S1 closed
tPHZ; Output HIGH to Tri-state 0.15 2.0 µsC
L = 100pF, Fig. 33 & 39; S2 closed
RS-422/V.11
tPZL; Tri-state to Output LOW 2.80 10.0 µsC
L = 100pF, Fig. 33 & 36; S1 closed
tPZH; Tri-state to Output HIGH 0.10 2.0 µsC
L = 100pF, Fig. 33 & 36; S2 closed
tPLZ; Output LOW to Tri-state 0.10 2.0 µsC
L = 15pF, Fig. 33 & 36; S1 closed
tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC
L = 15pF, Fig. 33 & 36; S2 closed
V.35
tPZL; Tri-state to Output LOW 2.60 10.0 µsC
L = 100pF, Fig. 33 & 36; S1 closed
tPZH; Tri-state to Output HIGH 0.10 2.0 µsC
L = 100pF, Fig. 33 & 36; S2 closed
tPLZ; Output LOW to Tri-state 0.10 2.0 µsC
L = 15pF, Fig. 33 & 36; S1 closed
tPHZ; Output HIGH to Tri-state 0.15 2.0 µsC
L = 15pF, Fig. 33 & 36; S2 closed
RECEIVER DELAY TIME BETWEEN ACTIVE MODE AND TRI-STATE MODE
RS-232/V.28
tPZL; Tri-state to Output LOW 0.12 2.0 µsC
L = 100pF, Fig. 34 & 37; S1 closed
tPZH; Tri-state to Output HIGH 0.10 2.0 µsC
L = 100pF, Fig. 34 & 37; S2 closed
tPLZ; Output LOW to Tri-state 0.10 2.0 µsC
L = 100pF, Fig. 34 & 37; S1 closed
tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC
L = 100pF, Fig. 34 & 37; S2 closed
RS-423/V.10
tPZL; Tri-state to Output LOW 0.10 2.0 µsC
L = 100pF, Fig. 34 & 37; S1 closed
tPZH; Tri-state to Output HIGH 0.10 2.0 µsC
L = 100pF, Fig. 34 & 37; S2 closed
tPLZ; Output LOW to Tri-state 0.10 2.0 µsC
L = 100pF, Fig. 34 & 37; S1 closed
tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC
L = 100pF, Fig. 34 & 37; S2 closed
8
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
OTHER AC CHARACTERISTICS: Continued
TA = 0 to 70°C and VCC = +3.3V unless otherwise noted.
PARAMETER MIN. TYP. MAX. UNITS CONDITIONS
RS-422/V.11
tPZL; Tri-state to Output LOW 0.10 2.0 µsC
L = 100pF, Fig. 34 & 38; S1
closed
tPZH; Tri-state to Output HIGH 0.10 2.0 µsC
L = 100pF, Fig. 34 & 38; S2
closed
tPLZ; Output LOW to Tri-state 0.10 2.0 µsC
L = 15pF, Fig. 34 & 38; S1
closed
tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC
L = 15pF, Fig. 34 & 38; S2
closed
V.35
tPZL; Tri-state to Output LOW 0.10 2.0 µsC
L = 100pF, Fig. 34 & 38; S1
closed
tPZH; Tri-state to Output HIGH 0.10 2.0 µsC
L = 100pF, Fig. 34 & 38; S2
closed
tPLZ; Output LOW to Tri-state 0.10 2.0 µsC
L = 15pF, Fig. 34 & 38; S1
closed
tPHZ; Output HIGH to Tri-state 0.10 2.0 µsC
L = 15pF, Fig. 34 & 38; S2
closed
TRANSCEIVER TO TRANSCEIVER SKEW (per Figures 32, 35, 37)
RS-232 Driver 100 ns [ (tphl )Tx1 – (tphl )Txn ]
100 ns [ (tplh )Tx1 – (tplh )Txn]
RS-232 Receiver 20 ns [ (tphl )Rx1 – (tphl )Rxn ]
20 ns [ (tphl )Rx1 – (tphl )Rxn ]
RS-422 Driver 2 ns [ (tphl )Tx1 – (tphl )Txn ]
2ns[ (t
plh )Tx1 – (tplh )Txn ]
RS-422 Receiver 3 ns [ (tphl )Rx1 – (tphl )Rxn ]
3ns[ (t
phl )Rx1 – (tphl )Rxn ]
RS-423 Driver 5 ns [ (tphl )Tx2 – (tphl )Txn ]
5ns[ (t
plh )Tx2 – (tplh )Txn ]
RS-423 Receiver 5 ns [ (tphl )Rx2 – (tphl )Rxn ]
5ns[ (t
phl )Rx2 – (tphl )Rxn ]
V.35 Driver 4 ns [ (tphl )Tx1 – (tphl )Txn ]
4ns[ (t
plh )Tx1 – (tplh )Txn ]
V.35 Receiver 6 ns [ (tphl )Rx1 – (tphl )Rxn ]
6ns[ (t
phl )Rx1 – (tphl )Rxn]
9
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
PINOUT
GND 1
SDEN
2
TTEN
3
STEN 4
RSEN
5
TREN 6
RRCEN 7
RLEN 8
LLEN 9
RDEN 10
RTEN 11
TXCEN 12
CSEN13
DMEN 14
RRTEN 15
ICEN 16
TMEN 17
D0 18
D1 19
D2 20
D_LATCH 21
TERM_OFF 22
VCC 23
C3P 24
GND 25
C3N 26
VSS2 27
AGND 28
AVCC 29
LOOPBACK 30
TXD 31
TXCE 32
ST 33
RTS 34
DTR
35
DCD_DCE 36
RL 37
LL 38
RXD 39
RXC 40
TXC 41
CTS 42
DSR 43
DCD_DTE 44
RI 45
TM 46
GND 47
VCC 48
RD(b) 49
RD(a) 50
75 GND
74 C1P
73 VCC
72 C2P
71 GND
70 C1N
69 C2N
68 VSS1
67 RL(a)
66 VCC
65 LL(a)
64 TM(a)
63 IC
62 RRT(a)
61 RRT(b)
60 GNDV10
59 DM(a)
58 DM(b)
57 CS(a)
56 CS(b)
55 TXC(a)
54 GND
53 TXC(b)
52 RT(a)
51 RT(b)
100 VCC
99 SD(b)
98 VCC
97 SD(a)
96 GND
95 TT(b)
94 VCC
93 TT(a)
92 GND
91 ST(b)
90 VCC
89 ST(a)
88 GND
87 TR(b)
86 VCC
85 TR(a)
84 GND
83 RS(b)
82 VCC
81 RS(a)
80 GND
79 RRC(a)
78 VCC
77 RCC(b)
76 VDD
SP3508
®
10
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
SP3508 Pin Designation
Pin Number Pin Name Description Pin Number Pin Name Description
1GND Signal Ground 51 RT(B) RxC Non-Inverting Input
2SDEN TxD Driver Enable Input 52 RT(A) RxC Inverting Input
3TTEN TxCE Driver Enable Input 53 TxC(B) TxC Non-Inverting Input
4STEN ST Driver Enable Input 54 GND Signal Ground
5RSEN RTS Driver Enable Input 55 TxC(A) TxC Inverting Input
6TREN DTR Driver Enable Input 56 CS(B) CTS Non-Inverting Input
7RRCEN DCD Driver Enable Input 57 CS(A) CTS Inverting Input
8RLEN RL Driver Enable Input 58 DM(B) DSR Non-Inverting Input
9LLEN LL Driver Enable Input 59 DM(A) DSR Inverting Input
10 RDEN RxD Receiver Enable Input 60 GNDV10 V.10 Rx Reference Node
11 RTEN RxC Receiver Enable Input 61 RRT(B) DCDDTE Non-Inverting Input
12 TxCEN TxC Receiver Enable Input 62 RRT(A) DCDDTE Inverting Input
13 CSEN CTS Receiver Enable Input 63 IC RI Receiver Input
14 DMEN DSR Receiver Enable Input 64 TM(A) TM Receiver Input
15 RRTEN DCDDTE Receiver Enable Input 65 LL(A) LL Driver Output
16 ICEN RI Receiver Enable Input 66 VCC Power Supply Input
17 TMEN TM Receiver Enable Input 67 RL(A) RL Driver Output
18 D0 Mode Select Input 68 VSS1 -2xVCC Charge Pump Output
19 D1 Mode Select Input 69 C2N Charge Pump Capacitor
20 D2 Mode Select Input 70 C1N Charge Pump Capacitor
21 D_LATCH Decoder Latch Input 71 GND Signal Ground
22 TERM_OFF Termination Disable Input 72 C2P Charge Pump Capacitor
23 VCC Power Supply Input 73 VCC Power Supply Input
24 C3P Charge Pump Capacitor 74 C1P Charge Pump Capacitor
25 GND Signal Ground 75 GND Signal Ground
26 C3N Charge Pump Capacitor 76 VDD 2xVCC Charge Pump Output
27 VSS2 Minus VCC 77 RRC(B) DCDDCE Non-Inverting Output
28 AGND Signal Ground 78 VCC Power Supply Input
29 AVCC Power Supply Input 79 RRC(A) DCDDCE Inverting Output
30 LOOPBACK Loopback Mode Enable Input 80 GND Signal Ground
31 TxD TxD Driver TTL Input 81 RS(A) RTS Inverting Output
32 TxCE TxCE Driver TTL Input 82 VCC Power Supply Input
33 ST ST Driver TTL Input 83 RS(B) RTS Non-Inverting Output
34 RTS RTS Driver TTL Input 84 GND Signal Ground
35 DTR DTR Driver TTL Input 85 TR(A) DTR Inverting Output
36 DCD_DCE DCDDCE Driver TTL Input 86 VCC Power Supply Input
37 RL RL Driver TTL Input 87 TR(B) DTR Non-Inverting Output
38 LL LL Driver TTL Input 88 GND Signal Ground
39 RxD RxD Receiver TTL Output 89 ST(A) ST Inverting Output
40 RxC RxC Receiver TTLOutput 90 VCC Power Supply Input
41 TxC TxC Receiver TTL Output 91 ST(B) ST Non-Inverting Output
42 CTS CTS Receiver TTL Output 92 GND Signal Ground
43 DSR DSR Receiver TTL Output 93 TT(A) TxCE Inverting Output
44 DCD_DTE DCDDTE Receiver TTL Output 94 VCC Power Supply Input
45 RI RI Receiver TTL Output 95 TT(B) TxCE Non-Inverting Output
46 TM TM Receiver TTL Output 96 GND Signal Ground
47 GND Signal Ground 97 SD(A) TxD Inverting Output
48 VCC Power Supply Input 98 VCC Power Supply Input
49 RD(B) RXD Non-Inverting Input 99 SD(B) TxD Non-Inverting Output
50 RD(A) RXD Inverting Input 100 VCC Power Supply Input
11
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Table 1. Driver Mode Selection
Table 2. Receiver Mode Selection
SP3508 Driver Table
SP3508 Receiver Table
tuptuOrevirD niP edoM53.V 035-AIE edoM
232-SR edoM )82.V(
A035-AIE edoM
944-SR edoM )63.V(
edoM12.X )11.V( nwodtuhS detsegguS langiS
EDOM )2D,1D,0D( 100010110001101011111
T
1
)a(TUO53.V11.V82.V11.V11.V11.VZ-hgiH)a(DxT
T
1
)b(TUO53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(DxT
T
2
)a(TUO53.V11.V82.V11.V11.V11.VZ-hgiH)a(ECxT
T
2
)b(TUO53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(ECxT
T
3
)a(TUO53.V11.V82.V11.V11.V11.VZ-hgiH)a(ECD_CxT
T
3
)b(TUO53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(ECD_CxT
T
4
)a(TUO82.V11.V82.V11.V11.V11.VZ-hgiH)a(STR
T
4
)b(TUOZ-hgiH11.VZ-hgiH11.V11.V11.VZ-hgiH)b(STR
T
5
)a(TUO82.V11.V82.V01.V11.V11.VZ-hgiH)a(RTD
T
5
)b(TUOZ-hgiH11.VZ-hgiHZ-hgiH11.V11.VZ-hgiH)b(RTD
T
6
)a(TUO82.V11.V82.V11.V11.V11.VZ-hgiH)a(ECD_DCD
T
6
)b(TUOZ-hgiH11.VZ-hgiH11.V11.V11.VZ-hgiH)b(ECD_DCD
T
7
)a(TUO82.V01.V82.V01.V01.VZ-hgiHZ-hgiHLR
T
8
)a(TUO82.V01.V82.V01.V01.VZ-hgiHZ-hgiHLL
tupnIrevieceR niP edoM53.V 035-AIE edoM
232-SR edoM )82.V(
A035-AIE edoM
944-SR edoM )63.V(
edoM12.X )11.V( nwodtuhS detsegguS langiS
EDOM )2D,1D,0D( 100010110001101011111
R
1
)a(NI53.V11.V82.V11.V11.V11.VZ-hgiH)a(DxR
R
1
)b(NI53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(DxR
R
2
)a(NI53.V11.V82.V11.V11.V11.VZ-hgiH)a(CxR
R
2
)b(NI53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(CxR
R
3
)a(NI53.V11.V82.V11.V11.V11.VZ-hgiH)a(ETD_CxT
R
3
)b(NI53.V11.VZ-hgiH11.V11.V11.VZ-hgiH)b(ETD_CxT
R
4
)a(NI82.V11.V82.V11.V11.V11.VZ-hgiH)a(STC
R
4
)b(NIZ-hgiH11.VZ-hgiH11.V11.V11.VZ-hgiH)b(STC
R
5
)a(NI82.V11.V82.V01.V11.V11.VZ-hgiH)a(RSD
R
5
)b(NIZ-hgiH11.VZ-hgiHZ-hgiH11.V11.VZ-hgiH)b(RSD
R
6
)a(NI82.V11.V82.V11.V11.V11.VZ-hgiH)a(ETD_DCD
R
6
)b(NIZ-hgiH11.VZ-hgiH11.V11.V11.VZ-hgiH)b(ETD_DCD
R
7
)a(NI82.V01.V82.V01.V01.VZ-hgiHZ-hgiHIR
R
8
)a(NI82.V01.V82.V01.V01.VZ-hgiHZ-hgiHMT
12
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 1. V.28 Driver Output Open Circuit Voltage Figure 2. V.28 Driver Output Loaded Voltage
Figure 3. V.28 Driver Output Slew Rate Figure 4. V.28 Driver Output Short-Circuit Current
Figure 6. V.28 Driver Output Rise/Fall Times
Figure 5. V.28 Driver Output Power-Off Impedance
TEST CIRCUITS
A
V
OC
C
A
V
T
C
3kΩ
A
VT
C
7kΩOscilloscope
Scope used for slew rate
measurement.
A
I
sc
C
A
C
V
CC
= 0V
±2V
Ix
A
C
3kΩ2500pF
Oscilloscope
13
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 7. V.28 Receiver Input Impedance Figure 8. V.28 Receiver Input Open Circuit Bias
Figure 9. V.10 Driver Output Open-Circuit Voltage Figure 10. V.10 Driver Output Test Terminated Voltage
Figure 12. V.10 Driver Output Power-Off CurrentFigure 11. V.10 Driver Output Short-Circuit Current
A
C
I
ia
±15V
A
C
voc
A
V
OC
3.9kΩ
C
A
V
t
450Ω
C
A
Isc
C
A
C
±0.25V
V
CC
= 0V
Ix
14
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 13. V.10 Driver Output Transition Time Figure 14. V.10 Receiver Input Current
Figure 15. V.10 Receiver Input IV Graph Figure 16. V.11 Driver Output Open-Circuit Voltage
Figure 17. V.11 Driver Output Test Terminated Voltage Figure 18. V.11 Driver Output Short-Circuit Current
A
450Ω
C
Oscilloscope
A
C
I
ia
±10V
A
B
V
OC
3.9kΩ
V
OCA
V
OCB
C
A
B
VT
50Ω
VOS
C
50Ω
A
B
C
I
sa
I
sb
V.10 RECEIVER
+3.25mA
-3.25mA
+3V +10V
-3V-10V
Maximum Input Current
Versus Voltage
15
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 19. V.11 Driver Output Power-Off Current Figure 20. V.11 Receiver Input Current
Figure 21. V.11 Driver Output Rise/Fall Time Figure 22. V.11 Receiver Input IV Graph
A
B
C
I
xa
±0.25V
A
B
C
I
xb
±0.25V
VCC = 0V
VCC = 0V
A
B
C
I
ia
±10V
C
I
ib
±10V
A
B
A
B
50Ω
C
50Ω
50ΩVE
Oscilloscope
V.11 RECEIVER
+3.25mA
-3.25mA
+3V +10V
-3V-10V
Maximum Input Current
Versus Voltage
16
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 23. V.11 Receiver Input Current w/ Termination
Figure 24. V.11 Receiver Input Graph with Termination
Figure 25. V.35 Driver Output Test Terminated Voltage
Figure 26. V.35 Driver Output Source Impedance
A
B
C
I
ia
±6V
C
I
ib
±6V
A
B
100Ω to
150Ω
100Ω to
150Ω
A
B
V
2
50Ω
C
24kHz, 550mV
p-p
Sine Wave
V
1
A
B
50Ω
C
50Ω
VT
VOS
V.11 RECEIVER
w/ Optional Cable Termination
(100Ω to 150Ω)
i [mA] = V [V] / 0.1
i [mA] = V [V] - 3) / 4.0
i [mA] = V [V] / 0.1
i [mA] = V [V] - 3) / 4.0
-6V -3V
+3V +6V
Maximum Input Current
versus Voltage
Figure 27. V.35 Driver Output Short-Circuit Impedance
A
B
C
I
SC
±2V
17
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 31. Driver Output Leakage Current Test
Figure 32. Driver/Receiver Timing Test Circuit
Figure 29. V.35 Receiver Input Source Impedance
Figure 28. V.35 Driver Output Rise/Fall Time
Figure 30. V.35 Receiver Input Short-Circuit Impedance
A
B
C
50Ω
Oscilloscope
50Ω
50Ω
A
B
V
2
50Ω
C
24kHz, 550mV
p-p
Sine Wave
V
1
A
B
C
I
sc
±2V
A
B
I
ZSC
Logic “1”
±10V
11 1
D
2
D
1
D
0
V
CC
= 0V
V
CC
Any one of the three conditions for disabling the driver.
I
ZSC
±10V
CL1
15pF
R
OUT
B
A
B
A
T
IN
CL2
f
IN (50% Duty Cycle, 2.5VP-P)
18
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 33. Driver Timing Test Load Circuit Figure 34. Receiver Timing Test Load Circuit
Figure 35. Driver Propagation Delays
Figure 36. Driver Enable and Disable Times
Figure 37. Receiver Propagation Delays
500Ω
C
L
Output
Under
Test
S
1
S
2
V
CC
1KΩ
1KΩC
RL
Receiver
Output S
1
S
2
Test Point
V
CC
+3V
0V
5V
V
OL
A, B
0V
1.5V 1.5V
t
ZL
t
ZH
V
OH
A, B 2.3V
2.3V
t
LZ
t
HZ
0.5V
0.5V
Output normally LOW
Output normally HIGH
Mx or Tx_Enable
f = 1MHz; t
R
≤ 10ns; t
F
≤ 10ns
VOH
VOL
RECEIVER OUT (V
OH
- V
OL
)/2 (V
OH
- V
OL
)/2
tPLH
f > 10MHz; tR < 5ns; tF < 5ns
OUTPUT
V0D2+
V0D2–
A – B 0V 0V
tPHL
INPUT
t
SKEW
= | t
PHL
- t
PLH
|
+3V
0V
DRIVER
INPUT
A
B
DRIVER
OUTPUT
V
O
+
DIFFERENTIAL
OUTPUT
V
B
– V
A
0V
V
O
–
1.5V 1.5V
t
PLH
t
R
t
F
f > 10MHz; t
R
< 5ns; t
F
< 5ns
V
O
1/2V
O
1/2V
O
t
PHL
t
DPLH
t
DPHL
t
SKEW =
|
t
DPLH -
t
DPHL
|
19
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 38. Receiver Enable and Disable Times
Figure 39. V.28 (RS-232) and V.10 (RS-423) Driver Enable and Disable Times
+3V
0V
Tx_Enable 1.5V 1.5V
tZL
f = 60kHz; tR < 10ns; tF < 10ns
TOUT
tLZ
Output LOW
0V
+3V
0V
VOH
1.5V 1.5V
tZH
f = 60kHz; tR < 10ns; tF < 10ns
TOUT
tHZ
Output HIGH
0V
Tx_Enable
VOL
0.5V
VOH -
VOL 0.5V
-VOL 0.5V
-
+3V
0V
+3.3V
RECEIVER OUT
0V
1.5V 1.5V
tZL
tZH
f = 1MHz; tR < 10ns; tF < 10ns
RECEIVER OUT 1.5V
1.5V
tLZ
tHZ
0.5V
0.5V
Output normally LOW
Output normally HIGH
VIL
VIH
DECx
RxENABLE
20
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 40. Typical V.10 Driver Output Waveform. Figure 41. Typical V.11 Driver Output Waveform.
Figure 42. Typical V.28 Driver Output Waveform. Figure 43. Typical V.35 Driver Output Waveform.
21
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 44. Functional Diagram
TxD
SD(a)
SD(b)
SDEN
V
CC
V
DD
C1-C1+
+3.3V
(decoupling capacitor not shown)
1µF
SP3508
TxCE
TT(a)
TT(b)
TTEN
ST
ST(a)
ST(b)
STEN
RD(a)
RxD
RDEN
RD(b)
RT(a)
RxC
RTEN
RT(b)
TxC(a)
TxC
TxCEN
TxC(b)
CS(a)
CTS
CSEN
CS(b)
DM(a)
DSR
DMEN
DM(b)
RRT(a)
DCD_DTE
RRTEN
RRT(b)
TM(a)
TM
TMEN
RTS
RS(a)
RS(b)
RSEN
DTR
TR(a)
TR(b)
TREN
DCD_DCE
RRC(a)
RRC(b)
RRCEN
LL
LL(a)
LLEN
C2-C2+
1µF
1µF
GND
D0
D1
D2
TERM-OFF
D-LATCH
V.10-GND
RL
RL(a)
RLEN
IC
RI
ICEN
LOOPBACK
76
29
50
39
10
49
52
40
11
51
55
41
12
53
57
42
14
56
59
43
13
58
62
44
15
61
63
45
16
64
46
17
18
19
20
21
22
30
+3.3V
(S
ee p
i
nout ass
i
gnments
f
or
GND and V
CC
pins)
74 70 72 69
AGND
31
97
99
2
32
93
95
3
33
89
91
4
34
81
83
6
35
85
87
5
36
79
77
7
37
67
8
38
65
9
60
28
V.35 MODE
RX ENABLE
51ohms
51ohms
124ohms
RECEIVER TERMINATION NETWORK
V.11 MODE
V.35 MODE
TX ENABLE
51ohms
51ohms
124ohms
V.35 DRIVER TERMINATION NETWORK
V
SS1
68
V
SS2
1µF
27
1µF
1µF
24
26
AV
CC
C3-
C3+
Inverter
Regulated Charge Pump
C
VDD
C1 C2
C3
C
VSS1
C
VSS2
22
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
The SP3508 contains highly integrated serial
transceivers that offer programmability between
interface modes through software control. The
SP3508 offers the hardware interface modes for
RS-232 (V.28), RS-449/V.36 (V.11 and V.10),
EIA-530 (V.11 and V.10), EIA-530A (V.11 and
V.10), V.35 (V.35 and V.28) and X.21(V.11).
The interface mode selection is done via three
control pins, which can be latched via micropro-
cessor control.
The SP3508 has eight drivers, eight receivers,
and Sipex's patented on-board charge pump
(5,306,954) that is ideally suited for wide area
network connectivity and other multi-protocol
applications. Other features include digital and
line loopback modes, individual enable/disable
control lines for each driver and receiver, fail-
safe when inputs are either open or shorted.
THEORY OF OPERATION
The SP3508 device is made up of
1) the drivers
2) the receivers
3) charge pumps
4) DTE/DCE switching algorithm
5) control logic.
Drivers
The SP3508 has eight enhanced independent
drivers. Control for the mode selection is done
via a three-bit control word into D0, D1, and D2.
The drivers are prearranged such that for each
mode of operation, the relative position and
functionality of the drivers are set up to accom-
modate the selected interface mode. As the
mode of the drivers is changed, the electrical
characteristics will change to support the re-
quired signal levels. The mode of each driver in
the different interface modes that can be se-
lected is shown in Table 1.
There are four basic types of driver circuits –
ITU-T-V.28 (RS-232), ITU-T-V.10 (RS-423),
ITU-T-V.11 (RS-422), and CCITT-V.35.
The V.28 (RS-232) drivers output single-ended
signals with a minimum of +5V (with 3kΩ &
2500pF loading), and can operate over 120kbps.
Since the SP3508 uses a charge pump to gener-
ate the RS-232 output rails, the driver outputs
will never exceed +10V. The V.28 driver archi-
tecture is similar to Sipex's standard line of RS-
232 transceivers.
The RS-423 (V.10) drivers are also single-ended
signals which produce open circuit VOL and
VOH measurements of +4.0V to +6.0V. When
terminated with a 450Ω load to ground, the
driver output will not deviate more than 10% of
the open circuit value. This is in compliance of
the ITU V.10 specification. The V.10 (RS-423)
drivers are used in RS-449/V.36, EIA-530, and
EIA-530A modes as Category II signals from
each of their corresponding specifications. The
V.10 driver can transmit over 120Kbps if neces-
sary.
The third type of drivers are V.11 (RS-422)
differential drivers. Due to the nature of differ-
ential signaling, the drivers are more immune to
noise as opposed to single-ended transmission
methods. The advantage is evident over high
speeds and long transmission lines. The strength
of the driver outputs can produce differential
signals that can maintain +2V differential out-
put levels with a load of 100Ω. The strength
allows the SP3508 differential driver to drive
over long cable lengths with minimal signal
degradation. The V.11 drivers are used in RS-
449, EIA-530, EIA-530A and V.36 modes as
Category I signals which are used for clock and
data. Sipex's new driver design over its prede-
cessors allow the SP3508 to operate over 20Mbps
for differential transmission.
FEATURES
23
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
The fourth type of drivers are V.35 differential
drivers.
There are only three available on the
SP3508 for data and clock (TxD, TxCE, and TxC
in DCE mode). These drivers are current sources
that drive loop current through a differential pair
resulting in a 550mV differential voltage at the
receiver. These drivers also incorporate fixed
termination networks for each driver in order to
set the VOH and VOL depending on load conditions.
This termination network is basically a “Y”
configuration consisting of two 51Ω resistors
connected in series and a 124Ω resistor connected
between the two 50Ω resistors to GND. Filtering
can be done on these pins to reduce common
mode noise transmitted over the transmission
line by connecting a capacitor to ground.
The drivers also have separate enable pins
which simplifies half-duplex configurations for
some applications, especially programmable
DTE/DCE. The enable pins will either enable or
disable the output of the drivers according to the
appropriate active logic illustrated on Figure 44.
The enable pins have internal pull-up and pull-
down devices, depending on the active polarity
of the receiver, that enable the driver upon power-
on if the enable lines are left floating. During
disabled conditions, the driver outputs will be at
a high impedance 3-state.
The driver inputs are both TTL or CMOS
compatible. All driver inputs have an internal
pull-up resistor so that the output will be at a
defined state at logic LOW (“0”). Unused driver
inputs can be left floating. The internal pull-up
resistor value is approximately 500kΩ.
Receivers
The SP3508 has eight enhanced independent
receivers. Control for the mode selection is done
via a three-bit control word that is the same as the
driver control word. Therefore, the modes for
the drivers and receivers are identical in the
application.
Like the drivers, the receivers are prearranged
for the specific requirements of the synchronous
serial interface. As the operating mode of the
receivers is changed, the electrical characteristics
will change to support the required serial interface
protocols of the receivers. Table 1 shows
the mode of each receiver in the different
interface modes that can be selected. There are
two basic types of receiver circuits—ITU-T-V .28
(RS-232) and ITU-T-V.11, (RS-422).
The RS-232 (V.28) receiver is single-ended and
accepts RS-232 signals from the RS-232 driver.
The RS-232 receiver has an operating input
voltage range of +15V and can receive signals
downs to +3V. The input sensitivity complies
with RS-232 and V.28 at +3V. The input
impedance is 3kΩ to 7kΩ in accordance to RS-
232 and V.28. The receiver output produces a
TTL/CMOS signal with a +2.4V minimum for
a logic “1” and a +0.4V maximum for a logic “0”.
The RS-232 (V.28) protocol uses these receivers
for all data, clock and control signals. They are
also used in V.35 mode for control line signals:
CTS, DSR, LL, and RL. The RS-232 receivers
can operate over 120kbps.
The second type of receiver is a differential type
that can be configured internally to support
ITU-T-V.10 and CCITT-V.35 depending on its
input conditions. This receiver has a typical
input impedance of 10kΩ and a differential
threshold of less than +200mV, which complies
with the ITU-T-V.11 (RS-422) specifications.
V.11 receivers are used in RS-449/V.36,
EIA-530, EIA-530A and X.21 as Category I
signals for receiving clock, data, and some control
line signals not covered by Category II V.10
circuits. The differential V.11 transceiver has
improved architecture that allows over 20Mbps
transmission rates.
Receivers dedicated for data and clock (RxD,
RxC, TxC) incorporate internal termination for
V.11. The termination resistor is typically 120Ω
connected between the A and B inputs. The
termination is essential for minimizing crosstalk
and signal reflection over the transmission line .
The minimum value is guaranteed to exceed
100Ω, thus complying with the V.11 and RS-422
specifications. This resistor is invoked when the
receiver is operating as a V.11 receiver, in modes
EIA-530, EIA-530A, RS-449/V.36, and X.21.
FEATURES
24
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
The same receivers also incorporate a termination
network internally for V.35 applications. For
V.35, the receiver input termination is a “Y”
termination consisting of two 51Ω resistors
connected in series and a 124Ω resistor connected
between the two 50Ω resistors and GND. The
receiver itself is identical to the V.11 receiver.
The differential receivers can be configured to
be ITU-T-V.10 single-ended receivers by
internally connecting the non-inverting input to
ground. This is internally done by default from
the decoder. The non-inverting input is rerouted
to V10GND and can be grounded separately.
The ITU-T-V.10 receivers can operate over
120Kbps and are used in RS-449/V.36, E1A-
530, E1A-530A and X.21 modes as Category II
signals as indicated by their corresponding
specifications. All receivers include an enable/
disable line for disabling the receiver output
allowing convenient half-duplex configurations.
The enable pins will either enable or disable the
output of the receivers according to the
appropriate active logic illustrated on Figure 44.
The receiver’s enable lines include an internal
pull-up or pull-down device, depending on the
active polarity of the receiver, that enables the
receiver upon power up if the enable lines are left
floating. During disabled conditions, the receiver
outputs will be at a high impedance state. If the
receiver is disabled any associated termination is
also disconnected from the inputs.
FEATURES
All receivers include a fail-safe feature that
outputs a logic high when the receiver inputs are
open, terminated but open, or shorted together.
For single-ended V.28 and V.10 receivers, there
are internal 5kΩ pull-down resistors on the inputs
which produces a logic high (“1”) at the receiver
outputs. The differential receivers have a
proprietary circuit that detect open or shorted
inputs and if so, will produce a logic HIGH (“1”)
at the receiver output.
CHARGE PUMP
SP3508 uses an internal capacitive charge pump
to generate Vdd and Vss. The design is Sipex
patented (5,306,954) four-phased voltage shift-
ing charge pump converters that converts the
input voltage of 3.3V to nominal output volt-
ages of +/-6V (Vdd & Vss1). SP3508 also in-
cludes an inverter block that inverts Vcc to -Vcc
(Vss2). There is a free-running oscillator that
controls the four phases of the voltage shifting.
A description of each phase follows.
4-phased doubler pump
Phase 1
-VSS1 charge storage -During this phase of the
clock cycle, the positive side of capacitors C1
and C2 are initially charged to VCC. C1+ is then
switched to ground and the charge in C1- is
transferred to C2-. Since C2+ is connected to
VCC, the voltage potential across capacitor C2 is
now 2xVCC.
VCC = +3V
–3V –3V
+3V
VSS1 Storage Capacitor
VDD Storage Capacitor
C1C2
+
+
++
–
–
––
CVDD
C
VSS1
Figure 45. Charge Pump - Phase 1.
25
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Phase 2
-VSS1 transfer -Phase two of the clock connects the negative terminal of C2 to the VSS1 storage capacitor
and the positive terminal of C2 to ground, and transfers the negative generated voltage to CVSS1. This
generated voltage is regulated to -5.5V. Simultaneously, the positive side of the capacitor C1 is switched
to VCC and the negative side is connected to ground.
FEATURES
Phase 3
-VDD charge storage -The third phase of the clock is identical to the first phase-the charge transferred in
C1 produces -VCC in the negative terminal of C1 which is applied to the negative side of the capacitor C2.
Since C2+ is at VCC, the voltage potential across C2 is 2xVCC.
V
CC
= +3V
–6V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
+
+
++
–
–
––
C
VDD
C
VSS1
Figure 46. Charge Pump - Phase 2.
V
CC
= +3V
–3V
+3V
–3V
V
SS1
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
+
+
++
–
–
––
C
VSS1
C
VDD
Figure 47.Charge Pump - Phase 3.
Phase 4
-VDD transfer -The fourth phase of the clock connects the negative terminal of C2 to ground, and transfers
the generated 5.5V across C2 to CVDD, the VDD storage capacitor. This voltage is regulated to +5.5V. At
the regulated voltage, the internal oscillator is disabled and simultaneously with this, the positive side of
capacitor C1 is switched to VCC and the negative side is connected to ground, and the cycle begins again.
The charge pump cycle will continue as long as the operational conditions for the internal oscillator are
present. Since both V+ and V- are separately generated from VCC; in a no-load condition V+ and V- will
be symmetrical. Older charge pump approaches that generate V- from V+ will show a decrease in the
magnitude of
V- compared to V+ due to the inherent inefficiencies in the design. The clock rate for the charge pump
typically operates at 250kHz. The external capacitors can be as low as 1µF with a 16V breakdown voltage
rating.
26
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
VCC = +3V
+6V
VSS1 Storage Capacitor
VDD Storage Capacitor
C1C2
+
+
++
–
–
––
CVDD
CVSS1
Figure 48. Charge Pump - Phase 4.
2-phased inverter pump
Phase 1
Please refer to figure below: In the first phase of the clock cycle, switches S2 and S4 are opened and S1 and
S3 closed. This connects the flying capacitor, C3, from Vin to ground. C3 charge up to the input voltage
applied at Vcc.
Phase 2
In the second phase of the clock cycle, switches S2 and S4 are closed and S1 and S3 are opened. This
connects the flying capacitor, C3, in parallel with the output capacitor, CVSS2. The Charge stored in C3 is
now transferred to CVSS2. Simultaneously, the negative side of CVSS2 is connected to VSS2 and the positive
side is connected to ground. With the voltage across CVSS2 smaller than the voltage across C3, the charge
flows from C3 to CVSS2 until the voltage at the VSS2 equals -VCC.
C
3
S
2
S
1
S
3
S
4
V
SS2
C
VSS2
++
V
CC
V
SS2
= -V
CC
Figure 49. Circuit for an Ideal Voltage Inverter.
FEATURES
27
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Recommended Signals and Port Pin Assignments
Pin
Number
Pin Mnemonic Circuit Pin Mnemonic
Pin
Number
Signal
Type
Mnemo
nic
DB-25
Pin(F)
Signal
Type
Mnemo
nic
DB-25
Pin(F)
Signal
Type
Mnemo
nic
DB-37
Pin(F)
Signal
Type
Mnemo
nic
M34
Pin(F)
Signal
Type
Mnemo
nic
DB-15
Pin(F)
31 TxD SD(A) 97 V.28 BB 3 V.11 BB(A) 3 V.11 RD(A) 6 V.35 104 R V.11 R(A) 4
2SDEN SD(B) 99 V.11 BB(B) 16 V.11 RD(B) 24 V.35 104 T V.11 R(B) 11
32 TxCE TT(A) 93 V.28 DD 17 V.11 DD(A) 17 V.11 RT(A) 8 V.35 115 V V.11 B(A) 7**
3TTEN TT(B) 95 V.11 DD(B) 9 V.11 RT(B) 26 V.35 115 X V.11 B(B) 14**
33 ST ST(A) 89 V.28 DB 15 V.11 DB(A) 15 V.11 ST(A) 5 V.35 114 Y V.11 S(A) 6
4STEN ST(B) 91 V.11 DB(B) 12 V.11 ST(B) 23 V.35 114 AA V.11 S(B) 13
34 RTS RS(A) 81 V.28 CB 5 V.11 CB(A) 5 V.11 CS(A) 9 V.28 106 D V.11 I(A) 5
5RSEN RS(B) 83 V.11 CB(B) 13 V.11 CS(B) 27 V.11 I(B) 12
35 DTR TR(A) 85 V.28 CC 6 V.11 CC(A) 6 V.11 DM(A) 11 V.28 107 E
6TREN TR(B) 87 V.11 CC(B) 22 V.11 DM(B) 29
36 DCD_DCE RRC(A) 79 V.28 CF 8 V.11 CF(A) 8 V.11 RR(A) 13 V.28 109 F
7RRCEN RRC(B) 77 V.11 CF(B) 10 V.11 RR(B) 31
37 RL RL(A) 67 V.28 CE 22 V.28 125 J
8RLEN
38 LL LL(A) 65 V.28 TM 25 V.10 TM 25 V.10 TM 18 V.28 142 NN
9LLEN#
39 RxD RD(A) 50 V.28 BA 2 V.11 BA(A) 2 V.11 SD(A) 4 V.35 103 P V.11 T(A) 2
10 RDEN# RD(B) 49 V.11 BA(B) 12 V.11 SD(B) 22 V.35 103 S V.11 T(B) 9
40 RxC RT(A) 52 V.28 DA 24 V.11 DA(A) 24 V.11 TT(A) 17 V.35 113 U V.11 X(A) 7**
11 RTEN# RT(B) 51 V.11 DA(B) 11 V.11 TT(B) 35 V.35 113 W V.11 X(B) 14**
41 TxC TxC(A) 55
12 TxCEN# TxC(B) 53
42 CTS CS(A) 57 V.28 CA 4 V.11 CA(A) 4 V.11 RS(A) 7 V.28 105 C V.11 C(A) 3
13 CSEN# CS(B) 56 V.11 CA(B) 19 V.11 RS(B) 25 V.11 C(B) 10
43 DSR DM(A) 59 V.28 CD 20 V.11 CD(A) 20 V.11 TR(A) 12 V.28 108 H
14 DMEN# DM(B) 58 V.11 CD(B) 23 V.11 TR(B) 30
44 DCD_DTE RRT(A) 62
15 RRTEN# RRT(B) 61
45 RI IC 63 V.28 RL 21 V.10 RL 21 V.10 RL 14 V.28 140 N
16 ICEN#
46 TM TM(A) 64 V.28 LL 18 V.10 LL 18 V.10 LL 10 V.28 141 L
17 TMEN
SP3508 Multiprotocol Configured as DCE
Interface to System Logic
Interface to Port-
Connector
Receiver_4
Receiver_5
Receiver_6
Driver_7
Driver_8
RS-449
V.35
X.21
Driver_1
RS-232 or V.24
EIA-530
Receiver_2
Receiver_3
Driver_2
Driver_3
Driver_4
Driver_5
Receiver_1
Driver_6
Spare drivers and receivers may be used for optional signals (Signal
Quality, Rate Detect, Standby) or may be disabled using individual
enable pins for each driver and receiver
** X.21 use either B() or
X(), not both
Pin assignments and signal functions are subject to national or regional variation and
proprietary / non-standard implementations
Receiver_7
Receiver_8
DCE CONFIGURATION
Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
27
28
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Recommended Signals and Port Pin Assignments
Pin
Number
Pin Mnemonic Circuit Pin Mnemonic
Pin
Number
Signal
Type
Mnemo
nic
DB-25
Pin(M)
Signal
Type
Mnemo
nic
DB-25
Pin(M)
Signal
Type
Mnemo
nic
DB-37
Pin(M)
Signal
Type
Mnemo
nic
M34
Pin(M)
Signal
Type
Mnemo
nic
DB-15
Pin(M)
31 TxD SD(A) 97 V.28 BA 2 V.11 BA(A) 2 V.11 SD(A) 4 V.35 103 P V.11 T(A) 2
2SDEN SD(B) 99 V.11 BA(B) 12 V.11 SD(B) 22 V.35 103 S V.11 T(B) 9
32 TxCE TT(A) 93 V.28 DA 24 V.11 DA(A) 24 V.11 TT(A) 17 V.35 113 U V.11 X(A) 7**
3TTEN TT(B) 95 V.11 DA(B) 11 V.11 TT(B) 35 V.35 113 W V.11 X(B) 14**
33 ST ST(A) 89
4STEN ST(B) 91
34 RTS RS(A) 81 V.28 CA 4 V.11 CA(A) 4 V.11 RS(A) 7 V.28 105 C V.11 C(A) 3
5RSEN RS(B) 83 V.11 CA(B) 19 V.11 RS(B) 25 V.11 C(B) 10
35 DTR TR(A) 85 V.28 CD 20 V.11 CD(A) 20 V.11 TR(A) 12 V.28 108 H
6TREN TR(B) 87 V.11 CD(B) 23 V.11 TR(B) 30
36 DCD_DCE RRC(A) 79
7RRCEN RRC(B) 77
37 RL RL(A) 67 V.28 RL 21 V.10 RL 21 V.10 RL 14 V.28 140 N
8RLEN
38 LL LL(A) 65 V.28 LL 18 V.10 LL 18 V.10 LL 10 V.28 141 L
9LLEN#
39 RxD RD(A) 50 V.28 BB 3 V.11 BB(A) 3 V.11 RD(A) 6 V.35 104 R V.11 R(A) 4
10 RDEN# RD(B) 49 V.11 BB(B) 16 V.11 RD(B) 24 V.35 104 T V.11 R(B) 11
40 RxC RT(A) 52 V.28 DD 17 V.11 DD(A) 17 V.11 RT(A) 8 V.35 115 V V.11 B(A) 7**
11 RTEN# RT(B) 51 V.11 DD(B) 9 V.11 RT(B) 26 V.35 115 X V.11 B(B) 14**
41 TxC TxC(A) 55 V.28 DB 15 V.11 DB(A) 15 V.11 ST(A) 5 V.35 114 Y V.11 S(A) 6
12 TxCEN# TxC(B) 53 V.11 DB(B) 12 V.11 ST(B) 23 V.35 114 AA V.11 S(B) 13
42 CTS CS(A) 57 V.28 CB 5 V.11 CB(A) 5 V.11 CS(A) 9 V.28 106 D V.11 I(A) 5
13 CSEN# CS(B) 56 V.11 CB(B) 13 V.11 CS(B) 27 V.11 I(B) 12
43 DSR DM(A) 59 V.28 CC 6 V.11 CC(A) 6 V.11 DM(A) 11 V.28 107 E
14 DMEN# DM(B) 58 V.11 CC(B) 22 V.11 DM(B) 29
44 DCD_DTE RRT(A) 62 V.28 CF 8 V.11 CF(A) 8 V.11 RR(A) 13 V.28 109 F
15 RRTEN# RRT(B) 61 V.11 CF(B) 10 V.11 RR(B) 31
45 RI IC 63 V.28 CE 22 V.28 125 J
16 ICEN#
46 TM TM(A) 64 V.28 TM 25 V.10 TM 25 V.10 TM 18 V.28 142 NN
17 TMEN
RS-449
V.35
X.21
Receiver_7
Receiver_8
RS-232 or V.24
EIA-530
Receiver_4
Receiver_5
Receiver_6
Driver_7
Driver_8
Driver_6
Driver_2
Driver_3
Driver_4
Driver_5
Spare drivers and receivers may be used for optional signals (Signal
Quality, Rate Detect, Standby) or may be disabled using individual
enable pins for each driver and receiver
** X.21 use either B() or
X(), not both
Pin assignments and signal functions are subject to national or regional variation and
proprietary / non-standard implementations
SP3508 Multiprotocol Configured as DTE
Interface to System Logic
Interface to Port-
Connector
Driver_1
Receiver_1
Receiver_2
Receiver_3
Date: 06/14/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
28
DTE CONFIGURATION
29
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
TERM_OFF FUNCTION
The SP3508 contains a TERM_OFF pin that dis-
ables all three receiver input termination networks
regardless of mode. This allows the device to be
used in monitor mode applications typically found
in networking test equipment.
The TERM_OFF pin internally contains a pull-
down device with an impedance of over 500kΩ,
which will default in a "ON" condition during
power-up if V.35 receivers enable line and the
SHUTDOWN mode from the decoder will disable
the termination regardless of TERM_OFF.
LOOPBACK FUNCTION
The SP3508 contains a LOOPBACK pin that
invokes a loopback path. This loopback path is
illustrated in Figure 50. LOOPBACK has an inter-
nal pull-up resistor that defaults to normal mode
during power up or if the pin is left floating. During
loopback, the driver output and receiver input
characteristics will still adhere to its appropriate
specifications.
DECODER AND D_LATCH FUNCTION
The SP3508 contains a D_LATCH pin that latches
the data into the D0, D1 and D2 decoder inputs. If
tied to a logic LOW ("0"), the latch is transparent,
allowing the data at the decoder inputs to propa-
gate through and program the SP3508 accord-
ingly. If tied to a logic HIGH ("1"), the latch locks
out the data and prevents the mode from changing
until this pin is brought to a logic LOW.
FEATURES
There are internal pull-up devices on D0, D1 and
D2, which allow the device to be in SHUTDOWN
mode ("111") upon power up. However, if the
device is powered-up with the D_LATCH at a
logic HIGH, the decoder state of the SP3508 will
be undefined.
CTR1/CTR2 EUROPEAN COMPLIANCY
As with all of Sipex's previous multi-protocol
serial transceiver IC's the drivers and receivers
have been designed to meet all the requirements to
NET1/NET2 and TBR2 in order to meet CTR1/
CTR2 compliancy. The SP3508 is also tested in-
house at Sipex and adheres to all the NET1/2
physical layer testing and the ITU Series V speci-
fications before shipment. Please note that al-
though the SP3508, as with its predecessors, ad-
here to CRT1/CTR2 compliancy testing, any com-
plex or usual configuration should be double-
checked to ensure CTR1/CTR2 compliance. Con-
sult the factory for details.
30
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 50. Loopback Path
SD(a)
SD(b)
RD(a)
RD(b)
TT(a)
TT(b)
RT(a)
RT(b)
TxD
RxD
TxCE
RxC
ST(a)
ST(b)
TxC(a)
TxC(b)
ST
TxC
RS(a)
RS(b)
CS(a)
CS(b)
TR(a)
TR(b)
DM(a)
DM(b)
RTS
CTS
DTR
DSR
RRC(a)
RRC(b)
RRT(a)
RRT(b)
DCD_DCE
DCD_DTE
RL(a)
IC
RL
RI
LL(a)
TM(a)
LL
TM
31
39
32
40
33
41
34
42
35
43
36
44
37
45
38
46
97
99
50
49
93
95
52
51
89
91
55
53
81
83
57
56
85
87
59
58
79
77
62
61
67
63
65
64
31
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
Figure 51. SP3508 Typical Operating Configuration to Serial Port Connector with DCE/DTE programmability
20 (V.11, V.28) DTR_DSR_A
23 (V.11) DTR_DSR_B
1µF1µF
C
VDD
V
CC
V
DD
C1- C2-
C1+ C2+
1µF
SP3508CF
TxD
TxCE
ST
RTS
DTR
DCD_DCE
RL
RxC
TxC
CTS
DSR
DCD_DTE
RI
TM
10µF
µ
DB-26 Serial Port Connector Pins Signal (DTE_DCE)
2 (V .11, V.35, V.28) TXD_RXD_A
14 (V.11, V.35) TXD_RXD_B
11 (V.11, V.35) TXCE_TXC_B
25 (V.10, V.28) LL_TM
15 (V .11, V.35, V .28) *TXC_RXC_A
12 (V.11, V.35) *TXC_RXC_B
SDEN
24 (V .11, V.35, V.28) TXCE_TXC_A
3 (V .11, V.35, V.28) RXD_TXD_A
16 (V.11, V.35) RXD_TXD_B
8 (V.11, V.28) DCD_DCD_A
10 (V.11) DCD_DCD_B
9 (V.11, V.35) RXC_TXCE_B
17 (V .11, V.35, V.28) RXC_TXCE_A
LLEN
STEN
GND
* - Driver applies for DCE only on pins 15 and 12.
Receiver applies for DTE only on pins 15 and 12.
+3.3V
I/O Lines represented by double arrowhead signifies a bi-directional bus.
Input Line
Output Line
LL
RxD
TTEN
RSEN
TREN
RRCEN
RLEN
RDEN
TMEN
TxCEN
RTEN
CSEN
DMEN
RRTEN
ICEN
TERM_OFF
D_LATCH
D0
D1
D2
Charge Pump Section
Transceiver Section
Logic Section
+3.3V
21 (V.10, V.28) RL_RI
22 (V.10, V.28) RI_RL
18 (V.10, V.28) LL_TM
DCE/DTE
Driver applies for DCE only on pins 8 and 10.
Receiver applies for DTE only on pins 8 and 10.
LOOPBACK
+3.3V
19 (V.11) RTS_CTS_B
4 (V.11, V.28) RTS_CTS_A
6 (V.11, V.28) DSR_DTR_A
22 (V.11) DSR_DTR_B
13 (V.11) CTS_RTS_B
5 (V.11, V.28) CTS_RTS_A
31 SD(a)
35
34
38
39
40
42
43
44
41
32
36
45
37
46
AGND
SD(b)
TT(a)
TT(b)
ST(a)
ST(b)
RS(a)
RS(b)
TR(a)
TR(b)
RRC(a)
RRC(b)
RL(a)
RD(a)
LL(a)
RD(b)
RT(a)
RT(b)
TxC(a)
TxC(b)
CS(a)
CS(b)
DM(a)
DM(b)
RRT(a)
RRT(b)
IC
TM(a)
18
19
20
97
99
93
95
89
91
81
83
85
87
79
77
67
50
65
49
51
55
53
57
56
59
58
62
61
63
64
52
21
22
30
28
+3.3V
AV
CC
24
26
68
27
V
SS2
V
SS1
C3+
C3-
6972
7074
76
29
1µF
C1 C2
C3
C
VSS1
C
VSS2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
33
32
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
PACKAGE: 100 PIN LQFP
100 PIN LQFP
PIN 1
E1
D1
D
C
L
be
Seating
Plane
A1
C
LE
A
L
11°-13°
0°MIN
0°–7°
0.2 RAD MAX.
0.08 RAD MIN.
DIMENSIONS
Minimum/Maximum
(mm)
SYMBOL
A
A1
A2
b
D
D1
e
E
E1
N
100–PIN LQFP
JEDEC MS-026
(BED) Variation
MIN NOM MAX
1.60
0.05 0.15
1.35 1.40 1.45
0.17 0.22 0.27
16.00 BSC
14.00 BSC
0.50 BSC
16.00 BSC
14.00 BSC
100
A
c
L1
A2
11°-13°
COMMON DIMENSIONS
SYMBL MIN NOM MAX
c 0.09 0.20
L 0.45 0.60 0.75
L1 1.00 REF
33
Date: 10/12/04 SP3508 Enhanced WAN Multi–Mode Serial Transceiver © Copyright 2004 Sipex Corporation
ORDERING INFORMATION
Part Number Temperature Range Package Types
SP3508CF ............................................. 0°C to +70°C ................................................. 100–pin JEDEC LQFP
SP3508EF ......................................... -40°C to +85°C ................................................. 100–pin JEDEC LQFP
Corporation
ANALOG EXCELLENCE
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
REVISION HISTORY
Available in lead free packaging. To order add “-L” suffix to part number.
Example: SP3508EF = standard; SP3508EF-L = lead free
DATE REVISION DESCRIPTION
1/12/04 A Implemented tracking revision.
2/27/04 B Included Diamond column in spec table indicating which specs apply
over full operating temp. range. In figure 51, fixed typo on pin 61 and
62 from an input line to a bidirectional bus.
3/31/04 C Corrected max dimension for symbol c on LQFP package.
6/3/04 D Added tables to page 27 and 28.
10/12/04 E Certified conformance to NET1/NET2 and TBR-1 TBR-2 BY TUV
Rheinland (Test Report # TBR2/30451940.001/04)
