HAT2139H Silicon N Channel Power MOS FET Power Switching REJ03G0055-0400Z (Previous ADE-208-1580A(Z)) Rev.4.00 Jul.15.2003 Features * * * * Capable of 7 V gate drive Low drive current High density mounting Low on-resistance RDS(on) = 9 m typ. (at VGS = 10 V) Outline LFPAK 5 5 D 4 G 4 1, 2, 3 Source 4 Gate 5 Drain S S S 1 2 3 Rev.4.00, Jul.15.2003, page 1 of 9 3 1 2 HAT2139H Absolute Maximum Ratings (Ta = 25C) Item Symbol Ratings Unit Drain to source voltage VDSS 40 V Gate to source voltage VGSS 20 V Drain current ID 20 A Drain peak current ID(pulse)Note1 80 A Body-drain diode reverse drain current IDR 20 A 10 A Avalanche current IAP Note 3 Avalanche energy EAR Note 3 Channel dissipation Pch Note2 Channel temperature Tch 150 C Storage temperature Tstg -55 to +150 C Notes: 1. PW 10 s, duty cycle 1% 2. Tc = 25C 3. Value at Tch = 25C, Rg 50 Rev.4.00, Jul.15.2003, page 2 of 9 8 mJ 15 W HAT2139H Electrical Characteristics (Ta = 25C) Item Symbol Min Typ Max Unit Test Conditions -- -- V ID = 10 mA, VGS = 0 V(BR)GSS 20 -- -- V IG = 100 A, VDS = 0 Gate to source leak current IGSS -- -- 10 A VGS = 16 V, VDS = 0 Zero gate voltage drain current IDSS -- -- 1 A VDS = 40 V, VGS = 0 Gate to source cutoff voltage VGS(off) 2.0 -- 3.5 V VDS = 10 V, I D = 1 mA Static drain to source on state RDS(on) -- 9.0 11.5 m ID = 10 A, VGS = 10 V Note4 resistance RDS(on) -- 11.0 15.0 m ID = 10 A, VGS = 7 V Note4 Forward transfer admittance |yfs| 15 25 -- S ID = 10 A, VDS = 10 V Note4 Input capacitance Ciss -- 2000 -- pF VDS = 10 V Output capacitance Coss -- 290 -- pF VGS = 0 Reverse transfer capacitance Crss -- 175 -- pF f = 1 MHz Total gate charge Qg -- 30 -- nc VDD = 10 V Gate to source charge Qgs -- 8 -- nc VGS = 10 V Gate to drain charge Qgd -- 5 -- nc ID = 20 A Turn-on delay time td(on) -- 17 -- ns VGS = 10 V, ID = 10 A Rise time tr -- 23 -- ns VDD 10 V Turn-off delay time td(off) -- 58 -- ns RL = 1.0 Fall time tf -- 10 -- ns Rg = 4.7 Body-drain diode forward voltage VDF -- 0.83 1.08 V IF = 20 A, VGS = 0 Note4 -- 50 -- ns IF = 20 A, VGS = 0 diF/ dt = 50 A/ s Drain to source breakdown voltage V(BR)DSS Gate to source breakdown voltage Body-drain diode reverse recovery trr time Notes: 4. Pulse test Rev.4.00, Jul.15.2003, page 3 of 9 40 HAT2139H Main Characteristics Power vs. Temperature Derating Maximum Safe Operation Area (A) 1000 30 ID 1 20 10 50 100 Case Temperature m s DC PW = O 1 10 0 pe m ra tio s n Operation in s 0 s this area is 1 limited by R DS(on) 150 0.1 0.1 1 10 Drain to Source Voltage VDS 200 Tc (C) Typical Output Characteristics 16 Typical Transfer Characteristics V DS = 10 V Pulse Test ID 4.0V 12 3.8 V 8 4 VGS = 3.5 V 100 (V) 20 4.2 V (A) 10 V 4.5 V Drain Current 20 I D (A) 10 Tc = 25C 1 shot Pulse 0 Drain Current 10 100 Drain Current Channel Dissipation Pch (W) 40 16 12 8 Tc = 75C 25C -25C 4 Pulse Test 0 2 4 6 Drain to Source Voltage Rev.4.00, Jul.15.2003, page 4 of 9 8 10 V DS (V) 0 2 4 6 Gate to Source Voltage 10 8 V GS (V) HAT2139H Static Drain to Source on State Resistanc vs. Drain Current Pulse Test 300 200 100 ID = 10 A 5A 2A Static Drain to Source on State Resistance RDS(on) (m) 0 4 8 12 Gate to Source Voltage 16 Pulse Test 25 ID = 10 A 2 A, 5 A 15 VGS = 7 V 10 5 0 -25 10 V ID = 2 A, 5 A, 10 A 0 25 50 75 100 125 150 Case Temperature Tc (C) Rev.4.00, Jul.15.2003, page 5 of 9 Pulse Test 50 20 VGS = 7 V 10 10 V 5 2 1 1 VGS (V) 35 20 100 20 Static Drain to Source on State Resistance vs. Temperature 30 Drain to Source On State Resistance RDS(on) (m) 400 Forward Transfer Admittance |yfs| (S) Drain to Source Voltage VDS(on) (mV) Drain to Source Saturation Voltage vs. Gate to Source Voltage 3 10 Drain Current 30 ID (A) 100 Forward Transfer Admittance vs. Drain Current 100 10 Tc = -25C 1 75C 25C 0.1 VDS = 10 V Pulse Test 0.01 0.01 1 10 0.1 Drain Current ID (A) 100 HAT2139H Body-Drain Diode Reverse Recovery Time Typical Capacitance vs. Drain to Source Voltage 10000 Capacitance C (pF) Reverse Recovery Time trr (ns) 100 50 20 VGS = 0 f = 1 MHz 3000 Ciss 1000 300 Coss di/dt = 50 A/s VGS = 0, Ta = 25C 10 0.1 0.3 1 3 10 30 Reverse Drain Current IDR (A) Crss 100 0 100 30 VDD = 25 V 10 V 5V VDS 0 12 8 20 10 16 VDD = 25 V 10 V 5V 10 20 30 40 Gate Charge Qg (nc) Rev.4.00, Jul.15.2003, page 6 of 9 4 0 50 Switching Time t (ns) VGS 40 30 40 1000 VGS (V) ID = 20 A 20 Switching Characteristics 20 Gate to Source Voltage Drain to Source Voltage VDS (V) Dynamic Input Characteristics 50 10 Drain to Source Voltage VDS (V) 300 100 td(off) 30 td(on) 10 tr tf 3 1 0.1 VGS = 10 V , VDS = 10 V Rg = 4.7 , duty < 1 % 0.3 1 3 10 30 Drain Current ID (A) 100 HAT2139H 16 5V 12 VGS = 0.5 V 8 4 Pulse Test 0 0.4 0.8 1.2 Source to Drain Voltage 1.6 VSD 2.0 (mJ) (A) 10 V 10 Repetitive Avalanche Energy EAR 20 Reverse Drain Current IDR Maximum Avalanche Energy vs. Channel Temperature Derating Reverse Drain Current vs. Source to Drain Voltage 8 IAP = 10 A VDD = 15 V duty < 0.1 % Rg > 50 6 4 2 0 25 (V) 50 75 100 125 150 Channel Temperature Tch (C) Avalanche Test Circuit V DS Monitor Avalanche Waveform EAR = L 1 2 I AP Monitor L * IAP2 * VDSS VDSS - V DD V (BR)DSS I AP Rg D. U. T V DS VDD ID Vin 15 V 50 0 Rev.4.00, Jul.15.2003, page 7 of 9 VDD HAT2139H Normalized Transient Thermal Impedance vs. Pulse Width Normalized Transient Thermal Impedance s (t) 3 Tc = 25C 1 D=1 0.5 0.3 0.2 0.1 ch - c(t) = s (t) * ch - c ch - c = 8.33C/ W, Tc = 25C 0.1 0.05 0.03 PDM 0.02 e uls 1 0.0 0.01 10 D= PW p ot T h 1s PW T 100 1m 100 m 10 m 1 10 Pulse Width PW (s) Switching Time Test Circuit Switching Time Waveform Vout Monitor Vin Monitor Rg 90% D.U.T. RL Vin Vin 10 V V DS = 10 V Vout 10% 10% 90% td(on) Rev.4.00, Jul.15.2003, page 8 of 9 tr 10% 90% td(off) tf HAT2139H Package Dimensions As of January, 2003 Unit: mm 4.9 5.3 Max 4.0 0.2 +0.05 4.2 6.1 -0.3 +0.1 3.95 5 4 0 - 8 +0.25 +0.05 *0.20 -0.03 0.6 -0.20 1.3 Max 1 1.1 Max +0.03 0.07 -0.04 3.3 1.0 0.25 -0.03 0.75 Max 0.10 1.27 *0.40 0.06 *Ni/Pd/Au plating Rev.4.00, Jul.15.2003, page 9 of 9 0.25 M Package Code JEDEC JEITA Mass (reference value) LFPAK -- -- 0.080 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. http://www.renesas.com (c) 2003. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 0.0