CY62147EV30 MoBL(R) 4-Mbit (256K x 16) Static RAM 4-Mbit (256K x 16) Static RAM Features portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99 percent when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when: Very high speed: 45 ns Temperature ranges Industrial: -40 C to +85 C Wide voltage range: 2.20 V to 3.60 V Pin compatible with CY62147DV30 Ultra low standby power Typical standby current: 1 A Maximum standby current: 7 A (Industrial) Ultra low active power Typical active current: 2 mA at f = 1 MHz [1] and OE features Easy memory expansion with CE Automatic power-down when deselected Complementary metal oxide semiconductor (CMOS) for optimum speed and power Available in Pb-free 48-ball very fine ball grid array (VFBGA) (single/dual CE option) and 44-pin thin small outline package (TSOP) II packages Byte power-down feature Deselected (CE HIGH) Outputs are disabled (OE HIGH) Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) Write operation is active (CE LOW and WE LOW) To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of read and write modes. For a complete list of related documentation, click here. Functional Description The CY62147EV30 is a high performance CMOS static RAM (SRAM) organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. It is ideal for providing More Battery LifeTM (MoBL) in Logic Block Diagram SENSE AMPS ROW DECODER DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 256K x 16 RAM Array I/O0-I/O7 I/O8-I/O15 COLUMN DECODER A17 A15 A16 A13 A14 CIRCUIT A12 BHE BLE A11 CE POWER DOWN BHE WE [1] CE OE BLE Note 1. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Cypress Semiconductor Corporation Document Number: 38-05440 Rev. *R * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised December 5, 2017 CY62147EV30 MoBL(R) Contents Product Portfolio .............................................................. 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Load and Waveforms ......................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 11 Document Number: 38-05440 Rev. *R Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagrams .......................................................... 13 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC(R)Solutions ....................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 CY62147EV30 MoBL(R) Product Portfolio Product Range CY62147EV30LL Speed (ns) VCC Range (V) Min Typ [2] Max 2.2 3.0 3.6 Industrial 45 Power Dissipation Operating ICC (mA) f = 1 MHz Standby ISB2 (A) f = fmax Typ [2] Max Typ [2] Max Typ [2] Max 2 2.5 15 20 1 7 Pin Configurations Figure 1. 48-ball VFBGA pinout (Single Chip Enable) [3, 4] 1 2 3 4 5 6 A BLE OE A0 A1 A2 CE2 A I/O0 B I/O8 BHE A3 A4 CE1 I/O0 B I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 C VCC D VSS I/O11 A17 A7 VCC D I/O4 VSS E VCC NC A16 I/O4 VSS E A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 F 1 2 3 4 5 6 BLE OE A0 A1 A2 NC I/O8 BHE A3 A4 CE I/O9 I/O10 A5 A6 I/O1 VSS I/O11 A17 A7 VCC NC A16 I/O14 I/O13 A14 I/O12 Figure 2. 48-ball VFBGA pinout (Dual Chip Enable) [3, 4] I/O3 I/O12 I/O3 I/O15 NC A12 A13 WE I/O7 G I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H NC A8 A9 A10 A11 NC H Figure 3. 44-pin TSOP II pinout [3] A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A17 A16 A15 A14 A13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A8 A9 A10 A11 A12 Notes 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 3. NC pins are not connected on the die. 4. Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively. Document Number: 38-05440 Rev. *R Page 3 of 18 CY62147EV30 MoBL(R) DC input voltage [5, 6] ....... -0.3 V to 3.9 V (VCC(max) + 0.3 V) Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature ............................... -65 C to + 150 C Ambient temperature with power applied ................................... -55 C to +125 C Supply voltage to ground potential ........ -0.3 V to + 3.9 V (VCC(max) + 0.3 V) DC voltage applied to outputs in High Z state [5, 6] .......... -0.3 V to 3.9 V (VCC(max) + 0.3 V) Output current into outputs (LOW) ............................. 20 mA Static discharge voltage (MIL-STD-883, method 3015) ................................ > 2001 V Latch-up current .................................................... > 200 mA Operating Range Device Range Ambient Temperature VCC [7] CY62147EV30LL Industrial -40 C to +85 C 2.2 V to 3.6 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 45 ns (Industrial) Min Typ [8] Max Unit IOH = -0.1 mA 2.0 - - V IOH = -1.0 mA, VCC > 2.70 V 2.4 - - V IOL = 0.1 mA - - 0.4 V IOL = 2.1 mA, VCC = 2.70 V - - 0.4 V VCC = 2.2 V to 2.7 V 1.8 - VCC + 0.3 V VCC= 2.7 V to 3.6 V 2.2 - VCC + 0.3 V VCC = 2.2 V to 2.7 V -0.3 - 0.6 V VCC= 2.7 V to 3.6 V -0.3 - 0.8 V IIX Input leakage current GND < VI < VCC -1 - +1 A IOZ Output leakage current GND < VO < VCC, output disabled -1 - +1 A ICC VCC operating supply current f = fmax = 1/tRC - 15 20 mA - 2 2.5 f = 1 MHz VCC = VCC(max) IOUT = 0 mA CMOS levels ISB1[9] Automatic CE power-down CE > VCC - 0.2 V, current - CMOS inputs VIN > VCC - 0.2 V, VIN < 0.2 V, f = fmax (address and data only), f = 0 (OE, BHE, BLE and WE), VCC = 3.60 V - 1 7 A ISB2 [9] Automatic CE power-down CE > VCC - 0.2 V, current - CMOS inputs VIN > VCC - 0.2 V or VIN < 0.2 V, f = 0, VCC = 3.60 V - 1 7 A Notes 5. VIL(min) = -2.0 V for pulse durations less than 20 ns. 6. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns. 7. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 9. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document Number: 38-05440 Rev. *R Page 4 of 18 CY62147EV30 MoBL(R) Capacitance Parameter [10] Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Thermal Resistance Parameter [10] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) 48-ball VFBGA 44-pin TSOP II Unit Package Package Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 42.10 55.52 C/W 23.45 16.03 C/W AC Test Load and Waveforms Figure 4. AC Test Load and Waveforms R1 VCC OUTPUT VCC 30 pF 10% GND Rise Time = 1 V/ns R2 INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THEVENIN EQUIVALENT OUTPUT Parameters 2.50 V R1 R2 RTH VTH 3.0 V Unit 16667 1103 15385 1554 RTH 8000 645 VTH 1.20 1.75 V Note 10. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-05440 Rev. *R Page 5 of 18 CY62147EV30 MoBL(R) Data Retention Characteristics Over the Operating Range Parameter VDR Description Conditions VCC for data retention ICCDR [12] Data retention current VCC = 1.5 V, CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V Min Typ [11] Max Unit 1.5 - - V - 0.8 7 A tCDR [13] Chip deselect to data retention time 0 - - ns tR [14] Operation recovery time 45 - - ns Data Retention Waveform Figure 5. Data Retention Waveform [15, 16] DATA RETENTION MODE VCC CE or VCC(min) tCDR VDR > 1.5V VCC(min) tR BHE.BLE Notes 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 C. 12. Chip enable (CE) and byte enables (BHE and BLE) need to be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 13. Tested initially and after any design or process changes that may affect these parameters. 14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 15. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 16. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling the chip enable signals or by disabling both BHE and BLE. Document Number: 38-05440 Rev. *R Page 6 of 18 CY62147EV30 MoBL(R) Switching Characteristics Over the Operating Range Parameter [17, 18] Description 45 ns (Industrial) Min Max Unit Read Cycle tRC Read cycle time 45 - ns tAA Address to data valid - 45 ns tOHA Data hold from address change 10 - ns tACE CE LOW to data valid - 45 ns tDOE OE LOW to data valid - 22 ns 5 - ns - 18 ns tLZOE tHZOE OE LOW to low Z [19] OE HIGH to high Z [19, 20] [19] tLZCE CE LOW to low Z 10 - ns tHZCE CE HIGH to high Z [19, 20] - 18 ns tPU CE LOW to power-up 0 - ns tPD CE HIGH to power-down - 45 ns tDBE BLE/BHE LOW to data valid - 45 ns tLZBE BLE/BHE LOW to low Z [19, 21] 5 - ns - 18 ns tHZBE Write Cycle BLE/BHE HIGH to high Z [19, 20] [22, 23] tWC Write cycle time 45 - ns tSCE CE LOW to write end 35 - ns tAW Address setup to write end 35 - ns tHA Address hold from write end 0 - ns tSA Address setup to write start 0 - ns tPWE WE pulse width 35 - ns tBW BLE/BHE LOW to write end 35 - ns tSD Data setup to write end 25 - ns tHD Data hold from write end 0 - ns tHZWE WE LOW to high Z [19, 20] - 18 ns 10 - ns tLZWE WE HIGH to low Z [19] Notes 17. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns (1V/ns) or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 4 on page 5. 18. In an earlier revision of this device, under a specific application condition, READ and WRITE operations were limited to switching of the byte enable and/or chip enable signals as described in the Application Notes AN13842 and AN66311. However, the issue has been fixed and in production now, and hence, these Application Notes are no longer applicable. They are available for download on our website as they contain information on the date code of the parts, beyond which the fix has been in production. 19. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 20. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 21. If both byte enables are toggled together, this value is 10 ns. 22. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 23. The minimum write cycle pulse width for Write Cycle No. 3 (WE Controlled, OE LOW) should be equal to the sum of tSD and tHZWE. Document Number: 38-05440 Rev. *R Page 7 of 18 CY62147EV30 MoBL(R) Switching Waveforms Figure 6. Read Cycle No. 1 (Address Transition Controlled) [24, 25] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 7. Read Cycle No. 2 (OE Controlled) [25, 26, 27] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB Notes 24. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL. 25. WE is HIGH for read cycle. 26. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 27. Address valid before or similar to CE and BHE, BLE transition LOW. Document Number: 38-05440 Rev. *R Page 8 of 18 CY62147EV30 MoBL(R) Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (WE Controlled) [28, 29, 30, 31] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA I/O tSD tHD DATAIN NOTE 32 tHZOE Figure 9. Write Cycle No. 2 (CE Controlled) [28, 29, 30, 31] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 32 tHZOE Notes 28. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 29. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE, or both = VIL. All signals must be active to initiate a write and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write. 30. Data I/O is high impedance if OE = VIH. 31. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 32. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05440 Rev. *R Page 9 of 18 CY62147EV30 MoBL(R) Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (WE Controlled, OE LOW) [33, 34, 35] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA I/O NOTE 36 tHD DATAIN tLZWE tHZWE Figure 11. Write Cycle No. 4 (BHE/BLE Controlled) [33, 34] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 36 tSD tHD DATAIN tLZWE Notes 33. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 34. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 35. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE. 36. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 38-05440 Rev. *R Page 10 of 18 CY62147EV30 MoBL(R) Truth Table CE [37, 38] WE OE BHE BLE H X X X X High Z Deselect/Power-down Standby (ISB) L X X H H High Z Deselect/Power-down Standby (ISB) L H L L L Data out (I/O0-I/O15) Read Active (ICC) L H L H L Data out (I/O0-I/O7); I/O8-I/O15 in High Z Read Active (ICC) L H L L H Data out (I/O8-I/O15); I/O0-I/O7 in High Z Read Active (ICC) L H H L L High Z Output disabled Active (ICC) L H H H L High Z Output disabled Active (ICC) L H H L H High Z Output disabled Active (ICC) L L X L L Data in (I/O0-I/O15) Write Active (ICC) L L X H L Data in (I/O0-I/O7); I/O8-I/O15 in High Z Write Active (ICC) L L X L H Data in (I/O8-I/O15); I/O0-I/O7 in High Z Write Active (ICC) I/Os Mode Power Notes 37. BGA packaged device is offered in single CE and dual CE options. In this data sheet, for a dual CE device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. 38. For the Dual Chip Enable device, CE refers to the internal logical combination of CE1 and CE2 such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH. Intermediate voltage levels are not permitted on any of the Chip Enable pins (CE for the Single Chip Enable device; CE1 and CE2 for the Dual Chip Enable device). Document Number: 38-05440 Rev. *R Page 11 of 18 CY62147EV30 MoBL(R) Ordering Information Speed (ns) 45 Ordering Code Package Diagram Package Type CY62147EV30LL-45BVI 51-85150 48-ball VFBGA [39] CY62147EV30LL-45BVXI 51-85150 48-ball VFBGA (Pb-free) [39] CY62147EV30LL-45B2XI 51-85150 48-ball VFBGA (Pb-free) [40] CY62147EV30LL-45ZSXI 51-85087 44-pin TSOP Type II (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 621 4 7 E V30 LL - 45 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = ZS or BV or B2 ZS = 44-pin TSOP Type II BV = 48-ball VFBGA B2 = 48-ball VFBGA Dual Chip Enable Speed Grade: 45 ns Low Power Voltage Range: 3 V Typical Process Technology: E = 90 nm Bus Width: 7 = x 16 Density: 4 = 4-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Notes 39. This BGA package is offered with single chip enable. 40. This BGA package is offered with dual chip enable. Document Number: 38-05440 Rev. *R Page 12 of 18 CY62147EV30 MoBL(R) Package Diagrams Figure 12. 48-ball VFBGA (6 x 8 x 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 38-05440 Rev. *R Page 13 of 18 CY62147EV30 MoBL(R) Package Diagrams (continued) Figure 13. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Document Number: 38-05440 Rev. *R Page 14 of 18 CY62147EV30 MoBL(R) Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory ns nanosecond TSOP Thin Small Outline Package ohm VFBGA Very Fine-Pitch Ball Grid Array pF picofarad WE Write Enable V volt W watt Document Number: 38-05440 Rev. *R Symbol Unit of Measure Page 15 of 18 CY62147EV30 MoBL(R) Document History Page Document Title: CY62147EV30 MoBL(R), 4-Mbit (256K x 16) Static RAM Document Number: 38-05440 Revision ECN Orig. of Change Submission Date ** 201861 AJU 01/13/04 New data sheet. *A 247009 SYT See ECN Changed status from Advanced Information to Preliminary Moved Product Portfolio to Page 2 Changed Vcc stabilization time in footnote #8 from 100 s to 200 s Removed Footnote #15(tLZBE) from Previous Revision Changed ICCDR from 2.0 A to 2.5 A Changed typo in Data Retention Characteristics(tR) from 100 s to tRC ns Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for 45 ns Speed Bin Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns Speed Bin Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns Speed Bin Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for 45 ns Speed Bin Changed tDOE from 15 to 18 ns for 35 ns Speed Bin Changed Ordering Information to include Pb-Free Packages *B 414807 ZSD See ECN Changed status from Preliminary to Final Changed the address of Cypress Semiconductor Corporation on Page #1 from "3901 North First Street" to "198 Champion Court" Removed 35ns Speed Bin, "L" version of CY62147EV30 Changed ball E3 from DNU to NC. Removed redundant foot note on DNU. Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from 1.5 mA to 2 mA at f = 1 MHz Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from 2.5 A to 7 A. Changed ICCDR from 2.5 A to 7 A. Added ICCDR typical value. Changed AC test load capacitance from 50 pF to 30 pF on Page #4, changed tLZOE from 3 ns to 5 ns, changed tLZCE, tLZBE and tLZWE from 6 ns to 10 ns, changed tHZCE from 22 ns to 18 ns, changed tPWE from 30 ns to 35 ns and changed tSD from 22 ns to 25 ns. Updated the package diagram 48-pin VFBGA from *B to *D Updated the ordering information table and replaced the Package Name column with Package Diagram. *C 464503 NXR See ECN Included Automotive Range in product offering Updated Ordering Information. *D 925501 VKN See ECN Added Preliminary Automotive-A information Added footnote #9 related to ISB2 and ICCDR Added footnote #14 related AC timing parameters *E 1045701 VKN See ECN Converted Automotive-A and Automotive -E specs from preliminary to final *F 2577505 VKN / PYRS 10/03/08 Added -45B2XI part (Dual CE option) *G 2681901 VKN / PYRS 04/01/09 Added CY62147EV30LL-45ZSXA in the ordering information table *H 2886488 AJU 03/02/2010 Document Number: 38-05440 Rev. *R Description of Change Added Contents. Added Note 38. Updated Package Diagrams. Updated links in Sales, Solutions, and Legal Information. Page 16 of 18 CY62147EV30 MoBL(R) Document History Page (continued) Document Title: CY62147EV30 MoBL(R), 4-Mbit (256K x 16) Static RAM Document Number: 38-05440 Revision ECN Orig. of Change Submission Date *I 3109050 PRAS 12/13/2010 Changed Table Footnotes to Notes. Added Ordering Code Definitions. *J 3123973 RAME 01/31/2011 Separated Industrial and Auto parts from this datasheet Removed Automotive info Added Acronyms and Units of Measure. *K 3296744 RAME 08/09/2011 Updated Functional Description (Removed reference to AN1064 SRAM system guidelines). Added ISB1 to footnote 9 and 12. Notes 17 and 18 moved to parameter section of Switching Characteristics. Added Note 21 and referred the same note in the description of tLZBE parameter. *L 3456837 TAVA 12/06/2011 Updated Package Diagrams. Updated to new template. *M 3724736 JISH 08/23/2012 Fixed typo errors and minor clean-up. *N 4102445 VINI 08/22/2013 Updated Switching Characteristics: Updated Note 18. Updated Package Diagrams: spec 51-85150 - Changed revision from *G to *H. spec 51-85087 - Changed revision from *D to *E. Updated to new template. Completing Sunset Review. *O 4576526 VINI 11/21/2014 Updated Functional Description: Added "For a complete list of related documentation, click here." at the end. Updated Switching Characteristics: Added Note 23 and referred the same note in "Write Cycle". Updated Switching Waveforms: Added Note 35 and referred the same note in Figure 10. *P 4918858 VINI 09/14/2015 Updated Switching Waveforms: Updated caption of Figure 11 (Removed "OE LOW"). Updated to new template. Completing Sunset Review. *Q 5445135 VINI 09/22/2016 Updated Thermal Resistance: Updated all values of JA and JC parameters. Updated to new template. Completing Sunset Review. *R 5984537 AESATMP9 12/05/2017 Updated logo and copyright. Document Number: 38-05440 Rev. *R Description of Change Page 17 of 18 CY62147EV30 MoBL(R) Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R)Solutions Products ARM(R) Cortex(R) Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless (c) Cypress Semiconductor Corporation, 2004-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). 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Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-05440 Rev. *R Revised December 5, 2017 Page 18 of 18