Si5347/46 Rev D Data Sheet
Dual/Quad DSPLL™ Any-Frequency, Any-Output Jitter Attenua-
tors
The Si5347 is a high-performance, jitter-attenuating clock multiplier which integrates
four any-frequency DSPLLs for applications that require maximum integration and inde-
pendent timing paths. The Si5346 is a dual DSPLL version in a smaller package. Each
DSPLL has access to any of the four inputs and can provide low jitter clocks on any of
the device outputs. Based on 4th generation DSPLL technology, these devices provide
any-frequency conversion with typical jitter performance under 100 fs. Each DSPLL
supports independent free-run, holdover modes of operation, as well as automatic and
hitless input clock switching. The Si5347/46 is programmable via a serial interface with
in-circuit programmable non-volatile memory so that it always powers up in a known
configuration. Programming the Si5347/46 is easy with Silicon Labs' ClockBuilder
Pro™ software. Factory preprogrammed devices are also available.
Applications
• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• Broadcast video
KEY FEATURES
• Four or two independent DSPLLs, any
output frequency from any input frequency
•Ultra-low jitter of 95 fs rms
• Input frequency range:
• External Crystal: 25–54 MHz
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• Differential: 100 Hz to 720 MHz
• LVCMOS: 100 Hz to 250 MHz
• Status Monitoring
• Hitless switching
• Si5347: 4 input, 8 output, 64-QFN 9×9 mm
• Si5346: 4 input, 4 output, 44-QFN 7×7 mm
OUT7
OUT6
OUT5
OUT1
OUT4
OUT3
OUT2
OUT0
Si5346A/B
Si5347A/B
I2C / SPI Control NVM
Status Flags Status Monitor
XBXA
25-54 MHz XTAL
OSC
÷FRAC DSPLL D
DSPLL C
DSPLL B
DSPLL A
÷FRAC
÷FRAC
÷FRAC
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
÷INT
4 Input
Clocks
IN0
IN1
IN2
IN3
Si5347C/D
silabs.com | Building a more connected world. Rev. 1.1
Table of Contents
1. Feature List ................................4
2. Ordering Guide ..............................5
3. Functional Description............................6
3.1 Frequency Configuration ..........................6
3.2 DSPLL Loop Bandwidth ...........................6
3.2.1 Fastlock Feature ............................6
3.3 Modes of Operation ............................6
3.3.1 Initialization and Reset ..........................6
3.3.2 Free-run Mode ............................7
3.3.3 Lock Acquisition Mode ..........................7
3.3.4 Locked Mode .............................7
3.3.5 Holdover Mode ............................8
3.4 Digitally-Controlled Oscillator (DCO) Mode ....................8
3.5 External Reference (XA/XB) .........................9
3.6 Inputs (IN0, IN1, IN2, IN3) ..........................10
3.6.1 Input Selection ............................10
3.6.2 Manual Input Selection ..........................10
3.6.3 Automatic Input Selection .........................10
3.6.4 Input Configuration and Terminations .....................11
3.6.5 Hitless Input Switching ..........................12
3.6.6 Ramped Input Switching .........................12
3.6.7 Glitchless Input Switching .........................12
3.6.8 Synchronizing to Gapped Input Clocks ....................12
3.7 Fault Monitoring .............................13
3.7.1 Input LOS Detection...........................13
3.7.2 XA/XB LOS Detection ..........................13
3.7.3 OOF Detection ............................14
3.7.4 LOL Detection.............................15
3.7.5 Interrupt Pin (INTRb) ..........................17
3.8 Outputs ................................17
3.8.1 Output Crosspoint ...........................18
3.8.2 Differential Output Terminations.......................19
3.8.3 LVCMOS Output Terminations .......................19
3.8.4 Output Signal Format ..........................19
3.8.5 Programmable Common Mode Voltage For Differential Outputs ............19
3.8.6 LVCMOS Output Impedance Selection ....................20
3.8.7 LVCMOS Output Signal Swing .......................20
3.8.8 LVCMOS Output Polarity .........................20
3.8.9 Output Enable/Disable ..........................21
3.8.10 Output Disable During LOL ........................21
3.8.11 Output Disable During XAXB_LOS .....................21
3.8.12 Output Driver State When Disabled .....................21
3.8.13 Synchronous/Asynchronous Output Disable ..................21
silabs.com | Building a more connected world. Rev. 1.1 | 2
3.8.14 Output Divider (R) Synchronization .....................22
3.9 Power Management ............................22
3.10 In-Circuit Programming...........................22
3.11 Serial Interface .............................22
3.12 Custom Factory Preprogrammed Parts .....................22
3.13 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory
Pre-programmed Devices ..........................22
4. Register Map ..............................24
5. Electrical Specifications ..........................25
6. Typical Application Schematic ........................39
7. Detailed Block Diagrams ..........................40
8. Typical Operating Characteristics (Jitter and Phase Noise) .............42
9. Pin Descriptions .............................44
10. Package Outlines ............................49
10.1 Si5347 9x9 mm 64-QFN Package Diagram ....................49
10.2 Si5346 7x7 mm 44-QFN Package Diagram ....................50
11. PCB Land Pattern ............................51
12. Top Marking ..............................53
13. Device Errata ..............................54
14. Revision History............................. 55
silabs.com | Building a more connected world. Rev. 1.1 | 3
1. Feature List
The Si5347/46-D features are listed below:
• Four or two DSPLLs to synchronize to multiple inputs
• Generates any combination of output frequencies from any in-
put frequency
• Ultra low jitter:
• 95 fs typ (12 kHz – 20 MHz)
• Input frequency range:
• Differential: 8 kHz to 750 MHz
• LVCMOS: 8 kHz to 250 MHz
• Output frequency range:
• Differential: up to 720 MHz
• LVCMOS: up to 250 MHz
• Flexible crosspoints route any input to any output clock
• Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz
to 4 kHz
• Highly configurable outputs compatible with LVDS, LVPECL,
LVCMOS, CML, and HCSL with programmable signal ampli-
tude
• Status monitoring (LOS, OOF, LOL)
• Hitless input clock switching: automatic or manual
• Locks to gapped clock inputs
•Automatic free-run and holdover modes
• Fastlock feature for low nominal bandwidths
• Glitchless on-the-fly DSPLL frequency changes
• DCO mode: as low as 0.01 ppb steps per DSPLL
• Core voltage:
• VDD: 1.8 V ±5%
• VDDA: 3.3 V ±5%
• Independent output clock supply pins: 3.3, 2.5, or 1.8 V
• Output-output skew:
• Using same DSPLL: 65 ps (Max)
•Serial interface: I2C or SPI
• In-circuit programmable with non-volatile OTP memory
•ClockBuilder Pro software simplifies device configuration
• Si5347: Quad DSPLL, 64-QFN 9×9 mm
• Si5346: Dual DSPLL, 44-QFN 7×7 mm
• Temperature range: –40 to +85 °C
• Pb-free, RoHS-6 compliant
Si5347/46 Rev D Data Sheet
Feature List
silabs.com | Building a more connected world. Rev. 1.1 | 4
2. Ordering Guide
Table 2.1. Si5347/46 Ordering Guide
Ordering Part Number Number Of
DSPLLs
Number of
Outputs
Output Clock
Frequency Range
Package RoHS-6,
Pb-Free
Temp Range
Si5347A-D-GM1,2 4 8 0.0001 to 720 MHz 64-Lead 9x9
QFN
Yes –40 to 85 °C
Si5347B-D-GM1,2 0.0001 to 350 MHz
Si5347C-D-GM1,2 4 0.0001 to 720 MHz
Si5347D-D-GM1,2 0.0001 to 350 MHz
Si5346A-D-GM1,2 2 4 0.0001 to 720 MHz 44-Lead 7x7
QFN
Si5346B-D-GM1,2 0.0001 to 350 MHz
Si5347-D-EVB — — — Evaluation
Board
— —
Si5346-D-EVB — — — — —
Notes:
1. Add an R at the end of the device part number to denote tape and reel ordering options.
2. Custom, factory pre-programmed devices are available. Ordering part numbers are assigned by the ClockBuilder Pro software.
Part number format is: Si5347A-Dxxxxx-GM or Si5346A-Dxxxxx-GM, where “xxxxx” is a unique numerical sequence representing
the pre-programmed configuration.
Si534fg-Rxxxxx-GM
Timing product family
f = Multi-PLL clock family member (7, 6)
g = Device grade (A, B, C, D)
Product Revision*
Custom ordering part number (OPN) sequence ID**
Package, ambient temperature range (QFN, -40 °C to +85°C)
*See Ordering Guide table for current product revision
** 5 digits; assigned by ClockBuilder Pro
Figure 2.1. Ordering Part Number Fields
Si5347/46 Rev D Data Sheet
Ordering Guide
silabs.com | Building a more connected world. Rev. 1.1 | 5
3. Functional Description
The Si5347 takes advantage of Silicon Labs’ 4th generation DSPLL technology to offer the industry’s most integrated and flexible jitter
attenuating clock generator solution. Each of the DSPLLs operate independently from each other and are controlled through a common
serial interface. Each DSPLL has access to any of the four inputs (IN0 to IN3) with manual or automatic input selection. Any of the
output clocks (OUT0 to OUT7) can be configured to any of the DSPLLs using a flexible crosspoint connection. The Si5346 is a smaller
form factor dual DSPLL version with four inputs and four outputs.
3.1 Frequency Configuration
The frequency configuration for each of the DSPLLs is programmable through the serial interface and can also be stored in non-volatile
memory. The combination of fractional input dividers (Pn/Pd), fractional frequency multiplication (Mn/Md), and integer output division
(Rn) allows each of the DSPLLs to lock to any input frequency and generate virtually any output frequency. All divider values for a spe-
cific frequency plan are easily determined using the ClockBuilder Pro software.
3.2 DSPLL Loop Bandwidth
The DSPLL loop bandwidth determines the amount of input clock jitter attenuation. Register-configurable DSPLL loop bandwidth set-
tings in the range of 0.1 Hz to 4 kHz are available for selection for each of the DSPLLs. Since the loop bandwidth is controlled digitally,
each of the DSPLLs will always remain stable with less than 0.1 dB of peaking regardless of the loop bandwidth selection.
3.2.1 Fastlock Feature
Selecting a low DSPLL loop bandwidth (e.g. 0.1 Hz) will generally lengthen the lock acquisition time. The fastlock feature allows setting
a temporary Fastlock Loop Bandwidth that is used during the lock acquisition process. Higher fastlock loop bandwidth settings will ena-
ble the DSPLLs to lock faster. Fastlock Loop Bandwidth settings in the range of 100 Hz to 4 kHz are available for selection. Once lock
acquisition has completed, the DSPLL’s loop bandwidth will automatically revert to the DSPLL Loop Bandwidth setting, as described in
Section 3.2 DSPLL Loop Bandwidth. The fastlock feature can be enabled or disabled independently for each of the DSPLLs.
3.3 Modes of Operation
Once initialization is complete, each of the DSPLLs operates independently in one of four modes: Free-run Mode, Lock Acquisition
Mode, Locked Mode, or Holdover Mode. A state diagram showing the modes of operation is shown in Figure 3.1 Modes of Operation
on page 7. The following sections describe each of these modes in greater detail.
3.3.1 Initialization and Reset
Once power is applied, the device begins an initialization period where it downloads default register values and configuration data from
NVM and performs other initialization tasks. Communicating with the device through the serial interface is possible once this initializa-
tion period is complete. No clocks will be generated until the initialization is complete. There are two types of resets available. A hard
reset is functionally similar to a device power-up. All registers will be restored to the values stored in NVM, and all circuits will be re-
stored to their initial state including the serial interface. A hard reset is initiated using the RSTb pin or by asserting the hard register
reset bit. A soft reset bypasses the NVM download. It is simply used to initiate register configuration changes. A hard reset affects all
DSPLLs, while a soft reset can either affect all or each DSPLL individually.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 6
No valid
input clocks
selected
Lock Acquisition
(Fast Lock)
Locked
Mode
Holdover
Mode
Phase lock on
selected input
clock is achieved
An input is
qualified and
available for
selection
No valid input
clocks available
for selection
Free-run
Valid input clock
selected
Reset and
Initialization
Power-Up
Selected input
clock fails
Yes
No
Holdover
History
Valid?
Other Valid
Clock Inputs
Available?
No
Yes
Input Clock
Switch
Figure 3.1. Modes of Operation
3.3.2 Free-run Mode
Once power is applied to the Si5347 and initialization is complete, all four DSPLLs will automatically enter Free-run Mode. The frequen-
cy accuracy of the generated output clocks in Free-run Mode is entirely dependent on the frequency accuracy of the external crystal or
reference clock on the XA/XB pins. For example, if the crystal frequency is ±100 ppm, then all the output clocks will be generated at
their configured frequency ±100 ppm in Free-run Mode. Any drift of the crystal frequency will be tracked at the output clock frequencies.
A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in Free-run Mode or Hold-
over Mode.
3.3.3 Lock Acquisition Mode
Each of the DSPLLs independently monitors its configured inputs for a valid clock. If at least one valid clock is available for synchroni-
zation, a DSPLL will automatically start the lock acquisition process.
If the fast lock feature is enabled, a DSPLL will acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL
Loop Bandwidth setting when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO
frequency change as it pulls-in to the input clock frequency.
3.3.4 Locked Mode
Once locked, a DSPLL will generate output clocks that are both frequency and phase locked to their selected input clocks. At this point,
any XTAL frequency drift will not affect the output frequency. Each DSPLL has its own LOLb pin and status bit to indicate when lock is
achieved. See 3.7.4 LOL Detection for more details on the operation of the loss of lock circuit.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 7
3.3.5 Holdover Mode
Any of the DSPLLs will automatically enter Holdover Mode when the selected input clock becomes invalid and no other valid input
clocks are available for selection. Each DSPLL uses an averaged input clock frequency as its final holdover frequency to minimize the
disturbance of the output clock phase and frequency when an input clock suddenly fails. The holdover circuit for each DSPLL stores up
to 120 seconds of historical frequency data while locked to a valid clock input. The final averaged holdover frequency value is calcula-
ted from a programmable window within the stored historical frequency data. Both the window size and delay are programmable, as
shown in the figure below. The window size determines the amount of holdover frequency averaging. The delay value allows ignoring
frequency data that may be corrupt just before the input clock failure.
Programmable delay
Clock Failure and
Entry into Holdover
time
Historical Frequency Data Collected
Programmable historical data window
used to determine the final holdover value
120 seconds
Figure 3.2. Programmable Holdover Window
When entering Holdover Mode, a DSPLL will pull its output clock frequency to the calculated averaged holdover frequency. While in
Holdover Mode, the output frequency drift is entirely dependent on the external crystal or external reference clock connected to the
XA/XB pins. If the clock input becomes valid, a DSPLL will automatically exit the Holdover Mode and reacquire lock to the new input
clock. This process involves pulling the output clock frequencies to achieve frequency and phase lock with the input clock. This pull-in
process is glitchless, and its rate is controlled by the DSPLL bandwidth or the fastlock bandwidth. These options are register program-
mable.
Add new section The DSPLL output frequency when exiting holdover can be ramped (recommended). Just before the exit is initiated,
the difference between the current holdover frequency and the new desired frequency is measured. Using the calculated difference and
a user-selectable ramp rate, the output is linearly ramped to the new frequency. The ramp rate can be 0.2 ppm/s, 40,000 ppm/s, or any
of about 40 values in between. The DSPLL loop BW does not limit or affect ramp rate selections (and vice versa). CBPro defaults to
ramped exit from holdover. The same ramp rate settings are used for both exit from holdover and ramped input switching. For more
information on ramped input switching, see 3.6.6 Ramped Input Switching.
Note: If ramped holdover exit is not selected, the holdover exit is governed either by (1) the DSPLL loop BW or (2) a user-selectable
holdover exit BW.
3.4 Digitally-Controlled Oscillator (DCO) Mode
The DSPLLs support a DCO mode where their output frequencies are adjustable in predefined steps defined by frequency step words
(FSW).The frequency adjustments are controlled through the serial interface or by pin control using frequency increment (FINC) or dec-
rement (FDEC). A FINC will add the frequency step word to the DSPLL output frequency, while a FDEC will decrement it. The DCO
mode is available when the DSPLL is operating in either Free-run or Locked Mode.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 8
3.5 External Reference (XA/XB)
An external crystal (XTAL) is used in combination with the internal oscillator (OSC) to produce an ultra-low jitter reference clock for the
DSPLLs and for providing a stable reference for the Free-run and Holdover Modes. A simplified diagram is shown in the figure below.
The device includes internal XTAL loading capacitors, which eliminates the need for external capacitors and also has the benefit of
reduced noise coupling from external sources. Refer to Table 5.12 Crystal Specifications1 on page 36 for crystal specifications. A
crystal in the range of 48 MHz to 54 MHz is recommended for best jitter performance. The Si5347-46 Rev D Reference Manual pro-
vides additional information on PCB layout recommendations for the crystal to ensure optimum jitter performance.
To achieve optimal jitter performance and minimize BOM cost, a crystal is recommended on the XA/XB reference input. For SyncE line
card PLL applications (e.g. loop bandwidth set to 0.1 Hz), a TCXO is required on the XA/XB reference to minimize wander and to pro-
vide a stable holdover reference. See the Si5347-46 Rev D Reference Manual for more information. Selection between the external
XTAL or REFCLK is controlled by register configuration. The internal crystal loading capacitors (CL) are disabled in the REFCLK mode.
Refer to Table 5.3 Input Clock Specifications on page 27 for REFCLK requirements when using this mode. The Si5347-46 Rev D
Reference Manual provides additional information on PCB layout recommendations for the crystal to ensure optimum jitter perform-
ance. A PREF divider is available to accommodate external clock frequencies higher than 54 MHz. Although the REFCLK frequency
range of 25 MHz to 54 MHz is supported, frequencies in the range of 48 MHz to 54 MHz will achieve the best output jitter performance.
Differential XO/Clock
Connection
2xCL2xCL
XB XA
OSC
÷ PREF
25-54 MHz XO/Clock
LVCMOS XO/Clock
Connection
2xCL2xCL
XB XA
OSC
÷ PREF
R2
R1
C1
25-54 MHz XO/Clock LVCMOS
Crystal Resonator
Connection
2xCL2xCL
XB XA
OSC
÷ PREF
25-54 MHz XTAL
X1
X2 X1 X2
NC NC
X1 X2
NC NC
Note: See Pin
Descriptions for
X1/X2 connections
C1 is recommended to
increase the slew rate
at Xa
See the Reference Manual for the
recommended R1, R2, C1 values
Figure 3.3. Crystal Resonator and External Reference Clock Connection Options
Note: See Table 5.3 Input Clock Specifications on page 27 and the Si5347-46 Rev D Reference Manual for more information.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 9
3.6 Inputs (IN0, IN1, IN2, IN3)
There are four inputs that can be used to synchronize any of the DSPLLs. The inputs accept both differential and single-ended clocks.
A crosspoint between the inputs and the DSPLLs allows any of the inputs to connect to any of the DSPLLs, as shown in the figure
below.
Input
Crosspoint
DSPLL
A
DSPLL
B
DSPLL
C
DSPLL
D
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
Si5347
÷P0n
P0d
÷P1n
P1d
÷P2n
P2d
÷P3n
P3d
IN0
IN0b
IN1
IN1b
IN2
IN2b
IN3
IN3b
Figure 3.4. DSPLL Input Selection Crosspoint
3.6.1 Input Selection
Input selection for each of the DSPLLs can be made manually through register control or automatically using an internal state machine.
3.6.2 Manual Input Selection
In Manual Mode, the input selection is made by writing to a register. If there is no clock signal on the selected input, the DSPLL will
automatically enter Holdover Mode.
3.6.3 Automatic Input Selection
When configured in this mode, the DSPLL automatically selects a valid input that has the highest configured priority. The priority
scheme is independently configurable for each DSPLL and supports revertive or non-revertive selection.
All inputs are continuously monitored for loss of signal (LOS) and/or invalid frequency range (OOF). Only inputs that do not assert both
the LOS and OOF monitors can be selected for synchronization by the automatic state machine. The DSPLL(s) will enter the Holdover
mode if there are no valid inputs available.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 10
3.6.4 Input Configuration and Terminations
Each of the inputs can be configured as differential or single-ended LVCMOS. The recommended input termination schemes are shown
in the figure below. Standard 50% duty cycle signals must be ac-coupled, while low duty cycle Pulsed CMOS signals can be dc-cou-
pled. Unused inputs can be disabled and left unconnected when not in use.
3.3V, 2.5V, 1.8V
LVCMOS
INx
50
Standard AC-Coupled Differential (IN0-IN3)
INx
50
Pulsed CMOS
Standard
50
R1
Pulsed CMOS
Standard
See the Reference Manual for details on R1 and R2 values.
RS matches the CMOS driver to a 50 ohm
transmission line (if used)
Standard AC-Coupled Single-Ended (IN0-IN3)
Pulsed CMOS DC-Coupled Single Ended only for Frequencies < 1MHz
RS
LVDS, LVPECL, CML
INxb
INxb
When 3.3V LVCMOS driver is present, C1 (optional), R1 and R2 may be needed to keep the signal at
INx < 3.6 Vpp_se. See the Reference Manual for details.
INx
3.3/2.5/1.8V LVCMOS
Pulsed CMOS
Standard
R1
50
RS
RS matches the CMOS driver to a 50 ohm
transmission line (if used)
C1
INxb
R2
R2
Figure 3.5. Termination of Differential and LVCMOS Input Signals
Note: See Table 5.3 Input Clock Specifications on page 27 and the Si5347-46 Rev D Reference Manual for more information.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 11
3.6.5 Hitless Input Switching
Hitless switching is a feature that prevents a phase offset from propagating to the output when switching between two clock inputs that
have a fixed phase relationship. A hitless switch can only occur when the two input frequencies are frequency locked, meaning that
they have to be exactly at the same frequency, or at an integer frequency relationship to each other. When hitless switching is enabled,
the DSPLL simply absorbs the phase difference between the two input clocks during an input switch. When disabled, the phase differ-
ence between the two inputs is propagated to the output at a rate determined by the DSPLL Loop Bandwidth. The hitless switching
feature supports clock frequencies down to the minimum input frequency of 8 kHz. Hitless switching can be enabled on a per DSPLL
basis.
3.6.6 Ramped Input Switching
When switching between two plesiochronous input clocks (i.e., the frequencies are "almost the same" but not quite), ramped input
switching should be enabled to ensure a smooth transition between the two inputs. Ramped input switching avoids frequency transients
and overshoot when switching between frequencies and so is the default switching mode in CBPro. The feature should be turned off
when switching between input clocks that are always frequency locked (i.e., are always the same exact frequency). The same ramp
rate settings are used for both holdover exit and clock switching. For more information on ramped exit from holdover, see 3.3.5 Hold-
over Mode.
3.6.7 Glitchless Input Switching
The DSPLLs have the ability of switching between two input clock frequencies that are up to ±500 ppm apart. The DSPLL will pull-in to
the new frequency using the DSPLL Loop Bandwidth or using the Fastlock Loop Bandwidth if it is enabled. The loss of lock (LOL) indi-
cator will assert while the DSPLL is pulling-in to the new clock frequency. There will be no output runt pulses generated at the output
during the transition.
3.6.8 Synchronizing to Gapped Input Clocks
Each of the DSPLLs support locking to an input clock that has missing periods. This is also referred to as a gapped clock. The purpose
of gapped clocking is to modulate the frequency of a periodic clock by selectively removing some of its cycles. Gapping a clock severely
increases its jitter, so a phase-locked loop with high jitter tolerance and low loop bandwidth is required to produce a low-jitter periodic
clock. The resulting output will be a periodic non-gapped clock with an average frequency of the input with its missing cycles. For exam-
ple, an input clock of 100 MHz with one cycle removed every 10 cycles will result in a 90 MHz periodic non-gapped output clock. This is
shown in the figure below.
DSPLL
100 ns 100 ns
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9
100 MHz clock
1 missing period every 10
90 MHz non-gapped clock
10 ns 11.11111... ns
Gapped Input Clock Periodic Output Clock
Period Removed
Figure 3.6. Generating an Averaged Clock Output Frequency from a Gapped Clock Input
A valid gapped clock input must have a minimum frequency of 10 MHz with a maximum of two missing cycles out of every 8. Locking to
a gapped clock will not trigger the LOS, OOF, and LOL fault monitors. Clock switching between gapped clocks may violate the hitless
switching specification in Table 5.8 Performance Characteristics on page 32 when the switch occurs during a gap in either input clock.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 12
3.7 Fault Monitoring
All four input clocks (IN0, IN1, IN2, IN3) are monitored for LOS and OOF, as shown in the figure below. The reference at the XA/XB
pins is also monitored for LOS since it provides a critical reference clock for the DSPLLs. Each of the DSPLLs also has an LOL indica-
tor, which is asserted when synchronization is lost with their selected input clock.
Si5347
IN3
IN3b
XB
XA
OSC
LOS
DSPLL A
PD LPF
÷M
LOL
DSPLL B
PD LPF
÷M
LOL
DSPLL C
PD LPF
÷M
LOL
DSPLL D
PD LPF
÷M
LOL
IN1
IN1b
IN2
IN2b
IN0
IN0b
Precision
Fast
OOF
LOS
Precision
Fast
OOF
LOS
Precision
Fast
OOF
LOS
Precision
Fast
OOF
LOS
÷P0n
P0d
÷P1n
P1d
÷P2n
P2d
÷P3n
P3d
Figure 3.7. Si5347 Fault Monitors
3.7.1 Input LOS Detection
The loss of signal monitor measures the period of each input clock cycle to detect phase irregularities or missing clock edges. Each of
the input LOS circuits has its own programmable sensitivity which allows ignoring missing edges or intermittent errors. Loss of signal
sensitivity is configurable using the ClockBuilder Pro software. The LOS status for each of the monitors is accessible by reading a sta-
tus register. The live LOS register always displays the current LOS state and a sticky register always stays asserted until cleared. An
option to disable any of the LOS monitors is also available.
LOS
en
Monitor
LOS
LOS
Sticky
Live
Figure 3.8. LOS Status Indicators
3.7.2 XA/XB LOS Detection
A LOS monitor is available to ensure that the external crystal or reference clock is valid. By default the output clocks are disabled when
XAXB_LOS is detected. This feature can be disabled such that the device will continue to produce output clocks when XAXB_LOS is
detected.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 13
3.7.3 OOF Detection
Each input clock is monitored for frequency accuracy with respect to an OOF reference, which it considers as its “0_ppm” reference.
This OOF reference can be selected as either:
•XA/XB pins
• Any input clock (IN0, IN1, IN2, IN3)
The final OOF status is determined by the combination of both a precise OOF monitor and a fast OOF monitor, as shown in the figure
below. An option to disable either monitor is also available. The live OOF register always displays the current OOF state and its sticky
register bit stays asserted until cleared.
en
en
Precision
Fast
OOF
Monitor
LOS
OOF
Sticky
Live
Figure 3.9. OOF Status Indicator
Precision OOF Monitor
The precision OOF monitor circuit measures the frequency of all input clocks to within 1/16 ppm accuracy with respect to the selected
OOF frequency reference. A valid input clock frequency is one that remains within the OOF frequency range, which is register configu-
rable up to ±500 ppm in steps of 1/16 ppm. A configurable amount of hysteresis is also available to prevent the OOF status from tog-
gling at the failure boundary. An example is shown in the figure below. In this case, the OOF monitor is configured with a valid frequen-
cy range of ±6 ppm and with 2 ppm of hysteresis. An option to use one of the input pins (IN0 – IN3) as the 0 ppm OOF reference
instead of the XA/XB pins is available. This option is register-configurable.
OOF
Reference
Hysteresis Hysteresis
OOF Declared
OOF Cleared
-6 ppm
(Set)
-4 ppm
(Clear)
0 ppm +4 ppm
(Clear)
+6 ppm
(Set)
fIN
Figure 3.10. Example of Precise OOF Monitor Assertion and De-assertion Triggers
Fast OOF Monitor
Because the precision OOF monitor needs to provide 1/16 ppm of frequency measurement accuracy, it must measure the monitored
input clock frequencies over a relatively long period of time. This may be too slow to detect an input clock that is quickly ramping in
frequency. An additional level of OOF monitoring called the Fast OOF monitor runs in parallel with the precision OOF monitors to quick-
ly detect a ramping input frequency. The Fast OOF monitor asserts OOF on an input clock frequency that has changed by greater than
±4000 ppm.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 14
3.7.4 LOL Detection
There is an LOL monitor for each of the DSPLLs. The LOL monitor asserts an LOL register bit when a DSPLL has lost synchronization
with its selected input clock. There is also a dedicated loss of lock pin that reflects the loss of lock condition for each of the DSPLLs
(LOL_Ab, LOL_Bb, LOL_Cb, LOL_Db). The LOL monitor functions by measuring the frequency difference between the input and feed-
back clocks at the phase detector. There are two LOL frequency monitors, one that sets the LOL indicator (LOL Set) and another that
clears the indicator (LOL Clear). An optional timer is available to delay clearing of the LOL indicator to allow additional time for the
DSPLL to completely lock to the input clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the
DSPLL completes lock acquisition. A block diagram of the LOL monitor is shown in the figure below. The live LOL register always dis-
plays the current LOL state and a sticky register always stays asserted until cleared. The LOLb pin reflects the current state of the LOL
monitor.
LOS
LOL Status Registers
Sticky
Live
DSPLL B
PD LPF
÷M
LOL Monitor
DSPLL A
DSPLL C
DSPLL D
LOL_Ab
LOL_Bb
LOL_Cb
LOL_Db
DSPLL A
t
LOL
Clear
LOL
Set
fIN
Si5347
Figure 3.11. LOL Status Indicators
Each of the LOL frequency monitors has adjustable sensitivity, which is register-configurable from 0.1 ppm to 10,000 ppm. Having two
separate frequency monitors allows for hysteresis to help prevent chattering of LOL status. An example configuration where LOCK is
indicated when there is less than 0.1 ppm frequency difference at the inputs of the phase detector and LOL is indicated when there is
more than 1 ppm frequency difference is shown in the figure below.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 15
Phase Detector Frequency Difference (ppm)
Hysteresis
LOL
LOCKED
Clear LOL
Threshold
Set LOL
Threshold
Lock Acquisition
0
Lost Lock
10,0000.1 1
Figure 3.12. LOL Set and Clear Thresholds
An optional timer is available to delay clearing of the LOL indicator to allow additional time for the DSPLL to completely lock to the input
clock. The timer is also useful to prevent the LOL indicator from toggling or chattering as the DSPLL completes lock acquisition. The
configurable delay value depends on frequency configuration and loop bandwidth of the DSPLL and is automatically calculated using
the ClockBuilder Pro software.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 16
3.7.5 Interrupt Pin (INTRb)
An interrupt pin (INTRb) indicates a change in state with any of the status indicators for any of the DSPLLs. All status indicators are
maskable to prevent assertion of the interrupt pin. The state of the INTRb pin is reset by clearing the sticky status registers.
OOF_FLG 0x0012[6]
LOS_FLG 0x0012[2]
IN2
OOF_FLG 0x0012[5]
LOS_FLG 0x0012[1]
IN1
LOS_FLG 0x0012[3]
OOF_FLG 0x0012[4]
LOS_FLG 0x0012[0]
IN0
LOSXAXB_INTR_MSK 0x0017[1]
LOL_FLG_PLL[D] 0x0013[3]
LOL_FLG_PLL[C] 0x0013[2]
LOL_FLG_PLL[A] 0x0013[0]
HOLD_FLG_PLL[D] 0x0013[7]
HOLD_FLG_PLL[C] 0x0013[6]
HOLD_FLG_PLL[A] 0x0013[4]
OOF_FLG 0x0012[7]
Si5347
HOLD_FLG_PLL[B] 0x0013[5]
LOL_FLG_PLL[B] 0x0013[1]
INTRb
IN2
LOL
Hold
CAL
CAL_FLG_PLL[A] 0x000F[4]
CAL_FLG_PLL[B] 0x000F[5]
CAL_FLG_PLL[C] 0x000F[6]
CAL_FLG_PLL[D] 0x000F[7]
Figure 3.13. Interrupt Triggers and Masks
3.8 Outputs
The Si5347 supports up to eight differential output drivers and the Si5346 supports four. Each driver has a configurable voltage ampli-
tude and common mode voltage covering a wide variety of differential signal formats including LVPECL, LVDS, HCSL, and CML. In
addition to supporting differential signals, any of the outputs can be configured as single-ended LVCMOS (3.3 V, 2.5 V, or 1.8 V) provid-
ing up to 16 single-ended outputs, or any combination of differential and single-ended outputs.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 17
3.8.1 Output Crosspoint
A crosspoint allows any of the output drivers to connect with any of the DSPLLs, as shown in the figure below. The crosspoint configu-
ration is programmable and can be stored in NVM so that the desired output configuration is ready at power-up.
Si5347A/B Output
Crosspoint
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
A
B
C
D
DSPLL
C
DSPLL
D
DSPLL
A
DSPLL
B
OUT0b
OUT0
÷R0
VDDO0
÷R1OUT1b
VDDO1
OUT1
OUT2b
VDDO2
OUT2
÷R2
÷R3OUT3b
VDDO3
OUT3
÷R4OUT4b
VDDO4
OUT4
÷R5OUT5b
VDDO5
OUT5
÷R6OUT6b
VDDO6
OUT6
÷R7OUT7b
VDDO7
OUT7
Figure 3.14. Si5347A/B DSPLL to Output Driver Crosspoint
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 18
3.8.2 Differential Output Terminations
Note: In this document, the terms "LVDS" and "LVPECL" refer to driver formats that are compatible with these signaling standards.
The differential output drivers support both ac-coupled and dc-coupled terminations, as shown in the figure below.
AC Coupled LVDS/LVPECL
AC Coupled CMLDC Coupled LVDS
100
50
50
Internally
self-biased
OUTx
OUTxb
LVDS: VDDO = 3.3V, 2.5V, 1.8V
LVPECL: VDDO = 3.3V, 2.5V
VDDRX
Standard
HCSL
Receiver
R1
AC Coupled HCSL
OUTx
OUTxb
R1
R2 R2
VDDO = 3.3V, 2.5V, 1.8V
50
50
50
50
VDD – 1.3V
5050
OUTx
OUTxb
VDDO = 3.3V, 2.5V
50
50
100
OUTx
OUTxb
LVDS: VDDO = 3.3V, 2.5V, 1.8V
Figure 3.15. Supported Differential Output Terminations
Note: See the Si5347/46 Rev D Family Reference Manual for resistor values.
3.8.3 LVCMOS Output Terminations
LVCMOS outputs are dc-coupled, as shown in the figure below.
3.3 V, 2.5 V, 1.8 V
LVCMOS
VDDO = 3.3 V, 2.5 V, 1.8 V
50
Rs
50
Rs
DC Coupled LVCMOS
OUTx
OUTxb
Si5347/46
Figure 3.16. LVCMOS Output Terminations
3.8.4 Output Signal Format
The differential output amplitude and common mode voltage are both fully programmable and compatible with a wide variety of signal
formats, including LVDS and LVPECL. In addition to supporting differential signals, any of the outputs can be configured as LVCMOS
(3.3 V, 2.5 V, or 1.8 V) drivers providing up to 16 single-ended outputs or any combination of differential and single-ended outputs.
3.8.5 Programmable Common Mode Voltage For Differential Outputs
The common mode voltage (VCM) for the differential modes is programmable and depends on the voltage available at the output’s
VDDO pin. Setting the common mode voltage is useful when dc-coupling the output drivers.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 19
3.8.6 LVCMOS Output Impedance Selection
Each LVCMOS driver has a configurable output impedance to accommodate different trace impedances and drive strengths. A source
termination resistor is recommended to help match the selected output impedance to the trace impedance. There are three programma-
ble output impedance selections for each VDDO option, as shown in the table below. Note that selecting a lower source impedance
may result in higher output power consumption.
Table 3.1. Typical Output Impedance (ZS)
VDDO CMOS_DRIVE_Selection
OUTx_CMOS_DRV = 1 OUTx_CMOS_DRV = 2 OUTx_CMOS_DRV = 3
3.3 V 38 Ω 30 Ω 22 Ω
2.5 V 43 Ω 35 Ω 24 Ω
1.8 V — 46 Ω 31 Ω
3.8.7 LVCMOS Output Signal Swing
The signal swing (VOL/VOH) of the LVCMOS output drivers is set by the voltage on the VDDO pins. Each output driver has its own
VDDO pin allowing a unique output voltage swing for each of the LVCMOS drivers.
3.8.8 LVCMOS Output Polarity
When a driver is configured as an LVCMOS output, it generates a clock signal on both pins (OUTx and OUTxb). By default the clock on
the OUTxb pin is generated with the same polarity (in phase) with the clock on the OUTx pin. The polarity of these clocks is configura-
ble, which enables complementary clock generation and/or inverted polarity with respect to other output drivers.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 20
3.8.9 Output Enable/Disable
The Si5347/46 allows enabling/disabling outputs by pin or register control, or a combination of both. Two output enable pins are availa-
ble (OE0b, OE1b). The output enable pins can be mapped to any of the outputs (OUTx) through register configuration. By default OE0b
controls all of the outputs while OE1b remains unmapped and has no effect until configured. The figure below shows an example of an
output enable mapping scheme that is register configurable and can be stored in NVM as the default at power-up.
Enabling and disabling outputs can also be controlled by register control. This allows disabling one or more output when the OEb pin(s)
has them enabled. By default the output enable register settings are configured to allow the OEb pins to have full control.
Si5346
OUT0b
OUT0
OUT1b
OUT2b
OUT3b
OUT1
OUT2
OUT3
÷R0
÷R1
÷R2
÷R3
Output
Crosspoint
OE0b
DSPLL
A
DSPLL
B
OE1b
A
B
In its default state the OE0b pin enables/disables all outputs.
The OE1b pin is not mapped and has no effect on outputs.
A
B
A
B
A
B
An example of a configurable output enable scheme. In this
case OE0b controls the outputs associated with DSPLL A,
while OE1b controls the outputs of DSPLL B.
Si5346
OUT0b
OUT0
OUT1b
OUT2b
OUT3b
OUT1
OUT2
OUT3
÷R0
÷R1
÷R2
÷R3
Output
Crosspoint
DSPLL
A
DSPLL
B
A
B
A
B
A
B
A
B
OE0b
OE1b
Figure 3.17. Example of Configuring Output Enable Pins
3.8.10 Output Disable During LOL
By default a DSPLL that is out of lock will generate either free-running clocks or generate clocks in holdover mode. There is an option to
disable the outputs when a DSPLL is LOL. This option can be useful to force a downstream PLL into holdover.
3.8.11 Output Disable During XAXB_LOS
The internal oscillator circuit (OSC) in combination with the external crystal (XTAL) provides a critical function for the operation of the
DSPLLs. In the event of a crystal failure the device will assert an XAXB_LOS alarm. By default all outputs will be disabled during asser-
tion of the XAXB_LOS alarm. There is an option to leave the outputs enabled during an XAXB_LOS alarm, but the frequency accuracy
and stability will be indeterminate during this fault condition.
3.8.12 Output Driver State When Disabled
The disabled state of an output driver is register configurable as disable low or disable high.
3.8.13 Synchronous/Asynchronous Output Disable
Outputs can be configured to disable synchronously or asynchronously. In synchronous disable mode the output will wait until a clock
period has completed before the driver is disabled. This prevents unwanted runt pulses from occurring when disabling an output. In
asynchronous disable mode, the output clock will disable immediately without waiting for the period to complete.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 21
3.8.14 Output Divider (R) Synchronization
All the output R dividers are reset to a known state during the power-up initialization period. This ensures consistent and repeatable
phase alignment across all output drivers. Resetting the device using the RSTb pin or asserting the hard reset bit will have the same
result.
3.9 Power Management
Unused inputs, output drivers, and DSPLLs can be powered down when unused. Consult the Si5347-46 Rev D Reference Manual and
the ClockBuilder Pro software for details.
3.10 In-Circuit Programming
The Si5347/46 is fully configurable using the serial interface (I2C or SPI). At power-up the device downloads its default register values
from internal non-volatile memory (NVM). Application specific default configurations can be written into NVM allowing the device to gen-
erate specific clock frequencies at power-up. Writing default values to NVM is in-circuit programmable with normal operating power sup-
ply voltages applied to its VDD and VDDA pins. The NVM is two time writable. Once a new configuration has been written to NVM, the
old configuration is no longer accessible. Refer to the Si5347-46 Rev D Reference Manual for a detailed procedure for writing registers
to NVM.
3.11 Serial Interface
Configuration and operation of the Si5347/46 is controlled by reading and writing registers using the I2C or SPI interface. The I2C_SEL
pin selects I2C or SPI operation. Communication with both 3.3 V and 1.8 V host is supported. The SPI mode operates in either 4-wire or
3-wire mode. See the Si5347-46 Rev D Reference Manual for details.
3.12 Custom Factory Preprogrammed Parts
For applications where a serial interface is not available for programming the device, custom pre-programmed parts can be ordered
with a specific configuration written into NVM. A factory pre-programmed part will generate clocks at power-up. Custom, factory-pre-
programmed devices are available. Use the ClockBuilder Pro custom part number wizard to quickly and easily request and generate a
custom part number for your configuration.
In less than three minutes, you will be able to generate a custom part number with a detailed data sheet addendum matching your
design’s configuration. Once you receive the confirmation email with the data sheet addendum, simply place an order with your local
Silicon Labs sales representative. Samples of your pre-programmed device will typically ship in about two weeks.
3.13 Enabling Features and/or Configuration Settings Not Available in ClockBuilder Pro for Factory Pre-programmed Devices
As with essentially all modern software utilities, the ClockBuilder Pro software is continuously updated and enhanced. By registering at
www.silabs.com, you will be notified whenever changes are made and what the impact of those changes are. This update process will
ultimately enable ClockBuilder Pro software users to access all features and register setting values documented in this data sheet and
the Si5347-46 Rev D Reference Manual.
However, if you must enable or access a feature or register setting value so that the device starts up with this feature or a register
setting, but the feature or register setting is not yet available in CBPro, you must contact a Silicon Labs applications engineer for assis-
tance. One example of this type of feature or custom setting is the customizable output amplitude and common voltages for the clock
outputs. After careful review of your project file and requirements, the Silicon Labs applications engineer will email back your CBPro
project file with your specific features and register settings enabled using what is referred to as the manual "settings override" feature of
CBPro. "Override" settings to match your request(s) will be listed in your design report file. Examples of setting "overrides" in a CBPro
design report are shown in the table below.
Table 3.2. Setting Overrides
Location Name Type Target Dec Value Hex Value
0x0535[0] FORCE_HOLD_PLLB No NVM N/A 1 0x1
0x0B48[4:0] OOF_DIV_CLK_DIS User OPN and EVB 31 0x1F
Once you receive the updated design file, simply open it in CBPro. The device will begin operation after startup with the values in the
NVM file. The flowchart for this process is shown in the figure below.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 22
Do I need a
pre-programmed device with
a feature or setting which is
unavailable in ClockBuilder
Pro?
No
Yes
Contact Silicon Labs
Technical Support
to submit & review
your
non-standard
configuration
request & CBPro
project file
Configure device
using CBPro
Load project file
into CBPro and test
Receive
updated CBPro
project file
from
Silicon Labs
with “Settings
Override”
Generate
Custom OPN
in CBPro
Does the updated
CBPro Project file
match your
requirements?
Yes
End: Place
sample order
Start
Figure 3.18. Process for Requesting Non-Standard CBPro Features
Note: Contact Silicon Labs Technical Support at www.silabs.com/support/Pages/default.aspx.
Si5347/46 Rev D Data Sheet
Functional Description
silabs.com | Building a more connected world. Rev. 1.1 | 23
5. Electrical Specifications
Table 5.1. Recommended Operating Conditions
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%,TA = –40 to 85 °C)
Parameter Symbol Min Typ Max Unit
Ambient Temperature TA–40 25 85 °C
Junction Temperature TJMAX — — 125 °C
Core Supply Voltage
VDD 1.71 1.80 1.89 V
VDDA 3.14 3.30 3.47 V
Output Driver Supply Voltage VDDO
3.14 3.30 3.47 V
2.37 2.50 2.62 V
1.71 1.80 1.89 V
Status Pin Supply Voltage VDDS
3.14 3.30 3.47 V
1.71 1.80 1.89 V
Note:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical val-
ues apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise noted.
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 25
Table 5.2. DC Characteristics
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Core Supply Current1, 2
IDD
Si5347, 4 DSPLLs — 300 450 mA
S5347, 1 DSPLL — 190 340 mA
Si5346 — 185 280 mA
IDDA
Si5347, 4 DSPLLs — 125 140 mA
Si5347, 1 DSPLL — 125 140 mA
Si5346 — 125 140 mA
Output Buffer Supply Current IDDO
LVPECL Output3
@ 156.25 MHz
— 22 26 mA
LVDS Output3
@ 156.25 MHz
— 15 18 mA
3.3 V LVCMOS4 Output
@ 156.25 MHz
— 22 30 mA
2.5 V LVCMOS4 Output
@ 156.25 MHz
— 18 23 mA
1.8 V LVCMOS4 Output
@ 156.25 MHz
— 12 16 mA
Total Power Dissipation5Pd
Si5347, 4 DSPLLs1— 1200 1600 mW
Si5347, 1 DSPLL1— 1050 1420 mW
Si53462— 880 1100 mW
Notes:
1. Si5347 test configuration: 7×2.5 V LVDS outputs enabled @156.25 MHz. Excludes power in termination resistors.
2. Si5346 test configuration: 4×2.5 V LVDS outputs enabled @ 156.25 MHz. Excludes power in termination resistors.
3. Differential outputs terminated into an AC coupled 100 Ω load.
4. LVCMOS outputs measured into a 5-inch 50 Ω PCB trace with 4.7 pF load. The LVCMOS outputs were set to
OUTx_CMOS_DRV = 3, which is the strongest driver setting. Refer to the Si5347-46 Rev D Reference Manual for more details
on register settings.
5. Detailed power consumption for any configuration can be estimated using the ClockBuilder Pro software when an evaluation
board (EVB) is not available. All EVBs support detailed current measurements for any configuration.
50
50
100
OUT
OUTb
IDDO
Differential Output Test Configuration
0.1 uF
0.1 uF
LVCMOS Output Test Configuration
OUTx
OUTxb
IDDO
499
56
4.7pF
50 Scope Input
50
499
56
4.7pF
50 Scope Input
50
Trace length 5
inches
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 26
Table 5.3. Input Clock Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Standard AC-Coupled Differential or Single-Ended (IN0/IN0b, IN1/IN1b, IN2/IN2b, IN3/IN3b)
Input Frequency Range fIN
Differential 0.008 — 750 MHz
All Single-ended signals
(including LVCMOS)
0.008 — 250 MHz
Voltage Swing1VIN
Differential AC-coupled
fIN < 250 MHz
100 — 1800 mVpp_se
Differential AC-coupled
250 MHz < fIN < 750 MHz
225 — 1800 mVpp_se
Single-ended AC-coupled
fIN< 250 MHz
100 — 3600 mVpp_se
Slew Rate2,3 SR 400 — — V/µs
Duty Cycle DC 40 — 60 %
Input Capacitance CIN — 2.4 — pF
Input Resistance Differential RIN_DIFF — 16 — kΩ
Input Resistance Single-ended RIN_SE — 8 — kΩ
LVCMOS / Pulsed CMOS, DC-Coupled, Single-Ended (IN0, IN1, IN2, IN3)4
Input Frequency
fIN_LVCMOS 0.008 — 250 MHz
fIN_PULSED_CM
OS
0.008 — 1.0 MHz
Input Voltage
VIL –0.2 — 0.4 V
VIH 0.8 — — V
Slew Rate2,3 SR 400 — — V/µs
Minimum Pulse Width PW Pulse Input 1.6 — — ns
Input Resistance RIN — 8 — kΩ
REFCLK (Applied to XA/XB)
REFCLK Frequency fIN_REF
Full operating range. Jitter
performance may be re-
duced.
24.97 — 54.06 MHz
Range for best jitter. 48 — 54 MHz
Input Voltage Swing
VIN_DIFF 365 — 2500 mVpp_diff
VIN_SE 365 — 2000 mVpp_se
Slew rate2,3 SR Imposed for best jitter per-
formance 400 — — V/µs
Input Duty Cycle DC 40 — 60 %
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 27
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Voltage swing is specified as single-ended mVpp.
OUTxb
OUTx
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
Vcm
2. Recommended for specified jitter performance. Jitter performance can degrade if the minimum slew rate specification is not met
(see Si5347-46 Rev D Reference Manual).
3. Rise and fall times can be estimated using the following simplified equation: tr/tf80-20 = ((0.8 - 0.2) x VIN_Vpp_se) / SR.
4. Pulsed CMOS mode is intended primarily for single-ended LVCMOS input clocks < 1 MHz, which must be dc-coupled because
they have a duty cycle significantly less than 50%. A typical application example is a low frequency video frame sync pulse. Since
the input thresholds (VIL, VIH) of this buffer are non-standard (0.4 and 0.8 V, respectively), refer to the input attenuator circuit for
DC-coupled Pulsed LVCMOS in the Si5347-46 Rev D Reference Manual. Otherwise, for standard LVCMOS input clocks, use the
Standard AC-coupled, Single-ended input mode.
Table 5.4. Serial and Control Input Pin Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Si5347 Serial and Control Input Pins (I2C_SEL, RSTb, OE0b, A1/SDO, SCLK, A0/CSb, FINC, A0/CSb, SDA/SDIO,
DSPLL_SEL[1:0])
Input Voltage
VIL — — 0.3 x VDDIO1V
VIH 0.7 x VDDIO1— — V
Input Capacitance CIN — 1.5 — pF
Input Resistance RL— 20 — kΩ
Minimum Pulse Width PW RSTb, FINC 100 — — ns
Update Rate FUR FINC — — 1 MHz
Si5347 Control Input Pins (FDEC, OE1b)
Input Voltage
VIL — — 0.3 x VDDS V
VIH 0.7 x VDDS — — V
Input Capacitance CIN — 1.5 — pF
Minimum Pulse Width PW FDEC 100 — — ns
Update Rate FUR FDEC — — 1 MHz
Si5346 Serial and Control Input Pins (I2C_SEL, RSTb, OE0b, OE1b, A1/SDO, SCLK, A0/CSb, SDA/SDIO)
Input Voltage
VIL — — 0.3 x VDDIO1V
VIH 0.7 x VDDIO1— — V
Input Capacitance CIN — 1.5 — pF
Input Resistance RL— 20 — kΩ
Minimum Pulse Width PW RSTb 100 — — ns
Note:
1. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD.
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 28
Table 5.5. Differential Clock Output Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Output Frequency fOUT 0.0001 — 720 MHz
Duty Cycle DC
fOUT < 400 MHz 48 — 52 %
400 MHz < fOUT < 720 MHz 45 — 55 %
Output-Output Skew
Using Same DSPLL
TSKS
Outputs on same DSPLL
(Measured at 720 MHz)
— 0 75 ps
OUT-OUTb Skew TSK_OUT Measured from positive to
negative output pins — 0 50 ps
Output Voltage Amplitude1VOUT
VDDO = 3.3 V,
2.5 V, or 1.8 V LVDS 350 430 510
mVpp_se
VDDO = 3.3 V,
2.5 V LVPECL 640 750 900
Common Mode Voltage1,2 VCM
VDDO = 3.3 V
LVDS 1.10 1.20 1.30
V
LVPECL 1.90 2.00 2.10
VDDO = 2.5 V LVPECL,
LVDS 1.10 1.20 1.30
VDDO = 1.8 V sub-LVDS 0.80 0.90 1.00
Rise and Fall Times
(20% to 80%)
tR/tF— 100 150 ps
Differential Output Impedance ZO— 100 — Ω
Power Supply Noise Rejection2PSRR
10 kHz sinusoidal noise — –101 — dBc
100 kHz sinusoidal noise — –96 — dBc
500 kHz sinusoidal noise — –99 — dBc
1 MHz sinusoidal noise — –97 — dBc
Output-output Crosstalk3XTALK
Si5347 — –72 — dB
Si5346 — –88 — dB
Notes:
1. Output amplitude and common mode voltage are programmable through register settings and can be stored in NVM. Each output
driver can be programmed independently. The maximum LVDS single-ended amplitude can be up to 110 mV higher than the TIA/
EIA-644 maximum. Refer to the Si5347-46 Rev D Reference Manual for more suggested output settings. Not all combinations of
voltage amplitude and common mode voltages settings are possible.
2. Measured for 156.25 MHz carrier frequency. 100 mVpp of sinewave noise added to VDDO = 3.3 V and noise spur amplitude
measured.
3. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25
MHz. Refer to application note, “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Sys-
tems”, guidance on crosstalk minimization. Note that all active outputs must be terminated when measuring crosstalk.
OUTxb
OUTx
Vpp_se
Vpp_se
Vpp_diff = 2*Vpp_se
Vcm
Vcm
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 29
Table 5.6. LVCMOS Clock Output Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Output Frequency fOUT 0.0001 — 250 MHz
Duty Cycle DC
fOUT <100 MHz 48 — 52
%
100 MHz < fOUT < 250 MHz 45 — 55
Output Voltage High1,2,3 VOH
VDDO = 3.3 V
OUTx_CMOS_DRV=1 IOH = –10 mA
VDDO x 0.85
— —
VOUTx_CMOS_DRV=2 IOH = –12 mA — —
OUTx_CMOS_DRV=3 IOH = –17 mA — —
VDDO = 2.5 V
OUTx_CMOS_DRV=1 IOH = –6 mA
VDDO x 0.85
— —
VOUTx_CMOS_DRV=2 IOH = –8 mA — —
OUTx_CMOS_DRV=3 IOH = –11 mA — —
VDDO = 1.8 V
OUTx_CMOS_DRV=2 IOH = –4 mA
VDDO x 0.85
— —
V
OUTx_CMOS_DRV=3 IOH = –5 mA — —
Output Voltage Low1,2,3 VOL
VDDO = 3.3 V
OUTx_CMOS_DRV=1 IOL = 10 mA — —
VDDO x 0.15 VOUTx_CMOS_DRV=2 IOL = 12 mA — —
OUTx_CMOS_DRV=3 IOL = 17 mA — —
VDDO = 2.5 V
OUTx_CMOS_DRV=1 IOL = 6 mA — —
VDDO x 0.15 VOUTx_CMOS_DRV=2 IOL = 8 mA — —
OUTx_CMOS_DRV=3 IOL = 11 mA — —
VDDO = 1.8 V
OUTx_CMOS_DRV=2 IOL = 4 mA — —
VDDO x 0.15 V
OUTx_CMOS_DRV=3 IOL = 5 mA — —
LVCMOS Rise and Fall
Times3
(20% to 80%)
tr/tf
VDDO = 3.3V — 400 600 ps
VDDO = 2.5 V — 450 600 ps
VDDO = 1.8 V — 550 750 ps
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 30
Parameter Symbol Test Condition Min Typ Max Unit
1. Driver strength is a register programmable setting and stored in NVM. Options are OUTx_CMOS_DRV = 1, 2, 3. Refer to the
Si5347-46 Rev D Reference Manual for more details on register settings.
2. IOL/IOH is measured at VOL/VOH as shown in the dc test configuration.
3. A 5 pF capacitive load is assumed. The LVCMOS outputs were set to OUTx_CMOS_DRV = 3, at 156.25 MHz.
Zs
IOL/IOH
VOL/VOH
LVCMOS Output Test Configuration
OUTx
OUTxb
IDDO
499
56
4.7pF
50 Scope Input
50
499
56
4.7pF
50 Scope Input
50
Trace length 5
inches
Table 5.7. Output Serial and Status Pin Specifications
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, VDDS = 3.3 V ±5%, 1.8 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Si5347 Serial and Status Output Pins (LOL_Ab, LOL_Bb, LOL_Cb, LOL_Db, INTRb, LOS_XAXBb, SDA/SDIO1, A1/SDO)
Output Voltage
VOH IOH = –2 mA VDDIO2 x
0.85 — — V
VOL IOL = 2 mA — — VDDIO2 x
0.15 V
Si5346 Status Output Pins (INTRb, LOS_XAXBb, SDA/SDIO1, A1/SDO)
Output Voltage
VOH IOH = –2 mA VDDIO2 x
0.85 — — V
VOL IOL = 2 mA — — VDDIO2 x
0.15 V
Si5346 Serial and Status Output Pins (LOL_Ab, LOL_Bb)
Output Voltage
VOH IOH = –2 mA VDDS x 0.85 — — V
VOL IOL = 2 mA — — VDDS x 0.15 V
Notes:
1. The VOH specification does not apply to the open-drain SDA/SDIO output when the serial interface is in I2C mode or is unused
with I2C_SEL pulled high. VOL remains valid in all cases.
2. VDDIO is determined by the IO_VDD_SEL bit. It is selectable as VDDA or VDD. Users normally select this option in the ClockBuild-
er Pro GUI. Alternatively, refer to the Si5347-46 Rev D Reference Manual for more details on register settings.
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 31
Table 5.8. Performance Characteristics
(VDD = 1.8 V ±5%, or 3.3 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Test Condition Min Typ Max Unit
PLL Loop Bandwidth
Programming Range1fBW 0.1 — 4000 Hz
Initial Start-Up Time tSTART
Time from power-up to
when the device gener-
ates free-running clocks
— 30 45 ms
PLL Lock Time2tACQ
With Fastlock enabled,
fIN = 19.44 MHz — 280 300 ms
POR to Serial Interface Ready3tRDY — — 15 ms
Jitter Peaking JPK
Measured with a frequen-
cy plan running a 25 MHz
input, 25 MHz output, and
a loop bandwidth of 4 Hz
— — 0.1 dB
Jitter Tolerance JTOL
Compliant with G.8262
Options 1&2
Carrier Frequency =
10.3125 GHz
Jitter Modulation Frequen-
cy = 10 Hz
— 3180 — UI pk-pk
Maximum Phase
Transient During a
Hitless Switch
tSWITCH
Manual or automatic
switch between two input
clocks at same frequency5
— — 2.4 ns
Pull-in Range ωP— 500 — ppm
RMS Phase Jitter4JGEN 12 kHz to 20 MHz — 95 140 fs rms
Notes:
1. Actual loop bandwidth might be lower; please refer to CBPro for actual value on your frequency plan.
2. Lock Time can vary significantly depending on several parameters, such as bandwidths, LOL thresholds, etc. For this case, lock
time was measured with nominal and fastlock bandwidths, both set to 100 Hz, LOL set/clear thresholds of 6/0.6 ppm respectively,
using IN0 as clock reference by removing the reference and enabling it again, then measuring the delta time between the first
rising edge of the clock reference and the LOL indicator de-assertion.
3. Measured as time from valid VDD/VDDA rails (90% of their value) to when the serial interface is ready to respond to commands.
4. Jitter generation test conditions: fIN = 19.44 MHz, fOUT = 156.25 MHz LVPECL, loop bandwidth = 100 Hz.
Does not include jitter from input reference.
5. For input frequency configurations, which have Fpfd > 1 MHz. Consult your CBPro Design report for the Fpfd frequency of your
configuration.
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 32
Table 5.9. I2C Timing Specifications (SCL, SDA)
Parameter Symbol Test Condition
Standard Mode
100 kbps
Fast Mode
400 kbps Unit
Min Max Min Max
SCL Clock
Frequency fSCL — 100 — 400 kHz
SMBus Timeout — When Timeout is
Enabled 25 35 25 35 ms
Hold Time (repeated)
START Condition tHD:STA 4.0 — 0.6 — µs
Low Period of the SCL Clock tLOW 4.7 — 1.3 — µs
HIGH Period of the SCL
Clock tHIGH 4.0 — 0.6 — µs
Set-up Time for a Repeated
START Condition tSU:STA 4.7 — 0.6 — µs
Data Hold Time tHD:DAT 100 — 100 — ns
Data Set-up Time tSU:DAT 250 — 100 — ns
Rise Time of Both SDA and
SCL Signals tr— 1000 20 300 ns
Fall Time of Both SDA and
SCL Signals tf— 300 — 300 ns
Set-up Time for STOP Con-
dition tSU:STO 4.0 — 0.6 — µs
Bus Free Time between a
STOP and START Condition tBUF 4.7 — 1.3 — µs
Data Valid Time tVD:DAT — 3.45 — 0.9 µs
Data Valid Acknowledge
Time tVD:ACK — 3.45 — 0.9 µs
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 33
Figure 5.1. I2C Serial Port Timing Standard and Fast Modes
Table 5.10. SPI Timing Specifications (4-Wire)
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Min Typ Max Unit
SCLK Frequency fSPI — — 20 MHz
SCLK Duty Cycle TDC 40 — 60 %
SCLK Period TC50 — — ns
Delay Time, SCLK Fall to SDO Active TD1 — — 18 ns
Delay Time, SCLK Fall to SDO TD2 — — 15 ns
Delay Time, CSb Rise to SDO Tri-State TD3 — — 15 ns
Setup Time, CSb to SCLK TSU1 5 — — ns
Hold Time, SCLK Fall to CSb TH1 5 — — ns
Setup Time, SDI to SCLK Rise TSU2 5 — — ns
Hold Time, SDI to SCLK Rise TH2 5 — — ns
Delay Time Between Chip Selects (CSb) TCS 2 — — TC
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 34
SCLK
CSb
SDI
SDO
TSU1 TD1
TSU2
TD2
TC
TCS
TD3
TH2
TH1
Figure 5.2. 4-Wire SPI Serial Interface Timing
Table 5.11. SPI Timing Specifications (3-Wire)
(VDD = 1.8 V ±5%, VDDA = 3.3 V ±5%, TA = –40 to 85 °C)
Parameter Symbol Min Typ Max Units
SCLK Frequency fSPI — — 20 MHz
SCLK Duty Cycle TDC 40 — 60 %
SCLK Period TC50 — — ns
Delay Time, SCLK Fall to SDIO Turn-on TD1 — — 20 ns
Delay Time, SCLK Fall to SDIO Next-bit TD2 — — 15 ns
Delay Time, CSb Rise to SDIO Tri-State TD3 — — 15 ns
Setup Time, CSb to SCLK TSU1 5 — — ns
Hold Time, SCLK Fall to CSb TH1 5 — — ns
Setup Time, SDI to SCLK Rise TSU2 5 — — ns
Hold Time, SDI to SCLK Rise TH2 5 — — ns
Delay Time Between Chip Selects (CSb) TCS 2 — — TC
SCLK
CSb
SDIO
TSU1
TD1
TSU2
TD2
TC
TCS
TD3
TH2
TH1
Figure 5.3. 3-Wire SPI Serial Interface Timing
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 35
Table 5.12. Crystal Specifications1
Parameter Symbol Test Condition Min Typ Max Unit
Crystal Frequency Range fXTAL
Full operating range. Jit-
ter performance may be
reduced.
24.97 — 54.06 MHz
Range for best jitter. 48 — 54 MHz
Load Capacitance CL— 8 — pF
Crystal Drive Level dL— — 200 µW
Equivalent Series Resistance
Shunt Capacitance
rESR
CO
Refer to the Si5347-46 Rev D Reference Manual to determine ESR and shunt ca-
pacitance.
Notes:
1. Refer to the Si534x/8x Recommended Crystal, TCXO and OCXOs Reference Manual for recommended 48 to 54 MHz crystals.
The Si5348 is designed to only work with crystals that meet these specifications and not with XOs.
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 36
Table 5.13. Thermal Characteristics
Parameter Symbol Test Condition1Value Unit
Si5347–64QFN
Thermal Resistance
Junction to Ambient
θJA
Still Air 22
°C/W
Air Flow 1 m/s 19.4
Air Flow 2 m/s 18.3
Thermal Resistance
Junction to Case
θJC 9.5
Thermal Resistance
Junction to Board
θJB 9.4
ψJB 9.3
Thermal Resistance
Junction to Top Center
ψJT 0.2
Si5346–44QFN
Thermal Resistance
Junction to Ambient
θJA
Still Air 22.3
°C/W
Air Flow 1 m/s 19.4
Air Flow 2 m/s 18.4
Thermal Resistance
Junction to Case
θJC 10.9
Thermal Resistance
Junction to Board
θJB 9.3
ψJB 9.2
Thermal Resistance
Junction to Top Center
ψJT 0.23
Note:
1. Based on PCB Dimension: 3” x 4.5”, PCB Thickness: 1.6 mm, PCB Land/Via under GNP pad: 36, Number of Cu Layers: 4
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 37
Table 5.14. Absolute Maximum Ratings1, 2, 3, 4
Parameter Symbol Test Condition Value Unit
DC Supply Voltage
VDD –0.5 to 3.8 V
VDDA –0.5 to 3.8 V
VDDO –0.5 to 3.8 V
VDDS –0.5 to 3.8 V
Input Voltage Range
VI15IN0 – IN3 –1.0 to 3.8 V
VI2
RSTb, OE0b, OE1b,
I2C_SEL,
FINC, FDEC, PLL_SEL[1:0]
SDA/SDIO, A1/SDO, SCLK,
A0/CSb
–0.5 to 3.8 V
VI3 XA/XB –0.5 to 2.7 V
Latch-up Tolerance LU JESD78 Compliant
ESD Tolerance HBM 100 pF, 1.5 kΩ 2.0 kV
Max Junction Temperature in Operation TJCT 125 °C
Storage Temperature Range TSTG –55 to 150 °C
Soldering Temperature
(Pb-free profile)3TPEAK 260 °C
Soldering Temperature Time at TPEAK
(Pb-free profile)4TP20–40 s
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2. 64-QFN and 44-QFN packages are RoHS-6 compliant.
3. For detailed MSL and packaging information, go to www.silabs.com/support/quality/pages/RoHSInformation.aspx.
4. The device is compliant with JEDEC J-STD-020.
5. The minimum voltage at these pins can be as low as –1.0 V when an AC input signal of 10 MHz or greater is applied. See Table
5.3 Input Clock Specifications on page 27 spec for Single-ended AC Coupled fIN < 250 MHz.
Si5347/46 Rev D Data Sheet
Electrical Specifications
silabs.com | Building a more connected world. Rev. 1.1 | 38
6. Typical Application Schematic
DSPLL A
LPF
PD
÷Mn_A
Md_A
PHY
DSPLL B
LPF
PD
÷Mn_B
Md_B
PHY
DSPLL C
LPF
PD
÷Mn_C
Md_C
PHY
DSPLL D
LPF
PD
÷Mn_D
Md_D
PHY
Si5347
Data
Clock
Client #4
Data
Clock
Client #3
Data
Clock
Client #2
Data
Clock
Client #1
OTN
De-Mapper
40G OTN
10GbE
OTN Muxponder
Gapped Clock Non-gapped
Jitter Attenuated Clock
Gapped Clock Non-gapped
Jitter Attenuated Clock
Gapped Clock Non-gapped
Jitter Attenuated Clock
Gapped Clock Non-gapped
Jitter Attenuated Clock
10GbE
10GbE
10GbE
Figure 6.1. Using the Si5347 to Clean Gapped Clocks in an OTN Application
Si5347/46 Rev D Data Sheet
Typical Application Schematic
silabs.com | Building a more connected world. Rev. 1.1 | 39
7. Detailed Block Diagrams
DSPLL A
LPFPD
DSPLL B
LPFPD
DSPLL C
LPFPD
DSPLL D
LPFPD
Si5347
÷Mn_A
Md_A
÷Mn_B
Md_B
÷Mn_C
Md_C
÷Mn_D
Md_D
DSPLL_SEL[1:0]
SDA/SDIO
A1/SDO
SCLK
A0/CSb
I2C_SEL
SPI/
I2C
RSTb
OE0b
OE1b
VDD
VDDA
3
IN2
IN2b ÷P2n
P2d
IN0
IN0b ÷P0n
P0d
IN1
IN1b
÷P1n
P1d
IN3
IN3b ÷P3n
P3d
÷R0
÷R1
OUT0b
VDDO0
OUT0
OUT1b
VDDO1
OUT1
÷R2
÷R3
OUT2b
VDDO2
OUT2
OUT3b
VDDO3
OUT3
÷R4
÷R5
OUT4b
VDDO4
OUT4
OUT5b
VDDO5
OUT5
÷R6
÷R7
OUT6b
VDDO6
OUT6
OUT7b
VDDO7
OUT7
FDEC
FINC
Status
Monitors
LOS_XAXB
LOL_Ab
LOL_Bb
LOL_Cb
LOL_Db
INTRb
NVM
2
48-54MHz XTAL
or REFCLK
OSC
XBXA
÷PXAXB
VDDS
Si5347C/D
Si5347A/B
Figure 7.1. Si5347 Block Diagram
Si5347/46 Rev D Data Sheet
Detailed Block Diagrams
silabs.com | Building a more connected world. Rev. 1.1 | 40
Si5346
SDA/SDIO
A1/SDO
SCLK
A0/CSb
I2C_SEL
SPI/
I2CNVM
RSTb
OE0b
OE1b
Status
Monitors
LOS_XAXB
INTRb
LOL_Ab
LOL_Bb
IN2
IN2b ÷P2n
P2d
IN0
IN0b ÷P0n
P0d
IN1
IN1b
÷P1n
P1d
IN3
IN3b ÷P3n
P3d
÷R0
÷R1
OUT0b
VDDO0
OUT0
OUT1b
VDDO1
OUT1
÷R2
÷R3
OUT2b
VDDO2
OUT2
OUT3b
VDDO3
OUT3
DSPLL A
LPFPD
DSPLL B
LPFPD
÷Mn_A
Md_A
÷Mn_B
Md_B
VDD
VDDA
4
VDDS
2
48-54MHz XTAL
or REFCLK
OSC
XBXA
÷PREF
Figure 7.2. Si5346 Block Diagram
Si5347/46 Rev D Data Sheet
Detailed Block Diagrams
silabs.com | Building a more connected world. Rev. 1.1 | 41
8. Typical Operating Characteristics (Jitter and Phase Noise)
Figure 8.1. Input = 25 MHz; Output = 156.25 MHz, 2.5 V LVDS
Figure 8.2. Input = 25 MHz; Output = 625 MHz, 2.5 V LVDS
Si5347/46 Rev D Data Sheet
Typical Operating Characteristics (Jitter and Phase Noise)
silabs.com | Building a more connected world. Rev. 1.1 | 42
Figure 8.3. Input = 19.44 MHz; Output = 644.53125 MHz, 2.5 V LVDS
Figure 8.4. Input = 25 MHz; Output = 644.53125 MHz, 2.5 V LVDS
Si5347/46 Rev D Data Sheet
Typical Operating Characteristics (Jitter and Phase Noise)
silabs.com | Building a more connected world. Rev. 1.1 | 43
9. Pin Descriptions
OE0b
INTRb
SCLK
VDD
GND
Pad
IN1
IN1b
INTRb
LOL_Ab
LOL_Bb
I2C_SEL
X1
XA
XB
X2
OE0b
VDDA
IN2
IN2b
SDA/SDIO
A1/SDO
VDD
RSVD
RSVD
VDDO0
OUT0b
OUT0
LOS_XAXBb
DSPLL_SEL0
A0/CSb
NC
VDDO1
OUT1b
OUT1
FINC
LOL_Db
VDD
OUT4
OUT4b
VDDO4
FDEC
OE1b
VDDS
OUT3
OUT3b
VDDO3
OUT2
OUT2b
VDDO2
VDDO5
OUT5b
OUT5
VDDO6
OUT6b
OUT6
RSVD
RSVD
VDDO7
OUT7b
OUT7
VDD
IN3
IN3b
IN0
IN0b
Si5347A/B 64QFN
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LOL_Cb
RSTb
SCLK
DSPLL_SEL1
GND
Pad
IN1
IN1b
INTRb
LOL_Ab
LOL_Bb
I2C_SEL
X1
XA
XB
X2
OE0b
VDDA
IN2
IN2b
SDA/SDIO
A1/SDO
VDD
RSVD
RSVD
VDDO0
OUT0b
OUT0
LOS_XAXBb
DSPLL_SEL0
A0/CSb
NC
RSVD
RSVD
RSVD
FINC
LOL_Db
VDD
OUT2
OUT2b
VDDO2
FDEC
OE1b
VDDS
OUT1
OUT1b
VDDO1
RSVD
RSVD
RSVD
VDDO3
OUT3b
OUT3
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
VDD
IN3
IN3b
IN0
IN0b
Si5347C/D 64QFN
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
LOL_Cb
RSTb
SCLK
DSPLL_SEL1
GND
Pad
IN1
IN1b
XA
XB
X2
VDDA
VDDA
IN2
A0/CSb
SDA/SDIO
A1/SDO
OUT0b
OUT0
VDDO0 I2C_SEL
OUT1
OUT1b
VDDO1
VDDO3
OUT3b
OUT3
IN3
IN3b
IN0
IN0b
Si5346 44QFN
Top View
1
2
3
4
5
6
7
8
9
10
33
32
31
30
29
28
27
26
25
24
12
13
14
15
16
17
18
19
20
21
44
43
42
41
40
39
38
37
36
35
OUT2
OUT2b
VDDO2
VDDS
LOL_Bb
LOS_XAXBb
VDD
OE1b
IN2b 11 23
NC 22
VDD
VDD
34
RSTb
X1
LOL_Ab
Figure 9.1. Si5347/46 Pin Descriptions
Si5347/46 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 44
Table 9.1. Si5347/46 Pin Descriptions1
Pin
Name
Pin Number Pin
Type2
Function
Si5347A/B Si5347C/D Si5346
Inputs
XA 8 8 5 I Crystal Input. Input pin for external crystal (XTAL). Alter-
natively these pins can be driven with an external refer-
ence clock (REFCLK). An internal register bit selects
XTAL or REFCLK mode. Default is XTAL mode.
XB 9 9 6 I
X1 7 7 4 I XTAL Ground. Connect these pins directly to the XTAL
ground pins. X1, X2, and the XTAL ground pins should be
separated from the PCB ground plane. Refer to the
Si5347-46 Rev D Reference Manual for layout guidelines.
These pins should be left disconnected when connecting
XA/XB pins to an external reference clock (REFCLK).
X2 10 10 7 I
IN0 63 63 43 I Clock Inputs. These pins accept an input clock for syn-
chronizing the device. They support both differential and
single-ended clock signals. Refer to 3.6.4 Input Configura-
tion and Terminations for input termination options. These
pins are high-impedance and must be terminated external-
ly. The negative side of the differential input must be
grounded when accepting a single-ended clock.
IN0b 64 64 44 I
IN1 1 1 1 I
IN1b 2 2 2 I
IN2 14 14 10 I
IN2b 15 15 11 I
IN3 61 61 41 I
IN3b 62 62 42 I
Outputs
OUT0 24 24 20 O Output Clocks. These output clocks support a program-
mable signal amplitude and common mode voltage. De-
sired output signal format is configurable using register
control. Termination recommendations are provided in
3.8.2 Differential Output Terminations and 3.8.3 LVCMOS
Output Terminations. Unused outputs should be left un-
connected.
OUT0b 23 23 19 O
OUT1 31 38 25 O
OUT1b 30 37 24 O
OUT2 35 45 31 O
OUT2b 34 44 30 O
OUT3 38 51 36 O
OUT3b 37 50 35 O
OUT4 45 — — O
OUT4b 44 — — O
OUT5 51 — — O
OUT5b 50 — — O
OUT6 54 — — O
OUT6b 53 — — O
OUT7 59 — — O
OUT7b 58 — — O
Si5347/46 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 45
Pin
Name
Pin Number Pin
Type2
Function
Si5347A/B Si5347C/D Si5346
Serial Interface
I2C_SEL 39 39 38 I I2C Select.3 This pin selects the serial interface mode as
I2C (I2C_SEL = 1) or SPI (I2C_SEL = 0). This pin is inter-
nally pulled high.
SDA/SDIO 18 18 13 I/O Serial Data Interface.3 This is the bidirectional data pin
(SDA) for the I2C mode, or the bidirectional data pin
(SDIO) in the 3-wire SPI mode, or the input data pin (SDI)
in 4-wire SPI mode. When in I2C mode, this pin must be
pulled-up using an external resistor of
> 1 kΩ. No pull-up resistor is needed when in SPI mode.
A1/SDO 17 17 15 I/O Address Select 1/Serial Data Output.3 In I2C mode this
pin functions as the A1 address input pin. In 4-wire SPI
mode this is the serial data output (SDO) pin.
SCLK 16 16 14 I Serial Clock Input.3 This pin functions as the serial clock
input for both I2C and SPI modes. When in I2C mode, this
pin must be pulled-up using an external resistor of > 1 kΩ.
No pull-up resistor is needed when in SPI mode.
A0/CSb 19 19 16 I Address Select 0/Chip Select.3 This pin functions as the
hardware controlled address A0 in I2C mode. In SPI
mode, this pin functions as the chip select input (active
low). This pin is internally pulled-up.
Control/Status
INTRb 12 12 17 O Interrupt.3 This pin is asserted low when a change in de-
vice status has occurred. It should be left unconnected
when not in use.
RSTb 6 6 3 I Device Reset.3 Active low input that performs power-on
reset (POR) of the device. Resets all internal logic to a
known state and forces the device registers to their default
values. Clock outputs are disabled during reset. This pin is
internally pulled-up.
OE0b 11 11 12 I Output Enable 0.3 This pin is used to enable (when held
low) and disable (when held high) the output clocks. By
default this pin controls all outputs. It can also be config-
ured to control a subset of outputs. See 3.8.9 Output Ena-
ble/Disable for details. This pin is internally pulled-down.
OE1b 41 41 — Output Enable 1. (Si5347)4 This is an additional output
enable pin that can be configured to control a subset of
outputs. By default it has no control on the outputs until
configured. See 3.8.9 Output Enable/Disable for details.
There is no internal pull-up/pull-down for this pin. This pin
must be pulled up or down externally (do not leave floating
when not in use).
— — 37 Output Enable 1. (Si5346)3 This is an additional output
enable pin that can be configured to control a subset of
outputs. By default it has no control on the outputs until
configured. See 3.8.9 Output Enable/Disable for details.
This pin is internally pulled-down.
Si5347/46 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 46
Pin
Name
Pin Number Pin
Type2
Function
Si5347A/B Si5347C/D Si5346
LOL_Ab 3 3 28 O Loss Of Lock_A/B/C/D.3, 4 These output pins indicate
when DSPLL A, B, C, D is out-of-lock (low) or locked
(high). They can be left unconnected when not in use.
Si5347: See Note 3, Si5346: See Note 4.
LOL_Bb 4 4 27 O
LOL_Cb 5 5 — O
LOL_Db 47 47 — O
LOS_XAXBb 25 25 33 O Status Pins.3 This pin indicates a loss of signal alarm on
the XA/XB pins. This either indicates a XTAL failure or a
loss of external signal on the XA/XB pins. This pin can be
left unconnected when unused.
DSPLL_SEL
0
26 26 — I DSPLL Select Pins (Si5347 only).3 These pins are used
in conjunction with the FINC and FDEC pins. The
DSPLL_SEL[1:0] pins determine which DSPLL is affected
by a frequency change using the FINC and FDEC pins.
See 3.4 Digitally-Controlled Oscillator (DCO) Mode for de-
tails. These pins are internally pulled-down.
DSPLL_SEL
1
27 27 — I
FDEC 42 42 — I Frequency Decrement Pin (Si5347 only).4 This pin is
used to step-down the output frequency of a selected
DSPLL. The frequency change step size is register config-
urable. The DSPLL that is affected by the frequency
change is determined by the DSPLL_SEL[1:0] pins. This
pin must be pulled up or down externally (do not leave
floating when not in use).
FINC 48 48 — I Frequency Increment Pin (Si5347 only).3 This pin is
used to step-up the output frequency of a selected DSPLL.
The frequency change step size is register configurable.
The DSPLL that is affected by the frequency change is de-
termined by the DSPLL_SEL[1:0] pins. This pin is pulled
low internally and can be left unconnected when not in
use.
RSVD 20 20 — — Reserved. These pins are connected to the die. Leave
disconnected.
21 21 — —
— 29 — —
— 30 — —
— 31 — —
— 33 — —
— 34 — —
— 35 — —
— 52 — —
— 53 — —
— 54 — —
55 55 — —
56 56 — —
— 57 — —
— 58 — —
— 59 — —
Si5347/46 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 47
Pin
Name
Pin Number Pin
Type2
Function
Si5347A/B Si5347C/D Si5346
NC 28 28 22 — No Connect. These pins are not connected to the die.
Leave disconnected.
Power
VDD 32 32 21 P Core Supply Voltage. The device core operates from a
1.8 V supply. See the Si5347-46 Rev D Reference Manual
for power supply filtering recommendations. A 0402 1 µF
capacitor should be placed very near each of these pins.
46 46 32
60 60 39
— — 40
VDDA 13 13 8 P Core Supply Voltage 3.3 V. This core supply pin requires
a 3.3 V power source. See the Si5347-46 Rev D Refer-
ence Manual for power supply filtering recommendations.
A 0402 1 µF capacitor should be placed very near each of
these pins.
— — 9 P
VDDS 40 40 26 P Status Output Voltage. The voltage on this pin deter-
mines VOL/VOH on the Si5346 LOL_Ab and LOL_Bb out-
puts. On the Si5347, this pin determines VIL/VIH for the
FDEC and OE1b inputs. Connect to either 3.3 V or 1.8 V.
A 0.1 µF bypass capacitor should be placed very close to
this pin.
VDDO0 22 22 18 P Output Clock Supply Voltage 0–7. Supply voltage (3.3
V, 2.5 V, 1.8 V) for OUTn, OUTnb outputs. A 0.1 uF by-
pass capacitor should be placed very close to this pin.
Leave VDDO pins of unused output drivers unconnected.
An alternate option is to connect the VDDO pin to a power
supply and disable the output driver to minimize current
consumption. A 0402 1 µF capacitor should be placed
very near each of these pins.
VDDO1 29 36 23 P
VDDO2 33 43 29 P
VDDO3 36 49 34 P
VDDO4 43 — — P
VDDO5 49 — — P
VDDO6 52 — — P
VDDO7 57 — — P
GND PAD — — — P Ground Pad. This pad provides connection to ground and
must be connected for proper operation. Use as many vias
as practical and keep the via length to an internal ground
plan as short as possible.
Notes:
1. Refer to the Si5347-46 Rev D Reference Manual for more information on register setting names.
2. I = Input, O = Output, P = Power.
3. The IO_VDD_SEL control bit (0x0943 bit 0) selects 3.3 V or 1.8 V operation.
4. The voltage on the VDDS pin(s) determines 3.3 V or 1.8 V operation.
5. All status pins except I2C and SPI are push-pull.
Si5347/46 Rev D Data Sheet
Pin Descriptions
silabs.com | Building a more connected world. Rev. 1.1 | 48
10. Package Outlines
10.1 Si5347 9x9 mm 64-QFN Package Diagram
The figure below illustrates the package details for the Si5347. The table below lists the values for the dimensions shown in the illustra-
tion.
Figure 10.1. 64-Pin Quad Flat No-Lead (QFN)
Table 10.1. Package Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 9.00 BSC
D2 5.10 5.20 5.30
e 0.50 BSC
E 9.00 BSC
E2 5.10 5.20 5.30
L 0.30 0.40 0.50
aaa — — 0.15
bbb — — 0.10
ccc — — 0.08
ddd — — 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si5347/46 Rev D Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 1.1 | 49
10.2 Si5346 7x7 mm 44-QFN Package Diagram
The figure below illustrates the package details for the Si5346. The table below lists the values for the dimensions shown in the illustra-
tion.
Figure 10.2. 44-Pin Quad Flat No-Lead (QFN)
Table 10.2. Package Dimensions
Dimension Min Nom Max
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
D 7.00 BSC
D2 5.10 5.20 5.30
e 0.50 BSC
E 7.00 BSC
E2 5.10 5.20 5.30
L 0.30 0.40 0.50
aaa — — 0.15
bbb — — 0.10
ccc — — 0.08
ddd — — 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-220.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si5347/46 Rev D Data Sheet
Package Outlines
silabs.com | Building a more connected world. Rev. 1.1 | 50
11. PCB Land Pattern
The figure below illustrates the PCB land pattern details for the devices. The table below lists the values for the dimensions shown in
the illustration. Refer to the Si5347-46 Rev D Reference Manual for information about thermal via recommendations.
Si5347 Si5346
Figure 11.1. PCB Land Pattern
Si5347/46 Rev D Data Sheet
PCB Land Pattern
silabs.com | Building a more connected world. Rev. 1.1 | 51
Table 11.1. PCB Land Pattern Dimensions
Dimension Si5347 (Max) Si5346 (Max)
C1 8.90 6.90
C2 8.90 6.90
E 0.50 0.50
X1 0.30 0.30
Y1 0.85 0.85
X2 5.30 5.30
Y2 5.30 5.30
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition is calculated based on a fabrication
Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
4. A 3x3 array of 1.25 mm square openings on 1.80 mm pitch should be used for the center ground pad.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Si5347/46 Rev D Data Sheet
PCB Land Pattern
silabs.com | Building a more connected world. Rev. 1.1 | 52
12. Top Marking
TW
YYWWTTTTTT
Rxxxxx-GM
Si5347g-
e4 TW
YYWWTTTTTT
Rxxxxx-GM
Si5346g-
e4
Figure 12.1. Si5347/46 Top Marking
Table 12.1. Si5347/46 Top Marking Explanation
Line Characters Description
1 Si5347g-
Si5346g-
Base part number and Device Grade.
Si5347: Quad PLL; 64-QFN
Si5346: Dual PLL; 44-QFN
g = Device Grade. See Section 2. Ordering Guide for more information.
– = Dash character.
2 Rxxxxx-GM R = Product revision. (See Section 2. Ordering Guide for current revision.)
xxxxx = Customer specific NVM sequence number. (Optional NVM code assigned for
custom, factory pre-programmed devices. Characters are not included for standard,
factory default configured devices). See Section 2. Ordering Guide for more informa-
tion.
-GM = Package (QFN) and temperature range (–40 to +85 °C).
3 YYWWTTTTTT YYWW = Characters correspond to the year (YY) and work week (WW) of package
assembly.
TTTTTT = Manufacturing trace code.
4 Circle w/ 1.6 mm (64-QFN) or
1.4 mm (44-QFN) diameter
Pin 1 indicator; left-justified
e4
TW
Pb-free symbol; Center-Justified
TW = Taiwan; Country of Origin (ISO Abbreviation)
Si5347/46 Rev D Data Sheet
Top Marking
silabs.com | Building a more connected world. Rev. 1.1 | 53
14. Revision History
Revision 1.1
September, 2018
• Updated Figure 3.3 Crystal Resonator and External Reference Clock Connection Options on page 9.
• Updated Figure 3.5 Termination of Differential and LVCMOS Input Signals on page 11.
• Updated Figure 3.15 Supported Differential Output Terminations on page 19.
• Updated Table 5.3 Input Clock Specifications on page 27.
• Updated Output-to-Output Skew specification in Table 5.5 Differential Clock Output Specifications on page 29.
• Removed Output-to-Output Skew specification in Table 5.6 LVCMOS Clock Output Specifications on page 30.
• Removed Input-to-Output Delay Variation specification in Table 5.8 Performance Characteristics on page 32.
Revision 1.0
July, 2016
• Initial release.
Si5347/46 Rev D Data Sheet
Revision History
silabs.com | Building a more connected world. Rev. 1.1 | 55
http://www.silabs.com
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
USA
ClockBuilder Pro
One-click access to Timing tools,
documentation, software, source
code libraries & more. Available for
Windows and iOS (CBGo only).
www.silabs.com/CBPro
Timing Portfolio
www.silabs.com/timing SW/HW
www.silabs.com/CBPro Quality
www.silabs.com/quality Support and Community
community.silabs.com
Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant
personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass
destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.
Trademark Information
Silicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®,
EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®,
Gecko®, ISOmodem®, Micrium, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress®, Zentri, Z-Wave, and others are trademarks or
registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited.
All other products or brand names mentioned herein are trademarks of their respective holders.
