MT8976AP - Zarlink Semiconductor, Inc.

Zarlink Semiconductor, formerly

Mitel Semiconductor, announced its new trade identity on

May 29, 2001.

To reﬂect that new identity, rebranding of all product

documentation will be completed by August 31, 2001.

4-29

Features

• D3/D4 or ESF framing and SLC-96 compatible

• 2 frame elastic buffer with 32 µsec jitter buffer

• Inser tion and detection of A, B,C,D bits.

Signalling freeze, optional debounce

• Selectable B8ZS, jammed bit (ZCS) or no zero

code suppression

• Yellow alarm and blue alarm signal capabilities

• Bipolar violation count, FT error count, CRC

error count

• Selectable robbed bit signalling

• Frame and superframe sync. signals, Tx and Rx

• AMI encoding and decoding

• Per channel, overall, and remote loop around

• Digital phase detector between T1 line & ST-

BUS

• One uncommitted scan point and drive point

• Pin compatible with MT8977 and MT8979

• ST-BUS compatible

Applications

• DS1/ESF digital trunk interfaces

• Computer to PBX interfaces (DMI and CPI)

• High speed computer to computer data links

Description

The MT8976 is Mitel’s second generation T1

interface solution. The MT8976 meets the Extended

Super Frame format (ESF), the current D3/D4 for mat

and is compatible with SLC-96 systems.

The MT8976 interfaces to DS1 1.544 Mbit/sec digital

trunk.

Figure 1 - Functional Block Diagram

TxSF

C2i

F0i

RxSF

DSTo

DSTi

CSTi0

CSTi1

CSTo

XCtl

XSt

ST-BUS

Timing

Data

Interface

Serial

Control

Interface

Control Logic

2 Frame

Elastic Buffer

with Slip

Control

2048-1544

Converter

ABCD

Signalling RAM

DS1

Link

Phase

Detector DS1

Counter

Remote &

Digital

Loopbacks

C1.5i

RxFDLClk

RxFDL

RxA

RxB

TxA

TxB

TxFDLClk

TxFDL

RxD

E1.5i

E8Ko

VSS

VDD

•

Circuitry

Interface

Ordering Information

MT8976AE 28 Pin Plastic DIP

MT8976AP 44 Pin PLCC

-40°C to 85°C

ISSUE 11 October 1997

MT8976

T1/ESF Framer Circuit

ISO-CMOS ST-BUS FAMILY

MT8976 ISO-CMOS

4-30

Figure 2 - Pin Connections

Pin Description

Pin # Name Description

DIP PLCC

1 2 TxA Transmit A Output. Unipolar output that can be used in conjunction with TxB and

external line driver circuitry to generate the bipolar DS1 signal.

2 3 TxB Transmit B Output. Unipolar output that can be used in conjunction with TxA and

external line driver circuitry to generate the bipolar DS1 signal.

3 5 DSTo Data ST-BUS Output. A 2048 kbit/s serial output stream which contains the 24

PCM or data channels received from the DS1 line.

44 NC No Connection.

59 RxA Receive A Complementary Input. Accepts a unipolar split phase signal decoded

externally from the received DS1 bipolar signal. This input, in conjunction with RxB,

detects bipolar violations in the received signal.

610 RxB Receive B Complementary Input. Accepts a unipolar split phase signal decoded

externally from the received DS1 bipolar signal. This input, in conjunction with RxA,

detects bipolar violations in the received signal.

7 11 RxD Receive Data Input. Unipolar RZ data signal decoded from the received DS1

signal. Generally the signals input at RxA and RxB are combined externally with a

NAND gate and the resulting composite signal is input at this pin.

8 13 CSTi1 Control ST-BUS Input #1. A 2048 kbit/s serial control stream which carries 24 per-

channel control words.

9 14 TxFDL Transmit Facility Data Link (Input). A 4 kHz serial input stream that is multiplexed

into the FDL position in the ESF mode, or the Fs pattern when in SLC-96 mode. It is

clocked in on the rising edge of TxFDLClk.

10 16 TxFDLClk Transmit Facility Data Link Cloc k (Output). A 4 kHz cloc k used to cloc k in the FDL

data.

11 NC No connection.

VSS

DSTo

TxB

TxA

F0i

E1.5i

C1.5i

RxSF

TxSF

C2i

RxFDL

RxA

RxB

RxD

CSTi1

TxFDL

TxFDLClk

VSS

CSTi0

E8Ko

VSS

XSt

CSTo

RxFDLClk

DSTi

XCtl VDD

28 PIN PDIP

TxA

TxB

DSTo

RxA

RxB

RxD

CSTi1

TxFDL

TxFDLClk

CSTi0

E8Ko

VSS

VDD

F0i

E1.5i

C1.5i

RxSF

TxSF

C2i

RxFDL

DSTi

RxFDLClk

CSTo

XSt

XCtl

65432 44434241

231819202122 2425262728

17 29

44 PIN PLCC

14 15

ISO-CMOS MT8976

4-31

12 19 CSTi0 Control ST-BUS Input #0. A 2048 kbit/s serial control stream that contains 24 per

channel control words and two master control words.

13 20 E8Ko Extracted 8 kHz Output. The E1.5i cloc k is internally divided by 193 to produce an 8

kHz clock which is aligned with the receiv ed DS1 fr ame and output at this pin. The 8

kHz signal is derived from C1.5 in Digital Loopback mode.

14 6,

18,

VSS System Ground.

15 23 XCtl External Control (Output). This is an uncommitted e xternal output pin which is set

or reset via bit 3 in Master Control Word 1 on CSTi0. The state of XCtl is updated

once per frame.

16 24 XSt External Status (Schmitt Trigger Input). The state of this pin is sampled once per

frame and the status is reported in bit 5 of Master Status Word 2 on CSTo.

17 26 CSTo Control ST-BUS Output. This is a 2048 kbit/s serial control stream which provides

the 24 per-channel status words, and two master status words.

18 27 RxFDLClk Receive Facility Data Link Cloc k (Output). A 4 kHz cloc k signal used to cloc k out

FDL information. The data is clocked out on the rising edge of RxFDLClk.

19 28 DSTi Data ST-BUS Input. This pin accepts a 2048 kbit/s serial stream which contains the

24 PCM or data channels to be transmitted on the T1 trunk.

20 29 RxFDL Received Facility Data Link (Output). A 4 kHz serial output stream that is

demultiplexed from the FDL in ESF mode, or the received FS bit pattern in SLC-96

mode. It is clocked out on the rising edge of RxFDLClk.

21 34 C2i 2.048 MHz Clock Input. This is the master clock used for clocking serial data into

DSTi, CSTi0 and CSTi1. It is also used to clock serial data out of CSTo and DSTo.

22 37 TxSF Transmit Superframe Pulse Input. A low going pulse applied at this pin will make

the ne xt transmit frame the ﬁrst frame of a superfr ame. The de vice will free run if this

pin is held high.

23 38 RxSF Received Superframe Pulse Output. A pulse output on this pin designates that the

next frame of data on the ST-BUS is from frame 1 of the received superframe. The

period is 12 frames long in D3/D4 modes and 24 frames in ESF mode. Pulses are

output only when the device is synchronized to the received DS1 signal.

24 39 C1.5i 1.544 MHz Clock Input . This is the DS1 transmit cloc k and is used to output data on

TxA and TxB. It must be phase-locked to C2i. Data is clocked out on the rising

edge of C1.5i.

25 40 E1.5i 1.544 MHz Extracted Clock (Input). This cloc k which is extracted from the received

data is used to clock in data at RxA, RxB and RxD . The f alling edge of the cloc k is

nominally aligned with the center of the received bit on RxD, RxA and RxB.

26 42 F0i Frame Pulse Input. This is the frame synchronization signal which deﬁnes the

beginning of the 32 channel ST-BUS frame.

27 44 IC Internal Connection. Tied to VSS for normal operation.

28 1 VDD Positive Power Supply Input. +5V ± 5%.

Pin Description (Continued)

Pin # Name Description

DIP PLCC

MT8976 ISO-CMOS

4-32

Functional Timing Diagrams

Figure 3 - ST-BUS Timing

Figure 4 - DS1 Receive Timing

Figure 5 - DS1 Transmit Timing

C2i

DSTi

DSTo

CSTi0/CSTi1

CSTo

•

•••••••

•

•••••••

765 43210

7210

125µSec

E1.5i

INT DATA

DS1 AMI

LINE SIGNAL

RxA

RxB

RxD

E8Ko

11001101

125µSec

C1.5i

INT DATA

TxA

TxB

DS1 AMI

LINE SIGNAL

ISO-CMOS MT8976

4-33

ST-BUS CHANNEL VERSUS DS1 CHANNEL TRANSMITTED

ST-BUS CHANNEL VERSUS DS1 CHANNEL RECEIVED

PCCW =PER CHANNEL CONTROL WORD

MCW1/2 =MASTER CONTROL WORD 1/2 ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED

PCCW =PER CHANNEL CONTROL WORD

ST-BUS CHANNEL VERSUS DS1 CHANNEL CONTROLLED

PCSW =PER CHANNEL STATUS WORD

PSW =PHASE STATUS WORD

MSW =MASTER STATUS WORD ST-BUS VERSUS DS1 CHANNEL STATUS

Figure 6 - ST-BUS Channel Allocations

X=UNUSED CHANNEL

DSTi 0

X1234

X5678

X9101112

X13 14 15 16

X17 18 19 20

X21 22 23 24

X25 26 27 28

X29 30 31

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

DSTo 0

X1234

X5678

X9 101112

X13 14 15 16

X17 18 19 20

X21 22 23 24

X25 26 27 28

X29 30 31

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CSTi0 0

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CSTi1 0

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

CSTo 0

PCS

DS1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MT8976 ISO-CMOS

4-34

Functional Description

The MT8976 provides a simple interface to a

bidirectional DS1 link. All of the formatting and

signalling insertion and detection is done by the

device. Various programmable options in the device

include: ESF, D3/D4, or SLC-96 mode, common

channel or robbed bit signalling, zero code

suppression, alarms, and local and remote loop

back. All data and control information is

communicated to the MT8976 via 2048 kbit/s serial

streams confor ming to Mitel’s ST-BUS format.

The ST-BUS is a TDM serial bus that operates at

2048 kbits/s. The serial streams are divided into 125

µsec frames that are made up of 32 8 bit channels . A

serial stream that is made up of these 32 8 bit

channels is known as an ST-BUS stream, and one of

these 64 kbit/s channels is known as an ST-BUS

channel.

The system side of the MT8976 is made up of ST-

BUS inputs and outputs, i.e., control inputs and

outputs (CSTi/o) and data inputs and outputs

(DSTi/o). These signals are functionally represented

in Figure 3. The line side of the device is made up of

the split phase inputs and outputs that can be

interfaced to an external bipolar receiver and

transmitter. Functional transmit and receive timing

is shown in Figures 4 and 5.

Data for transmission on the DS1 line is clocked

serially into the device at the DSTi pin. The DSTi pin

accepts a 32 channel time division multiplexed ST-

BUS stream. Data is clocked in with the falling edge

of the C2i clock. ST-BUS frame boundaries are

deﬁned by the frame pulse applied at the F0i pin.

Only 24 of the available 32 channels on the ST-BUS

serial stream are actually transmitted on the DS1

side. The unused 8 channels are ignored by the

device.

Data received from the DS1 line is clocked out of the

device in a similar manner at the DSTo pin. Data is

clocked out on the rising edge of the C2i clock. Only

24 of the 32 channels output by the device contain

the information from the DS1 line. The DSTo pin is,

however, actively driven during the unused channel

timeslots. Figure 6 shows the correspondence

between the DS1 channels and the ST-BUS

channels.

All control and monitoring of the device is

accomplished through two ST-BUS serial control

inputs and one serial control output. Control ST-BUS

input number 0 (CSTi0) accepts an ST-BUS serial

stream which contains the 24 per channel control

words and two master control words. The per

channel control words relate directly to the 24

information channels output on the DS1 side. The

master control words affect operation of the whole

device. Control ST-BUS input number 1 (CSTi1)

accepts an ST-BUS stream containing the A, B, C

and D signalling bits. The relationship between the

CSTi channels and the controlled DS0 channels is

shown in Figure 6. Status and signalling information

is received from the device via the control ST-BUS

output (CSTo). This serial output stream contains two

master status words, 24 per channel status words

and one Phase Status Word. Figure 6 shows the

correspondence between the received DS1 channels

and the status words. Detailed information on the

operation of the control interface is presented below.

Programmable Features

The main features in the device are programmed

through two master control words which occupy

channels 15 and 31 in Control ST-BUS input stream

number 0 (CSTi0). These two eight bit words are

used to:

• Select the different operating modes of the

device ESF, D3/D4 or SLC-96.

• Activate the features that are needed in a

certain application; common channel signalling,

zero code suppression, signalling debounce,

etc.

• Tur n on in ser vice alar ms, diagnostic loop

arounds, and the external control function.

Tables 1 and 2 contain a complete e xplanation of the

function of the different bits in Master Control Words

1 and 2.

Major Operating Modes

The major operating modes of the device are

enabled by bits 2 and 4 of Master Control Word 2.

The Extended Superframe(ESF) mode is enabled

when bit 4 is set high. Bit 2 has no effect in this

mode. The ESF mode enables the transmission of

the S bit pattern shown in Table 3. This includes the

frame/superframe pattern, the CRC-6, and the

Facility Data Link (FDL). The device generates the

frame/multiframe pattern and calculates the CRC for

each superframe. The data clocked into the device

on the TxFDL pin is incorporated into the FDL. ESF

mode will also insert A, B, C and D signalling bits

into the 24 frame multiframe. The DS1 frame begins

after approximately 25 periods of the C1.5i clock

from the F0i frame pulse.

During synchronization the receiver locks to the

incoming frame, calculates the CRC and compares it

ISO-CMOS MT8976

4-35

Table 1. Master Control Word 1 (Channel 15, CSTi0)

Bit Name Description

7 Debounce When set the received A, B, C and D signalling bits are reported directly in the per channel

status words output at CSTo. When clear, the signalling bits are debounced for 6 to 9 ms

before they are placed on CSTo.

6 TSPZCS Transparent Zero Code Suppression. When this bit is set, no zero code suppression is

implemented.

5 B8ZS Binary Eight Zero Suppression. When this bit is set, B8ZS zero code suppression is

enabled. When clear, bit 7 in data channels containing all zeros is f orced high before being

transmitted on the DS1 side. This bit is inactive if the TSPZCS bit is set.

4 8KHSel 8 kHz Output Select. When set, the E8Ko pin is held high. When clear, the E8Ko

generates an 8 kHz output derived from the E1.5i or C1.5 clock (see Pin Description for

E8Ko).

3 XCtl External Control Pin. When set, the XCtl pin is held high. When clear, XCtl is held low.

2 ESFYLW ESF Yellow Alarm. Valid only in ESF mode. When set, a sequence of eight 1’s followed

by eight 0’s is sent in the FDL bit positions. When clear, the FDL bit contains data input at

the TxFDL pin.

1 Robbed bit When this bit is set, robbed bit signalling is disabled on all DS0 transmit channels. When

clear, A, B , C and D signalling bit insertion in bit 8 f or all DS0 tr ansmit channels in e v ery 6 th

frame is enabled.

0 YLALR Yellow Alarm. When set, bit 2 of all DS1 channels is set low. When clear, bit 2 operates

normally.

to the CRC received in the next multiframe. The

device will not declare itself to be in synchronization

unless a valid framing pattern in the S-bit is detected

and a correct CRC is received. The CRC check in

this case provides protection against false framing.

The CRC check can be turned off by setting bit 1 in

Master Control Word 2.

The device can be forced to resynchronize itself. If

Bit 3 in Master Control Word 2 is set for one frame

and then subsequently reset, the device will start to

search for a new frame position. The decision to

reframe is made by the user’s system processor on

the basis of the status conditions detected in the

received master status words. This may include

consideration of the number of errors in the received

CRC in conjunction with an indication of the

presence of a mimic. When the device attains

synchronization the mimic bit in Master Status Word

1 is set if the device found another possible

candidate when it was searching for the framing

pattern.

Note that the device will resynchronize automatically

if the errors in the terminal framing pattern (FT or

FPS) exceed the threshold set with bit 0 in Master

Control Word 2.

Standard D3/D4 framing is enabled when bit 4 of

Master Control Word 2 is reset (logic 0). In this

mode the device searches for and inserts the

framing pattern shown in Table 4. This mode only

supports AB bit signalling, and does not contain a

CRC check.

The CRC/MIMIC bit in Master Control Word 2, when

set high, allows the device to synchronize in the

presence of a mimic. If this bit is reset, the de vice will

not synchronize in the presence of a mimic (Also,

refer to section on Framing algorithm).

In the D3/D4 mode the device can also be made

compatible with SLC-96 by setting bit two of Master

Control Word 2. This allows the user to insert and

extract the signalling framing pattern on the DS1 bit

stream using the FDL input and output pins. The

user must format this 4 kbits of information externally

to meet all of the requirements of the SLC-96

speciﬁcation (see Table 5). The device multiplexes

and demultiplexes this information into the proper

position. This mode of operation can also be used for

any other application that uses all or part of the

signalling framing pattern. As long as the serial

stream clocked into the TxFDL contains two proper

sets of consecutive synchronization bits (as shown

in Table 5 for frames 1 to 24), the device will be able

to insert and extract the A, B signalling bits. The

TxSF pin should be held high in this mode.

Superframe boundaries cannot be deﬁned by a

pulse on this input. The RxSF output functions

normally and indicates the superframe boundaries

based on the synchronization pattern in the FS

received bit position.

Zero Code Suppression

The combination of bits 5 and 6 in Master Control

Word 1 allow one of three zero code suppression

4-36

MT8976 ISO-CMOS

Table 2. Master Control Word 2 (Channel 31, CSTi0)

Bit Name Description

7 RMLOOP Remote Loopback. When set, the data received at RxA and RxB is looped back to TxB

and TxA respectively. The data is clocked into the device with E1.5i. The device still

monitors the received data and outputs it at DSTo. The de vice operates normally when the

bit is clear.

6 DGLOOP Digital Loopback. When set, the data input on DSTi is looped around to DSTo. The

normal received data on RxA, RxB and RxD is ignored. However, the data input at DSTi

is still transmitted on TxA and TxB. The device frames up on the looped data using the

C1.5i clock.

5 ALL1'S All One’s Alarm. When set, the chip transmits an unframed all 1's signal on TxA and TxB.

4 ESF/D4 ESF/D4 Select. When set, the device is in ESF mode. When clear, the device is in

D3/D4 mode.

3 ReFR Reframe. If set for at least one frame and then cleared, the chip will begin to search for a

new frame position. Only the change from high to low will cause a reframe, not a

continuous low level.

2 SLC-96 SLC-96 Mode Select. The chip is in SLC-96 mode when this bit is set. This enables input

and output of the FSbit pattern using the same pins as the facility data link in ESF mode.

The chip will use the same framing algorithm as D3/D4 mode. The user must insert the

valid FS bits in 2 out of 6 superframes to allow the receiver to ﬁnd superframe sync, and

the transmitter to insert A and B bits in every 6th frame. The SLC-96 FDL completely

replaces the FS pattern in the outgoing S bit position. Inactive in ESF mode.

1 CRC/MIMIC In ESF mode, when set, the chip disregards the CRC calculation during synchronization.

When clear, the device will check for a correct CRC before going into synchronization. In

D3/D4 mode, when set, the device will synchronize on the ﬁrst correct S-bit pattern

detected. When this bit is clear , the de vice will not synchronize if it has detected more than

one candidate for the frame alignment pattern (i.e., a mimic).

0 Maint. Maintenance Mode. When set, the device will declare itself out-of-sync if 4 out of 12

consecutive FT bits are in error. When clear, the out-of-sync threshold is 2 errors in 4 FT

bits. In this mode, four consecutive bits following an errored FT bit are examined.

schemes to be selected. The three choices are:

none, binary 8 zero suppression (B8ZS), or jammed

bit (bit 7 forced high). No zero code suppression

allows the device to interface with systems that have

already applied some for m of zero code suppression

to the data input on DSTi. B8ZS zero code

suppression replaces all strings of 8 zeros with a

known bit pattern and a speciﬁc pattern of bipolar

violations. This bit pattern and violation pattern is

shown in Figure 7. The receiver monitors the

received bit pattern and the bipolar violation pattern

and replaces all matching strings with 8 zeros.

Loopback Modes

Remote and digital loopback modes are enabled by

bits 6 and 7 in Master Control Word 2. These modes

can be used for diagnostics in locating the source of

a fault condition. Remote loop around loops back

data received at RxA a nd RxB ba ck out on TxA and

TxB, thus effectively sending the received DS1 data

back to the far end unaltered so that the transmission

line can be tested. The received signal is still

monitored with the appropriate received channels on

the DS1 side made available in the proper format at

DSTo.

The digital loop around mode diverts the data

received at DSTi back out the DSTo pin. Data

received on DSTi is, however, still transmitted out via

TxA and TxB. This loop back mode can be used to

test the near end interface equipment when there is

no transmission line or when there is a suspected

failure of the line.

The all one’s transmit alar m (also known as the blue

alarm or the keep alive signal) can be activated in

conjunction with the digital loop around so that the

transmission line sends an all 1's signal while the

normal data is looped back locally.

The MT8976 also has a per channel loopback mode.

See Table 6 and the following section for more

information.

Per Channel Control Features

In addition to the two master control words in CSTi0

there are also 24 Per Channel Control Words. These

control words only affect individual DS0 channels.

The correspondence between the channels on CSTi0

and the affected DS0 channel is shown in Fig. 6.

ISO-CMOS MT8976

4-37

Table 3. ESF Frame Pattern

† These signalling bits are only valid if the robbed bit signalling is

active.

Table 4. D3/D4 Framer

† These signalling bits are only valid if the robbed bit signalling is

active.

Each control word has three bits that enable robbed

bit signalling, DS0 channel loopback and inversion of

the DS0 channel. A full description of each of the bits

is provided in Table 6.

Transmit Signalling Bits

Control ST-BUS input number 1 (CSTi1) contains 24

additional per channel control words. These 24 ST-

BUS channels contain the A, B, C and D signalling

bits that the device uses at transmit time. The

position of these 24 per channel control words in the

ST-BUS is shown in Figure 6 and the position of the

ABCD signalling bits is shown in Table 7. Even

though the device only inserts the signalling

information in every 6th DS1 frame this information

must be input ever y ST-BUS frame.

Robbed bit signalling can be disabled for all

channels on the DS1 link by bit 1 of Master Control

Word 1. It can also be disabled on a per channel

basis by bit 0 in the Per Channel Control Word 1.

Operating Status Information

Status Information regarding the operation of the

device is output serially via the Control ST-BUS

output (CSTo). The CSTo serial stream contains

Master Status Words 1 and 2, 24 Per Channel Status

Words, and a Phase Status Word. The Master Status

Words contain all of the information needed to

determine the state of the interface and how well it is

operating. The information provided includes frame

and super frame synchronization, slip, bipolar

violation counter, alarms, CRC error count, FT error

count, synchronization pattern mimic and a phase

status word. Tables 8 and 9 give a description of

each of the bits in Master Status Words 1 and 2, and

Table 10 gives a description of the Phase Status

Word.

Alarm Detection

The device detects the yellow alarm for both D3/D4

frame format and ESF format. The D3/D4 yellow

alarm will be activated if a ‘0‘ is received in bit

position 2 of every DS0 channel for 600 msec. It will

be released in 200 msec after the contents of the bit

change. The alarm is detectable in the presence of

errors on the line. The ESF yellow alarm will become

active when the device has detected a string of eight

0’s followed by eight 1’s in the facility data link. It is

not detectable in the presence of errors on the line.

This means that the ESF yellow alarm will drop out

for relatively short per iods of time, so the system will

have to integrate the ESF yellow alarm. The blue

alarm signal, in Master Status Word 2 , will also drop

out if there are errors on the line.

Mimic Detection

The mimic bit in Master Status Word 1 will be set if,

during synchronization, a frame alignment pattern

(FT or FPS bit pattern) was observed in more than

one position, i.e., if more than one candidate for the

frame synchronization position was observed. It will

be reset when the device resynchronizes. The mimic

bit, the terminal framing error bit and the CRC error

counter can be used separately or together to decide

if the receiver should be forced to reframe.

Frame # FPS FDL CRC Signalling†

2 CB1

6 CB2 A

10 CB3

11 X

12 1 B

13 X

14 CB4

15 X

16 0

17 X

18 CB5 C

19 X

20 1

21 X

22 CB6

23 X

24 1 D

Frame # FTFSSignalling †

61A

10 1

11 0

12 0 B