1. General description
The 74HC594; 74HCT594 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL).
The 74HC594; 74HCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register that
feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct
overriding clears (SHR and STR) are provided on both the shift and storage registers.
A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register will always be one count pulse ahead of the
storage register.
2. Features
nSynchronous serial input and output
nComplies with JEDEC standard No.7A
n8-bit parallel output
nShift and storage registers have independent direct clear and clocks
nIndependent clocks for shift and storage registers
n100 MHz (typical)
nMultiple package options
nSpecified from 40 °Cto+85°C and from 40 °C to +125 °C
3. Applications
nSerial-to parallel data conversion
nRemote control holding register
74HC594; 74HCT594
8-bit shift register with output register
Rev. 03 — 20 December 2006 Product data sheet
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 2 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
4. Ordering information
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature
range Name Description Version
74HC594D 40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HC594DB 40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HC594N 40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HCT594D 40 °C to +125 °C SO16 plastic small outline package; 16 leads;
body width 3.9 mm SOT109-1
74HCT594DB 40 °C to +125 °C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HCT594N 40 °C to +125 °C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
Fig 1. Functional diagram
mbc320
Q7Q0 Q1 Q2 Q3 Q4 Q5 Q6
DS
SHCP
SHR
STCP
STR
14
10
13
11
12
15
9
1234567
8-STAGE SHIFT REGISTER
8-BIT STORAGE REGISTER
Q7S
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 3 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
Fig 2. Logic symbol Fig 3. IEC logic symbol
mbc319
STCPSHCP
STRSHR
DS
Q7S
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
14
10 13
11 12
15
9
1
2
3
4
5
6
7
mbc322
SHCP
STCP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SHR
STR
DS 15
9
1
2
3
4
5
6
7
1D 2D
C1/
10
11
14
C2
12
13 R2
SRG8R1
Q7S
Fig 4. Logic diagram
mbc321
Q0 Q1 Q2 Q3 Q4 Q5 Q6
DS
SHCP
SHR
STCP
STR
DQ
CP
FFSH0
R
STAGE 0
DQ
CP
FFST0
R
STAGES 1 TO 6
DQ
Q7
DQ
CP
FFSH7
R
STAGE 7
DQ
CP
FFST7
R
Q7S
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 4 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
6. Pinning information
6.1 Pinning
Fig 5. Timing diagram
mbc323
Q7S
Q0
STR
SHR
STCP
DS
SHCP
Q1
Q6
Q7
Fig 6. Pin configuration SO16
Q1 VCC
Q2 Q0
Q3 DS
Q4 STR
Q5 STCP
Q6 SHCP
Q7 SHR
GND Q7S
001aaf611
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC594
74HCT594
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 5 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
6.2 Pin description
Fig 7. Pin configuration SSOP16 Fig 8. Pin configuration DIP16
74HC594
74HCT594
Q1 VCC
Q2 Q0
Q3 DS
Q4 STR
Q5 STCP
Q6 SHCP
Q7 SHR
GND Q7S
001aaf613
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC594
74HCT594
Q1 VCC
Q2 Q0
Q3 DS
Q4 STR
Q5 STCP
Q6 SHCP
Q7 SHR
GND Q7S
001aaf614
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
Q1 1 parallel data output 1
Q2 2 parallel data output 2
Q3 3 parallel data output 3
Q4 4 parallel data output 4
Q5 5 parallel data output 5
Q6 6 parallel data output 6
Q7 7 parallel data output 7
GND 8 ground (0 V)
Q7S 9 serial data output
SHR 10 shift register reset (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
STR 13 storage register reset (active LOW)
DS 14 serial data input
Q0 15 parallel data output 0
VCC 16 supply voltage
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 6 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
= LOW-to-HIGH transition;
X = don’t care.
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP16 packages: above 70 °C the value of Ptot derates linearly with 12 mW/K.
For SO16 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.
For SSOP16 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.
Table 3. Function table[1]
Function Input
SHR STR SHCP STCP DS
Clear shift register L X X X X
Clear storage register X L X X X
Load DS into shift register stage 0, advance previous stage data to the next stage H X X H or L
Transfer shift register data to storage register and outputs Qn X H X X
Shift register one count pulse ahead of storage register H H ↑↑X
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7.0 V
IIK input clamping current VI < 0.5 V or VI>V
CC + 0.5 V [1] -±20 mA
IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] -±20 mA
IOoutput current VO=0.5 V to VCC + 0.5 V
Serial data output Q7S - ±25 mA
Parallel data output - ±35 mA
ICC supply current Serial data output Q7S - 50 mA
Parallel data output - 70 mA
IGND ground current Serial data output Q7S - 50 mA
Parallel data output - 70 mA
Tstg storage temperature 65 +150 °C
Ptot total power dissipation Tamb = 40 °C to +125 °C[2] - 500 mW
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 7 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
9. Recommended operating conditions
10. Static characteristics
Table 5. Recommended operating conditions
Symbol Parameter Conditions Min Typ Max Unit
Type 74HC594
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 °C
trrise time VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
tffall time VCC = 2.0 V - - 1000 ns
VCC = 4.5 V - 6.0 500 ns
VCC = 6.0 V - - 400 ns
Type 74HCT594
VCC supply voltage 4.5 5.0 5.5 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 °C
trrise time VCC = 4.5 V - 6.0 500 ns
tffall time VCC = 4.5 V - 6.0 500 ns
Table 6. Static characteristics type 74HC594
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 1.2 - V
VCC = 4.5 V 3.15 2.4 - V
VCC = 6.0 V 4.2 3.2 - V
VIL LOW-level input voltage VCC = 2.0 V - 0.8 0.5 V
VCC = 4.5 V - 2.1 1.35 V
VCC = 6.0 V - 2.8 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - V
IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - V
IO = 7.8 mA; VCC = 6.0 V 5.48 5.81 - V
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 8 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
VOL LOW-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V - 0.15 0.26 V
IO = 7.8 mA; VCC = 6.0 V - 0.16 0.26 V
IIinput leakage current VI=V
CC or GND; VCC = 6.0 V - - ±0.1 µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V - - 8.0 µA
Ciinput capacitance - 3.5 - pF
Tamb = 40 °C to +85 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V 3.84 - - V
IO = 5.2 mA; VCC = 6.0 V 5.34 - - V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V 3.84 - - V
IO = 7.8 mA; VCC = 6.0 V 5.34 - - V
VOL LOW-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V - - 0.33 V
IO = 5.2 mA; VCC = 6.0 V - - 0.33 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V - - 0.33 V
IO = 7.8 mA; VCC = 6.0 V - - 0.33 V
IIinput leakage current VI=V
CC or GND; VCC = 6.0 V - - ±1.0 µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V --80µA
Tamb = 40 °C to +125 °C
VIH HIGH-level input voltage VCC = 2.0 V 1.5 - - V
VCC = 4.5 V 3.15 - - V
VCC = 6.0 V 4.2 - - V
Table 6. Static characteristics type 74HC594
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 9 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
VIL LOW-level input voltage VCC = 2.0 V - - 0.5 V
VCC = 4.5 V - - 1.35 V
VCC = 6.0 V - - 1.8 V
VOH HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V 3.7 - - V
IO = 5.2 mA; VCC = 6.0 V 5.2 - - V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V 3.7 - - V
IO = 7.8 mA; VCC = 6.0 V 5.2 - - V
VOL LOW-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V - - 0.4 V
IO = 5.2 mA; VCC = 6.0 V - - 0.4 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V - - 0.4 V
IO = 7.8 mA; VCC = 6.0 V - - 0.4 V
IIinput leakage current VI=V
CC or GND; VCC = 6.0 V - - ±1.0 µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 6.0 V - - 160 µA
Table 6. Static characteristics type 74HC594
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 10 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
Table 7. Static characteristics type 74HCT594
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = 25 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 V
VOH HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V 3.98 4.32 - V
VOL LOW-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V - 0.16 0.26 V
IIinput leakage current VI=V
CC or GND; VCC = 5.5 V - - ±0.1 µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V - - 8.0 µA
ICC additional supply current per input pin; VI=V
CC 2.1 V and
other inputs at VCC or GND;
IO= 0 A; VCC = 4.5 V to 5.5 V
pins SHR, SHCP, STCP, STR - 150 540 µA
pin DS - 25 90 µA
Ciinput capacitance - 3.5 - pF
Tamb = 40 °C to +85 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V 3.84 - - V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V 3.84 - - V
VOL LOW-level output voltage VI = VIH or VIL
Serial data output
IO = 4.0 mA; VCC = 4.5 V - - 0.33 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V - - 0.33 V
IIinput leakage current VI=V
CC or GND; VCC = 5.5 V - - ±1.0 µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V --80µA
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 11 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
ICC additional supply current per input pin; VI=V
CC 2.1 V and
other inputs at VCC or GND;
IO= 0 A; VCC = 4.5 V to 5.5 V
pins SHR, SHCP, STCP, STR - - 675 µA
pin DS - - 112.5 µA
Tamb = 40 °C to +125 °C
VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - V
VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 V
VOH HIGH-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V 3.7 - - V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V 3.7 - - V
VOL LOW-level output voltage VI = VIH or VIL
Serial data output Q7S
IO = 4.0 mA; VCC = 4.5 V - - 0.4 V
Parallel data outputs
IO = 6.0 mA; VCC = 4.5 V - - 0.4 V
IIinput leakage current VI=V
CC or GND; VCC = 5.5 V - - ±1.0 µA
ICC supply current VI = VCC or GND; IO = 0 A;
VCC = 5.5 V - - 160 µA
ICC additional supply current per input pin; VI=V
CC 2.1 V and
other inputs at VCC or GND;
IO= 0 A; VCC = 4.5 V to 5.5 V
pins SHR, SHCP, STCP, STR - - 735 µA
pin DS - - 122.5 µA
Table 7. Static characteristics type 74HCT594
…continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 12 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
11. Dynamic characteristics
Table 8. Dynamic characteristics type 74HC594
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF; see Figure 15.
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
tpd propagation
delay SHCP to Q7S;
see Figure 9 [1]
VCC = 2.0 V - 44 150 - 185 - 225 ns
VCC = 4.5 V - 16 30 - 37 - 45 ns
VCC = 5.0 V;
CL = 15 pF -13- - - - -ns
VCC = 6.0 V - 14 26 - 31 - 38 ns
STCP to Qn; see
Figure 10
VCC = 2.0 V - 44 150 - 185 - 225 ns
VCC = 4.5 V - 16 30 - 37 - 45 ns
VCC = 5.0 V;
CL = 15 pF -13- - - - -ns
VCC = 6.0 V - 14 26 - 31 - 38 ns
tPHL HIGH to
LOW
propagation
delay
SHRtoQ7S;see
Figure 13
VCC = 2.0 V - 39 150 - 185 - 225 ns
VCC = 4.5 V - 14 30 - 37 - 45 ns
VCC = 5.0 V;
CL = 15 pF -11- - - - -ns
VCC = 6.0 V - 12 26 - 31 - 38 ns
STR to Qn; see
Figure 14
VCC = 2.0 V - 39 125 - 155 - 185 ns
VCC = 4.5 V - 14 25 - 31 - 37 ns
VCC = 5.0 V;
CL = 15 pF -11- - - - -ns
VCC = 6.0 V - 12 21 - 26 - 31 ns
tTHL HIGH to
LOW output
transition
time
see Figure 9
Serial data output Q7S
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
Parallel data outputs
VCC = 2.0 V - 14 60 - 75 - 90 ns
VCC = 4.5 V - 5 12 - 15 - 18 ns
VCC = 6.0 V - 4 10 - 13 - 15 ns
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 13 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
tTLH LOW to
HIGH output
transition
time
see Figure 9
Serial data output Q7S
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
Parallel data outputs
VCC = 2.0 V - 14 60 - 75 - 90 ns
VCC = 4.5 V - 5 12 - 15 - 18 ns
VCC = 6.0 V - 4 10 - 13 - 15 ns
tWpulse width SHCP (HIGH or
LOW); see
Figure 9
VCC = 2.0 V 80 10 - 100 - 120 - ns
VCC = 4.5 V 16 4 - 20 - 24 - ns
VCC = 6.0 V 14 3 - 17 - 20 - ns
STCP (HIGH or
LOW); see
Figure 10
VCC = 2.0 V 80 10 - 100 - 120 - ns
VCC = 4.5 V 16 4 - 20 - 24 - ns
VCC = 6.0 V 14 3 - 17 - 20 - ns
SHR and STR
(HIGH or LOW);
see Figure 13
and Figure 14
VCC = 2.0 V 80 14 - 100 - 120 - ns
VCC = 4.5 V 16 5 - 20 - 24 - ns
VCC = 6.0 V 14 4 - 17 - 20 - ns
Table 8. Dynamic characteristics type 74HC594
…continued
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF; see Figure 15.
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 14 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
tsu set-up time DS to SHCP;
see Figure 11
VCC = 2.0 V 100 10 - 125 - 150 - ns
VCC = 4.5 V 20 4 - 25 - 30 - ns
VCC = 6.0 V 17 3 - 21 - 26 - ns
SHR to STCP;
see Figure 12
VCC = 2.0 V 100 14 - 125 - 150 - ns
VCC = 4.5 V 20 5 - 25 - 30 - ns
VCC = 6.0 V 17 4 - 21 - 26 - ns
SHCP to STCP;
see Figure 10
VCC = 2.0 V 100 17 - 125 - 150 - ns
VCC = 4.5 V 20 6 - 25 - 30 - ns
VCC = 6.0 V 17 5 - 21 - 26 - ns
thhold time DS to SHCP;
see Figure 11
VCC = 2.0 V 25 8 - 30 - 35 - ns
VCC = 4.5 V 5 3- 6 - 7 -ns
VCC = 6.0 V 4 2- 5 - 6 -ns
trec recovery
time SHR to SHCP
and
STR to STCP;
see Figure 13
and Figure 14
VCC = 2.0 V 50 14 - 65 - 75 - ns
VCC = 4.5 V 10 5 - 13 - 15 - ns
VCC = 6.0 V 9 4 - 11 - 13 - ns
fmax maximum
frequency SHCP or STCP;
see Figure 9 and
Figure 10
VCC = 2.0 V 6.0 30 - 4.8 - 4.0 - MHz
VCC = 4.5 V 30 92 - 24 - 20 - MHz
VCC = 5.0 V;
CL = 15 pF - 100 - - - - - MHz
VCC = 6.0 V 35 109 - 28 - 24 - MHz
Table 8. Dynamic characteristics type 74HC594
…continued
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF; see Figure 15.
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 15 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
[1] tpd is the same as tPHL and tPLH.
[2] CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi×N+(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL×VCC2×fo) = sum of outputs.
CPD power
dissipation
capacitance
VI= GND to VCC;
VCC =5V;
fi= 1 MHz
[2] -84- - - - -pF
Table 8. Dynamic characteristics type 74HC594
…continued
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF; see Figure 15.
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
Table 9. Dynamic characteristics type 74HCT594
GND = 0 V;
V
CC
= 4.5 V;
t
r
= t
f
= 6 ns; C
L
= 50 pF; see Figure 15.
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
tpd propagation
delay SHCP to Q7S;
see Figure 9 [1] - 18 32 - 40 - 48 ns
VCC = 5.0 V;
CL = 15 pF -15- - - - -ns
STCP to Qn; see
Figure 10 - 18 32 - 40 - 48 ns
VCC = 5.0 V;
CL = 15 pF -15- - - - -ns
tPHL HIGH to
LOW
propagation
delay
SHRtoQ7S;see
Figure 13 - 17 30 - 38 - 45 ns
VCC = 5.0 V;
CL = 15 pF -14- - - - -ns
STR to Qn; see
Figure 14 - 17 30 - 38 - 45 ns
VCC = 5.0 V;
CL = 15 pF -14- - - - -ns
tTHL HIGH to
LOW output
transition
time
see Figure 9
Serial data output Q7S
VCC = 4.5 V - 7 15 - 19 - 22 ns
Parallel data outputs
VCC = 4.5 V - 5 12 - 15 - 18 ns
tTLH LOW to
HIGH output
transition
time
see Figure 9
Serial data output Q7S
VCC = 4.5 V - 7 15 - 19 - 22 ns
Parallel data outputs
VCC = 4.5 V - 5 12 - 15 - 18 ns
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 16 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
[1] tpd is the same as tPHL and tPLH.
[2] CPD is used to determine the dynamic power dissipation (PD in µW):
PD=C
PD ×VCC2×fi×N+(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL×VCC2×fo) = sum of outputs.
tWpulse width SHCP (HIGH or
LOW); see
Figure 9
16 4 - 20 - 24 - ns
STCP (HIGH or
LOW); see
Figure 10
16 4 - 20 - 24 - ns
SHR and STR
(HIGH or LOW);
see Figure 13
and Figure 14
16 6 - 20 - 24 - ns
tsu set-up time DS to SHCP;
see Figure 11 20 4 - 25 - 30 - ns
SHR to STCP;
see Figure 12 20 6 - 25 - 30 - ns
SHCP to STCP;
see Figure 10 20 7 - 25 - 30 - ns
thhold time DS to SHCP;
see Figure 11 53- 6 - 7 -ns
trec recovery
time SHR to SHCP
and
STR to STCP;
see Figure 13
and Figure 14
10 5 - 13 - 15 - ns
fmax maximum
frequency SHCP or STCP;
see Figure 9 and
Figure 10
30 92 - 24 - 20 - MHz
VCC = 5.0 V;
CL = 15 pF - 100 - - - - - MHz
CPD power
dissipation
capacitance
VI= GND to VCC
1.5 V;
VCC =5V;
fi= 1 MHz
[2] -89- - - - -pF
Table 9. Dynamic characteristics type 74HCT594
…continued
GND = 0 V;
V
CC
= 4.5 V;
t
r
= t
f
= 6 ns; C
L
= 50 pF; see Figure 15.
Symbol Parameter Conditions 25 °C40 °C to +85 °C40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 17 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
12. Waveforms
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
tTLH = LOW to HIGH output transition time; tTHL = HIGH to LOW output transition time.
Fig 9. The shift clock (SHCP) to output (Q7S) propagation delays, the shift clock pulse
width, the maximum shift clock frequency, and output transition times
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Fig 10. The storage clock (STCP) to output (Qn), propagation delays, the storage clock
pulse width, the maximum storage clock pulse frequency and the shift clock to
storage clock set-up time
001aae341
SHCP input
Q7S output
VM
tPLH
tTLH tTHL
tPHL
VM
tW
1/fmax
VM
tW
1/ fmax
VM
VM
tsu
tPLH
Qn outputs
STCP input
SHCP input
tPHL
mla512
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 18 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
Measurement points are given in Table 10.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
Fig 11. The data set-up time and hold times for DS input to SHCP
Measurement points are given in Table 10.
Fig 12. The set-up time shift reset (SHR) to storage clock (STCP)
001aae342
th
tsu th
tsu
VM
VM
VM
Q7 output
SHCP input
DS input
mbc326
VM
tsu
VM
VM
STCP input
Qn outputs
SHR input
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 19 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Fig 13. The shift reset (SHR) pulse width, the shift reset to output (Q7S) propagation delay
and the shift reset to shift clock (SHCP) recovery time
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Fig 14. The storage reset (STR) pulse width, the storage reset to output (Qn) propagation
delay and the storage reset to storage clock (STCP) recovery time
Table 10. Measurement points
Type Input Output
VMVM
74HC594 0.5 ×VCC 0.5 ×VCC
74HCT594 1.3 V 1.3 V
mbc324
VM
tPHL
VM
trec
tW
VM
SHCP input
Q7S output
SHR input
mbc325
VM
tPHL
VM
trec
tW
VM
STCP input
Qn outputs
STR input
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 20 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 15. Load circuitry for measuring switching times
Table 11. Test data
Type Input Load S1 position
VItr, tfCLRLtPHL, tPLH tPZH, tPHZ tPZL, tPLZ
74HC594 VCC 6 ns 15 pF, 50 pF 1 kopen GND VCC
74HCT594 3 V 6 ns 15 pF, 50 pF 1 kopen GND VCC
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
001aad983
DUT
VCC VCC
VIVO
RT
RLS1
CL
open
PULSE
GENERATOR
74HC_HCT594_3 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 03 — 20 December 2006 21 of 26
NXP Semiconductors 74HC594; 74HCT594
8-bit shift register with output register
13. Package outline
Fig 16. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e