306666-12
August 2008
Numonyx™ StrataFlash® Embedded Memory
(P30)
Datasheet
Product Features
High perf orma nce
— 85 ns initial access
— 52 MHz with zero wait states, 17ns clock-to-data output
synchronous-burst read mode
— 25 ns asynchronous-page read mode
— 4-, 8-, 16-, and continuous-word burst mode
— Buffered Enhanced Factory Programming (BEFP) at 5 μs/
byte (Typ)
— 1.8 V buffered programming at 7 μs/byte (Typ)
Architecture
— Multi-Level Cell Technology: Highest Density at Lowest
Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or bottom
configuration
— 128-KByte main blocks
Vo lt age and Power
—V
CC (core) voltage: 1.7 V – 2.0 V
—V
CCQ (I/O) voltage: 1.7 V – 3.6 V
— Standby current: 20μA (Typ) for 64-Mbit
— 4-Word synchronous read current:
13 mA (Typ) at 40 MHz
Quality and Reliability
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ VIII process technology
Security
— One-Time Programmable Registers:
• 64 unique factory device identifier bits
• 2112 user-programmable OTP bits
— Selectable OTP Space in Main Array:
• Four pre-defined 128-KByte blocks (top or bottom
configuration)
• Up to Full Array OTP Lockout
— Absolute write protection: VPP = VSS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Software
—20 μs (Typ) program suspend
—20 μs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Command Set
compatible
— Common Flash Interface capable
Density and Packaging
— 56- Lead TSOP pack age (64, 128, 256,
512- Mbit)
— 64- Ball Numonyx™ Easy BGA package (64,
128, 256, 512- Mbit)
— Numonyx™ QUAD+ SCSP (64 , 128, 256,
512- Mbit)
— 16-bit wide data bus
Datasheet August 2008
2306666-12
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE , TO ANY INT ELLEC TUA L PROPERTY RIGHTS IS GRAN TED BY THIS DOC UM ENT. EXCEPT AS PROVIDED IN NUM ONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHA TSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATI NG TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility a ppl ica tio ns.
Numo nyx B.V. may make changes to specific ations and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sal es offic e o r your distributor to o btain the latest specificat ions and be fore placing yo ur product order.
Copies of documents which have an o rder number and are ref erenced in this document, or other Num o nyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numo nyx, the Numonyx logo, and StrataF lash are trademarks or regis t ered trademarks of Numonyx B. V. or its subsidiarie s in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009, Numonyx, B.V., All R ights Reserved.
August 2008 Datasheet
306666-12 3
P30
Contents
1.0 Functional Description...............................................................................................5
1.1 Introduction .......................................................................................................5
1.2 Overview ...........................................................................................................5
1.3 Virtual Chip Enable Description..............................................................................6
1.4 Memor y Ma ps ..................... ............... ....................... ............... ....................... ....6
2.0 Package Information .................................................................................................9
2.1 56-Le ad TSO P..... ....................... ................ ...................... ................ ...................9
2.2 64-Ba ll Easy BGA P ack age.... ............... ............... ....................... ............... .......... 10
2.3 QUAD+ SC SP Packa g es............... ....................... ............... ....................... .......... 12
3.0 Ballouts................................................................................................................... 15
4.0 Signals .................................................................................................................... 18
4.1 Dual-Di e C on figurat ions ..................................... ............... ....................... .......... 20
5.0 Bus Operations........................................................................................................21
5.1 Reads..............................................................................................................21
5.2 Writes..............................................................................................................21
5.3 Output Disable.................................................................................................. 21
5.4 Standby...........................................................................................................22
5.5 Reset...............................................................................................................22
6.0 Command Set..........................................................................................................23
6.1 Device Command Codes.....................................................................................23
6.2 Device Command Bus Cycles .............................................................................. 24
7.0 Read Operation........................................................................................................26
7.1 Asynchro no us Pag e-Mod e R ea d............ ....................... ....................... ............... .. 26
7.2 Synchronous Burst-Mode Read............................................................................26
7.3 Read Device Identifier........................................................................................27
7.4 Read CFI.......................................................................................................... 27
8.0 Program Operation..................................................................................................28
8.1 Word Pr ogra mming .................... ....................... ............... ....................... .......... 28
8.2 Facto ry Word Prog ramming ................. ............... ....................... ....................... ..29
8.3 Buffere d Progr a mming ................ ....................... ............... ................ .................29
8.4 Buffere d Enhanced Factory Prog ramming............................. ................ ............... .. 30
8.4.1 BEFP Requirements an d Consid erations..... ....................... ............... .......... 30
8.4.2 BEFP Setup Pha se ........... ....................... ............... ....................... .......... 31
8.4.3 BEFP Progra m/Ve r ify Pha se ...... ....................... ............... ............... .......... 31
8.4.4 BEFP Exit Phase .............. ................ ............... ....................... ............... .. 32
8.5 Progra m Susp end................ ............... ....................... ............... ....................... .. 32
8.6 Progra m Resume. ........ ....................... ............... ....................... ............... ..........32
8.7 Progra m Prot ection..................................... ............... ....................... ............... .. 33
9.0 Erase Operations .....................................................................................................34
9.1 Block Er ase ........ ................ ....................... ............... ....................... ............... ..34
9.2 Erase Susp end........................... ....................... ............... ....................... .......... 34
9.3 Erase R esume..... ....................... ................ ...................... ................ ................. 35
9.4 Erase P rotection.......... ....................... ....................... ............... ....................... ..35
10.0 Security Mode s........................................................................................................36
10.1 Block Locking...... ................ ............... ....................... ............... ....................... .. 36
10.1.1 Lock Block.............................................................................................36
10.1.2 Unlock Block.......................................................................................... 36
P30
Datasheet August 2008
4306666-12
10.1.3 Lock-Down Block ....................................................................................36
10.1.4 Block Lock Sta tus ...................... ....................... ............... .......................37
10.1.5 Block Lock ing During Susp end............. ............... ....................... ...............37
10.2 Select able O ne-Time Pr ogra mma ble Blocks ............. ....................... ............... ........38
11.0 Registers .................................................................................................................39
11.1 Read St atus Regist er............................. ....................... ............... .......................39
11.1.1 C le ar St atus Re gis ter .. ............... ....................... ............... .......................40
11.2 Read Configur a tion R egiste r........... ....................... ............... ....................... ........40
11.2.1 Read Mode.............................................................................................41
11.2.2 Latency Count........................................................................................41
11.2.3 W AI T P olarit y............................ ............... ....................... .......................43
11.2.4 Da ta Hold .. ................ ....................... ............... ....................... ...............44
11.2.5 W AI T De lay ....................... ................ ...................... ................ ...............44
11.2.6 Burst Seque n ce ................. ....................... ............... ....................... ........45
11.2.7 Clock Edge.............................................................................................45
11.2.8 Burst Wrap ............................... ............... ....................... ............... ........46
11.2.9 Burst Leng th...... ....................... ............... ....................... ............... ........46
11.2.10End of Word Line (E OWL) C on side ratio ns .................... ....................... ........46
11.3 One-Time-P r ogra mma b le (O TP ) Register s ............... ....................... ............... ........46
11.3.1 Reading the OTP registers........................................................................47
11.3.2 P ro gramming the OTP Regi ste rs........... ...................... ................ ...............48
11.3.3 L o cking the OTP Regi ste rs... ........ ....................... ............... .......................48
12.0 Power and Reset Specifications ...............................................................................49
12.1 Power-Up and Power-Do wn............ ....................... ............... ....................... ........49
12.2 Reset Spe cif ica tions ............... ....................... ...................... ................ ...............49
12.3 Power Sup ply Decoupli ng........ ....................... ............... ....................... ...............50
13.0 Maximum Ratings and Operating Conditions ............................................................51
13.1 Absolute Maximum Ratings .................................................................................51
13.2 Operating Conditions.............. ............... ....................... ............... .......................51
14.0 Electrical Specifications ...........................................................................................52
14.1 DC Current Characteristics..................................................................................52
14.2 DC Voltage Characteristics ..................................................................................53
15.0 AC Characteristics....................................................................................................54
15.1 AC Test Condit io ns................. ....................... ...................... ................ ...............54
15.2 Capacitance ......................................................................................................55
15.3 AC Read Specif ica tions ........... ............... ....................... ............... .......................55
15.4 AC Write Specificati on s.................. ....................... ............... ....................... ........62
16.0 Program and Erase Characteristics...........................................................................66
17.0 Ordering Information...............................................................................................67
17.1 Discrete Pr oduct s.................................. ............... ....................... ............... ........67
17.2 SCSP Products.............................. ................ ...................... ................ ...............68
A Supplemental Reference Information.......................................................................69
B Conventions - Additional Information ......................................................................94
C Revision History.......................................................................................................96
August 2008 Datasheet
Order Number: 306666-12 5
P30
1.0 Functional Description
1.1 Introduction
This doc um ent prov ide s in form a tion about the Num o nyx™ St rata Fla sh® Embedded
Memory (P30) product and describes its features, operation, and specifications.
The Numonyx™ StrataFlash® E mbedde d Memo ry ( P30 ) p rodu ct is the l ates t ge ner a tion
of Numonyx™ StrataFlash® memory devices. Offered in 64-Mbit up through 512-Mbit
densiti es, the P30 d evice brings relia bl e, two- b it-p er-cell storag e te ch no logy to the
embedded flash market segment. Benefits include more density in less space, high-
speed interface, lowest cost-per-bit NOR device, and support for code and data
storage. Features include high-performance synch ronous-burst read mode, fast
asynchronous access times, low power, flexible security options, and three industry
standard package choices. The P30 product family is manufactured using Intel* 130 nm
ETOX™ VIII process techn ology.
The P 3 0 pr o duc t famil y i s al s o plan n ed on th e Intel* 65nm proce ss lithography. 65nm
AC timing changes are noted in this datasheet, and should be taken into account for all
new designs.
1.2 Overview
This sectio n pro vid es an overvie w of the features and cap abilities of th e P30 .
The P30 family p r ovide s density upgrade s from 64-Mbit thro ugh 512-Mb it. This family
of de v i ces pr o v ides hi gh per f orm an c e at low voltag e on a 16 - bit da ta bu s . Indi vi dual ly
erasable memory blocks are sized for optimum code and data storage.
Upon in itia l powe r up or retu rn from reset , the device de fa ult s to asynchr on o us pa g e-
mode read. Configuring the Read Configuration Register enables synchronous burst-
mo de re ad s . In s yn chron o u s b u rst m o de, outp u t data is sy n c h r o n i zed wi th a user-
supplied clock signa l. A WAIT signal provides an easy CPU-to-flash memory
synchronization.
In add itio n to the en h a n c ed ar c h it ec tur e and in terfa c e, the device incor pora tes
technology that enables fast factory progra m and erase operations. Designed for low-
voltage sy ste ms, the
P30 supports read operations with VCC at 1.8 V, and erase and program operations with
VPP at 1.8 V or 9 .0 V. Buffered Enhanced Factory Programming (BEFP) provides the
fastest flash arr ay programming performance with VPP at 9.0 V, which increases factory
throughput. With VPP at 1.8 V, VCC and VPP can be tied together for a simple, ultra low
power design. In addition to voltage flexibility, a dedicated VPP connection provides
complete data protection when VPP ≤ VPPLK.
A Command User Interface (CUI) is the interface between the system processor and all
internal operations of the device. An internal Write State Machine (WSM) automatically
execut es th e alg o r ith m s an d tim in g s ne c ess ary fo r block eras e and pr o g ram. A Status
R egister indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes progr am and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Susp en d
allows s ystem software to pause programming to read other locations. Data is
p r o g ramm ed in wo r d in crem en ts (16 bi ts).
P30
Datasheet August 2008
6306666-12
The P30 protection register allows unique flash device identification that can be used to
increase system security. The individual Block Lock feature provides zero-latency block
loc kin g an d u n lock in g. In add i tio n , th e P 3 0 device also has four pre-defined spaces in
the main array that can be configured as One-Time Programmable (OTP).
1.3 Virtual Chip Enable Description
The P3 0 512Mbit devices emplo y a Virtua l Ch ip Enabl e which co m b ines tw o 256 -Mb it
die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA and
TSOP packages. (Refer to Figure 9 on page 21 and Figure 10 on page 21). Address A24
(Quad+ package) or A25 (Easy BGA and TS OP packages) is then used to select
betw een the die pai r wi th F1 - C E # / CE # as s erted depen ding upon th e pac kage opt i o n
used. When chip enable is asserted and QUAD+ A24 (Easy BGA/TSOP A25) is low (VIL),
Th e lo wer parameter die is se lected ; wh en ch ip en a ble i s ass erted an d QUA D + A24
(Easy BGA/TSOP A25) is hig h (VIH), the u pp er parameter die is selected . Ref er to
Table 1 and Table 2 for add i tional detail s .
Tab le 1: Virtual Chip Enable Truth Tab le for 512 Mb (QUAD+ Package)
Die Selected F1-CE# A24
Lower Param Die L L
Upper Param Die L H
Table 2: Virtual Chip Enable Truth Table for 512 Mb (Easy BGA & TSOP Packages)
Die Selected CE# A25
Lower Param Die L L
Upper Param Die L H
August 2008 Datasheet
Order Number: 306666-12 7
P30
1.4 Memory Maps
Table 3 through Table 5 show the P30 memory maps. The memory array is divided into
multiple 8-Mbit Programming Regions (see Sect ion 8.0, “P ro gram Operation” on
page 29).
Table 3: Discrete Top Parameter Memory Maps (all packages)
Size
(KB) Blk 64-Mbit Size
(KB) Blk 128-Mbit
One
Programming
Region
32 66 3FC000 - 3FFFFF
One
Programming
Region
32 130 7FC000 - 7FFFFF
...
...
...
...
...
...
32 63 3F0000 - 3F3FFF 32 127 7F0000 - 7F3FFF
128 62 3E0000 - 3EFFFF 128 126 7E0000 - 7EFFFF
...
...
...
...
...
...
128 56 380000 - 38FFFF 128 120 780000 - 78FFFF
Seven
Programming
Regions
128 55 370000 - 37FFFF
Fifteen
Programming
Regions
128 119 770000 - 77FFFF
128 54 360000 - 36FFFF 128 118 760000 - 76FFFF
...
...
...
...
...
...
128 1 010000 - 01FFFF 128 1 010000 - 01FFFF
128 0 000000 - 00FFFF 128 0 000000 - 00FFFF
Size
(KB) Blk 256-Mbit
One
Programming
Region
32 258 FFC000 - FFFFFF
...
...
...
32 255 FF0000 - FF3FFF
128 254 FE0000 - FEFFFF
...
...
...
128 248 F80000 - F8FFFF
Thirty-One
Programming
Regions
128 247 F70000 - F7FFFF
128 246 F60000 - F6FFFF
...
...
...
128 1 010000 - 01FFFF
128 0 000000 - 00FFFF
P30
Datasheet August 2008
8306666-12
Note: The Dual- Die P30 memory maps are the same for both parameter options because the
devices employ virtual chip enable (Refer to Section 1.3). The parameter option only defines
the placement of bottom parameter die.
Table 4: Discrete Bottom Parameter Memory Maps (all packages)
Size
(KB) Blk 64-Mbit Size
(KB) Blk 128-Mbit
Seven
Programming
Regions
128 66 3F0000 - 3FFFFF
Fifteen
Programming
Regions
128 130 7F0000 - 7FFFFF
128 65 3E0000 - 3EFFFF 128 129 7E0000 - 7EFFFF
...
...
...
...
...
...
128 12 090000 - 09FFFF 128 12 090000 - 09FFFF
128 11 080000 - 08FFFF 128 11 080000 - 08FFFF
One
Programming
Region
128 10 070000 - 07FFFF
One
Programming
Region
128 10 070000 - 07FFFF
...
...
...
...
...
...
128 4 010000 - 01FFFF 128 4 010000 - 01FFFF
32 3 00C000 - 00FFFF 32 3 00C000 - 00FFFF
...
...
...
...
...
...
32 0 000000 - 003FFF 32 0 000000 - 003FFF
Size
(KB) Blk 256-Mbit
Thirty-One
Programming
Regions
128 258 FF0000 - FFFFFF
128 257 FE0000 - FEFFFF
...
...
...
128 12 090000 - 09FFFF
128 11 080000 - 08FFFF
One
Programming
Region
128 10 070000 - 07FFFF
...
...
...
128 4 010000 - 01FFFF
32 3 00C000 - 00FFFF
...
...
...
32 0 000000 - 003FFF
Block size is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K-
Words w here a Word is the size of the flash output bus (16 bits).
August 2008 Datasheet
Order Number: 306666-12 9
P30
Table 5: 512-Mbit Top and Bottom Parameter Memory Map (Easy BGA and QUAD+ SCSP)
512-Mbi t Fla sh (2 x25 6-M b it w/ 1CE)
Die Sta c k Co nfig Size
(KB) Blk Addr ess Range
32 517 1FFC000 - 1FFFFFF
...
...
...
256-Mbit 32 514 1FF0000 - 1FF3FFF
Top Parameter Die 128 513 1FE0000 - 1FEFFFF
...
...
...
128 259 1000000 - 100FFFF
128 258 FF0000 - FFFFFF
...
...
...
256-Mbit 128 4 010000 - 01FFFF
Bottom Parameter Die 32 3 00C000 - 00FFFF
...
...
...
32 0 000000 - 003FFF
Note: Refe r to t he appropr iate 256-Mbi t Memory Map (Table 3 or Table 4) for Pr ogr amming Re gion in forma tion; Bl ock size
is referenced in K-Bytes where a byte=8 bits. Block Address range is referenced in K-Words where a Word is the size of
the flash output bus (16 bits).
P30
Datasheet August 2008
10 306666-12
2.0 P ac kage Info rmat io n
2.1 56-Lead TSOP
Figure 1: TSOP Mechanical Specifications
A
0
L
Detail A
Y
D
C
Z
Pin 1
E
D1
b
Detail B
See Detail A
e
See Detail B
A1
Seating
Plane
A2
See Note 2
[231369-90]
See Notes 1 and 3
Table 6: TSOP Package Dimensions (Sheet 1 of 2)
Product Information Symbol Millimeters Inches Notes
Min Nom Max Min Nom Max
Package Height A - - 1.200 - - 0.047
Standoff A10.050 - - 0.002 - -
Package Bo dy Thickness A20.965 0.995 1.025 0.038 0.039 0.040
Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008
Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008
Package Body Length D118.200 18.400 18.600 0.717 0.724 0.732
Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559
Lead Pitch e - 0.500 - - 0.0197 -
Terminal Dimension D 19.800 20.00 20.200 0.780 0.787 0.795
August 2008 Datasheet
Order Number: 306666-12 11
P30
2.2 64-Ball Easy BGA Package
Lead Tip Length L 0.500 0.600 0.700 0.020 0.024 0.028
Lead Count N - 56 - - 56 -
Lead Tip Angle ý 0° 3° 5° 0° 3° 5°
Seating Plane Coplanarity Y - - 0.100 - - 0.004
Lead to Package Offset Z 0.150 0.250 0.350 0.006 0.010 0.014
Notes:
1. One dimple on package denotes Pin 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
4. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology
http://developer.Numonyx.com/design/flash/packtech.
Figure 2: Easy BGA Mechanical Specifications
Table 6: TSOP Package Dimensions (Sheet 2 of 2)
Product Information Symbol Millimeters Inches Notes
Min Nom Max Min Nom Max
E
Seating
Plane
S1
S2
e
Top View - Ball side down Bottom View - Ball Side Up
Y
A
A1
D
Ball A1
Corner
A2
Note: Drawing not to scale
A
B
C
D
E
F
G
H
8765432187654321
A
B
C
D
E
F
G
H
b
Ball A1
Corner
P30
Datasheet August 2008
12 306666-12
Table 7: Easy BGA Package Dimensions
Product Information Symbol Millimeters Inches Notes
Min Nom Max Min Nom Max
Package Height (64/128/256-Mbit) A - - 1.200 - - 0.0472
Package Height (512-Mbit) A - - 1.300 - - 0.0512
Ball Height A1 0.250 - - 0.0098 - -
Package Body Thickness (64/128/256-
Mbit) A2 - 0.780 - - 0.0307 -
Package Body Thickness (512-Mbit) A2 - 0.910 - - 0.0358 -
Ball (Lead) Width b 0.330 0.430 0.530 0.0130 0.0169 0.0209
Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976
Package Body Length E 12.900 13.000 13.100 0.5079 0.5118 0.5157
Pitch [e] - 1.000 - - 0.0394 -
Ball (Lead) Count N - 64 - - 64 -
Seating Plane Coplanarity Y - - 0.100 - - 0.0039
Corner to Ball A1 Distance Along D S1 1.400 1.500 1.600 0.0551 0.0591 0.0630
Corner to Ball A1 Distance Along E S2 2.900 3.000 3.100 0.1142 0.1181 0.1220
Notes:
1. Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology
http://developer.Numonyx.com/design/flash/packtech.
August 2008 Datasheet
Order Number: 306666-12 13
P30
2.3 QUAD+ SCSP Packages
Figure 3: 64/128-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x10x1.2 mm)
Millimeters Inches
Dimensions Symbol Min Nom Max Min Nom Max
Package Height A - - 1.200 - - 0.0472
Ball Height A
1
0.200 - - 0.0079 - -
Package Body Thickness A
2
- 0.860 - - 0.0339 -
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Width D 9.900 10.000 10.100 0.3898 0.3937 0.3976
Package Body Length E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e - 0.800 - - 0.0315 -
Ball (Lead) Count N - 88 - - 88 -
Seating Plane Cop lanarity Y - - 0.100 - - 0.0039
Corner to Ball A1 Distance Along E S
1
1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D S
2
0.500 0.600 0.700 0.0197 0.0236 0.0276
Top View - Ball
Down Bottom View - Ball Up
A
A
2
D
E
Y
A
1
Drawing not to scale.
S
2
S
1
A
C
B
E
D
G
F
J
H
K
L
M
e
12345678
b
A
C
B
E
D
G
F
J
H
K
L
M
12345678
A1 Index
Mark
P30
Datasheet August 2008
14 306666-12
Figure 4: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm)
Millimeters Inches
Dimensions Symbol Min Nom Max Min Nom Max
Package Height A - - 1.000 - - 0.0394
Ball Height A1 0.117 - - 0.0046 - -
Package Bo dy Th icknes s A2 - 0.740 - - 0.0291 -
Ball (Lead) Width b 0.300 0.350 0.400 0.0118 0.0138 0.0157
Package Body Length D 10.900 11.00 11.100 0.4291 0.4331 0.4370
Package Bo dy W idt h E 7.900 8.00 8.100 0.3110 0.3150 0.3189
Pitch e - 0.80 - - 0.0315 -
Ball (Lead) Count N - 88 - - 88 -
Seating Plane Coplanarity Y - - 0.100 - - 0.0039
Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472
Top View - Ball Down Bottom View - Ball Up
A
A2
D
E
Y
A1
Drawing not to scale.
S2
S1
A
C
B
E
D
G
F
J
H
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L
M
e
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b
A
C
B
E
D
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L
M
A1 Index
Mark
12 3456 78
Note: Dimensions A1, A2, and b are preliminary
August 2008 Datasheet
Order Number: 306666-12 15
P30
Figure 5: 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm)
Millimeters Inches
Dimensions Symbol Min Nom Max Min Nom Max
Package Height A - - 1.200 - - 0.0472
Ball Height A1 0.200 - - 0.0079 - -
Package Body Thickness A2 - 0.860 - - 0.0339 -
Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167
Package Body Length D 10.900 11.000 11.100 0.4291 0.4331 0.4370
Package Body Width E 7.900 8.000 8.100 0.3110 0.3150 0.3189
Pitch e - 0.800 - - 0.0315 -
Ball (Lead) Count N - 88 - - 88 -
Seating Plane Coplanarity Y - - 0.100 - - 0.0039
Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512
Corner to Ball A1 Distance Along D S2 1.000 1.100 1.200 0.0394 0.0433 0.0472
Top View - Ball Down Bottom View - Ball Up
A
A2
D
E
Y
A1
Drawing not to scale .
S2
S1
A
C
B
E
D
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L
M
e
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b
A
C
B
E
D
G
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H
K
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M
A1 Index
Mark
12 3456 78
P30
Datasheet August 2008
16 306666-12
3.0 Ballouts
Notes:
1. A1 is the least significant address bit.
2. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).
3. A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC).
4. A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).
5. Please refer to the latest specification update for sy nch ronous read operat ion with the TSOP package. The synchronous read
input signals (i.e. ADV# and CLK) should be tied off to support asynchronous reads. See Section 4.0, “Signals” on page 19.
Figure 6: 56-Lead TSOP Pinout (64/128/256/512- Mbit)
Intel StrataFlash®
Embedded Memory (P30)
56-Lead TSOP Pinout
14 mm x 20 mm
Top View
1
3
4
2
5
7
8
6
9
11
12
10
13
15
16
14
17
19
20
18
21
23
24
22
25
27
28
26
56
54
53
55
52
50
49
51
48
46
45
47
44
42
41
43
40
38
37
39
36
34
33
35
32
30
29
31
A14
A13
A12
A10
A9
A11
A23
A21
VSS
A22
VCC
WP#
A20
WE#
A19
A8
A7
A18
A6
A4
A3
A5
A2
A25
VSS
A24
WAIT
DQ15
DQ7
A17
DQ14
DQ13
DQ5
DQ6
DQ12
ADV#
CLK
DQ4
RST#
A16
DQ3
VPP
DQ10
VCCQ
DQ9
DQ2
DQ1
DQ0
VCC
DQ8
OE#
CE#
A1
VSS
A15
DQ11
August 2008 Datasheet
Order Number: 306666-12 17
P30
Notes:
1. A1 is the least significant address bit.
2. A23 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).
3. A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).
4. A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).
Figure 7: 64-Ball Easy BGA Ballout (64/128/256/512-Mbit)
18
234567
Easy BGA
Top View- Ball side down Easy BGA
Bottom View- Ball side up
1
8234
5
67
H
G
F
E
D
C
B
A
H
G
F
E
D
C
A
A2 VSS A9 A14CE# A19 RFUA25
RFU VSS VCC DQ13VSS DQ7 A24VSS
A3 A7 A10 A15A12 A20 A21WP#
A4 A5 A11 VCCQRST# A16 A17VCCQ
RFUDQ8 DQ1 DQ9 DQ4DQ3 DQ15CLK
RFU OE#DQ0 DQ10 DQ12DQ11 WAITADV#
WE#A23 RFU DQ2 DQ5VCCQ DQ14DQ6
A1 A6 A8 A13VPP A18 A22VCC
A23
A4A5A11VCCQ RST#A16A17 VCCQ
A1A6A8A13 VPPA18A22 VCC
A3A7A10A15 A12A20A21 WP#
RFU DQ8DQ1DQ9DQ4 DQ3DQ15 CLK
RFUOE# DQ0DQ10DQ12 DQ11WAIT ADV#
WE# RFUDQ2DQ5 VCCQDQ14 DQ6
A2VSSA9A14 CE#A19RFU A25
RFUVSSVCCDQ13 VSSDQ7A24 VSS
B
P30
Datasheet August 2008
18 306666-12
Notes:
1. A22 is valid for 128-Mbit densities and above; otherwise, it is a no connect (NC).
2. A23 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).
3. A24 is valid for 512-Mbit densities and above; otherwise, it is a no connect (NC).
4. F2-CE# a nd F2-OE# are no connect (NC) for all densities.
Figure 8: 88-Ball (80-Active Ball) QUAD+ SCSP Ballout
Pin 1
12345678
ADU DU Depop Depop Depop Depop DU DU A
BA4 A18 A19 VSS VCC VCC A21 A11 B
CA5 RFU A23 VSS RFU CLK A22 A12 C
DA3 A17 A24 VPP RFU RFU A9 A13 D
EA2 A7 RFU WP# ADV# A20 A10 A15 E
FA1 A6 RFU RST# WE# A8 A14 A16 F
GA0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT F2-CE# G
HRFU DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F2-OE# H
JRFU F1-OE# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ J
KF1-CE# RFU RFU RFU RFU VCC VCCQ RFU K
LVSS VSS VCCQ VCC VSS VSS VSS VSS L
MDU DU Depop Depop Depop Depop DU DU M
12345678
August 2008 Datasheet
Order Number: 306666-12 19
P30
4.0 Signals
This section has signal descriptions for the various P30 package s.
Table 8: TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)
Symbol Type Name and Function
A[MAX:1] Input ADDRESS INPUTS: Device address inputs. 64-Mbit: A[22:1]; 128-Mbit: A[23:1]; 256-Mbit:
A[24:1]; 512-Mbit: A[25:1]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the
dual-die 512-Mbit configuration is accomplished by setting A[25] high (VIH).
DQ[15:0] Input/
Output
DATA INPUT/OUTPUTS: Inputs data and commands du ring write cycles; outputs data du ring
memory, Status R e gister, P rotection R egi ster, and R ead Config urat ion Re gist er reads. Data balls fl oat
when the CE# or OE# are deasserted. Data is internally latched during writes.
ADV# Input
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the r ising edge of ADV#, or on the next valid CLK edge with ADV# l ow, whichever occurs fi rst.
In asynchronous mode, the address is latche d when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
CE# Input
FLA SH CH IP ENABL E: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: Chip enable must be driven high when device is not in u se.
CLK Input
CLOCK: Synchronizes the device with the system’ s bus frequency in synchronous-read mode. During
synchr onous read oper at ions, addr esses are latche d on the rising edge of AD V#, or on t he n ext va lid
CLK edge with ADV# low, which ever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OE# Input OUTPU T E NABLE: Active low input. OE# lo w en ables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
RST# Input RESET: Active low input. RST# resets internal autom ation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT Output
WAIT: Indicates data vali d in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR[10], WT) determines its polarity when asserted. WAIT’s active output is VOL or
VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronous page mode, and all write modes, WAIT is deasserted.
WE# Input W R ITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WP# Input WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism . Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
VPP Power/
Input
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when VPP ≤ VPPLK. Block erase and progra m at in v alid VPP volt ag es s hou ld
not be attem pted.
Set VPP = VPPL for in-sy stem progr am and er ase oper ati ons. To accommodate resistor or d iode drop s
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must r emain above VPPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
VCC Power Device Core Power S upply: Core (logic ) source voltage. Writes to the flash array a re inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ Power Output Power Supply: Output-driver source voltage.
VSS Power Ground: Connect to system ground. Do not float any VSS connection.
P30
Datasheet August 2008
20 306666-12
RFU — Reserved for Future Use: Reserved by Numonyx for future device functionality and enhancement.
These should be treated in the same way as a Do Not Use (DU) signal.
DU — Do Not Use : Do not connect to a ny other signal, or power supply; must be left floating.
NC — No Connect: No internal connection; can be driven or floated .
Table 8: TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)
Symbol Type Name and Function
Table 9: QUAD+ SCSP Signal Descriptions (Sheet 1 of 2)
Symbol Type Name and Function
A[MAX:0] Input ADD RES S INPUTS: Device address inputs. 64-Mbit: A[21:0]; 128-Mbit: A[22:0]; 256-Mbit:
A[23:0]; 512-Mbit: A[24:0]. Note: The virtual selection of the 256-Mbit “Top parameter” die in the
dual-die 512-Mbit configuration is accomplished by setting A[25] high (VIH).
DQ[15:0] Input/
Output
DATA INPUT/O U TPUT S: Inputs data and commands during write cycles; outputs data during
memory , Status Register, Protection Register, and Read Configuration Register reads. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
ADV# Input
ADDRES S VAL ID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
F1-CE# Input
FLASH CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifie rs are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
WARNING: Chip enable must be d riven high when device is not in use.
CLK Input
CLOCK: S ynchronizes the device with the system’ s bus frequency in synchronous-read mode. During
synchronous read oper ati ons, addres ses are latc hed on the risi ng edge of ADV#, or o n the next v alid
CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
F1-OE# Input OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
RST# Input RESET: Active low input. RST# res ets internal aut omation and inhibits write operations. This
provides data protectio n during power transitions. RST# high enable s normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT Output
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR [10], WT) dete rmines its polarity when asserted. WAIT’s active output is VOL or
VOH when CE# and OE# are VIL. WAIT is high-Z if CE# or OE# is VIH.
• In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
• In asynchronou s page mode, and all write modes, WAIT is deasserted.
WE# Input WRITE ENABLE: Ac tive low input. WE# controls writes to the device. Address and data are latched
on the rising edge of WE#.
WP# Input WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or pr ogrammed using software comma nds.
VPP Power/
lnput
Erase and Program Power: A valid voltage on this pin allows erasing or programming. Memory
contents cannot be alt ere d whe n V PP ≤ VPPLK. Block erase and program at invalid VPP voltages should
not be attempted.
Set V PP = VPPL for in-sy stem progr am and era se oper ation s. To a ccommodate resistor or diode drops
from the system supply, the VIH level of VPP can be as low as VPPL min. VPP must remain above VPPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
VPPH can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
August 2008 Datasheet
Order Number: 306666-12 21
P30
4.1 Dual-Die Configurations
Note: Amax = Vih selects the Top parameter Die; Amax = Vil selects the Bottom Parameter Die.
VCC Power Device Core Power S upply: Core (logic ) source voltage. Writes to the flash array a re inhibited
when VCC ≤ VLKO. Operations at invalid VCC voltages should not be attempted.
VCCQ Power Output Power Supply: Output-driver source voltage.
VSS Power Ground: Connect to system ground. Do not float any VSS connection.
RFU — Reserved for Future Use: Re ser ved by Num onyx fo r futur e devi ce func t ionali ty and enhance me nt.
These should be treated in the same way as a Do Not Use (DU) signal.
DU — Do N ot Use: Do not connect to any other signal, or power supply; must be left floating.
NC — No Connect: No int ernal connect ion; can be driven or floated.
Table 9: QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)
Symbol Type Name and Function
Figure 9: 512-Mbit Easy BGA and TSOP Top or Bottom Parameter Block Diagram
Top Param Die
(256-Mbit)
Bottom Param Die
(256-Mbit)
WP#
CLK
CE#
ADV#
OE#
WAIT
WE#
RST#
VCC
VPP
DQ[15:0]
A[MAX:1]
VCCQ
VSS
Easy BGA & TSOP 512-Mbit (Dual-Die) Top or Bottom Parameter
Configuration
Figure 10: 512-Mbit QUAD+ SCSP Top or Bottom Parameter Block Diagram
Top Param Die
(256-Mbit)
Bottom Param Die
(256-Mbit)
WP#
CLK
F1-CE#
ADV#
OE#
WAIT
WE#
RST#
VCC
VPP
DQ[15:0]
A[MAX:0]
VCCQ
VSS
QUAD+ 512-Mbit (Dual-Die) Top or Bottom Parameter
Configuration
P30
Datasheet August 2008
22 306666-12
5.0 Bus Operations
CE# low a n d RST# high ena ble dev ice r ea d operation s. The de vice interna lly de co de s
upper address inputs to determine the accessed block. ADV# low opens the internal
addres s latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
fir s t of ei th er th e r i s in g AD V# edg e or th e n ext vali d CLK ed ge w ith A D V# l ow (WE #
and RST# mus t be V IH; CE# must be VIL).
Bus cycles to/from the P30 device conform to standard microprocessor bus operations.
Table 10 summarizes the bus operations and the logic levels that must be applied to
the device control signal inputs.
5.1 Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
me m ory data is dr i ven o n to the I/O bus .
5.2 Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 12, “Command Bus Cycles” on page 26
shows the bus cycle sequence for each of the supported device commands, while
Tabl e 11, “ C o m ma nd Codes and Definiti o ns” o n page 24 describes each command. See
Section 15.0, “AC Charact eristics” on page 55 for signal-timing details.
Note: W rite operations with invalid VCC and/ or VPP voltages can produce spurious results and should
not be attempted.
5.3 Output Disable
When OE# is deasserted, device outputs DQ[15: 0] are disable d and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
Table 10: Bus Operations Summary
Bus Op er a tio n RST# CLK ADV# CE# OE# W E# WAIT DQ[15:0
]Notes
Read Asynchronous VIH XL L L H
Deasserted Output
Synchronous VIH Running L L L H Driven Output
Write VIH X L L H L High-Z Input 1
Output Disable VIH X X L H H High-Z High-Z 2
Standby VIH X X H X X High-Z High-Z 2
Reset VIL X X X X X High-Z High-Z 2,3
Notes:
1. R efer to the Table 12, “Command Bus Cycles” on page 26 for valid DQ[15:0] during a write
operation.
2. X = Don’t Care (H or L).
3. RST# must be at VSS ± 0 .2 V to meet the maximum specified power-down current.
August 2008 Datasheet
Order Number: 306666-12 23
P30
5.4 Standby
When C E# is dea sse rted the device is deselected and plac ed in sta ndb y, substa ntia lly
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent o f th e lev el placed on OE#. Sta n dby curr ent, ICCS, is the averag e c ur r en t
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average c ur r en t is measur ed ove r th e same tim e inter val 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
5.5 Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system proc essor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory r ese t, imp r ope r CPU init ia liza tio n may occur beca us e the flas h mem or y may
be providi ng status inform a tion rather tha n array data. Flash memo ry devices fro m
Numonyx allow proper CPU initialization following a system reset through the use of the
RST # i n pu t. RST# should be con tr o l le d by th e s am e low- tr u e r e set s i gnal th at re sets
the system CPU.
After initial powe r-up or rese t, the device de fa ult s to asynchronou s Read Array mode ,
and the Status Register is set to 0x80. Asserting RST# de-energizes all internal
circuits, and places the outpu t drivers in High-Z. When RST# is asse rte d, the device
shuts down the operation in progress, a process which takes a minimum amount of
time to complete. When RST# has been deasserted, the device is reset to
asynchronous Read Array state.
Note: If RST# is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a progr am) or block ( for an er ase) are no long er
valid, because the dat a may have been only pa rtia lly wr it ten or erased .
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restor e d. Se e Sect ion 15.0, “AC Characteristics” on page 55 for details
abo u t s i gnal- ti m in g.
P30
Datasheet August 2008
24 306666-12
6.0 Command Set
6.1 De vice Com ma nd Codes
Th e sys t em C PU prov ides co n tro l o f all in- s ystem re a d, wr it e, an d eras e o pe ratio ns of
the device via the system bus. The on-chip Write State Machine (WSM) m anag es all
bloc k-erase and wor d- pr o gram al go r i thms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
Table 11: Command Codes and Definitions (Sheet 1 of 2)
Mode Code D evice Mode Description
Read
0x FF Read Array Places the device in Read Array mode. Array data is output on DQ[15:0].
0x70 Read Status
Register
Places the devi ce i n R e ad Stat us R eg ist er m ode . The d ev ice ent ers th is mo de
after a program or erase command is issued. Status Register data is output
on DQ[7:0].
0x90 Read Device ID
or Configuration
Register
Places device in Read Device I dentifier mode. Sub sequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or Protection Register data on DQ[15:0].
0x98 Read CFI Places the dev ice i n R ead CF I mode. S ubse quent re ad s output C ommon F las h
Interface information on DQ[7:0].
0x50 Clear Statu s
Register The WSM can only set Status Register error bits. The Clear Status Register
command is used to clear the SR error bits.
Write 0x40 Word Program
Setup
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. C E# or ADV# must be toggled to
update the Status Register Data for synchronous Non-array reads. The Read
Array command must be issued to read ar ray data after programming has
finished.
Write
0x10 Alternat e Word
Program Setup Equivalent to the Word Program Setup command, 0x40.
0xE8 Buffered Program This com mand lo ads a variable number of words up to the buffer size of 32
words onto the program buffer.
0xD0 Buffered Program
Confirm
The confirm command is Issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, wr iting the data from the buffer to the flash memor y array.
0x80 BEFP Setup
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory
Program mode (BEFP). The CUI the n waits for the BEFP Confir m command,
0xD0, that initiates the BEFP algorithm. All other commands are ignored
when BEFP mode begins.
0xD0 BEFP Confirm If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
August 2008 Datasheet
Order Number: 306666-12 25
P30
6.2 Device Command Bus Cycles
Device o peration s are initia te d by writing spe cifi c device co mm a nds to the Comma n d
User Interface (CUI). Several commands are used to modify array data including Word
Program and Block Erase commands. Writing either command to the CUI initiates a
sequence of internally-timed functions that culminate in the completion of the
re qu e sted task. Howe v er, th e operation c an be aborted by ei ther asserting RST # or by
issuing an appropriate suspend command.
Erase
0x20 Block Erase Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase
op er ation. Th e W SM pe r f orm s the e r a s e al gorithm o n th e bl oc k ad dr es s e d b y
the Erase Confirm command. If the next command is not the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and
places the device in read status register mode.
0xD0 Block Erase Confirm
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
era se ope r ations , the de vice r espon ds on ly to R ead Stat us R egis ter and Era se
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
Status Register Data for synchronous Non-array reads
Suspend 0xB0 Program or Erase
Suspend
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR[2] (program
suspended) or SR[6] (er ase susp ended), along wi th SR[7] (ready). The W ri te
State Machine remains in the suspend mode regardless of control signal
states (except for RST# asserted).
0xD0 Suspend Resume This command issued t o a ny d evice address r esumes the suspended p rogra m
or block-erase operation.
Blo ck L ocki ng /
Unlocking
0x60 Lock Block Setup
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes. If the next command is not Block Lock (0x01), Block
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register bits
SR[4] and SR[5], indicating a command sequence error.
0x01 Lock Block If the previous command was Block Lock Setup (0x60), the addressed block
is lo cked .
0xD0 Unlock Block If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
0x2F Lock-Down Block If the previous command was Block Lock Setup (0x60), the addressed block
is lo cked down.
Protection 0xC0 Program Protection
Register Setup
First cycle of a 2-cycle command; prepares the device for a Protection
Register or Lock Register program operation. The second cycle latches the
register address and data, and starts the programming algorithm
Configuration
0x60 Read Configuration
Register Setup
First cycle of a 2-cycle command; prepares the CUI for device read
configurat ion. If the Set Read Configuration Register comm and (0x03) is not
the next command, the CUI sets Status Register bits SR[4] and SR[5],
indicating a command sequence error.
0x03 Read Configuration
Register
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[15:0] to the Read Configuration
Register. Following a Configure Read Configuration Re gister command,
subsequent read operations access array data.
Table 11: Command Codes and Definitions (Sheet 2 of 2)
Mode Code Device Mode Description
P30
Datasheet August 2008
26 306666-12
Table 12: Command Bus Cycles
Mode Command Bus
Cycles
First Bus Cycle Second Bus Cycle
Oper Addr(1) Data(2) Oper Addr(1) Data(2)
Read
Read Array 1 Write DnA 0xFF - - -
Read Device Id entifier ≥ 2 Write Dn A 0x 90 Read DBA + IA ID
Read CFI ≥ 2WriteDnA0x98Read
DBA + CFI-
ACFI-D
Read Status Register 2 Write DnA 0x70 Read DnA SRD
Clear Status Register 1 Write DnA 0x50 - - -
Program
Word Program 2 Write WA 0x40/
0x10 Write WA WD
Buffered Pro gram(3) > 2 Write WA 0xE8 Write WA N - 1
Buffered En hance d Factory
Program (BEFP)(4) > 2 Write WA 0x80 Write WA 0xD0
Erase Block Erase 2 Write BA 0x20 Write BA 0xD0
Suspend Program/Erase Suspend 1 Write DnA 0xB0 - - -
Program/Erase Resume 1WriteDnA0xD0- - -
Block
Locking/
Unlocking
Lock Block 2 Write BA 0x60 Write BA 0x01
Unlock Block 2 Write BA 0x60 Write BA 0xD0
Lock-down Block 2 Write BA 0x60 Write BA 0x2F
OTP Reg ist er Program OTP Register 2 Write PRA 0xC0 Write OTP-RA OTP-D
Program Lock Register 2 Write LRA 0xC0 Write LRA LRD
Configuration Program Read Configuration
Register 2 Write RCD 0x60 Write RCD 0x03
Notes:
1. First command cycle address should be the same as the operation’s target address.
DBA = Device Ba se Address (NOTE: needed for dual-die 512 Mb device)
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Rea d CFI address offset.
WA = Word address of memo ry location to be written.
BA = Address wi thin the block.
OTP-RA = Protection Register address.
LRA = Lock Register address.
RCD = Read Conf iguration Register data on QUAD+ A [15:0] o r EASY BGA A[16:1].
2. ID = Identifier data.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the wr ite buffer.
OTP-D = Protection Register data.
LRD = Lock Register data.
3 . The sec o nd cy cle of t he Buf fered Prog r am C om ma nd i s the word cou nt of th e d ata to be l oad ed int o th e wr i te buf fe r. Thi s
is followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming
operation.
4. The confirm command (0xD0) is followed by the buffer data.
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P30
7.0 Read Operation
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a
reset. The Read Configuration Re gister must be configured to enable synchronous burst
reads of the flash memory array (see Section 11.2, “Read Configuration Regi ster” on
page 41).
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read CFI. Upon power-up, or after a reset, the device defaults to Read Array. To
change the read state, the appropriate read command must be written to the device
(see S ection 6.0, “Command Set” on page 24).
7.1 Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read
mo de and th e devi c e is se t to Read Array. Howev er, to pe rf orm arra y read s afte r an y
other d evice operation (e. g. write oper at ion) , the Read Array command must be issued
in order to read from the flash memory array.
Note: Asynchronous page-mode reads can only be performed when Read Configur ati on R e gister bit
RCR[15] is set ( see Section 11.2, “Read Config uration Register” o n page 41).
To perform an asynchronous page-mode read, an addre ss is driven onto the Address
bus, an d C E # and A D V# ar e as se r ted . WE # an d R S T# mus t alr eady h av e been
deas serted. WAI T i s deas s er ted du r in g async h r o no u s pa ge mo de. ADV# c an be dr iv en
high to latch the ad dre ss, o r it mu st be held low th roug ho ut t he r ead cycle. CL K is no t
used for asynchronous page-mode reads, and is ignored. If only asynchronous reads
are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated
and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial
access time tAVQV dela y. (see Section 15.0, “A C Char acteristics” on page 55).
In asynchronous page mode, four data words are “sensed” simultaneously from the flash
mem o r y array and loaded i n to an i n ter n al page bu ffer. The buffer word corresponding
to the initial address on the Address bus is driven onto DQ[15:0] after the initial access
delay. The lowest two address bits determine which word of the 4-word page is output
fro m th e da ta bu ffe r at an y give n ti m e.
7.2 Synchronous Burst-Mode Read
To perform a synchronous burst-read, an initial address is driven onto the Address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can
remain asserted throughout the burst access, in which case the address is latched on
the next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay (see Section
11.2.2, “Lat ency Count” on page 42 ). Subsequent data is output on valid CLK edges
following a mi nimum delay. However, for a synchronous non- arra y read, the same word
of data will be output on successive clock edges until the burst length requirements are
satisfied . Refer to the followin g waveforms for mo re de ta iled infor matio n :
•Figure 24, “Synchronous Single-Word Array or Non-array Re ad Timing” on page 61
•Figure 25, “Continuous Burst Read, Showing An Output Delay Timing” on page 62
•Figure 26, “Synchronous Burst-Mode Four-Word Read Timing” on page 62
P30
Datasheet August 2008
28 306666-12
7.3 Read Device Identifier
The Read Device Identifier command instructs the device to output manufacturer code,
device id entifier code, block-lock status, protection register data, or configuration
re gi s ter dat a.
7.4 Read CFI
The R ead CFI command instructs the device to output Common Flash Interface (CFI)
data w hen r ead . See Section 6.0, “Command Set” on page 24 for details on issuing the
Read CFI command. Appendix A, “Common Flash Interface Tables” on page 70 shows
CFI information and address offsets within the CFI database.
Table 13: Device Identifier Information
Item Address(1) Data
Manufacturer Code 0x00 0089h
Device ID Code 0x01 ID
Block Lock Configuration:
BBA + 0x02
Lock Bit:
• Block Is Unlocked DQ0 = 0b0
• Block Is Locked DQ0 = 0b1
• B lock Is not Locked-Down DQ1 = 0b0
• B lock Is Locked-Down DQ1 = 0b1
Read Configuration Register 0x05 RCR Contents
Lock Register 0 0x80 PR-LK0
64-bit Factory-Programmed Protection Register 0x81–0x84 Factory Protection Register Data
64-bit User-Programmable Protection Register 0x85–0x88 User Protection Register Data
Lock Register 1 0x89 PR-LK1
128-bit User-Programmable Protection Registers 0x8A–0x109 Protection Register Data
Notes:
1. BBA = Block Base Address.
Table 14: Device ID codes
ID Code Type Device Density
Device Identifier Codes
–T
(Top Para meter) –B
(Bottom Parameter)
Device Code
64-Mbit 8817 881A
128-Mbit 8818 881B
256-Mbit 8919 891C
Note: The 512-Mbit devices do not have a Device ID associated with them. Each die within the stack can be identified by
either of the 256-Mbit Device ID codes depending on its parameter option.
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8.0 Program Operation
The device supports three programming methods: Word Programmi ng (40h/10h),
Buffered Programming (E8h, D0h), and Buffered Enhanced F actory Programming (80h,
D0h). See
Section 5.0, “B us Operat io ns” on page 22 f or details on the various programming
commands issued to the device. The following sections describe device programming in
detail.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be deasserted and the block must be unlocked before
attem ptin g to pr o gra m th e bl o c k. A ttem pting to prog ra m a l o c ke d b l o c k c au s es a
progra m er ror ( S R [ 4] and SR [1 ] se t) a n d ter m i n a ti o n o f th e op era tion. See Section
10.0, “Security Modes” on page 37 for details on locking and unlocking blocks.
The Product Name is segmented into multiple 8-Mbit Programming Regions. See
Se ct ion 1.4 , “Me mo ry M aps ” on pa ge 7 for complete addressing. Execute in Place (XIP)
applications must partition the memory such that code and data are in separate
programming regions. XIP is executing code directly from flash memory. Each
Programming Region should contain only code or data but not both. The following
terms define the difference between code and data. System designs must use these
definitions when partitioning their code and data for the P30 dev ice.
• Code: Execution code ra n out of the flash device on a continuous basis in the
system.
• Dat a: Info rmation per i o dic ally pr og ra m m e d i n to th e flash devic e an d re ad ba c k
(e.g. execution cod e shadowed an d executed in RA M, pictur es, log file s , etc.).
8.1 Word Programming
Wor d pro gramming ope ration s are initia te d b y writing the Word Program Set up
com m a n d to th e devic e (s ee Section 5.0, “Bus Operat ions” on page 22). This is
followed by a second write to the device with the address and data to be programmed.
The device outp u ts Stat us Regist er data when r ea d. See Figure 34, “Word Progra m
Flowchart” on pa ge 8 0. VPP must be above VPPLK, and wit hin the sp ecifie d VPPL min/
max values.
Du r i ng programmi ng, the W r ite State Mach in e (WSM) executes a sequ ence of
internall y-tim e d ev ents that pr og ram the des ire d data bits at th e addresse d location,
and verifies that the bits are sufficiently programmed. Programming the flash memory
array changes “ones” to “zeros”. Me mory array bits that are zeros can be changed to
ones only by erasing the block (see Section 9.0, “Erase Operations” on page 35).
The Status Register can be examined for programming progress and errors by reading
at any address. The device remains in the R ead Status Register state until another
comma nd is written to the device.
Status Regist er bit SR[7] indi cates the programming status while the sequ ence
executes. Commands that can be issued to the device during programming are
Program Suspend, Read Status Register, Read Device Identifier, Read CFI, and Read
Array (this returns unknown data).
When programming has finished, Status Register bit SR[4] (when set) indicates a
programming failure. If SR[3] is set, the WSM could not perform the word
programming oper ation because VPP was outside of its acceptable limits. If SR[1] is set,
the wo r d programming o pera tion attem pted to prog ram a loc ked block, c au s in g th e
operati o n to ab o r t.
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Datasheet August 2008
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Before issuing a new command, the Status Register contents should be examine d and
then cleared using the Clear Status R egister command. Any valid command can follow ,
when word programming has completed.
8.2 F ac to ry Wo rd Prog ramm ing
Factory word programming is similar to word programming in that it uses the same
commands and programming algorithms. However, factory word programming
enhances the programming performance with VPP = VPPH. This can enable faster
programming times during OEM manufacturing processes. Factory word programming
is not intended for extended use. See Section 13.2, “Operating Conditions” on page 52
for limitations when VPP = VPPH.
Note: When V PP = VPPL, the device draws programming current from the VCC supply. If VPP is driven
by a logic signal, VPPL must remain above VPPL MIN to program the device. When VPP = VPPH,
the device draws programming current from the VPP supply. Figure 1 1, “Exa m pl e VP P Supply
Connections” on page 34 shows examples of device power supply configurations.
8.3 Buffered Programming
The device features a 32-word buffer to enable optimum programm ing performance.
For Bu ffer ed Programm in g , data is fir st wr it ten to an on-ch ip wr ite buffer. Then th e
buff er data is pr o grammed int o th e fl as h mem or y ar ray in buf fer-siz e i n cremen ts . Th i s
can im p rove s ys t em pr o g ra mm in g perf o r m ance si gnifica n tly over no n -buff er ed
programming.
When the Buffered Programming Setup command is issued (see Se ction 6.0,
“Com mand Set” on page 24), Status Register info r ma ti on is updated and refl ects th e
availabilit y of the buffer. SR[7] in d ica tes buff er avail ability: if set, the buffer is
available ; if clea r ed , the buff er is n o t availabl e. To r et r y, issue the Bu ffer e d
Programming Setup command again, and re-check SR[7]. When SR[7] is set, the
buff er is read y for loading. (s ee Figure 36, “Buffer Program Flowchart” on page 8 2).
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. S ubsequent writes provide additional device addresses and
data. All data addre sses must lie withi n the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the st artin g ad dre ss at t he begi nni ng of a 32 -wo rd boun dary (A[ 4:0 ] = 0x0 0). C ro ssin g
a 32-w or d boun dar y du r i n g pr o gra m m ing wil l double the total prog rammin g ti m e.
Afte r the l ast data is wri tten to the buff er, th e Buffer ed Prog ramm ing Conf irm co mmand
must be i s sue d to th e orig i n al block address. The WSM begin s to pr ogram buf fer
contents to the flash memory array. If a command other than the Buffered
Programming Confirm command is written to the device, a command sequence error
occurs and Status Register bits SR[7,5,4] are set. If an error occurs whil e writing to the
array, the device stops programming, and Status Register bits SR[7,4] are set,
indica ti ng a program ming fa ilur e.
When Buffered Programming has completed, additional buffer writes can be initiated by
issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with VPP = VPPL or VPPH
(see Section 13.2, “Operating Conditions” on page 52 for lim it at io n s when o p erating
the device with VPP = V PPH).
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If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and Status Register bits SR[5,4] are set.
If Buffered programming is attempted while VPP is bel ow VPPLK, St atus R egis ter bits
SR[ 4 ,3] are set. If an y er r ors are detec ted that ha v e s et Statu s Register bi ts , th e
Status Register should be cleared using the Clear Status Register command.
8.4 Buffered Enhanced Factory Programming
Buffe red Enha nced Factory P ro graming (BE FP) sp eeds up Mult i-L eve l Cell (MLC) f lash
programming. The enhanced programming algorithm used in BEFP eliminates
traditiona l pro g ramm ing eleme n ts tha t d rive u p overh ea d in de vice pro grammer
systems.
BEF P c o n s is ts of th r ee ph ases : Setu p, Pr og ra m /Veri fy, a n d E x it (se e Figure 37, “BEFP
Flowchart” on pa ge 8 3). It uses a write buffer to spread MLC progra m performance
across 32 data words. Verification occurs in the sam e phase as programmin g to
accurat el y pr o gra m th e fla s h me m ory c ell to th e c o rr ect bit s ta te.
A single two-cycle command sequence programs the entire block of data. This
enha n cemen t elim inate s thr ee write cy cles per bu f f er : two co m m a n ds a n d th e wo rd
count for each set of 32 data words. Host programmer bus cycles fill the device’s write
buffer followe d by a status check. SR[0] indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increm ent s internal addr essing to auto matica lly sele ct the next 32-word array
boundary. This aspect of BEFP saves host progra mming equipm ent the address-b us
setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly . This eliminates
the external post-program verification and its associated overhead.
8.4.1 BEFP Requirements and Considerations
Note:
1. Wo rd buf fer bounda ri es in the arra y are determine d by A[4:0] (0x00 throug h 0x1F). The align ment start po int is A[ 4:0] =
0x00.
Table 15: BEFP Requirements
Parameter/Issue Requirement Notes
Case Temperature TC = 25 °C ± 5 °C
VCC Within operating range
VPP Driven to VPPH
Setup and Confirm Target block unlo cked before issuing the BEFP Setu p and Confirm commands
Programming The first-word address (WA0) of the block to be programmed must be held c onstant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired
Buffer Alignment WA0 must align with the start of an array buffer boundary 1
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Datasheet August 2008
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Note:
1. Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work
properly.
2. If the internal address counter increments beyond the block's maximum address, addressing wraps around to the
beginning of the block.
3. If the number of words is less than 32, remaining locatio ns must be filled with 0x FFF F.
8.4.2 BE F P Se tu p Phas e
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR[7] (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup.
A delay before checking SR[7] is required to allow the WSM enough time to perform all
of its setups and checks (Block-L ock status , VPP level, etc.). If an error is detected,
SR[4] is set and BEFP operation terminates. If the block was found to be locked, SR[1]
is also set. SR[3] is set if the error occurred due to an incorrect VPP level.
Note: Reading from the dev ice after the BEFP Setup and Confirm command sequence outputs
Sta tus Register data . Do not issue the Read Stat us Registe r comma n d ; it will be interp ret ed
as da ta to be loa ded into th e buffer.
8.4. 3 BEF P P r o g r am/Ve r if y Phase
After the BEFP Setup Phase has completed, the host programming system must check
S R[7, 0] to deter m in e th e avai labil ity of the write b u ffer fo r dat a s tr eam in g. S R [ 7 ]
cleared indi c ates the devi c e i s bus y and the BE FP program/verify phas e is activate d.
SR[ 0] in dicat es the write bu ffer is availabl e.
Two bas ic seque nces rep eat in thi s phase : loa ding of th e writ e buffe r, fo llowed by buffer
data pr o gra m m i n g to th e ar ray. For BEFP, th e cou n t valu e fo r bu ffer load i n g is alwa ys
the maximum buffer size of 32 words. During the buffer-loading sequence, data is
stored to sequential buffer locations starting at address 0x00. Programming of the
buffer contents to the flash memory array starts as soon as the bu ffer is full. If the
number of words is less than 32, the remaining buffer locations must be filled with 0xFFFF.
Caution: The buffer must be completely filled for programming to occur. Supplying an
address outside of the current block's range during a buffer-fill sequence
causes the algorithm to exit immediately. Any data previously loaded into the
buffer during the fill cycle is not programmed into the array.
Th e s tar tin g ad dr es s for data en tr y mus t be buffer s i ze aligne d , i f no t th e BE FP
algo rithm will be abor te d an d the pro gram fails a nd (SR[4]) flag will be set.
Data wor ds from the wr ite buf fer are direc t ed to sequ ential mem o ry lo cation s in the
flash memory array; progr amming continues f rom where the previous buffer sequence
en ded. The host pr o grammi n g s ys tem m u st po l l S R [ 0 ] to de ter m i n e wh en th e bu ff er
program sequence completes. SR[0] cleared indicates that all buffer data has been
transferred to the flash array; SR[0] set indicates that the buffer is not available yet for
the next fill cycle. The host system may check full status for errors at any time, but it is
Table 16: BEFP Considerations
Parameter/Issue Requirement Notes
Cycling For optimum performance, cycling must be limited below 100 erase cycles per block. 1
Programming blocks BEFP programs one block at a time; all buffer data must fall within a single bl ock 2
Suspend BEFP cannot be suspended
Programming the flash
memory array Programming to th e flash memory array c an occur only when the buffer is full. 3
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only nece ssary on a blo ck basis af te r BEFP exit . Aft er the buffe r fill cycle, no wr ite
cycles should be issued to the device until SR[0] = 0 and the device is ready for the
next buffer fill.
Note: Any spurio us writes are ig no red aft er a buff er fi ll oper at io n and wh en in te rn al p rogram is
proceeding.
The host progra mming syste m continues the BEFP algorithm by providing the next
group of data wo rds to be writt en to the buffer. Alter na tive ly, it can termina te this
ph ase by chan ging th e blo ck address to o n e o u tside of t h e c u r r en t bl o c k’s r ang e.
Th e Prog ram/Verify pha s e concludes when the program m er wr i tes to a dif ferent block
address; data supplied must be 0xFFF F. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
8.4.4 BE F P E xit Phase
When SR[7] is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. When exiting the BEFP algorithm with a block address change, the read
mode will not change. After BEFP exit, any v alid command can be issued to the device.
8.5 Program Suspend
Issui n g the Pr og ram Su s pend c omm an d wh i le pr o gram m i n g s u s p en ds th e
programming operation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program opera ti on can be suspended to perform reads only. Additionally, a
program operation that is running during an erase suspend can be suspended to
perform a read operation (see Figure 35, “Program Suspend/Resume Flowchart” on
page 81).
When a p rog ra m min g operation is exec utin g , iss uin g th e P r o gram Su spend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend
latency is specified in Sect ion 16.0, “Prog ram and Erase Characteristics” on page 6 7.
To read data from th e device, the Read Array command must be issued. Read A rray,
Read Status Registe r, Read Devi ce Identifie r, Rea d CFI, and Program Resume ar e vali d
commands during a progra m susp end.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in program suspend. If RST# is asserted, the device is reset.
8.6 Program Resume
The Resume com mand instructs the device to continue programmin g, and
automatically clears Sta tu s Register bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted (see Figure 35, “Program Suspend/
Resume Flowchart” on page 81).
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8.7 P rogram Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If
VPP is at or below VPPLK, programming operations halt and SR[3] is set indicating a VPP-
level err o r. Block lock reg isters are no t aff ect ed by the voltag e leve l on VPP; the y m ay
still be programmed and rea d , even if VPP is less than VPPLK.
Figure 11: Example VPP Supply Conne ctions
• Factory Programming with VPP = VPPH
• Complete write/Erase Protection when VPP ≤ VPPLK
VCC
VPP
VCC
VPP
• Low Voltage and Factory Programming
• Low-voltage Programming only
• Logic Control of Device Protection
VCC
VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable
VCC
VPP
≤ 10K Ω
VPP
VCC VCC
PROT #
VCC
VPP=VPPH
VCC
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9.0 Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an
erase co m mand sequ enc e is is su ed, and o n ly o n e blo ck is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
9.1 Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the address of the block to
be erased (see Section 6.0, “Command Set” on page 24). Next, the Block Erase Confirm command
is written to the address of the block to be erased. If the device is placed in standby (CE#
deasserted) during an erase operation, the device completes the erase operation before
entering standby.VPP must be above VPPLK and the block must be unlocked (see Fig ure 38, “Blo ck
Eras e Fl o w chart ” o n pa ge 84 ).
Duri ng a bloc k eras e, the Wri te St ate Ma c hin e (WSM) execu tes a s e qu enc e o f
internally-timed events that conditions, erases, and verifies all bits within the block.
Eras i n g th e flas h m em o ry array c h anges “z er o s ” to “ones ”. Me m ory ar ra y bi ts th at ar e
ones can be changed to zeros only by programming the block (see Section 8.0,
“Pr o gra m Ope rat i o n ” o n page 29).
The Statu s Regist er can be exa m ined for block er as e pr ogress and er rors by rea ding
any address. The device remains in the Read Status Register state until another
command is written. SR[0] indicates whether the addressed block is erasing. Status
Registe r bit SR[7] is set upon erase completion.
Status Register bit SR[7] indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR[5] indicates an erase
fai lu r e if s et. SR[3] set woul d in dicate th at the WSM c oul d n o t per fo r m th e era s e
operation because VPP was outside of its acceptable limits. SR[1] set indicates that the
erase operatio n at tem p ted to era se a lo c ked bloc k, ca us in g th e opera tio n to abor t.
Before issuing a new command, the Status Registe r contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase opera tion has completed.
9.2 Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend comma nd can be issued to any device address. A block
erase ope ratio n c an be sus pended to perform a w o rd or buf fer program operation , or a
read o pe ratio n within any blo ck except th e b lo ck th a t is erase s us p en d ed ( see
Figu r e 3 5, “P rogram Su s pend/ Resu m e Fl o wchart” o n page 8 1).
When a block erase operation is executing, issuing the Erase Suspend command
re qu ests th e WSM to sus pend the er ase algori th m at pred etermin ed poin ts . The d ev i ce
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in Secti on 16.0, “Program and Erase Characteristics” on page 67.
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Progra m command can be issued
to any block ot h er than th e er ase-s us p en ded bloc k. Bloc k era se c ann o t re s u me u n t il
program op era tions init ia ted du r ing eras e su s p en d c o m ple te. Read Ar ray, Read Stat u s
Register, Read Device Identifier, Read CFI, and Erase Resume are valid commands
P30
Datasheet August 2008
36 306666-12
dur ing Erase Susp end. Ad dition a lly, Clear Sta tus Regis te r, P rog ram, Program Sus pe n d,
Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. VPP must rem ain at a valid level, an d WP# mus t rema in unch ang ed
while in erase suspend. If RST# is asserte d, the device is rese t.
9.3 Erase Resume
The Erase Re sume command instructs th e device to continue erasing, and
automatically clears status register bits SR[7,6]. This command can be written to any
addres s. If status register error bits are set, the Status Register should be cleared
before issuing the next instruction. RST# must remain deasserted (see Figure 3 5,
“Program Suspend/Resume Flowchart” on page 81).
9.4 Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If
VPP is be low VPPLK, erase op erations h a lt an d SR[3] is set indicating a VPP-level erro r.
August 2008 Datasheet
Order Number: 306666-12 37
P30
10.0 Security Modes
The de vice fe atur es sec u r ity mo des used to prot ect the in f o r m ation s to r ed in th e fl as h
memory array. The following sections describe each security mode in detail.
10.1 Block Locking
Individual instant block locking is used to protect user code and/or data within the flash
memory a r ray. All b lo cks power up in a locked state to pro t ect array data from being
altered during power transitions. Any block can be locked or unlocked with no latency.
Locked blocks cannot be programmed or erased; they can only be read.
Software -co ntro lle d secu rity is imp lem e n te d using the Block Lock and Blo ck Unlo ck
commands. Hardware-controlled security can be implemented using the Block Lock-
Down command along with asserting WP#. Also, VPP dat a security can be used to
inhibit program and erase operations (see S ection 8.7, “Program Protect ion” on
page 34 and Section 9.4, “Erase Protection” on p age 36).
The P30 device also offers four pre-defined areas in the main array that can be
configured as One-Time Programmable (OTP) for the highest level of security. These
include the four 32 KB parameter blocks together as one and the three adjacent 128 KB
main blocks. This is available for top or bottom parameter devices.
10.1 .1 Lock Bloc k
To lock a block, issue the Lock Block Setup command. The next command must be the Lock Block command
issued to the desired block’s address (see Section 6.0, “Command Set” on page 24 and Figure 40,
“Block Lock Operations Flowchart” on page 86). If the Set Read Configuration Register
command is issued after the B lock Lock Setup comma nd, the device configures the RC R
instead.
Bl ock lock and un lock o per at io ns ar e not af fec ted by the volt ag e leve l o n VPP. The block
lock bits may be modified and/or read even if VPP is at or below VPPLK.
10.1.2 Unlock Block
The Unlock Block command is used to unlock blocks (see Section 6.0, “Command Set”
on page 24). Unl ocke d bl o c k s can be re ad, pr o grammed, and er ased. Unlo c ked bloc k s
return to a locked state when the device is reset or powered down. If a block is in a
lock-down state, WP# must be deasserted before it can be unlocked (see Figure 12,
“Bl o c k Lo ck ing St ate Diagra m ” o n page 38).
10.1.3 Lock-Down Block
A locked or unlocked block can be locked-down by writing the Lock - Down Block
command sequence (see Sec tion 6.0, “Comm and Set” on page 24). Blocks in a lock-
down state cannot be progr ammed or erased; they can only be read. However, unlike
locked blo c ks, their lo cked stat e c a n n ot be changed by software commands alone. A
locked-down block can only be unlocked by issuing the Unlock Block command with
WP# deasserted. To return an unlocked block to loc ked-down state, a Lock-Down
command must be issued prior to changing WP# to VIL. Locked-down blocks revert to
the locked state upon reset or power up the device (see Figure 12, “Block Locking State
Diagram” o n page 38).
P30
Datasheet August 2008
38 306666-12
10.1.4 Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 12.0, “Power and Reset Specifications” on page 50). Data bits DQ[1:0] disp lay
the addr essed bloc k’s lock statu s; DQ0 is the addressed block’s lock bit, wh ile DQ1 is
the addresse d block’s lock-down bit.
10.1.5 Block Locking During Suspend
Bloc k loc k an d unl o c k chan ges can be per formed durin g an erase sus pe n d. To chan ge
blo ck lo c kin g du r in g an eras e operatio n , firs t iss u e th e E ras e Sus p en d c omman d .
M o n itor th e Statu s Register until SR[7 ] an d SR[6 ] are se t, i n d i c a ti n g the devi ce is
suspended and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operatio n us ing the E rase Resume command.
Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block,
or Lock-Down Block produces a command sequence error and set Status Register bits SR[4]
and SR[5]. If a command sequence error occurs during an erase suspend, SR[4] and SR[5]
remains set, even after the erase operation is resumed. Unless the Status Register is cleared
using the Clear Status Register command before resuming the erase operation, possible erase
errors may be masked by the command sequence error.
Figure 12: Block Locking State Diagram
[X00]
[X01]
Power-Up/Reset
Unlocked
Locked
[011]
[111] [110]
Locked-
Down4,5
Software
Locked
[011]
Ha rd w a re
Locked5
Unlocked
W P# H a rd w a re C o n tro l
Notes: 1. [a,b,c] represents [WP#, DQ1, DQ0]. X = Don’t Care.
2. DQ1 indicates Block Lock-Down status. DQ1 = ‘0’, Lock-Down has not been issued
to this block. DQ1 = ‘1’, Lock-Down has been issued to this block.
3. DQ0 indicates block lock status. DQ0 = ‘0’, block is unlocked. DQ0 = ‘1’, block is
locked.
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked by system software to determine difference between
Hardware Locked and Locked-Down states.
Software Block Lock (0x60/0x01) or Software Block Unlock (0x60/0xD0)
Software Block Lock-Down (0x60/0x2F)
WP# hardware control
August 2008 Datasheet
Order Number: 306666-12 39
P30
If a block is locked or locked-down during an erase suspend of the same block, the lock
status bits change immediately. However, the erase operation completes when it is
resumed. Block lock operations cannot occur during a program suspend. See Appendix
A, “Write State Mach ine” on pa ge 87, which shows valid commands during an erase
suspend.
10.2 Selectable One-Time Programmable Blocks
Any o f fo ur pr e-defined areas fro m th e mai n ar ray (the four 3 2-KB param et er bl o c k s
tog ether as o n e and th r ee ad ja c en t 128 KB main blo cks ) can be config u red as OTP so
further program and erase operations are not allowed. This option is available for top or
botto m param e ter dev ic es .
Note: Ple ase see your local Num o nyx rep re sentative f or deta ils a bout the Se lect ab le OTP
implementation.
Table 17: Selectable OTP Block Mapping
Densit y To p Pa ra meter Con figuration Bottom Pa rameter Config uration
256-Mbit
blocks 258:255 (parameters) blocks 3:0 (parameters)
block 254 (main) block 4 (main)
block 253 (main) block 5 (main)
block 252 (main) block 6 (main)
128-Mbit
blocks 130:127 (parameters) blocks 3:0 (parameters)
block 126 (main) block 4 (main)
block 125 (main) block 5 (main)
block 124 (main) block 6 (main)
64-Mbit
blocks 66:63 (parameters) blocks 3:0 (parameters)
block 62 (main) block 4 (main)
block 61 (main) block 5 (main)
block 60 (main) block 6 (main)
Notes:
1. The 512-Mbit devices will have multiple die an d sel ectable OTP areas depending on the placement of the parameter
blocks.
2. Wh en prog ra mm in g th e OTP bits fo r a Top Parameter Device, the following upper address bits must also be driven
properly: A[Max:1 7] driven high (VIH) for TSOP and Easy BGA packages, and A[Max:16] driven high (VIH) for QUAD+
SCSP.
P30
Datasheet August 2008
40 306666-12
11.0 Registers
When n on -arr ay reads are pe r fo rm ed in asyn c h r o n ou s page mode only the fi r s t data is
valid and all subs eq u e nt data are undefin ed. Wh en a n o n - ar ra y re ad op erat io n occu rs
as synchr o no us burst mode, the same wo rd of dat a req uest ed will be output on
successive clock edges until the burst length requirem ent s are satisfied.
11.1 Read Status Register
To read th e S tat u s Regis ter, i s su e th e Read Status Regi s ter c o mman d at an y addr ess .
Sta tus Register inform a tion is availabl e to which the Read Status Register, Word
Program, or Block Erase command was issued. Status Register data is au tomatically
made available following a Word Program, Block Erase, or Block Lock command
sequence. Reads from the device after any of these command sequences outputs the
device’s status until another valid comman d is written (e.g. Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on
DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs
first) updates and latches the Status Register contents. However, reading the Status
Register in syn c h r on o u s bu r s t mo de, CE# or ADV # mus t be togg l ed to update stat u s
data.
T h e De vic e Writ e S tat u s bit (S R[7 ] ) pr o v ides overall st atus o f th e devi c e. Statu s
re gister bits SR [6 :1 ] pres ent s ta tus an d er ro r in for m at io n about the prog ram , era se,
suspend, VPP
, and bloc k-lock ed operation s .
Table 18: Status Register Description (Sheet 1 of 2)
Status Register (SR) Def a ult V a lue = 0x80
Device Write
Status Erase Suspend
Status Erase Status Program
Status VPP Status Program
Suspend
Status
Block-Locked
Status BEFP
Status
DWS ESS ES PS VPPS PSS BLS BWS
76543210
Bit Name Description
7 Device Write Status (DWS) 0 = Device is busy; program or erase cycle in progress; SR[0] valid.
1 = Device is ready; SR[6:1] are valid.
6 Erase Suspend Status (ESS) 0 = Erase suspend not in effect.
1 = Erase suspend in effect.
5 Erase Status (ES) 0 = Erase successful.
1 = Era se fail or p rogram sequence error when set with SR[4,7].
4Program Status (PS) 0 = Program successful.
1 = Program fail or program sequence erro r when set with SR[5,7]
3V
PP Status (VPPS) 0 = VPP within acceptable limits during program or erase operation.
1 = VPP < VPPLK during program or erase operation.
August 2008 Datasheet
Order Number: 306666-12 41
P30
Note: Always clear the Status Register prior to resuming erase operations. It avoids Status Register
ambiguity when issuing commands during Erase Suspend. If a command sequence error
occurs during an era se -susp end state, the Status Register contains the command sequence
error status (SR[7,5,4] set). Wh en the erase operation resumes and finishes, possible errors
during the erase operation cannot be detected via the Status R egist er because it contains t he
previous error status.
11.1.1 Cle ar Status Regis t er
The Clear Status Register command clears the status register. It functions independent
of VPP
. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits
SR[5:3,1] without clearing them. The Status Register should be cleared before starting
a command sequence to avoid any ambiguity. A device reset also clea rs the Status
Register.
11.2 Read Configuration Register
The Read Configuration R egister (RCR) is used to select the read mode (synchronous or
asynchronous), and it defines the synchronous burst characteristics of the device. To
modif y R CR setting s, u s e the Conf igur e Read C o nfig u ratio n Reg is te r comman d ( see
Section 6.0, “Comma nd Set ” on page 24).
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (se e Sectio n 12 .0, “Power a n d Reset Specif ica tion s” on
page 50).
The RCR is shown in Table 19. The following sections d escribe each RCR bit.
2 Program Suspend Status (PSS) 0 = Program suspend not in effect.
1 = Program suspend in effect.
1 Bloc k-Lo cked St at us (BL S ) 0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
0BEFP Status (BWS)
After Buffered Enhanced Factor y Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
1 = BEFP in-progress.
Table 18: Status Register Description (Sheet 2 of 2)
Status Regis ter (SR) Default Value = 0x80
Table 19: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read
Mode RES Latency Count WAIT
Polarity Data
Hold WAIT
Delay Burst
Seq CLK
Edge RES RES Burst
Wrap Burst Length
RM RLC[2:0] WP DH WD BS CE R R BW BL[2:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name Description
15 Read Mode (RM) 0 = Synchronous burst- mode read
1 = Asynchronous page-mode read (default)
14 Reserved (R) Reserved bits should be cleared (0)
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Datasheet August 2008
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11.2.1 Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
11.2.2 Lat ency C o u nt
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is to be driven onto DQ[15:0]. The input clock frequency is used to
det erm ine this value an d Figure 13 s h o ws the data output lat e nc y fo r th e diff er ent
settings of LC. The maximum Latency Count for P30 would be Code 4 based on the Max
Clock frequency specification of 52 mhz, and there will be zero WAIT States when
bursting within the word line. Please also refer to “End of Word Line (EOWL)
Considerat io ns” o n page 47 for more information on EOWL.
Refer to Table 20, “Latency Count (LC) and Frequency Support” on page 43 for Latency
Code Settings.
13:11 Latency Count (LC[2:0])
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7 (default)
(Other bit settings are reserved )
10 Wait Polarity (WP) 0 =WAIT signal is act ive low
1 =WAIT signal is active high (default )
9Data Hold (DH) 0 =Data held for a 1-clock data cycle
1 =Data held for a 2-clock data cycle (default)
8 Wait Delay (WD) 0 =WAIT deasserted with valid data
1 =WAIT deass erted one data cycle before va lid data (default)
7Burst Sequence (BS) 0 =Reserved
1 =Linear (default)
6Cloc k Edge (CE) 0 = Falling edge
1 = Rising edge (default)
5:4 Reserved (R) Reserved bits should be cleared (0)
3Burst Wrap (BW) 0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
2:0 Burst Length (BL[2:0])
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous- word burst (default)
(Other bit settings are reserved )
Note: Lat ency Code 2, Data Hold for a 2-clock data cycle (DH = 1) WAIT m ust be deasserted with valid data (WD = 0).
Latency Code 2, Data Hold for a 2-cock data cycle (DH=1) WAIT deasserted one data cycle before valid data (WD = 1)
combination is not supported. Ta ble 19, “Rea d Confi gu rati o n Regist er D es c r ipt i o n ” o n page 41 is
shown using the QUAD+ package. For EASY BGA and TSOP packages, the table reference should be adjusted using
address bits A[16:1].
Table 19: Read Configuration Register Description (Sheet 2 of 2)
August 2008 Datasheet
Order Number: 306666-12 43
P30
Figure 13: First-Access Latency Count
C ode 1
(Reserved
C ode 6
C ode 5
C ode 4
C ode 3
Code 2
C ode 0 (Rese rved)
C ode 7
Valid
Address
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output
Valid
Output
Address [A]
ADV# [V]
DQ15-0 [D/Q]
CLK [C]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
Table 20: Latency Count (LC) and Frequency Support
Latency Count Settings Frequency Support (MHz)
2£
27
3£ 40
4£ 52
Note: Synchronous burst read operation is currently not supported for the TSOP package.
P30
Datasheet August 2008
44 306666-12
11.2.3 WAIT Polarity
The WAIT Polarity bit (W P), RC R [10] de te rm ines t h e asse rte d leve l (VOH or VOL) o f
WAIT. When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is
asserted low. WAIT changes state on valid clock edg es during active bus cycles (CE#
asse rted, OE# asse rted, RST# d eassert ed).
11.2.3.1 WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR [15]=0). The WAIT signal is only “deasser t ed ” wh en data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read
status, read ID, or read CFI. The W AIT signal is also “deasserted” when data is valid on
the bus.
WAIT behavior during synchronous non-arra y reads at the end of word line works
correctly only on the first dat a access.
When the device is operating in asynchronous page mode, asynchronous single word
read mode, and all write operations, WAIT is set to a deasserted state as determined
by RCR[10]. See Figure 22, “Asynchronous Single-Word Read (ADV# Latch)” on
page 60, and Figure 23, “ A synchronous Pa ge-Mode Re ad Timing” on page 61.
Figure 14: Example Latency Count Setting using Code 3
CLK
CE#
ADV#
A[MAX:0]
D[15:0]
tData
Code 3
Address
Data
012
34
R103
High-Z
Table 21: WAIT Functionality Table (Sheet 1 of 2)
Condition WAIT Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’ High-Z 1
CE# =’0’, OE# = ‘0’ Active 1
Synchronous Array Reads Active 1
Synchronous Non-Array Reads Active 1
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P30
11.2.4 Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output
remains val id on DQ[15:0] for one or two clock cycles. This period of time is called the
“data cycle”. When DH is set, output data is held for two clocks (default). When DH is
cleared, output data is held for one clock (see Figure 15). The processor’s data setup
time and the flash memory’s clock-to-data output delay should be considered when
determining whether to hold output data for one or two clocks. A method for
determ ining the Data Hold confi gurati on is shown below:
To set the device at one clock data hold for subsequent reads, the following condition
must be satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns )
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4 ns. Applyin g these valu es to th e for m ula above:
20 ns + 4 ns ≤ 25 n s
The equation is satisfied and data will be available at every clock period with data hold
setting at one clock. If tCHQV (n s) + tDATA (ns) > One CLK Period (ns), data hold setting of
2 clock periods must be used.
11.2.5 WAIT Dela y
The WAIT Delay (WD ) bit contr ols the WAIT asse r tion-delay be havior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. Whe n WD is set , WAIT is deasserte d one dat a cycle
before valid data (de fa ult ). When WD is clear ed , WAIT is deasser t ed during valid data.
All Asynchronous Re ads Deasserted 1
All Wri te s High-Z 1,2
Notes:
1. Active: WAIT is asserted u ntil data b ec omes valid, th en deasserts
2. When OE# = VIH during wri tes, WAIT = High-Z
Table 21: WAIT Functionality Table (Sheet 2 of 2)
Condition WAIT Notes
Fig ure 15: Data Hold Timing
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
CLK [C]
D[15:0] [Q]
D[15:0] [Q]
2 CLK
Data Hold
1 CLK
Data Hold
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Datasheet August 2008
46 306666-12
11.2.6 Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 22 shows the synchronous burst sequence for all burst
le n gths , as we l l as the effect of the Bu r s t Wrap (B W) s ettin g.
11.2.7 Clo c k E dg e
The C lo ck Edg e (CE ) bit selects eith er a rising (defa ult) or falling cloc k ed ge for CLK .
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
Table 22: Burst Sequence Word Ordering
Start
Addr.
(DEC)
Burst
Wrap
(RCR[3])
Burst Addressing Sequence (DEC)
4-Word Burst
(BL [2:0] =
0b001)
8-Word Burst
(BL [2:0] = 0b 010) 16 -Wo r d B urs t
(BL[2: 0] = 0b 011) Continuous Burst
(BL[2:0] = 0b111)
0 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…
1 0 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5…15-0 1-2-3-4-5-6-7-…
2 0 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6…15-0-1 2-3-4-5-6-7-8-…
3 0 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7…15-0-1-2 3-4-5-6-7-8-9-…
40 4-5-6-7-0-1-2-3 4-5-6-7-8…15-0-1-2-3 4-5-6-7-8-9-10…
50 5-6-7-0-1-2-3-4 5-6-7-8-9…15-0-1-2-3-4 5-6-7-8-9-10-11…
60 6-7-0-1-2-3-4-5 6-7-8-9-10…15-0-1-2-3-4-
56-7-8-9-10-11-12-…
70 7-0-1-2-3-4-5-6 7-8-9-10…15-0-1-2-3-4-5-
67-8-9-10-11-12-13…
…
…
…
…
…
…
14 0 14-15-0-1-2…12-13 14-15-16-17-18-19-20-…
15 0 15-0-1-2-3…13-14 15-16-17-18-19-20-21-…
…
…
…
…
…
…
0 1 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4…14-15 0-1-2-3-4-5-6-…
1 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5…15-16 1-2-3-4-5-6-7-…
2 1 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6…16-17 2-3-4-5-6-7-8-…
3 1 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6-7…17-18 3-4-5-6-7-8-9-…
41 4-5-6-7-8-9-10-11 4-5-6-7-8…18-19 4-5-6-7-8-9-10…
51 5-6-7-8-9-10-11-12 5-6-7-8-9…19-20 5-6-7-8-9-10-11…
61 6-7-8-9-10-11-12-13 6-7-8-9-10…20-21 6-7-8-9-10-11-12-…
71 7-8-9-10-11-12-13-
14 7-8-9-10-11…21-22 7-8-9-10-11-12-13…
…
…
…
…
…
…
14 1 14-15-16-17-18…28-29 14-15-16-17-18-19-20-…
15 1 15-16-17-18-19…29-30 15-16-17-18-19-20-21-…
August 2008 Datasheet
Order Number: 306666-12 47
P30
11.2.8 Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length
accesses wrap within the selected word-length boundaries or cross word-length
boun d aries . W h en BW is s et, bur s t wrapping do es not occur (def au lt ) . When BW is
cleared, burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may
occur when the burst seque nce crosses its first device-row (16-word ) boundary. If the
burst sequence’s start address is 4-word aligned, then no delay occurs. If the start
address is at the end of a 4-word boundary, the worst case output delay is one clock
cycle less than the first access Latency Count. This delay can take place only once, and
doesn’ t occur if the burst sequence does not cross a device-row boundary. WAIT
informs the syst em o f this delay wh en it occu rs .
11.2.9 Burst Length
The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and
continuous word.
Continuous-burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 22, “ Bur s t Seq uen c e Word Orderin g” o n page 46). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
11.2.10 End of W ord Line (EOWL ) C o nsiderations
When performing synchronous burst reads with BW set (no wrap) and DH reset (1 clock
cycle), an output “delay” requ iring additi ons clock Wait States may occur when the
burst sequence crosses its first device-row (16-word) boundary. The delay would take
place only once, and will not occur if the burst sequence does not cross a device-row
boundary. The WAIT signal informs the system of this delay when it occurs. If the burst
sequence’s start add ress is 4-word aligned (i.e . 0x00h, 0x04h, 0x08h, 0x0Ch) then no
delay occurs. If the start address is at the end of a 4-word boundary (i.e. 0x03h,
0x07h, 0x0Bh, 0x0Fh), the worst case delay (number of Wait States require d) will be
one clock cycle less than the first acce ss Latency Count (LC-1) when crossing the first
device-row boundary (i.e. 0x0Fh to 0x10h). Other address misalig nments may require
wait states depending upon the LC setting and the starting address alignment. For
example, an LC setting of 3 with a starting address of 0xFD requires 0 wait states, but
the same LC setting of 3 with a starting address of 0xFE would require 1 wait state
when crossing the first device row boundary.
11.3 One-Time-Programmable (OTP) Registers
The d evice co n ta i n s 1 7 one-time- pro gra mm ab le ( OTP) re gister s that can be use d to
implement system security measures and/or device identifica tion. Each OTP register
can be individually l ocked.
The first 128-bit O TP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit s egm ent i s pr e-pr o grammed at the N u m o ny x fa c to r y w ith a un i que 6 4 -bit
number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
are blank. Users can program these registers as needed. When programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see Figure 16,
“OTP register map” on page 48).
The OTP Registers c o n ta in o n e-tim e pr o gram m a ble (OTP ) bits; w hen pr o g rammed, PR
bits cannot be erased. Each OTP Register can be accessed multiple times to program
individual bits, as long as the register remains unlocked.
P30
Datasheet August 2008
48 306666-12
Each OTP Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated OTP Register can only be read; it can no longe r be
programmed. Additionally, because the Lock Register bits themselves are OTP, when
pr ogra mm ed, L o ck Regis ter bits cann o t be eras ed . Th er ef o r e, wh en a OTP Register is
locked, it canno t be un locked .
.
11.3.1 Reading the OTP registers
The OTP registers can be read from any address. To read the OTP Register, first issue
the Read Device Identifier command at any add ress to place the device in the Read
Dev ice Identi f ier state (see Section 6.0, “Command Set” on page 24). Next, perform a
re ad op era tio n usin g th e ad dre s s of fset c o r respo n din g to th e re gi ster to be re ad.
Table 13 , “D evice Ide n tifier I n formati o n ” on page 28 shows the address offsets of the
OTP Registers and Lock Registers. PR data is read 16 bits at a time.
Figure 16: OTP register map
0x89
Lock Register 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x102
0x109
0x8A
0x91
128-bit Protection Register 16
(User-Programmable)
128-bit Protection Register 1
(User-Programmable)
0x88
0x85
64-bit Segment
(User-Programmable)
0x84
0x81
0x80
Lock Register 0
64-bit Segment
(Factory-Programmed)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128-Bit Protection Register 0
August 2008 Datasheet
Order Number: 306666-12 49
P30
11.3.2 Programming the OTP Registers
To program any of the OTP Re gisters, first issue the Program OT P Register command at
the parameter’s base address plus the offset to the desired OTP Register (see Section
6.0, “Command Set” o n page 24). Next, writ e th e desi r ed O TP Re gi ster data to the
same OTP Register address (see Figure 16, “OTP register map” on page 48).
The device programs the 64-bit and 128- bit user-programmab le OTP Register data 16
bit s at a tim e (see Figure 41, “Protection Register Programming Flowchart” on
page 87). Issuing the Program OTP Re gister command outside of the OTP Register’s
address space causes a progra m error (SR[4] set). Attempting to program a locked
OTP Register causes a program error (SR[4] set) and a lock error (SR[1] set).
Note: When programming the OTP bits in the OTP registers for a Top Parameter Device,
the following upper address bits must also be driven properly: A[M ax:17] driven high
(VIH) fo r TS O P an d E asy BG A packages , an d A[ Max: 1 6 ] driven h i gh ( V IH) for QUAD+
SCSP.
11.3 .3 Locking th e OTP Re gis ter s
Each OTP Register can be locked by programming its respective lock bit in the Lock
Register. To lock a OTP Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by the desired Lock Register
data (see Section 6.0, “Command Set” on page 24). The physical addresses of the Lock
R egisters are 0x80 for register 0 and 0x89 for register 1. These addresses are used
when programming the lock registers (see Table 13, “De vice Identi fier In fo rm ation” on
page 28).
Bit 0 of Lock Register 0 is already programmed during the manufacturing process at the
“factory”, loc king the lower, pre -programmed 64-b it region of the first 128-bit OTP
Register containing the unique identification number of the device. Bit 1 of Lock
R egister 0 can be programmed by the user to lock the user-programmable, 64-bit
region of the first 128-bit OTP Register. When programming Bit 1 of Lock Register 0, all
other bits need to be left as ‘1’ such that the data programmed is 0xFFFD.
Lock R egister 1 controls the locking of the upper sixteen 128-bit O TP Registers. Each of
the 16 bits of Lock Register 1 correspond to each of the upper sixteen 128-bit OTP
Registers. Programming a bit in Lock Reg ister 1 locks the corresponding 128- bit OTP
Register.
Caution: After being locked, the OTP Registers cannot be unlocked.
P30
Datasheet August 2008
50 306666-12
12.0 Power and Reset Specifications
12 .1 Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC an d VCCQ should attain th eir min i m u m ope rating voltage before appl yin g VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from ac cidental pro gramm i ng or erasu r e du r i n g po w er transiti o n s .
12.2 Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead o f ar ray data as expected. Con n ec t RST# to th e sam e active low r es et sig n al
use d fo r CP U initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 23: Reset Specifications
Num Symbol Parameter Min Max Unit Notes
P1 tPLPH RS T# puls e widt h low 100 - n s 1,2 , 3,4
P2 tPLRH RST# low to device reset during erase - 25
µs
1,3,4,7
RST# low to devic e reset during program - 25 1,3,4,7
P3 tVCCPH VCC Power valid to RST# de-assertion (high) 130nm 60 - 1,4,5,6
VCC Power valid to RST# de-asser tion (high) 65nm 300 - 1,4,5,6
Notes:
1. These specifications are valid for all device versions (packages and speeds).
2. The device may reset if tPLPH is < tPL PH MIN, but this is not guaranteed.
3. Not applicable if RST# is tied to Vcc.
4. Sampled, but not 100% tested.
5. When RST# is tied to the VCC supply, device will not be ready until tVCCPH aft er VCC ≥ VCCMIN.
6. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.
7. Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
August 2008 Datasheet
Order Number: 306666-12 51
P30
12.3 Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power
supply current considerations are 1) standby current levels, 2) active current levels,
and 3) transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuit s within the
device enable charge-pumps, and internal logic states change at high speed. All of
th ese in ternal acti vitie s pr oduce tr an sie nt sig nals. Trans ient c urre nt mag nitude s depe nd
on the device outputs’ capacitive and inductive loading. Two-line control and correct
de-coupling capacit or selection suppress transient voltage peaks.
Because Numonyx Multi-Level Cell (MLC) flash memory devices draw their power from
VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor to
ground. High-frequency , inherently low-inductance capacitors should be placed as close
as possible to package leads.
Addit io n a lly, for ever y eight dev i ces us ed in the s ystem, a 4.7 µF electrol ytic ca pacitor
sho u l d be placed b et ween po wer an d ground cl o s e to the de v ic es. T h e bulk c apacit o r i s
meant to overcome voltage droop caused by PCB trace inductance.
Figure 17: Reset Operation Waveforms
(
A) Reset during
read mode
(B ) R eset during
program or block erase
P1
≤
P2
(C ) R eset during
program or block erase
P1
≥
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power-u p to
RS T# high
P1 R5
P2
P3
P2 R5
R5
P30
Datasheet August 2008
52 306666-12
13.0 Maximum Ratings and Operating Conditions
13 .1 Absolute Maximum Ratings
Warning: Stress ing the de vice b eyond the “Absolute Maximum Ratings” may cause perm ane nt
damage. These are s tress ratings only.
13.2 Operating Conditions
Note: Op eratio n beyo nd the “Opera ting Co n d i tions ” i s n ot r ec ommended and exten ded expo s u r e
beyond the “Op erati n g Con ditio n s” may affe ct device reliability.
Table 24: Maximum Ratings
Parameter Maximum Rating Notes
Temperature under bias –40 °C to +85 °C
Storage temperature –65 °C to +125 °C
Voltage on any signal (except VCC, VPP and VCCQ) –0.5 V to +4.1 V 1
VPP voltage –0.2 V to +10 V 1,2,3
VCC voltage –0.2 V to +2.5 V 1
VCCQ voltage –0.2 V to +4.1 V 1
Output short circuit current 100 mA 4
Notes:
1. Voltages shown are specified with respect to VSS. Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on
VCC, VCCQ, and VPP. During transitions, this level may undershoot to –2.0 V for periods less than 20 ns. Maximum DC
voltage on VCC is VCC + 0.5 V, which, during transitions, may overshoot to VCC + 2.0 V for periods less than 20 ns.
Maximum DC voltage on input/output signals and VCCQ is VCCQ + 0.5 V, which, during transitions, may overshoot to
VCCQ + 2.0 V for periods less than 20 ns.
2. Maximum DC voltage on VPP may overshoot to +11.5 V for periods less than 20 ns.
3. Program/erase voltage is typically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for
1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability.
4. Output shorted for no more than one second. No more than one output shorted at a time.
Table 25: Operating Conditions
Symbol Parameter Min Max Units Notes
TCOperating Temperature –40 +85 °C 1
VCC VCC Supply Voltage 1.7 2.0
V
3
VCCQ I/O Supply Voltage CMOS inputs 1.7 3.6
TTL inputs 2.4 3.6
VPPL VPP Voltage Supp ly (Logic Level) 0.9 3.6
2
VPPH Factory word programming VPP 8.5 9.5
tPPH Maximum VPP Hours VPP = VPPH -80Hours
Block
Erase
Cycles
Main and Parameter Blocks VPP = VPPL 100,000 -
CyclesMain Blocks VPP = VPPH - 1000
Parameter Blocks VPP = VPPH - 2500
Notes:
1. TC = Case Temperature.
2. In typical operation VPP program voltage is VPPL.
3. 40Mhz burst oper at ion on t he TSOP p ack age h as a min Vcc value of 1.85V. Please refer to the latest Specification Update
regarding synchronous burst operation with the TSOP package
August 2008 Datasheet
Order Number: 306666-12 53
P30
14.0 Ele ctrical Spe cif ication s
14.1 DC Current Characteristi cs
Table 26: DC Current Characteristics (Sheet 1 of 2)
Sym Parameter
CMOS
Inputs
(VCCQ =
1.7 V - 3.6
V)
TTL Inputs
(VCCQ =
2.4 V - 3.6
V) Unit Tes t Condi tions Not es
Typ Max Typ Max
ILI Input Load Current - ±1 - ±2 µA VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or VSS 1
ILO Output
Leakage
Current D Q[15:0], WAIT -±1-±10µA
VCC = VCCMax
VCCQ = VCCQMax
VIN = VCCQ or VSS
ICCS,
ICCD
VCC Standby,
Power Down
64-Mbit 20 35 20 35
µA
VCC = VCCMax
VCCQ = VCCQMax
CE# = VCCQ
RST# = VCCQ (for ICCS)
RST# = VSS (for ICCD)
WP# = VIH
1,2
128-Mbit 30 75 30 75
256-Mbit 55 115 55 200
512-Mbit 110 230 110 400
ICCR
Average
VCC
Read
Current
Asynchronous Single-
Word f = 5 MHz (1 CLK) 14 16 14 16 mA 1-Word Read
VCC = VCCMax
CE# = VIL
OE# = VIH
Inputs: VIL or
VIH
1
Pag e - M od e Rea d
f = 13 MHz (5 CLK) 9 10 9 10 mA 4-Word Read
Synchronous B urst
f = 40 MHz
13 17 n/a n/a mA BL = 4W
15 19 n/a n/a mA BL = 8W
17 21 n/a n/a mA BL = 16W
21 26 n/a n/a mA BL = Cont.
Synchronous B urst
f = 52MHz
16 19 n/a n/a mA BL = 4W
19 23 n/a n/a mA BL = 8W
22 26 n/a n/a mA BL = 16W
23 28 n/a n/a mA BL = Cont.
ICCW,
ICCE
VCC Program Current,
VCC Erase Current
36 51 36 51 mA VPP = VPPL, pgm/ers in progress 1,3,5
26 33 26 33 VPP = VPPH, pgm/ers in progress 1,3,5
ICCWS,
ICCES
VCC Program Suspend
Current,
VCC Erase
Suspend Current
64-Mbit 20 35 20 35
µA CE# = VCCQ; suspend in
progress 1,3,4
128-Mbit 30 75 30 75
256-Mbit 55 115 55 200
512-Mbit 110 230 110 400
IPPS,
IPPWS,
IPPES
VPP Standby Current,
VPP Program Suspend Current,
VPP Erase Suspend Current 0.2 5 0.2 5 µA VPP = VPPL, suspend in progress 1,3
IPPR VPP Read 2 15 2 15 µA VPP = VPPL 1,3
IPPW VPP Program Current 0.05 0.10 0.05 0.10 mA VPP = VPPL, program in progress
822822 V
PP = VPPH, program in progress
P30
Datasheet August 2008
54 306666-12
14.2 DC Voltage Characteristics
IPPE VPP Erase Current 0.05 0.10 0.05 0.10 mA VPP = VPPL, erase in progress
822822 V
PP = VPPH, erase in progress
Notes:
1. All currents are RMS unless noted. Typical values at typical VCC, TC = +25 °C.
2. ICCS is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
3. Sampled, not 100% tested.
4. ICCES is specified with the device deselected. If device is read while in erase suspend, current is ICCES plus ICCR.
5. ICCW, ICCE measured over typical or max times specified in Sect ion 1 6.0, “P ro gram and Erase
Characteristics” on page 67.
Table 27: DC Voltage Characteristics
Sym Parameter
CMOS Inputs
(VC CQ = 1.7 V – 3.6 V) TTL Inputs (1)
(VCCQ = 2.4 V – 3.6 V) Unit Test Condition Notes
Min Max Min Max
VIL Input Low Voltage0 0.400.6V 2
VIH Input High Voltage VCCQ – 0.4 V VCCQ 2.0 VCCQ V
VOL Output Low Voltage - 0.1 - 0.1 V VCC = VCCMin
VCCQ = VCCQMin
IOL = 100 µA
VOH Output High Voltage VCCQ – 0.1 - VCCQ – 0.1 - V VCC = VCCMin
VCCQ = VCCQMin
IOH = –100 µA
VPPLK VPP Lock-Out Voltage - 0.4 - 0.4 V 3
VLKO VCC Loc k Volt age 1.0 - 1.0 - V
VLKOQ VCCQ Lock Voltage 0.9 - 0.9 - V
Notes:
1. Synchronous read mode is not supported with TTL inputs.
2. VIL can undershoot to –0.4 V and VIH ca n overshoot to VCCQ + 0.4 V for durations of 20 ns or less.
3. VPP ≤ VPPLK inhibits erase and program operations. Do not use VPPL and VPP H outside their valid ranges.
Table 26: DC Current Characteristics (Sheet 2 of 2)
Sym Parameter
CMOS
Inputs
(VCCQ =
1.7 V - 3.6
V)
TTL Inputs
(VCCQ =
2.4 V - 3. 6
V) Unit Test Conditions Notes
Typ Max Typ Max
August 2008 Datasheet
Order Number: 306666-12 55
P30
15.0 AC Characteristics
15 . 1 A C Te s t Co n diti ons
Note: AC test inputs are driven at VCCQ for L ogi c "1 " an d 0 V fo r Lo gi c "0 . " In put/out put t i mi ng be gins/ end s at V CCQ/2. I npu t ri se
and fall times (10% to 90%) < 5 ns. Worst case speed occurs at VCC = VCCMin.
Notes:
1. See the following table for component values.
2. Test configuration component value for worst-case speed conditions.
3. CL includes jig capacitance.
.
Figure 18: AC Input/Output Reference Waveform
Figure 19: Transient Equivalent Testing Load Circuit
Table 28: Test Configuration Component Value For Worst Case Speed Conditions
Test C onf iguration CL (pF)
VCCQMin Standard Test 30
Figure 20: Clock Input AC Waveform
IO_REF.WMF
I nput V
CCQ
/2 V
CCQ
/2 Output
V
CCQ
0V
Tes t Po i nts
Device
Unde r Tes t Out
CL
CLK [C]
V
IH
V
IL
R203R202
R201
P30
Datasheet August 2008
56 306666-12
15.2 Capacitance
15.3 AC Read Specifications
Table 29: Capacitance
Parameter Signals Min Typ Max Unit Condition Notes
Input Capacitance
Address, Data,
CE#, WE#, OE#,
RST#, CLK, AD V#,
WP#
26 7 pF Typ temp = 25 °C,
Max temp = 85 °C,
VCC = (0 V - 2.0 V),
VCCQ = (0 V - 3.6 V),
Discrete silicon die
1,2,3
Output Capacitance Data, WAIT 2 4 5 pF
Notes:
1. Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance values by the number of
dies in the stack.
2. Sampled, but not 100% tested.
3. Silicon die capacitance only; add 1 pF for discrete packages.
Table 30: AC Read Specifications for 64/128- Mbit Densities (Sheet 1 of 2)
Num Symbol Parameter Min Max Unit Notes
Asynchronous Specifications
R1 tAVAV Read cycle time 85 - ns
R2 tAVQV Address to output valid - 85 ns
R3 tELQV CE# l ow to output valid - 85 ns
R4 tGLQV OE# low to output valid - 25 ns 1,2
R5 tPHQV RST# high to output valid - 150 ns 1
R6 tELQX CE# l ow to output in low-Z 0 - ns 1,3
R7 tGLQX OE# low t o output in low-Z 0 - ns 1,2,3
R8 tEHQZ CE# high to output in high-Z - 24 ns
1,3
R9 tGHQZ OE# high to output in high-Z - 24 ns
R10 tOH Output hold from first occurring address, CE#, or
OE# change 0-ns
R11 tEHEL CE# pulse width high 20 - ns 1
R12 tELTV CE# low to WAIT valid - 17 ns
R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3
R15 tGLTV OE# low to WAIT valid - 17 ns 1
R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3
R17 tGHTZ OE# high to WAIT in high-Z - 20 ns
Latching Specifications
R101 tAVVH Address setup to ADV# high 10 - ns
1
R102 tELVH CE# low to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid - 85 ns
R104 tVLVH ADV# pulse width low 10 - ns
R105 tVHVL ADV# pulse width high 10 - ns
R106 tVHAX Address hold from ADV# high 9 - ns 1,4
August 2008 Datasheet
Order Number: 306666-12 57
P30
R108 tAPA Page address access - 25 ns 1
R111 tphvh RST# high to ADV# high 30 -ns
Clock Specifications
R200 fCLK CLK frequency -52MHz
1,3,5,6
TSOP - 40 MHz
R201 tCLK CLK period 19.2 - ns
TSOP 25 - ns
R202 tCH/CL CLK high/low time 5 - ns
R203 tFCLK/RCLK CLK fall/rise time - 3 ns
Synchr on ous Sp e cif ications(5,6)
R301 tAVCH/L Address setup to CLK 9 - ns
1
R302 tVLCH/L ADV# low setup to CLK 9 - ns
R303 tELCH/L CE# low setup to CLK 9 - n s
R304 tCHQV / tCLQV CLK to output valid - 17 ns
R305 tCHQX Output hold from C LK 3 - n s 1,7
R306 tCHAX Address hold from CLK 10 - ns 1,4,7
R307 tCHTV CLK to WAIT valid - 17 ns 1,7
R311 tCHVL CL K Valid to ADV# Setu p 3 - ns 1
R312 tCHTX WAIT Ho ld from CLK 3 - ns 1,7
Notes:
1. See Figure 18, “ AC Input/Output Reference W a veform” on page 55 for timing measurements and max
allowable input s lew rate.
2. OE# may be delayed by u p to tELQV – t GLQV after CE#’s fallin g edge without impact to tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package.
6. Synchro nous read mode is not supporte d with TTL level inputs.
7. Applies only to subsequent synchronous reads.
Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet 1 of 3)
Num Symbol Parameter Speed Min Max Unit Notes
Asynchronous Sp ecific a ti ons
R1 tAVAV Read cycle time
VCC = 1.8 V – 2.0
V85 -
ns
VCC = 1.7 V – 2.0
V88 -
256/512-Mb TSOP
packages 95
R2 tAVQV Address to output valid
VCC = 1.8 V – 2.0
V-85
ns
VCC = 1.7 V – 2.0
V-88
256/512-Mb TSOP
packages -95
Table 30: AC Read Specifications for 64/128- Mbit Densities (Sheet 2 of 2)
Num Symbol Parameter Min Max Unit Notes
P30
Datasheet August 2008
58 306666-12
R3 tELQV CE# l ow to output valid
VCC = 1.8 V – 2.0
V-85
ns
VCC = 1.7 V – 2.0
V-88
256/512-Mb TSOP
packages -95
R4 tGLQV OE# low t o output valid - 25 ns 1,2
R5 tPHQV RST# high to output valid - 150 ns 1
R6 tELQX CE# l ow to output in low-Z 0 - ns 1,3
R7 tGLQX OE# low t o output in low-Z 0 - ns 1,2,3
R8 tEHQZ CE# high to output in high-Z - 24 ns
1,3
R9 tGHQZ OE# high to output in high-Z - 24 ns
R10 tOH Out put hold from first occurring address, CE#, or OE#
change 0-ns
R11 tEHEL CE# pulse width high 20 - ns 1
R12 tELTV CE# low to WAIT valid - 17 ns
R13 tEHTZ CE# high to WAIT high-Z - 20 ns 1,3
R15 tGLTV OE# low to WAIT valid - 17 ns 1
R16 tGLTX OE# low to WAIT in low-Z 0 - ns 1,3
R17 tGHTZ OE# high to WAIT in high-Z - 20 ns
Latching Specifications
R101 tAVVH Address setup to ADV# high 10 - ns
1
R102 tELVH CE# low to ADV# high 10 - ns
R103 tVLQV ADV# low to output valid
VCC = 1.8 V – 2.0
V-85
ns
VCC = 1.7 V – 2.0
V-88
256/512-Mb TSOP
packages -95
R104 tVLVH ADV# pulse width low 10 - ns
R105 tVHVL ADV# pulse width high 10 - ns
R106 tVHAX Address hold from ADV# high 9 - ns 1,4
R108 tAPA Page address access - 25 ns 1
R111 tphvh RST# high to ADV# high 30 - ns
Clock Specifications
R200 fCLK CLK frequency - 52 MHz 1,3,5,6
TSOP Package - 40 MHz
R201 tCLK CLK period 19.2 - ns
TSOP Package 25 - ns
R202 tCH/CL CLK high/low time 5 - ns
R203 tFCLK/RCLK CLK fall/rise time - 3 ns
Sync hr onous Spec i ficati on s(5,6)
Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet 2 of 3)
Num Symbol Parameter Speed Min Max Unit Notes
August 2008 Datasheet
Order Number: 306666-12 59
P30
R301 tAVCH/L Address setup to CLK 9 - ns
1
R302 tVLCH/L ADV# low setup to CLK 9 - ns
R303 tELCH/L CE# low setup to CLK 9 - ns
R304 tCHQV / tCLQV CLK to output valid - 17 ns
R305 tCHQX Output hold from C LK 3 - ns 1,7
R306 tCHAX Address hold from CLK 10 - ns 1,4,7
R307 tCHTV CLK to WAIT valid - 17 ns 1,7
R311 tCHVL CL K Valid to ADV# Setu p 3 - ns 1
R312 tCHTX WAIT Ho ld from CLK 3 - ns 1,7
Notes:
1. See Figure 18, “AC Input/Output Refere nce Waveform” on page 55 for t iming measure me nts an d max
allowable input s lew rate.
2. OE# may be delayed by u p to tELQV – t GLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. Address hold in synchronous burst mode is tCHAX or tVHAX, whichever timing specification is satisfied first.
5. Please see the latest P30 Spec Update for synchronous burst operation with the TSOP package.
6. Synchro nous read mode is not supporte d with TTL level inputs.
7. Applies only to subsequent synchronous reads.
Table 31: AC Read Specifications for 256/512-Mbit Densities (Sheet 3 of 3)
Num Symbol Parameter Speed Min Max Unit Notes
Table 32: AC Read Specification differences for 65nm
Num Symbol Parameter Min Max Unit Notes
Asynchronous Sp ecific a ti ons
R1 tAVAV Read cycle time 100 - ns 2
TSOP 110 ns 2
R2 tAVQV Address to output valid - 100 ns 2
TSOP 110 ns 2
R3 tELQV CE# low to output valid - 100 ns 2
TSOP 110 ns 2
R103 tVLQV
ADV# low to output valid
- 100 ns 1,2
TSOP 110 ns 2
Notes:
1. See Figure 18, “AC Input/Output Reference Waveform” on page 55 for timing measurements and
max al lowabl e input slew rate.
2. This is the recommended specif ication for al l new designs supportin g both 130nm and 65nm lithos, or for new designs
that will use the 65nm lithography.
P30
Datasheet August 2008
60 306666-12
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).
Figure 21: Asynchronous Single-Word Read (ADV# Low)
R5
R7
R6
R17R15
R9R4
R8R3
R1
R2
R1
A
ddress [A]
ADV#
CE# [E}
OE# [G]
WAIT [T]
Data [D/Q]
RST # [P]
Figure 22: Asynchronous Single-Word Read (ADV# Latch)
R10
R7
R6
R17R15
R9R4
R8R3
R106
R101
R105R105
R2
R1
A
ddress [A]
A[1:0][A]
ADV#
CE# [E}
OE# [G]
WAIT [T]
Data [D/Q]
August 2008 Datasheet
Order Number: 306666-12 61
P30
Note: WAIT shown deasserted during asynchronous read mode (RCR[10]=0, Wait asserted low).
1. WAIT is driven per O E# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2. This diagram ill ustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
Figure 23: Asynchronous Page-Mode Read Timing
R108 R9R7
R17R15
R10R4
R8R3
R106
R101
R105R105
R1R1
R2
A
[Max:2] [A]
A[1:0]
ADV#
CE# [E]
OE# [G]
WAIT [T]
DATA [D/Q]
Figure 24: Synchronous Single-Word Array or Non-array Read Timing
R312
R305R304
R4
R17R307R15
R9R7
R8
R30 3
R102
R3
R104
R10 6R101
R104
R105R105
R2
R306R30 1
CLK [C]
A
ddress [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
P30
Datasheet August 2008
62 306666-12
Notes:
1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2. At the end of Wor d Line; the delay incurred when a burst access crosses a 16-word boundary and the starting a ddress is
not 4-word boundary aligned.
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR[1 0] = 0 , Wait asserted low).
Fig ure 25: Continuous Burst Read, Showin g An Output Delay Timing
Figure 26: Synchronous Burst-Mode Four-Word Read Timing
R305R305R305R305
R304
R4
R7
R312R307R15
R303
R102
R3
R106
R105R105
R101
R2
R304R304R304R306
R302
R301
CLK [C]
A
ddress [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
y
A
Q0 Q1 Q2 Q3
R307
R10
R304
R305R304
R4
R7
R17R15
R9
R8
R303
R3
R106
R102
R105R105
R101
R2
R306
R302
R301
CLK [C]
A
ddress [A]
ADV# [V]
CE# [E]
OE# [G]
WAIT [T]
Data [D/Q]
August 2008 Datasheet
Order Number: 306666-12 63
P30
15.4 AC Write Specific ati ons
Table 33: AC Write Specifications
Num Symbol Parameter Min Max Unit Notes
W1 tPHWL RST# high recovery to WE# low 150 - ns 1,2,3
W2 tELWL CE# setup to WE# low 0 - ns 1,2,3
W3 tWLWH WE# write pulse width low 50 - ns 1,2,4
W4 tDVWH Data setup to WE# high 50 - ns
1,2
W5 tAVWH Address setup to WE# high 50 - ns
W6 tWHEH CE# hold from WE# high 0 - ns
W7 tWHDX Data hold from WE# high 0 - ns
W8 tWHAX Address hold from WE# high 0 - ns
W9 tWHWL WE# pulse width high 20 - ns 1,2,5
W10 tVPWH V
PP setup to WE# high 200 - ns 1,2,3,7
W11 tQVVL VPP hold from Status read 0 - ns
W12 tQVBL WP# hold from Status read 0 - ns 1,2,3,7
W13 tBHWH WP# setup to WE# high 200 - ns
W14 tWHGL WE# high to OE# low 0 - ns 1,2,9
W16 tWHQV WE# high to read valid tAVQV + 35 - ns 1,2,3,6,10
Write to Asynchronous Read Speci fications
W18 tWHAV WE# high to Address valid 0 - ns 1,2,3,6,8
Write to Synch ronou s Read Specifications
W19 tWHCH/L WE# high to Clock valid 19 - ns 1,2,3,6,10
W20 tWHVH WE# high to ADV# high 19 - ns
Write Specifications with Clock Active
W21 tVHWL AD V# high to WE# low - 20 ns 1,2,3,11
W22 tCHWL Clock high to WE# low - 20 ns
Notes:
1. Write timing characteristics during erase suspend are the same as write-only operations.
2. A write operation can be terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5. Write pulse width high (tWH WL or tEHEL) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
(whichever occurs last). Hence, tWHWL = tEHEL = tWHEL = tEHWL).
6. tWHVH or t WHC H/L must be met when transitioning from a w rite cycle to a synchronous burst read.
7. VPP and WP# should be at a valid level until erase or program success is determined.
8. This sp ecification is only applicable when transitioning from a write cycle to an asynchronou s read. See spec W19 and
W20 for synchronous read.
9. When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
10. Add 10 ns if the write opera tion results in a RCR or block lock status change, for the subsequent read operation to reflect
this chan ge.
11. These specs are required only when the device is in a synchronous mode and clock is active during ad dress setup phase.
P30
Datasheet August 2008
64 306666-12
Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserte d.
Figure 27: Write-to-Write Timing
W1
W7W4W7W4
W3W9 W3W9W3W3
W6W2W6W2
W8W8 W5W5
A
ddress [A]
CE# [E}
WE# [W]
OE# [G]
Data [D/Q]
RST# [P]
Figure 28: Asynchronous Read-to-Write Timing
Q D
R5
W7
W4R10
R7
R6
R17R15
W6W3W3W2
R9R4
R8R3
W8W5
R1
R2
R1
A
ddress [A]
CE# [E}
OE# [G]
WE# [W]
WAIT [T ]
Data [D/Q]
RST # [P]
August 2008 Datasheet
Order Number: 306666-12 65
P30
Note: WAIT show n deas ser te d and High- Z per OE# deass ert ion duri ng writ e ope r ati on (RC R[1 0] =0, W a it ass ert ed low). C lock is
ignored during write operation.
Figure 29: Write-to-Asynchronous Read Timing
D Q
W1
R9
R8
R4
R3
R2
W7W4
R17R15
W14
W18W3W3
R10W6W2
R1R1W8W5
A
ddress [A]
ADV# [V]
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
Data [D/Q]
RST# [P]
Figure 30: Synchronous Read-to-Write Timing
Latency Count
Q D D
W7R305
R304
R7
R312R307R16
W15
W22
W21
W9
W8
W9W3
W22
W21
W3W2
R8
R4
W6
R11
R13
R11
R303
R3
R104R104
R106
R102
R105R105
W18
W5
R101
R2
R306
R302
R301
CLK [C]
A
ddress [ A]
ADV# [V]
CE# [E]
OE# [G]
WE#
WAIT [T]
Data [D/Q]
P30
Datasheet August 2008
66 306666-12
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR[10]=0, Wait asserted low).
Figure 31: Write-to-Synchron ous Read Timing
D Q Q
W1
R304
R305R304
R3
W7
W4
R307R15
R4
W20
W19
W18
W3W3
R11
R303
R11
W6
W2
R104
R106
R104
R306W8W5
R302
R301
R2
CLK
A
ddress [A]
ADV#
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
Data [D/Q]
RST# [P]
August 2008 Datasheet
Order Number: 306666-12 67
P30
16.0 Program and Erase Characteristics
Table 34: Program and Erase Specifications
Num Symbol Parameter VPPL VPPH Units Notes
Min Typ Max Min Typ Max
Conventional Word Programming
W200 tPROG/W Program
Time
Single word - 130nm - 90 200 - 85 190
µs 1Single word - 65nm - 150 456 - 150 456
Single cell - 30 60 - 30 60
Buffered Programming
W200 tPROG/W Program
Time Single word - 90 200 - 85 190 µs 1
W251 tBUFF 32-word buffer - 440 880 - 340 680
Buffered Enhanced Factory Programming
W451 tBEFP/W Program Single word n/a n/a n/a - 10 - µs 1,2
W452 tBEFP/Setup BEFP Setup n/a n/a n/a 5 - - 1
Erasing and Suspending
W500 tERS/PB Erase Time 32-KByte Parameter - 0.4 2.5 - 0.4 2.5 s
1
W501 tERS/MB 128-KByte Main - 1.2 4.0 - 1.0 4.0
W600 tSUSP/P Suspend
Latency
Program suspend - 20 25 - 20 25
µsW601 tSUSP/E Erase suspend - 20 25 - 20 25
W602 tERS/SUSP Erase to Suspend - 500 - - 500 - 1,3
Notes:
1. Typical values measured at TC = +25 °C and nominal voltages. Performance numbers are valid for all speed versions. Excludes system
overhead. Sampled, but not 100% tested.
2. Averaged over entire device.
3. W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
P30
Datasheet August 2008
68 306666-12
17.0 Ordering Inform ation
17.1 Di scr ete Pro ducts
Figure 32: Decoder for Discrete P30
F 6 4 P 3 0 B8E 2T 0
Product Line Designator
28F = Intel® Flash Memory
Package Designator
TE = 56-Lead TSOP, leaded
JS = 56-Lead TSOP, lead-free
RC = 64-Ball Easy BGA, leaded
PC = 64-Ball Easy BGA, lead-free
Device Density
640 = 64-Mbit
128 = 128-Mbit
256 = 256-Mbit
Product Family
P30 = Intel StrataFlash® Embedded Memory
VCC = 1.7 – 2.0 V
VCCQ = 1.7 – 3.6 V
Access Speed
85 ns
Para meter Location
B = Bottom Parameter
T = Top Parameter
8 5
Table 35: Valid Combinations for Discrete Products
64-Mbit 128-Mbit 256-Mbit
TE28F640P30B85 TE28F128P30B85 TE28F256P30B95
TE28F640P30T85 TE28F128P30T85 TE28F256P30T95
JS28F640P30B85 JS28F128P30B85 JS28F256P30B95
JS28F640P30T85 JS28F128P30T85 JS28F256P30T95
RC28F640P30B85 RC28F128P30B85 RC28F256P30B85
RC28F640P30T85 RC28F128P30T85 RC28F256P30T85
PC28F640P30B85 PC28F128P30B85 PC28F256P30B85
PC28F640P30T85 PC28F128P30T85 PC28F256P30T85
August 2008 Datasheet
Order Number: 306666-12 69
P30
17.2 SCSP Products
Note: For 512-Mbit only, “B” is used for both top and bottom Parameter/Mux configurations.
Note: * The “B” parameter is used for both “top” and “bottom” options in the 512-Mbit density.
Figure 33: Decoder for SCSP P30
Table 36: Valid Combinations for Dual- Die Products
64-Mbit 128-Mbit 256-Mbit 512-Mbit*
RD48F2000P0ZBQ0 RD48F3000P0ZBQ0 RD48F4000P0ZBQ0 RD48F4400P0VBQ0
RD48F2000P0ZTQ0 RD48F3000P0ZTQ0 RD48F4000P0ZTQ0 PF48F4400P0VBQ0
PF48F2000P0ZBQ0 PF48F3000P0ZBQ0 PF48F4000P0ZBQ0 RC48F4400P0VB00
PF48F2000P0ZTQ0 PF48F3000P0ZTQ0 PF48F4000P0ZTQ0 PC48F4400P0VB00
TE48F4400P0VB00
JS48F4400P0VB00
F 4 0 P 0 Z B8D 4R 0 0 Q
Group De signator
48F = Flash Memory only
Packag e D esignator
RD = Intel® SCSP, leaded
PF = Intel® SCSP, lead-free
RC = 64-Ball Easy BGA, leaded
PC = 64-Ball Easy BGA, lead-free
TE = 56-Lead TSOP, leaded
JS = 56-Lead TSOP, lead-free
Flash Density
0 = No die
2 = 64-Mbit
3 = 128-Mbit
4 = 256-Mbit
Flash #1
Flash #2
Flash #3
Flash #4
Flash Family 1/2
Flash Family 3/4
0
Produc t Family
P = Intel StrataFlash® Embedded Memory
0 = No die
Device Details
0 = Original version of the product
(refer to the latest version of the
datasheet for details)
Ballout Designator
Q = QUAD+ ballout
0 = Discrete ballout
Parameter, Mux C onfig uration
B = Bottom Parameter, Non Mux
T = Top Parameter, Non Mux
I/O Vo lta ge , CE # Co nfig uration
Z = Individual Chip Enable(s)
V = Virtual Chip Enable(s)
VCC = 1.7 V – 2.0 V
VCCQ = 1.7 V – 3.6 V
P30
Datasheet August 2008
70 306666-12
Appendix A Supplemental Reference Information
A. 1 Common Flas h Interface Tables
The C om m on Fla sh Inte r face (C F I) is par t of an overall specif ica tion for m ultiple
com man d-se t and control - in ter fac e descriptions. Thi s appendix describes the database
st r u c tu r e con tain in g th e data retur n ed by a re ad o perat ion after issui n g th e Read CFI
command (see Se ction 6.0, “Command Set ” on page 24). System software can parse
this database structure to obtain information about the flash device, such as block size,
density, bus width, and electrical specifications. The system software will then know
which command set(s) to use to properly perform flash writes, block erases, reads and
otherwise control the flash device.
A.1.1 CFI Structure Output
The CFI database allows system software to obtain information for controlling the flash
device. This section describes the device’s CFI-compliant interface that allows access to
CFI data.
CFI data are presente d on the lowest- order data outputs (DQ7-0) only. The numerical
offset value is the address relative to the maximum bus width supported by the device.
On this family of devices, the CFI table device starting address is a 10h, which is a word
address for x16 devices.
For a word-wide (x16) device, the first two CFI-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word add resses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0)
an d 00 h in th e h igh byte (DQ 15-8).
At CFI addresses containing two or more bytes of information, the least significant data
byt e is presented at th e lower address , and the m o s t s ig n if icant data byte is pres en ted
at th e hi gher addr ess.
In all of the follow ing tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
w ide devi c es i s alw ays “0 0 h ,” the leadin g “0 0 ” has been dr o pped fr o m the table
notation and only the lower byte value is shown. Any x16 device outputs can be
assumed to have 00h on the upper byte in this mode .
Table 37: Summary of CFI Structure Output as a Function of Device and Mode
Device Hex
Offset Hex
Code
A
SCII
V
alue
00010: 51 "Q"
Device Addresses 00011: 52 "R"
00012: 59 "Y"
August 2008 Datasheet
Order Number: 306666-12 71
P30
Table 38: Example of CFI Structure Output of x16- Devices
A.1.2 CFI Structure Overview
The CFI command causes the flash component to display the Common F lash Interface
(CFI) CFI structure or “database.” The structure sub-sections and address locations are
sum ma rized below.
Table 39: CFI Structure
Notes:
1. Refe r to the CFI S tructure Output section and offset 28 h for th e det ailed defin ition of offset a ddress as a fun ction of devic e
bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord).
3. Offset 15 defines “P” which po ints to the Primary Numonyx-specific Extended CFI Table.
A.1 .3 Read CF I Ide ntification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-spe cified command set(s).
Table 40: CFI Identification
Word Addressin
g
: B
y
te Addressin
g
:
Offset Hex Code Value Offset Hex Code Value
A
X
–A
0 D15
–
D0
A
X
–A
0 D7
–
D0
00010h 0051 "Q" 00010h 51 "Q"
00011h 0052 "R" 00011h 52 "R"
00012h 0059 "Y" 00012h 59 "Y"
00013h P_IDLO PrVendor 00013h P_IDLO PrVendo
r
00014h P_IDHI ID # 00014h P_IDLO ID #
00015h PLO PrVendor 00015h P_IDHI ID #
00016h PHI TblAd
r
00016h ... ...
00017h
A
_IDLO AltVendor 00017h
00018h
A
_IDHI ID # 00018h
... ... ... ...
Offset Su b-Se ction Name Descri
p
tion(1)
00001-Fh Reserved Reserved for vendor-specific information
00010h CFI query identification string Command set ID and vendor data offset
0001Bh System interface information Device timing & voltage information
00027h Device geometry definition Flash device layout
P(3) Primary Intel-specific Extended Query Table Vendor-defined additional information specific
to the Primary Vendor Algorithm
Offset Length Description Add. Hex
Code Value
10h 3 Query-unique ASCII string “QRY“ 10: --51 "Q"
11: --52 "R"
12: --59 "Y"
13h 2 Primary vendor command set and control interface ID code. 13: --01
16-bit ID code for vendor-s
p
ecified al
g
orithms 14: --00
15h 2 Extended Query Table primary algorithm address 15: --0A
16: --01
17h 2 Alternate vendor command set and control interface ID code. 17: --00
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query Table address. 19: --00
0000h means none exists 1A: --00
P30
Datasheet August 2008
72 306666-12
Table 41: System Interface Information
Offset Length Description Add. Hex
Code Value
1Bh 1 1B: --17 1.7V
1Ch 1 1C: --20 2.0V
1Dh 1 1D: --85 8.5V
1Eh 1 1E: --95 9.5V
1Fh 1 “n” such that t
yp
ical sin
g
le word
p
ro
g
ram time-out = 2n
μ
-sec 1F: --08 256μs
20h 1 “n” such that t
yp
ical max. buffer write time-out = 2n
μ
-sec 20: --09 512μs
21h 1 “n” such that t
yp
ical block erase time-out = 2nm-sec 21: --0A 1s
22h 1 “n” such that t
yp
ical full chi
p
erase time-out = 2n m-sec 22: --00 NA
23h 1 “n” such that maximum word
p
ro
g
ram time-out = 2n times t
yp
ical 23: --01 512μs
24h 1 “n” such that maximum buffer write time-out = 2n times t
yp
ical 24: --01 1024μs
25h 1 “n” such that maximum block erase time-out = 2n times t
yp
ical 25: --02 4s
26h 1 “n” such that maximum chi
p
erase time-out = 2n times t
yp
ical 26: --00 NA
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VPP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
August 2008 Datasheet
Order Number: 306666-12 73
P30
A.1.4 Device Geometry Definition
Table 42: Device Geometry Definition
Offset Len
g
th Description Code
27h 1“n” such that device size = 2nin number of bytes 27: See table below
76543210
28h 2 — — — — x64 x32 x16 x8 28: --01 x16
15 14 13 12 11 10 9 8
————————29:--00
2Ah 2“n” such that maximum number of bytes in write buffer = 2n2A: --06 64
2B: --00
2Ch 1 2C:
2Dh 4 Erase Block Region 1 Information 2D:
bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:
30:
31h 4 Erase Block Region 2 Information 31:
bits 0–15 = y, y+1 = number of identical-size erase blocks 32:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 33:
34:
35h 4 Reserved for future erase block region information 35:
36:
37:
38:
See table below
See table below
See table below
See table below
Flash device interface code assignment:
"n" such that n+1 specifies the bit field that represents the flash
device width capabilities as described in the table:
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
3. Symmetrically blocked partitions have one blocking region
Address 64-Mbit
–B –T –B –T –B –T
27: --17 --17 --18 --18 --19 --19
28: --01 --01 --01 --01 --01 --01
29: --00 --00 --00 --00 --00 --00
2A: --06 --06 --06 --06 --06 --06
2B: --00 --00 --00 --00 --00 --00
2C: --02 --02 --02 --02 --02 --02
2D: --03 --3E --03 --7E --03 --FE
2E: --00 --00 --00 --00 --00 --00
2F: --80 --00 --80 --00 --80 --00
30: --00 --02 --00 --02 --00 --02
31: --3E --03 --7E --03 --FE --03
32: --00 --00 --00 --00 --00 --00
33: --00 --80 --00 --80 --00 --80
34: --02 --00 --02 --00 --02 --00
35: --00 --00 --00 --00 --00 --00
36: --00 --00 --00 --00 --00 --00
37: --00 --00 --00 --00 --00 --00
38: --00 --00 --00 --00 --00 --00
128-Mbit 256-Mbit
P30
Datasheet August 2008
74 306666-12
A.1.5 Numonyx-Specific Extend ed CFI Table
Table 43: Primary Vendor-Specific Extended CFI
Discrete
–
B
–
T
–- –- die 1 (B) die 2 (T) die 1 (T) die 2 (B)
112: --00 --00 --40 --00 --40 --00
512-Mbit
Address
–B –T
Offset(1) Length Descri
p
tion Hex
P = 10Ah (Optional flash features and commands)
A
dd. Code
V
alue
(P+0)h 3 Primary extended query table 10A --50 "P"
(P+1)h Unique ASCII string “PRI“ 10B: --52 "R"
(P+2)h 10C: --49 "I"
(P+3)h 1 Major version number, ASCII 10D: --31 "1"
(P+4)h 1 Minor version number, ASCII 10E: --34 "4"
(P+5)h 4 Optional feature and command support (1=yes, 0=no) 10F: --E6
(P+6)h bits 11–29 are reserved; undefined bits are “0.” If bit 31 is 110: --01
(P+7)h “1” then another 31 bit field of O
p
tional features follows at 111: --00
(P+8)h the end of the bit–30 field. 112:
bit 0 Chip erase supported bit 0 = 0 No
bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 Suspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 0 No
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant individual block locking supported bit 5 = 1 Yes
bit 6 Protection bits supported bit 6 = 1 Yes
bit 7 Pagemode read supported bit 7 = 1 Yes
bit 8 Synchronous read supported bit 8 = 1 Yes
bit 9 Simultaneous operations supported bit 9 = 0 No
bit 10 Extended Flash Array Blocks supported bit 10 = 0 No
bit 30 CFI Link(s) to follow bit 30
bit 31 Another "Optional Features" field to follow bit 31
(P+9)h 1 113: --01
bit 0 Pro
g
ram su
pp
orted after erase sus
p
end bit 0 = 1 Yes
(P+A)h 2 Block status register mask 114: --03
(P+B)h bits 2–15 are Reserved; undefined bits are “0” 115: --00
bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 Block Lock-Down Bit Status active bit 1 = 1 Yes
bit 4 EFA Block Lock-Bit Status register active bit 4 = 0 No
bit 5 EFA Block Lock-Down Bit Status active bit 5 = 0 No
(P+C)h 1 116: --18 1.8V
(P+D)h 1 117: --90 9.0V
See table below
See
table
below
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
VPP optimum program/erase supply voltage
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
August 2008 Datasheet
Order Number: 306666-12 75
P30
Table 44: Protection Register Information
Table 45: Burst Read Information
Offset(1) Len
g
th Description Hex
P = 10Ah ( Optional flash features and commands)
A
dd. Code
V
alue
(P+E)h 1 118: --02 2
(P+F)h 4 Protection Field 1: Protection Description 119: --80 80h
(P+10)h This field describes user-available One Time Programmable 11A: --00 00h
(P+11)h
(
OTP
)
Protection re
g
ister b
y
tes. Some are pre-pro
g
rammed 11B: --03 8 byte
(P+12)h 11C: --03 8 byte
(P+13)h 10 Protection Field 2: Protection Description 11D: --89 89h
(P+14)h 11E: --00 00h
(P+15)h 11F: --00 00h
(P+16)h 120: --00 00h
(P+17)h 121: --00 0
(P+18)h bits 40–47 = “n” ∴n = factory pgm'd groups (high byte) 122: --00 0
(P+19)h 123: --00 0
(P+1A)h 124: --10 16
(P+1B)h 125: --00 0
(P+1C)h 126: --04 16
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n” ∴ n = user pgm'd groups (low byte)
bits 64–71 = “n” ∴n = user
pg
m'd
g
rou
p
s
(
hi
g
h b
y
te
)
bits 72–79 = “n” ∴ 2n = user programmable bytes/group
with device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programmed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
Bits 0–31 point to the Protection register physical Lock-word
address in the Jedec-plane.
Following bytes are factory or user-programmable.
bits 32–39 = “n” ∴ n = factory pgm'd groups (low byte)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Offset(1) Len
g
th Description Hex
P = 10Ah (Optional flash features and commands)
A
dd. Code
V
alue
(P+1D)h 1 127: --03 8 byte
(P+1E)h 1 128: --04 4
(P+1F)h 1 129: --01 4
(P+20)h 1 Synchronous mode read capability configuration 2 12A: --02 8
(P+21)h 1 Synchronous mode read capability configuration 3 12B: --03 16
(P+22)h 1 Synchronous mode read capability configuration 4 12C: --07 Cont
Page Mode Read capability
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read
p
a
g
e buffer.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the
maximum number of continuous synchronous reads when
the device is configured for its maximum word width. A value
of 07h indicates that the device is capable of continuous
linear bursts that will output data until the internal burst
counter reaches the end of the device’s burstable address
space. This field’s 3-bit value can be written directly to the
Read Configuration Register bits 0–2 if the device is
configured for its maximum word width. See offset 28h for
word width to determine the burst data out
p
ut width.
P30
Datasheet August 2008
76 306666-12
Table 46: Partition and Erase Block Region In formation
Table 47: Partition Region 1 Information
Offset
(1) See table below
P = 10Ah Descri
p
tion
A
ddress
Bottom To
p
(
O
p
tional flash features and commands
)
Len Bot Top
(P+23)h (P+23)h
1 12D: 12D:Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
Offset
(1) S ee tab l e be lo w
P = 10Ah Descri
p
tion
A
ddress
Bottom To
p
(
O
p
tional flash features and commands
)
Len Bot Top
(P+24)h (P+24)h Data size of this Parition Region Information field 2 12E: 12E
(P+25)h (P+25)h (# addressable locations, including this field) 12F 12F
(P+26)h (P+26)h Number of identical partitions within the partition region 2 130: 130:
(P+27)h (P+27)h 131: 131:
(P+28)h (P+28)h 1 132: 132:
(P+29)h (P+29)h 1 133: 133:
(P+2A)h (P+2A)h 1 134: 134:
(P+2B)h (P+2B)h 1 135: 135:Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w/ contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1
block sizes) + (Type 2 blocks)x(Type 2 block sizes) +…+
(Type n blocks)x(Type n block sizes)
Number of program or erase operations allowed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other partitions while a
partition in this region is in Program mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
Simultaneous program or erase operations allowed in other partitions while a
partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
August 2008 Datasheet
Order Number: 306666-12 77
P30
Table 48: Partition Region 1 Information (continued)
Offset
(1) S ee tab l e be lo w
P = 10Ah Descri
p
tion
A
ddress
Bottom To
p
(
O
p
tional flash features and commands
)
Len Bot Top
(P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information 4 136: 136:
(P+2D)h (P+2D)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition 137: 137:
(P+2E)h (P+2E)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 138: 138:
(P+2F)h (P+2F)h 139: 139:
(P+30)h (P+30)h Partition 1 (Erase Block Type 1) 213A:13A:
(P+31)h (P+31)h Block erase cycles x 1000 13B: 13B:
(P+32)h (P+32)h 1 13C: 13C:
(P+33)h (P+33)h 1 13D: 13D:
Partition Region 1 (Erase Block Type 1) Programming Region Information 6
(P+34)h (P+34)h bits 0–7 = x, 2^x = Programming Region aligned size (bytes)13E: 13E:
(P+35)h (P+35)h bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7) 13F: 13F:
(P+36)h (P+36)h bits 16–23 = y = Control Mode valid size in bytes 140: 140:
(P+37)h (P+37)h bits 24-31 = Reserved 141: 141:
(P+38)h (P+38)h bits 32-39 = z = Control Mode invalid size in bytes 142: 142:
(P+39)h (P+39)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) 143: 143:
(P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information 4 144: 144:
(P+3B)h (P+3B)h bits 0–15 = y, y+1 = # identical-size erase blks in a partition 145: 145:
(P+3C)h (P+3C)h bits 16–31 = z, region erase block(s) size are z x 256 bytes 146: 146:
(P+3D)h (P+3D)h 147: 147:
(P+3E)h (P+3E)h Partition 1 (Erase Block Type 2) 2 148: 148:
(P+3F)h (P+3F)h Block erase cycles x 1000 149: 149:
(P+40)h (P+40)h 114A:14A:
(P+41)h (P+41)h 114B:14B:
Partition Region 1 (Erase Block Type 2) Programming Region Information 6
(P+42)h (P+42)h bits 0–7 = x, 2^x = Programming Region aligned size (bytes)14C: 14C:
(P+43)h (P+43)h bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7) 14D: 14D:
(P+44)h (P+44)h bits 16–23 = y = Control Mode valid size in bytes 14E: 14E:
(P+45)h (P+45)h bits 24-31 = Reserved 14F: 14F:
(P+46)h (P+46)h bits 32-39 = z = Control Mode invalid size in bytes 150: 150:
(P+47)h (P+47)h bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32) 151: 151:
Partition 1 (erase block Type 1) page mode and synchronous mode capabilities
defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
Partition 1 (erase block Type 1) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (erase block Type 2) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
Partition 1 (erase block Type 2) page mode and synchronous mode capabilities
defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host writes permitted (1=yes, 0=no)
bits 3–7 = reserved for future use
P30
Datasheet August 2008
78 306666-12
Table 49: Partition and Erase Block Region In formation
Address 64-Mbit
–
B
–
T
–
B
–
T
–
B
–
T
12D: --01 --01 --01 --01 --01 --01
12E: --24 --24 --24 --24 --24 --24
12F: --00 --00 --00 --00 --00 --00
130: --01 --01 --01 --01 --01 --01
131: --00 --00 --00 --00 --00 --00
132: --11 --11 --11 --11 --11 --11
133: --00 --00 --00 --00 --00 --00
134: --00 --00 --00 --00 --00 --00
135: --02 --02 --02 --02 --02 --02
136: --03 --3E --03 --7E --03 --FE
137: --00 --00 --00 --00 --00 --00
138: --80 --00 --80 --00 --80 --00
139: --00 --02 --00 --02 --00 --02
13A: --64 --64 --64 --64 --64 --64
13B: --00 --00 --00 --00 --00 --00
13C: --02 --02 --02 --02 --02 --02
13D: --03 --03 --03 --03 --03 --03
13E: --00 --00 --00 --00 --00 --00
13F: --80 --80 --80 --80 --80 --80
140: --00 --00 --00 --00 --00 --00
141: --00 --00 --00 --00 --00 --00
142: --00 --00 --00 --00 --00 --00
143: --80 --80 --80 --80 --80 --80
144: --3E --03 --7E --03 --FE --03
145: --00 --00 --00 --00 --00 --00
146: --00 --80 --00 --80 --00 --80
147: --02 --00 --02 --00 --02 --00
148: --64 --64 --64 --64 --64 --64
149: --00 --00 --00 --00 --00 --00
14A: --02 --02 --02 --02 --02 --02
14B: --03 --03 --03 --03 --03 --03
14C: --00 --00 --00 --00 --00 --00
14D: --80 --80 --80 --80 --80 --80
14E: --00 --00 --00 --00 --00 --00
14F: --00 --00 --00 --00 --00 --00
150: --00 --00 --00 --00 --00 --00
151: --80 --80 --80 --80 --80 --80
128-Mbit 256-Mbit
August 2008 Datasheet
Order Number: 306666-12 79
P30
Table 50: CFI Link Information
Offse
t
(1) Len
g
th Descri
p
tion Hex
P = 10Ah (Optional flash featu res and commands)
A
dd. Code
V
alue
(P+48)h 4 CFI Link Field bit definitions 152:
(P+49)h Bits 0–9 = Address offset (within 32Mbit segment) of referenced CFI table 153:
(P+4A)h Bits 10–27 = nth 32Mbit segment of referenced CFI table 154:
(P+4B)h Bits 28–30 = Memory Type 155:
Bit 31 = Another CFI Link field immediately follows
(P+4C)h 1 CFI Link Field Quantity Subfield definitions 156:
Bits 0–3 = Quantity field (n such that n+1 equals quantity)
Bit 4 = Table & Die relative location
Bit 5 = Link Field & Table relative location
Bits 6–7 = Reserved
See table below
See table below
Discrete
–B –T
–- –- die 1 (B) die 2 (T) die 1 (T) die 2 (B)
152: --FF --FF --10 --FF --10 --FF
153: --FF --FF --20 --FF --20 --FF
154: --FF --FF --00 --FF --00 --FF
155: --FF --FF --00 --FF --00 --FF
156: --FF --FF --10 --FF --10 --FF
Address 512-Mbit
–B –T
P30
Datasheet August 2008
80 306666-12
A.2 Flowcharts
Figure 34: Word Program Flowchart
Program
Suspend
Loop
Start
Write 0x40,
Word Address
Write Data,
Word Address
Read Status
Register
SR[7] =
Full Status
Check
(if desired)
Program
Complete
Suspend?
1
0
No
Yes
WORD PROGRAM PROCEDURE
Repeat for subsequent Word Program operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set to the Read Array
state.
Comments
Bus
Operation Command
Data = 0x40
Addr = Location to program
Write Program
Setup
Data = Data to program
Addr = Location to program
Write Data
Status register dataRead None
Check SR[7]
1 = WSM Ready
0 = WSM Busy
Idle None
(Setup)
(Confirm)
FULL STAT US CHECK PROCEDURE
Read Status
Register
Program
Successful
SR[3] =
SR[1] =
0
0
SR[4] =
0
1
1
1VPP Range
Error
Device
Protect Error
Program
Error
If an error is detected, clear the Status Register before
continuing operations - only the Clear Staus Register
command clears the Status Register error bits.
Idle
Idle
Bus
Operation
None
None
Command
Check SR[3]:
1 = VPP Error
Check SR[4]:
1 = Data Program Error
Comments
Idle None Check SR[1]:
1 = Block locked; operation aborted
August 2008 Datasheet
Order Number: 306666-12 81
P30
Figure 35: Program Suspend/Resume Flowchart
Read Status
Register
SR.7 =
SR.2 =
Read Array
Data
Program
Completed
Done
Reading
Program
Resumed
Read Array
Data
0
No
0
Yes
1
1
PROG RAM SUSPEND / RESUME PRO CEDURE
Write Program
Resume
Data = D0h
Addr = Suspended block (BA)
Bus
Operation Command Comments
Write Program
Suspend
Data = B0h
Addr = X
Standby
Check SR.7
1 = WSM ready
0 = WSM busy
Standby
Check SR.2
1 = Program suspended
0 = Program completed
Write Read
Array
Data = FFh
Addr = Block address to read (BA)
Read Read array data from block other than
the one being programmed
Read
Status register data
Initiate a read cycle to update Status
register
Addr = Suspended block (BA)
PGM _ SU S. WMF
Start
Write B0h
Any Address
Pr ogram Suspend
Read Status
Write 70 h
Write FFh
Read Ar ray
Write D0h
Any Address
Program Resume
Write FFh
Read Array
Write Read
Status
Data = 70h
Addr = Block to suspend (BA )
P30
Datasheet August 2008
82 306666-12
Figure 36: Buffer Program Flowchart
Start
Get Next
Target Address
Issue Write to Buffer
Command E8h and
Block Address
Read Status Register
(at Block Address)
Is WSM Ready?
SR.7 =
1 = Yes
Device
Supports Buffer
Writes?
Set Timeout or
Loop Counter
Timeout
or Count
Expired ?
Write Confirm D0h
and Block Address
Another Buffered
Programming?
Yes
No
No
Write Buffer Data,
Start Address
X = 0
Yes
0 = No
No
Yes
Use Single Word
Programming
Abort Bufferred
Program?
No
X = N?
Write Buffer Data,
Block Address
X = X + 1
Write to another
Block Address
Buffered Program
Aborted
No
YesYes
Write Word Count,
Block Address
1. Word count values on DQ
0
-DQ
7
are loaded into the Count
register. Count ranges for this device are N = 0000h to 0001Fh.
2. The device outputs the status register when read.
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
4. Align the start address on a Write Buffer boundary for
maximum programming performance (i.e., A
4
–A
0
of the start
address = 0).
5. The device aborts the Buffered Program command if the
current address is outside the original block address.
6. The Status register indicates an "improper command
sequence" if the Buffered Program command is aborted. Follow
this with a Clear Status Register command.
Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation to reset
the device to read array mode.
Bus
Operation
Standby
Read
Command
Write Write to
Buffer
Read
Standby
Comments
Check SR.7
1 = WSM Ready
0 = WSM Busy
Status register Data
CE# and OE# low updates SR
Addr = Block Address
Data = E8H
Addr = Block Address
SR.7 = Valid
Addr = Block Address
Check SR.7
1 = Device WSM is Busy
0 = Device WSM is Ready
Write Program
Confirm
Data = D0H
Addr = Block Address
Write
(Notes 1, 2)
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Block Address
Write
(Notes 3, 4)
Data = Write Buffer Data
Addr = Start Address
Write
(Notes 5, 6)
Data = Write Buffer Data
Addr = Block Address
Suspend
Program
Loop
Read Status Register
SR.7 =?
Full Status
Check if Desired
Program Complete
Suspend
Program
1
0
No
Yes
August 2008 Datasheet
Order Number: 306666-12 83
P30
Figure 37: BEFP Flowchart
NOTES:
1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally increments addressing).
B EF P Ex it
Repeat for subsequent blocks ;
After BEFP exit, a full Status Register check can
determine if any program error occurred;
See full Status Register check procedure in the
Word Program flowchart.
Write 0xFF to enter Read Array state .
Standby
Read
Bus
State Operation
Status
Register
Check
Exit
Status
Comments
Data = Status Register Data
Address = 1st Word Addr.
Check SR[7]:
0 = Exit Not Completed
1 = Exit Completed
BEFP Setup
Comments
Bus
State Operation
Write
(Note 1)
BEFP
Setup
Write BEFP
Confirm
Read Status
Register
Standby
BEFP
Setup
Done?
Write Unlock
Block
Data = 0x80 @ 1st Word
Address
Data = 0x80 @ 1st Word
Address1
Data = Status Register Data
Address = 1st Word Addr.
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
VPPH
applied to VPP
Standby
Error
Condition
Check
If SR[7] is set, check:
SR[3] set = VPP Error
SR[1] set = Locked Block
No (SR[0]=1)
Write Data @ 1st
Word Address
Last
Data?
Write 0xFFFF,
Address Not within
Current Block
Program
Done?
Read
Status Reg.
Yes (SR[0]=0)
Y
No (SR[7]=0)
Full Status Check
Procedure
Program
Complete
Read
Status Reg.
BEFP
Exited?
Yes (SR[7]= 1)
Start
Write 80h @
1st Word Address
VPP applied
Block Unlocked
Write D0h @
1st Word Address
BEFP Setup
Done?
Read
Status Reg.
No (SR[7]=1)
Exit
N
Program & Verify Phase Ex it PhaseSetup Phase
BUFFERED ENHANCED FACTORY PROGRA MM ING (BEFP) PROC EDURE
Check
X = 32?
Initialize Count:
X = 0
Increment Count:
X = X+1
Y
N
Check VPP, Lock
errors (SR[3,1])
Yes (SR[7]=0)
BEFP Setup delay
Data Stream
Ready?
Read
Status Reg.
Yes (SR[0]=0)
No (SR[0]=1)
BEFP Program & Verify
Comments
Bus
State
Write
(note 2)
Load
Buffer
Standby Increment
Count
Standby Initialize
Count
Data = Data to Program
Address = 1st Word Addr.
X = X+1
X = 0
Read Status
Register
Standby Program
Done?
Data = Status Reg. Data
Address = 1st Word Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
Write Exit Prog &
Verify Phase
Data = 0xFFFF @ address
not in current block
Standby Last
Data?
No = Fill buffer again
Yes = Exit
Standby Buffer
Full?
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Read
Standby
Status
Register
Data Stream
Ready?
Data = Status Register Data
Address = 1st Word Addr.
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Operation
P30
Datasheet August 2008
84 306666-12
Figure 38: Block Erase Flowchart
Start
FULL ERASE STATUS CHECK PROCEDURE
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Write 0xFF after the last operation to enter read array mode.
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
No
Suspend
Erase
1
0
0
0
1
1,1
1
1
0Yes
Suspend
Erase
Loop
0
Write 0x20,
Block Address
Write 0xD0,
Block Address
Read Status
Register
SR[7] =
Full Erase
Status Check
(if desired)
Block Erase
Complete
Read Status
Register
Block Erase
Successful
SR[1] = Block Locked
Error
BLOCK ERASE PROCEDURE
Bus
Operation Command Comments
Write
Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write Erase
Confirm
Data = 0xD0
Addr = Block to be erased (BA)
Read None Status Register data.
Idle None
Check SR[7]:
1 = WSM ready
0 = WSM busy
Bus
Operation Command Comments
SR[3] = VPP Range
Error
SR[4,5] = Command
Sequence Error
SR[5] = Block Erase
Error
Idle None Check SR[3]:
1 = VPP Range Error
Idle None Check SR[4,5]:
Both 1 = Command Sequence Error
Idle None Check SR[5]:
1 = Block Erase Error
Idle None
Check SR[1]:
1 = Attempted erase of locked block;
erase aborted.
(Block Erase)
(Erase Confirm)
August 2008 Datasheet
Order Number: 306666-12 85
P30
Figure 39: Erase Suspend/Resume Flowchart
Erase
Completed
Read Array
Data
0
0
No
Read
1
Program
Program
Loop
Read Array
Data
1
Yes
Start
Read Status
Register
SR. 7 =
SR. 6 =
Erase
Resumed
Read or
Program ?
Done?
Write
Write
Standby
Standby
Write
Erase
Suspend
Read Array
or Program
Program
Resume
Data = B0h
Addr = Same partition address as
above
Data = FFh or 40h
Addr = Block to program or read
Check SR.7
1 = WSM ready
0 = WSM busy
Check SR.6
1 = Erase suspended
0 = Erase completed
Data = D0h
Addr = Any address
Bus
Operation Command Comments
Read
Status register data. Toggle CE# or
OE# to update Status register
Addr =X
Read or
Write
Read array or program data from/to
block other than the one being erased
ERASE SUSPEND / RESUME PROCEDURE
ER AS_ SU S .WM F
Write B0h
Any Address
Erase Suspend
Write 70h
Any Address
R ead Status
Write D0h
Any Address
Er ase Resume
Write 70h
Any Address
R ead Status
Write FFh
Any Addres
Read Ar ray
Write Read
Status
Data = 70h
Addr = Any device address
P30
Datasheet August 2008
86 306666-12
Figure 40: Block Lock Operations Flowchart
No
Op tion al
Start
Write 60 h
Block Address
Write 90 h
Read Block Lock
Status
Locking
Change?
Lock Change
Complete
Write 01,D0,2Fh
Block Address
Write FFh
Any Address
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Standby
(Optional)
Write
Lock
Setup
Lock,
Unlock, or
Lockdown
Confirm
Read ID
Plane
Block Lock
Status
Read
Array
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Data = 01h (Lock block)
D0h (Unlock block)
2Fh (Lockdown block)
Addr = Block to lock/unlock/lock-down (BA)
Data = 90h
Addr = Block address offset +2 (BA+2)
Block Lock status data
Addr = Block address offset +2 (BA+2)
Confirm locking change on DQ
1
, DQ
0
.
(See Block Locking State Transitions Table
for valid combinations.)
Data = FFh
Addr = Block address (BA)
Bus
Operation Command Comments
LO CKING O P ERATIO NS P ROCEDURE
LOCK_OP.WMF
Lock Confirm
Lock Setup
Read ID Plane
Read Array
August 2008 Datasheet
Order Number: 306666-12 87
P30
A.3 Write State Machine
Figure 42 thr o u gh Figure 47 show the command state transitions (Next State Table)
based on incom in g commands . Only one partiti on ca n be active ly pro g rammin g or
erasing at a time. Each partition stays in its last read state (Read Array, Read Device
ID , Read CFI or Read Status Register) until a new command changes it. The next WSM
state does not depend on the partition’s output state.
Figure 41: Protection Register Programming Flowchart
FULL STAT US CHECK PROCEDURE
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
Repeat for subsequent programming operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
Only the Clear Staus Register command clears SR[1, 3, 4].
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
1
0
1
1
1
PROTECTION REGISTER PROGRAMMING PROCEDURE
Start
Write 0xC0,
PR Address
Write PR
Address & Data
Read Status
Register
SR[7] =
Full Status
Check
(if desired)
Program
Complete
Read Status
Register Data
Program
Successful
SR[3] =
SR[4] =
SR[1] =
VPP Range Error
Program Error
Register Locked;
Program Aborted
Idle
Idle
Bus
Operation
None
None
Command
Check SR[3]:
1 =VPP Range Error
Check SR[4]:
1 =Programming Error
Comments
Write
Write
Idle
Program
PR Setup
Protection
Program
None
Data = 0xC0
Addr = First Location to Program
Data = Data to Program
Addr = Location to Program
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Bus
Operation Command Comments
Read None Status Register Data.
Idle None Check SR[1]:
1 =Block locked; operation aborted
(Program Setup)
(Confirm Data)
0
0
0
P30
Datasheet August 2008
88 306666-12
Figure 42: Write State Machine—Next State Table (Sheet 1 of 6)
Read
Array (2)
Word
Program (3,4)
Buffered
Program
(BP)
Erase
Setup (3,4)
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
BE Confirm,
P/E
Resume,
ULB,
Confirm (8)
BP / Prg /
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock, Unlock,
Lock-down,
CR setup (4)
(FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)
Ready Program
Setup BP Setup Erase
Setup BEFP Setup Lock/CR
Setup
Ready
(Unlock
Block)
Setup
Busy
Setup
Busy
Word
Program
Suspend
Suspend
Word
Program
Busy
Setup
BP Load 1
BP Load 2
BP
Confirm BP Busy
BP Busy BP Suspend
BP
Suspend BP Busy
Setup Erase Busy
Busy Erase
Suspend
Suspend Erase
Suspend
Word
Program
Setup in
Erase
Suspend
BP Setup in
Erase
Suspend
Erase Busy
Lock/CR
Setup in
Erase
Suspend
BP Suspend
Erase
BP Busy
Erase Busy
Erase Suspend Erase Suspend
Ready (Error)
Erase Busy
BP Suspend
Ready (Error)
Word
Program
Program Busy
Word Program Suspend
Word Program Busy
OTP
Ready (Lock Error)
Ready Ready
Ready (Lock Error)
OTP Busy
Current Chip
State (7)
Command Input to Chip and resulting Chip Next State
BP
BP Busy
Lock/CR Setup
BP Load 2
Ready (Error)Ready (Error)
Word Program Busy
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
Word Program Suspend
BP Load 1
August 2008 Datasheet
Order Number: 306666-12 89
P30
Figure 43: Write State Machine—Next State Table (Sheet 2 of 6)
Setup
Busy
Word
Program
Suspend in
Erase
Suspend
Suspend
Word
Program
Busy in
Erase
Suspend
Setup
BP Load 1
BP Load 2
BP
Confirm
BP Busy in
Erase
Suspend
BP Busy
BP Suspend
in Erase
Suspend
BP
Suspend
BP Busy in
Erase
Suspend
Erase
Suspend
(Unlock
Block)
Setup
BEFP
Loading
Data (X=32)
Erase Suspend (Error)
Erase Suspend (Lock Error [Botch])
Ready (Error) Ready (Error)
BP Suspend in Erase Suspend
Ready (Error in Erase Suspend)
BP Busy in Erase Suspend
BP Suspend in Erase Suspend
BP Busy in Erase Suspend
Word Program Busy in Erase Suspend
Word
Program in
Erase
Suspend
Word Program Busy in Erase Suspend
Word Program Suspend in Erase Suspend
Lock/CR Setup in Erase
Suspend Erase Suspend (Lock Error)
BP Confirm if Data load into Program Buffer is complete; Else BP Load 2
BP in Erase
Suspend
BP Load 2
Word Program Busy in Erase Suspend Busy
Word Program Suspend in Erase Suspend
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands treated as data. (7)
BEFP
Busy
Buffered
Enhanced
Factory
Program
Mode
BP Load 1
Read
Array
(
2
)
Word
Program (3,4)
Buffered
Program
(BP)
Erase
Setup (3,4)
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
BE Confirm,
P/E
Resume,
ULB,
Confirm (8)
BP / Prg /
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock, Unlock,
Lock-down,
CR setup (4)
(FFH) (10H/40H) (E8H) (20H) (80H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)
Cu rr ent Ch i p
State (7)
Com m a nd I nput to Chi p a nd r es ulting Chip Next State
P30
Datasheet August 2008
90 306666-12
Figure 44: Write State Machine—Next State Table (Sheet 3 of 6)
Setup
Busy
Setup
Busy
Suspend
Setup
BP Load 1
BP Load 2
BP
Confirm
BP Busy
BP
Suspend
Setup
Busy
Suspend
Erase
Word
Program
OTP
Ready
Current Chip
State (7)
BP
Lock/CR Setup
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confirm (8)
Write RCR
Confirm (8)
Block Address
(?WA0) 9
Illegal Cmds or
BEFP Data (1)
(C0H) (01H) (2FH) (03H) (XXXXH) (all other codes)
OTP
Setup
Ready
(Lock
Error)
Ready
(Lock
Block)
Ready
(Lock Down
Blk)
Ready
(Set CR)
Ready
N/A
Ready
Ready (BP Load 2 BP Load 2
Ready
BP Confirm if
Data load into
Program Buffer is
complete; ELSE
BP Load 2
Ready (Error)
(Proceed if
unlocked or lock
error)
Ready (Error)
Ready
Ready
N/A
BP Confirm if Data load into Program Buffer is
complete; ELSE BP load 2
Ready (Error)
BP Busy
Erase Busy
Word Program Suspend
BP Load 1
BP Load 2
OTP Busy
Word Program Busy
Word Program Busy
WSM
Operation
Completes
Comman d Input to Chip and resultin
g
Chip Next State
N/A
Ready (Lock Error)
Ready
BP Suspend
Ready (Error)
Erase Suspend
N/A
N/A
August 2008 Datasheet
Order Number: 306666-12 91
P30
Figure 45: Write State Machine—Next State Table (Sheet 4 of 6)
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confirm (8)
Write RCR
Confirm (8)
Block Address
(?WA0) 9
Illegal Cmds or
BEFP Data (1)
(C0H) (01H) (2FH) (03H) (XXXXH) (all other codes)
WSM
Operation
Completes
Command Input to Chip and resulting Chip Next State
Current Chip
State (7)
NA
Erase Suspend
N/A
Ready (BP Load 2 BP Load 2
Ready
BP Confirm if
Data load into
Program Buffer is
complete; Else
BP Load 2
Ready (Error)
(Proceed if
unlocked or lock
error)
Ready (Error)
Erase Suspend
Erase
Suspend
(Lock
Error)
Erase
Suspend
(Lock
Block)
Erase
Suspend
(Lock Down
Block)
Erase
Suspend
(Set CR)
Ready (BEFP
Loading Data) Ready (Error)
BEFP Program and Verify Busy (if Block Address
given matches address given on BEFP Setup
command). Commands treated as data. (7)
BP Load 1
Ready (Error)
BP Confirm if Data load into Program Buffer is
complete; Else BP Load 2
Ready (Error in Erase Suspend)
Word Program Suspend in Erase Suspend
BP Load 2
Ready
Word Program Busy in Erase Suspend Busy
Word Program Busy in Erase Suspend
BEFP Busy
Ready
Erase Suspend (Lock Error) N/A
BP Busy in Erase Suspend
BP Suspend in Erase Suspend
N/A
Setup
Busy
Suspend
Setup
BP Load 1
BP Load 2
BP
Confirm
BP Busy
BP
Suspend
Setup
BEFP
Busy
Buffered
Enhanced
Factory
Program
Mode
Lock/CR Setup in Erase
Suspend
BP in Erase
Suspend
Word
Program in
Erase
Suspend
P30
Datasheet August 2008
92 306666-12
Figure 46: Write State Machine—Next State Table (Sheet 5 of 6)
Read
Array
(
2
)
Word
Program
Setup (3,4)
BP Setup Erase
Setup (3,4)
Buffered
Enhanced
Factory Pgm
Setup (3, 4)
BE Confirm,
P/E
Resume,
ULB Confirm
(8)
Program/
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock, Unlock,
Lock-down,
CR setup (4)
(FFH) (10H/40H) (E8H) (20H) (30H) (D0H) (B0H) (70H) (50H) (90H, 98H) (60H)
Status Read
Command Input to Chip and resulting Output Mux Next State
Output Next State Table
Status Read
Output mux
does not
change.
Status
Read
ID Read
Status Read
Ready,
Erase Suspend,
BP Suspend
Status Read
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
Output does not change. Status Read
BEFP Setup,
BEFP Pgm & Verify
Busy,
Erase Setup,
OTP Setup,
BP: Setup, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Current chip state
OTP Busy
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Word Pgm Busy in
Erase Suspend,
Pgm Suspend In
Erase Sus
p
end
Read Array
August 2008 Datasheet
Order Number: 306666-12 93
P30
Notes:
1. "Illegal commands" incl ude co mmands outsid e of the all owed command set (allo wed commands: 40H [ pgm], 20H [er ase],
etc.)
2. If a "Read Array" is attempted from a busy partition, the result will be invalid data. The ID and CFI data are located at
different locations in the address map.
3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same partition address, or unexpected results will
occur.
4. To protect memory contents against erroneous command sequences, there are specific instances in a multi-cycle
command sequence in which the se cond cycle wil l be i gnored. For example, when th e device is p rogra m suspended and an
erase setup command (0x20) is given followed by a confirm/resume command (0xD0), the second command will be
ignored because it is unclear whether the user intends to erase the block or resume the program operation.
5. The C l ea r Status c omman d only c l ear s th e er ror b it s in the stat u s re gi s te r i f t he d ev i ce i s not in the f ol low i ng m o de s: WS M
running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes).
6. BEFP writes are only allowed when the status register bit #0 = 0, or else the data is ignored.
Figure 47: Write State Machine—Next State Table (Sheet 6 of 6)
OTP Busy
BP Busy,
Word Program
Busy,
Erase Busy,
BP Busy
BP Busy in Erase
Suspend
Word Pgm
Suspend,
Word Pgm Busy in
Erase Suspend,
Pgm Suspend In
Erase Sus
p
end
BEFP Setup,
BEFP Pgm & Verify
Busy,
Erase Setup,
OTP Setup,
BP: Setup, Load 1,
Load 2, Confirm,
Word Pgm Setup,
Word Pgm Setup in
Erase Susp,
BP Setup, Load1,
Load 2, Confirm in
Erase Suspend
Current chip state
Ready,
Erase Suspend,
BP Suspend
Lock/CR Setup,
Lock/CR Setup in
Erase Susp
OTP
Setup (4)
Lock
Block
Confirm (8)
Lock-Down
Block
Confirm (8)
Write CR
Confirm (8)
Block Address
(?WA0)
Illegal Cmds or
BEFP Data (1)
(C0H) (01H) (2FH) (03H) (FFFFH) (all other codes)
WSM
Operation
Completes
Output does
not change.
A
rray
Read Status Read
Array Read Output does not
change.
Output does not change.
Status
Read
Status Read
Status Read
Command Input t o C hip and re sult ing Output Mux Next Stat e
Output Next State Table
P30
Datasheet August 2008
94 306666-12
7. The "current state" is t hat o f the " chip " an d not of the "p artit ion" ; Each par ti tio n "reme mber s" which outp ut ( Arr a y, ID/CFI
or Status) it wa s last pointed to on the last ins truction to the "c hip", but the next state of the chip does not depend on
where the par tition's output mux is prese ntly pointing to.
8. Confirm commands (Lock Block, Unlock Block, Lock- Down Block, Configuration Register) perform the operation and then
move to the Ready State.
9. WA0 refers to the block address latched during the first write cycle of the current operation.
August 2008 Datasheet
Order Number: 306666-12 95
P30
Appendix B Conve ntion s - Addi tional Informat ion
B.1 Conventions
B.2 Acronyms
VCC: Signal or voltage connection
VCC: Signal or voltage level
0x: Hexadecimal num ber prefix
0b: Binary number prefix
SR[4]: Denotes an individual register bit.
A[15:0]: Denotes a group of similarly named signals, such as address or data bus.
A5: Denotes one element of a signal group membership, such as an individual address bit.
Bit: Binary unit
Byte: Eight bits
Word: Two bytes, or sixteen bits
Kbit: 1024 bits
KByte: 1024 bytes
KWord: 1024 words
Mbit: 1,048,576 bits
MByte: 1,048,576 bytes
MWord: 1,048,576 words
BEFP: Buffer Enhanced Factory Programming
CUI: Command User Interface
MLC: Multi-Level Cell
OTP: One-Time Programmable
PLR: Protection Lock Register
PR: Protection Register
RCR: Read Configuration Register
RFU: Reserved for Future Use
SR: Status Register
WSM: Write State Machine
P30
Datasheet August 2008
96 306666-12
B.3 Nomenclature
B.4 Additional Documentation
Block : A group of bits, bytes, or words within the flash memory array that erase
simultaneously. The P30 has two block sizes: 32 KByte and 128 KByte.
Main block : An arr ay block that is usually used to store code and/or data. Main blocks are large r
than parameter blocks.
Parame ter block : An array block that may be used to store fre quently chan ging data or small system
parameters that traditionally would be stored in EEPROM.
Top pa rame te r devic e : A dev ice with its parameter blocks located at the highest physical address of its
memory map.
Bottom parameter device : A device with its parameter blocks located at the lowest physical address of its
memory map.
Order/Document
Number Document/Tool
309045 P30 Family Specification Update
308291 Schematic Review Checklist for Numonyx™ StrataFlash® Embedded Memory (P30)
300783 Using Numonyx™ Flash Memory: Asynchronous Page Mode and Synchronous Burst Mode
290667 Numonyx™ StrataFlash® Memory (J3) Datasheet
306667 Migration Guide for Numonyx™ StrataFlash® Memory (J3) to Numonyx™ StrataFlash® Embedded
Memory (P30/P33) Application Note 812
314750 Numonyx™ Strata Flash® Memory (P30) to Numonyx™ StrataFlash® Embedded Memory (P33)
Co nversion Guide A pplication Note 86 7
290737 Numonyx™ StrataFlash® Synchronous Memory (K3/K18) Datasheet
306669 Migration Guide for Numonyx™ StrataFlash® Synchronous Memory (K3/K18) to Numonyx™
StrataFlash® Embedded Memory (P30) Application Note 825
290701 Nu monyx™ Wireless Flash Memory (W18) Datasheet
290702 Nu monyx™ Wireless Flash Memory (W30) Datasheet
252802 Nu monyx™ Flash Memory Design for a Stacked Chip Scale Package (SCSP)
298161 Nu monyx™ Flash Memory Chip Scale Package User’s Guide
253418 Numonyx™ Wireless Communications and Computing Package User's Guide
296514 N umonyx™ Small Outline Package Guide
297833 Numonyx™ Flash Data Integrator (Numonyx™ FDI) User Guide
298136 Numonyx™ Persistent Storage Manager (Numonyx™ PSM) User Guide
306668 Migration Guide for Spansion* S29GLxxxN to Numonyx™ StrataFlash® Embedded Memory (P30/P33)
Application Note 813
Note: Contact your local Numonyx or distribution sales office or visit Numonyx’s World Wide Web home page at http://
www.numonyx.com for technical documentation, tools, or the most current information on Numonyx™ Flash Memory.
August 2008 Datasheet
Order Number: 306666-12 97
P30
Appendix C Revision History
Revision Date Revision Description
April 2005 -001 Initial Release
August 2005 -002
Revised discrete memo ry maps in Section 1.4, “Memory Maps” on
page 7
Added memory maps for 512-Mbit top parameter devices in Section 1.4,
“Me mory Maps” on page 7
Fixed size of Programming Region for 256-Mbit to be 8-Mbit in Secti on 1.4 ,
“Me mor y Maps” on pag e 7 and Section 8.0, “Progra m Operation”
on page 29
Removed power supply sequencing requirement in Section 12.1, “P ower-Up
and Power-Down” on page 50
Updated cond itions for Table 29, “Capac it ance ” o n pa ge 56
Updated CFI table in Appendix A, “Common Flash Interface Tables”
September 2005 -003
Added note to Tabl e 14, “Device ID c o des” o n pa ge 28 for stacked
Device ID codes
Sync hronou s burst read ope r ati on is curren tl y not su pporte d for th e TSOP p acka ge
Updated 512-Mbit Easy BGA Ball Height (symbol A1) in Figure 2, “ E asy BGA
Mecha n ica l Spec if ica tions” o n pa ge 11
November 2005 -004 Updated read access speed for 265M TSOP package
February 2006 -005 Removed all references to 1 Gigabit.
April 2006 -006
• Added 52 MHz capabilities,
• Added TSOP Package information for 512 Mb throughout the document,
•Added
Section 1.3, “Virtua l C hip Ena ble Description” on
page 6,
• Modified figures in Section 4.1, “Dual-Die Configurations” on
page 21,
•Modified
Table 5 , “512-M bit Top and Bot tom Parameter
M em ory M a p ( E as y B GA and QUAD + SC S P)” o n page 9,
• Modified No tes 5 & 6 to Reset Specifications table in Section 12.2,
“Reset Specifications” on page 50,
• Added additional note on 512 Mb capability in Table 17, “Selectable
OTP Block Mapping” on page 3 9.
May 2006 -007
• Updated the following tables to 52 MHz: Table 30, “AC Read
Specifications for 64/128- Mbit Densities” on page 56 and
Table 31, “AC Read Specif ica tions for 256/512-Mbi t
Densities” on page 57.
May-2006 -008 • Added notes 1, 2, and 3 to Tabl e 29, “Capac i tance” on page 56.
June - 2007 -009
• Correct typos and add clarifications
• Enabled specific burst operation on TSOP packages.
• Updated device commands table.
• Updaed description on synchronous burst operation.
• Added EOWL description.
• Updated flowcharts
November 2007 -010 • Updated for 65nm lithography
• Added W602 - Erase to Suspend
November 2007 11 • Applied Numonyx branding.
August 2008 12 • Corrected si ngle word (65 nm) progr am time from 125 (typ) and 150 (m ax) to
150 (typ) and 456 (max) in Tab l e 34 , “Pr o gra m and E rase
Specifications” on page 67.
