INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications 74HC/HCT74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Feb 23 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. FEATURES * Output capability: standard * ICC category: flip-flops GENERAL DESCRIPTION Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT74 are dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC tPHL/ tPLH propagation delay HCT CL = 15 pF; VCC = 5 V nCP to nQ, nQ 14 15 ns nSD to nQ, nQ 15 18 ns nRD to nQ, nQ 16 18 ns fmax maximum clock frequency 76 59 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per flip-flop 24 29 pF notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V 1998 Feb 23 2 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION VERSION 74HC(T)74N DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 74HC(T)74D SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74HCT74DB SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 74HCT74PW TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 13 1RD, 2RD asynchronous reset-direct input (active LOW) 2, 12 1D, 2D data inputs 3, 11 1CP, 2CP clock input (LOW-to-HIGH, edge-triggered) 4, 10 1SD, 2SD asynchronous set-direct input (active LOW) 5, 9 1Q, 2Q true flip-flop outputs 6, 8 1Q, 2Q complement flip-flop outputs 7 GND ground (0 V) 14 VCC positive supply voltage Fig.1 Pin configuration. 1998 Feb 23 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 FUNCTION TABLE INPUTS OUTPUTS SD RD CP D Q Q L H X X H L H L X X L H L L X X H H INPUTS OUTPUTS SD RD CP D Qn+1 Qn+1 H H L L H H H H H L Note 1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH CP transition Qn+1 = state after the next LOW-to-HIGH CP transition Fig.4 Functional diagram. Fig.5 Logic diagram (one flip-flop). 1998 Feb 23 4 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: flip-flops AC CHARACTERISTICS GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH tW tW trem tsu th fmax propagation delay nCP to nQ, nQ -40 to +85 typ. max. min. max -40 to +125 min. UNIT VCC WAVEFORMS (V) max. 47 175 220 265 17 35 44 53 4.5 14 30 37 45 6.0 propagation delay nSD to nQ, nQ 50 200 250 300 18 40 50 60 14 34 43 51 propagation delay nRD to nQ, nQ 52 200 250 300 19 40 50 60 15 34 43 51 19 75 95 110 7 15 19 22 6 13 output transition time clock pulse width HIGH or LOW set or reset pulse width LOW removal time set or reset set-up time nD to nCP hold time nCP to nD maximum clock pulse frequency 1998 Feb 23 16 ns ns 2.0 2.0 Fig.7 4.5 6.0 ns 2.0 Fig.7 4.5 6.0 ns 2.0 Fig.6 4.5 19 6.0 80 19 100 120 16 7 20 24 14 6 17 20 80 19 100 120 16 7 20 24 4.5 14 6 17 20 6.0 30 3 40 45 6 1 8 9 4.5 5 1 7 8 6.0 60 6 75 90 12 2 15 18 4.5 10 2 13 15 6.0 ns 2.0 Fig.6 4.5 6.0 ns ns ns 2.0 2.0 2.0 3 -6 3 3 3 -2 3 3 4.5 3 -2 3 3 6.0 6.0 23 4.8 4.0 30 69 24 20 4.5 35 82 28 24 6.0 5 Fig.6 ns MHz 2.0 2.0 Fig.7 Fig.7 Fig.6 Fig.6 Fig.6 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: flip-flops Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT UNIT LOAD COEFFICIENT nD 0.70 nRD 0.70 nSD 0.80 nCP 0.80 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. -40 to +85 -40 to +125 typ. max. min. max. min. max. UNIT VCC WAVEFORMS (V) tPHL/ tPLH propagation delay nCP to nQ, nQ 18 35 44 53 ns 4.5 Fig.6 tPHL/ tPLH propagation delay nSD to nQ, nQ 23 40 50 60 ns 4.5 Fig.7 tPHL/ tPLH propagation delay nRD to nQ, nQ 24 40 50 60 ns 4.5 Fig.7 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.6 tW clock pulse width HIGH or LOW 18 9 23 27 ns 4.5 Fig.6 tW set or reset pulse width LOW 16 9 20 24 ns 4.5 Fig.7 trem removal time set or reset 6 1 8 9 ns 4.5 Fig.7 tsu set-up time nD to nCP 12 5 15 18 ns 4.5 Fig.6 th hold time nCP to nD 3 -3 3 3 ns 4.5 Fig.6 fmax maximum clock pulse frequency 27 54 22 18 MHz 4.5 Fig.6 1998 Feb 23 6 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency. handbook, full pagewidth VM(1) nCP INPUT trem nSD INPUT VM(1) trem tW VM(1) nRD INPUT tPLH tPHL VM(1) nQ OUTPUT tPHL (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. tW tPLH VM(1) nQ OUTPUT MGL350 Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nSD to nCP removal time. 1998 Feb 23 7 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 PACKAGE OUTLINES DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.020 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.10 0.30 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT27-1 050G04 MO-001AA 1998 Feb 23 EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-03-11 8 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp 1 L 7 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.010 0.057 0.004 0.049 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.050 0.028 0.024 0.01 0.01 0.004 0.028 0.012 inches 0.069 0.244 0.039 0.041 0.228 0.016 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06S MS-012AB 1998 Feb 23 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 9 o 8 0o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 2.0 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.4 0.9 8 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 1998 Feb 23 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 96-01-18 MO-150AB 10 o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 1998 Feb 23 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 94-07-12 95-04-04 MO-153 11 o Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: DIP * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. * The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. * Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). REPAIRING SOLDERED JOINTS During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. * Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. SO, SSOP and TSSOP A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. REPAIRING SOLDERED JOINTS Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. 1998 Feb 23 12 Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive-edge trigger 74HC/HCT74 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Feb 23 13