PIC18C242T-I/SO - Microchip Technology

 2002 Microchip Technology Inc. DS80058H-page 1

MPIC18CXX2

The PIC1 8CXX2 (Rev. B) p arts you have received co n-

form functionally to the Device Data Sheet

(DS39026C), except for the anomalies described

below.

All the problems listed here will be addressed in future

revision s of the P IC18CXX2 silicon.

1. Module: CPU

Using the LFSR ins truc ti on to lo ad a value into the

specified FSR register, may also corrupt a RAM

location.

Work around

Do not use the LFSR instruction. The use of MOVLW

and MOVWF instructions can be implemented to

load the FSR registers. The WREG register may

need to be saved before these operations and

restored afte rw ards .

EXAMPLE 1: DEFINED OPERATION

EXAMPLE 2: WORK AROUND

2. Module: CCP

When the CCP module is configured to

Compare mode toggle output pin

(CCPxCON = b’00xx0010’), unexpected pin

operation may be observed.

When the timer used for the CCP module time-

base is confi gured to ha ve a pre scale rat io g reater

than 1:1, the output on the CCP pin will toggle the

prescaled number of times for each compare

match. That is, for a n:1 timer prescale ratio, the

CCP output pin will toggle n times at each com-

pare match. The toggle occurs each instruction

cycle (TCY).

Work around

The prescale ratio for the timer used as the CCP

module time-base must be 1:1. If a longer com-

pare time is needed, the timer must be running in

Timer mode or Synchronized Counter mode

(external clock source).

Date Codes that pertain to this issue:

ALL

3. Module: Oscillator

In-Circuit Serial ProgrammingTM (ICSPTM) may

become unpredictable when a free-running clock

source is pres en t on OSC1.

When entering ICSP mode, the PIC18C452

switches from OSC1 to RB6 for its external clock

source. Refer to the PIC18CXXX Programming

Specification (DS39028) for additional informatio n.

If OSC1 is high at th e time , a hi gh-t o-low tra nsitio n

occurs upon the transition to RB6.The ICSP logic

interprets this as a clock, and advances the inter-

nal clock logic to Q2. This causes an unrecover-

able mismatch between ICSP logic and the clock.

Work around

Before enteri ng ICSP mode, OSC1 mu st be driven

to and held in a low state. This must occur before

changing states on MCLR/VPP, RB6 and RB7.

LFSR FSR1, Pointer

;

; Optionally save the WREG register

;

MOVLW HIGH (Pointer)

MOVWF FSR1H

MOVLW LOW (Pointer)

MOVWF FSR1L

;

; Optionally restore the WREG register

;

Note: When the manufacture date of a newer

version of silicon is in production, the last

date where this issue may occur, will be

specified.

PIC18CXX2 Rev. B Silicon/Data Sheet Errata

Note: As with any windowed EPROM device, please cover the window at all times, except when erasing.

PIC18CXX2

DS80058H-page 2  2002 Microchip Technology Inc.

4. Module: CCP (Compare Mode)

The Compare mode may not operate as expected

when configuring the compare match to drive the

I/O pin low (CCPx M<3:0> = 1001).

When the CCP module is changed to compare

output low (CCPxM<3:0> = 1001) from any other

non- compare C CP mo de, the I/O p in wil l imme di-

ately be driven low, regardless of the state of the

I/O data latch. The pin will remain low when the

compare match occurs (see Table 1).

However, when the CCP module is changed to

compare output high (CCPxM<3:0> = 1000) from

any other CCP mode, the I/O pin will immediately

be driven low, regardless of the state of the I/O

data latch. The pin will be driven high when the

compare match occurs.

TABLE 1: COMPARE OUTPUT LOW

SWITCHING

Work around

To have the I/O pin high until the compare match

low occurs, force a compare matc h hi gh to get the

I/O pin into the high state, then reconfigure the

compare match to force the I/O low when the

compare condition occurs.

5. Module: Timer1 and Timer3

When the prescaler select bits (bits 5:4 of the

T1CON or T3CON registers) are modified, the

timer may inadvertently increment. This can occur

even if the timer is in the OFF state. Changing the

prescaler may cause clock glitches, which may

cause the counter to increment improperly.

Work around

Always re-initialize the timer registers (either

TMR1H a nd TMR 1L, or T MR3H and TMR 3L) aft er

changing the prescaler bits of registers T1CON or

T3CON.

As an alternative, store the timer value before chang-

ing the prescaler bits of the timer control registers,

and restore the timer value after changing the bits.

6. Module: I/O (Parallel Slave Port)

The Input Buffer Status bit of the TRISE register

(TRISE<7>) may be inadvertently cleared, even

when the PORTE input buffer has not been read.

This will occur only when the following two condi-

tions occur simultaneously:

• The four Least Significant bits of the BSR

(BSR<3:0> = ‘1111’), and

• Any instruction that contains 83h in its 8

Least Significant bits (i.e., register file

addresses, literal data, address offsets,

etc.) is exec uted .

Work around

All wor k aro unds will in volve settin g th e conten ts of

BSR<3:0> to some value other than 0Fh. In addition

to those proposed below , other solutions may exist.

1. When developing or modifying code, keep

these guidelines in mind:

• Assign 12-bit addresses to all variables.

This all ows the as semb ler to kno w when

Access Banking can be used.

• Do not set the BSR to point to Bank 15

(BSR = 0Fh).

• Allow the assembler to manipulate the

Access bit present in most instructions.

Accessing the SFRs in Bank 15 will be

done through the Access Bank. Con-

tinue to use the BSR to select Banks 1

through 5 and the upper half of Bank 0.

2. If accessing a part of Bank 15 is required and

the use of Access Banking is not possible,

consider using indirect addressing.

3. If pointing the BSR to Ban k 15 is unavo idabl e,

review the absolute file listing. Verify that no

instruc tions cont a ins 83h i n t he 8 L east Si gnif-

icant bits while the BSR points to Bank 15

(BSR = 0Fh).

CCP Mode

CCPxM<3:0> = I/O Pin

State

Change CCP to

CCPxM<3:0> =

1001 1000

0xxx HLL

LLL

1000 HH—

LL—

1001 H—L

L—L

101x HLL

LLL

11xx HLL

LLL

 2002 Microchip Technology Inc. DS80058H-page 3

PIC18CXX2

7. Module: MSSP (I2C Master Mode)

The BF S tatus bit (SSPST AT<0>) may be inadvert-

ently c leared , even if the buf fer has not b een rea d.

This will occur when both of the following two

conditions are met:

•The four Least Significant bits of the BSR

are equal to 0Fh (BSR<3:0> = '1111'), and

•Any instruction that contains C9h in its 8

Least Significant bits (i.e., register file

address, literal data, instruction address

offset, etc.) is executed.

Work around

All work arounds involve setting the BSR to some

value other than 0Fh. Other solutions may exist in

addition to the work arounds proposed below.

1. When developing or modifying code, keep

these guidelines in mind:

•Assign 12-bit addresses to all variables.

This all ows the as semb ler to kno w when

Access Banking can be used.

•Do not set the BSR to point to Bank 15

(BSR = 0Fh).

•Allow the assembler to manipulate the

Access bit present in most instructions.

Access in g SFRs in Bank 15 wi ll be d one

through the Access Bank. Continue to

use the BSR to select Banks 1 through 5

and the upper half of Bank 0.

2. If accessing a part of Bank 15 is required and

the use of Access Banking is not possible,

consider using indirect addressing.

3. If pointin g the BSR to Ban k 15 is unavo idabl e,

review the absolute file listing. Verify that no

instruction contains C9h in the 8 Least

Significant bits while BSR points to Bank 15

(BSR = 0Fh).

8. Module: Interrupts

High priority interrupts may become improperly

enabled, while low priority interrupts become

improperly disabled at the same time. This may

occur when low priority interrupts are in an

enabled state and the following conditions occur

simultaneously:

•High priority interrupts are being changed

from an enabled to a disabled state

•One or more low priority interrupts occur

Work around

Always disable low priority interrupts before dis-

abling high priority interrupts. Re-enable the low

priori ty int errup t s afte rw ard, if neces sa ry.

9. Module: Watchdog Timer

After the WDT is allowed to time-out, all subse-

quent WDT periods following the very first, may

double in duration. This can occur if the CLRWDT

instruction is not executed prior to the timer timing

out.

Work around

Always execute the CLRWDT instruction prior to

entering a potential WDT time-out condition.

10. Module: WDT

When the device is configured for either EC or RC

oscillator modes, with the Power-up Timer

enabled, bit TO of the RCON register (RCON<3>)

may default to ‘0’, even though no WDT time-out

has occurred.

The TO bit functions normally in all other configu-

rations.

Work around

1. Use bit TO in conjunction with bit POR

(RCON<1>), to determine if a RESET condi-

tion has occu rred .

PIC18CXX2

DS80058H-page 4  2002 Microchip Technology Inc.

11. Module: I/O (PORTB

Interrupt-on-Change )

The RB Port Change Flag bit of the INTCON reg-

ister (RBIF, INTCON<0>) may be inadvertently

cleared, even when the PORTB<7:4> pins have

not been read. This will occur only when the follow-

ing two conditions occur simultaneously:

•The four Least Significant bits of the

BSR register are equal to 0Fh

(BSR<3:0> = ‘1111’), and

•Any instruction that contains 81h in its

8 Least Significant bits (i.e., register file

addresses, literal data, address offsets,

etc.) is executed.

Work around

All work arounds will involve setting the contents of

BSR<3:0> to some value other than 0Fh. In a ddition

to those pr oposed below , other sol utions may exist.

1. When developing or modifying code, keep

these guidelines in mind:

•Assign 12-bit addresses to all variables.

This all ows the as semb ler to kno w when

Access Banking can be used.

•Do not set the BSR to point to Bank 15

(BSR = 0Fh).

•Allow the assembler to manipulate the

Access bit present in most instructions.

Accessing the SFRs in Bank 15 will be

done through the Access Bank. Con-

tinue to use the BSR to select Banks 1

through 5, and the upper half of Bank 0.

2. If accessing a part of Bank 15 is required and

the use of Access Banking is not possible,

consider using indirect addressing.

3. If pointin g the BSR to Ban k 15 is unavo idabl e,

review the absolute file listing. Verify that no

instructions contain 81h in the 8 Least Signifi-

cant bits, while the BSR points to Bank 15

(BSR = 0Fh).

12. Module: Interrupts

When an interrupt occurs simultaneously with the

clearing of one or more interrupt enable f lags i n the

INTCON, PIE1 or PIE2 registers, the instruction

immediately following the interrupted instruction

may be executed before vectoring to the Interrupt

Service Routine (ISR). If that instruction is a con-

trol operation, the ISR may not execute as

intended.

In the case of cond itional b ranch inst ruction s, the

first instruction of the ISR may be skipped if the

tested condition would have resulted in a branch.

In the case of GOTO, CALL, or BRA instructions,

program execution may vector to the address

encoded in th e instr uction ; the ISR will not be exe-

cuted at all. The GIE bit will still be cleared, dis-

abling all interrupts.

Additionally, on return from the interrupt (by exe-

cuting RETFIE), the instruction following the inter-

rupted instruction may be executed again.

There may be other interrupt related symptoms.

Work around

Three possible solutions are presented here.

Other solutions may exist. None of these require

special attentio n when setting interrupt enable b its.

1.All instructions that clear interrupt enable bits

should be foll ow ed by a NOP instruction.

2.Prior to disabling any interrupt source, disable

all interrupts by clearing the GIE bit

(INTCON<7>). After disabling the desired inter-

rupts, re-enable all interrupts by setting GIE.

3.If interrupt priority is being used:

a)clear both GIEL and GIEH (in order) bits

(INTCON<7:6>) to disable all peripheral

interrupts

b)clear the desired interrupt enable bits

c)set both GI EH and GIEL, in order to r e-enable

peripheral interrupts

 2002 Microchip Technology Inc. DS80058H-page 5

PIC18CXX2

Clarifications/Corrections to the Data Sheet:

In the Device Data Sheet (DS39026C), the following

clarifications and corr ections should be noted.

1. Module: Brown-out Reset (BOR)

The voltage selection ranges for the BOR module

(parameter D005) have changed. The new values

are shown in Table 1 (below).

2. Module: Low Voltage Detect (LVD)

The voltage selection ranges for the LVD module

(parameter D420) have changed. The new values

are shown in Table 2 (below).

3. Module: Timer1

Section 11.1 (Timer1 Operation) is amended with

the following clarification:

When Timer1 is confi gure d to op erat e as an asyn-

chronous counter, care must be taken that there is

no incoming pulse while the module is being

turned off. If an incoming pulse arrives while

Timer1 is being turned off, the value of register

TMR1 may become unpredictable.

If an applic ati on req uire s tha t Timer1 be turned off

and if it is possible that Timer1 may receive an

incomi ng pulse whi le being turned off, sy nchronize

the externa l clock firs t, by clearing the T1 SYNC bit

of register T1CON. Please note that this may

cause Timer1 to miss up to one count.

TABLE 1: MINIMUM AND MAXIMUM BROWN-OUT RESET VOLTAGE SPECIFICATIONS

Param

No Symbol Characteristic New Specification Data Sheet

Specification Units

Min Typ Max Min Typ Max

D005 VBOR Brown- out Rese t

Voltage BORV<1:0> = 11 2.35 —2.80 2.50 —2.66 V

BORV<1 :0> = 10 2.55 —3.02 2.70 —2.86 V

BORV<1 :0> = 01 3.95 —4.71 4.20 —4.46 V

BORV<1 :0> = 00 4.23 —5.05 4.50 —4.78 V

TABLE 2: MINIMUM AND MAXIMUM LOW VOLTAGE DETECT SPECIFICATIONS

Param

No Symbol Characteristic New Specification Data Sheet

Specification Units

Min Typ Max Min Typ Max

D420 VLVD Low Voltag e

Detect LVV<3:0> = 0100 2.35 —2.80 2.5 —2.66 V

LVV<3:0> = 0101 2.55 —3.02 2.7 —2.86 V

LVV<3:0> = 0110 2.64 —3.14 3.0 —2.98 V

LVV<3:0> = 0111 2.83 —3.37 3.0 —3.20 V

LVV<3:0> = 1000 3.11 —3.71 3.3 —3.52 V

LVV<3:0> = 1001 3.29 —3.93 3.5 —3.72 V

LVV<3:0> = 1010 3.39 —4.04 3.6 —3.84 V

LVV<3:0> = 1011 3.58 —4.26 3.8 —4.04 V

LVV<3:0> = 1100 3.77 —4.49 4.0 —4.26 V

LVV<3:0> = 1101 3.95 —4.71 4.2 —4.46 V

LVV<3:0> = 1110 4.23 —5.05 4.5 —4.78 V

PIC18CXX2

DS80058H-page 6  2002 Microchip Technology Inc.

4. Module: Electrical Specifications

The operating frequency range for extended tem-

perature devices has been changed.

The maximum external clock frequency (EC and

ECIO modes) and oscillator frequency (HS mode)

for extended temperature devices has been

changed to 25 MHz. When the PLL is used

(HS+PLL mode), the maximum clock and oscilla-

tor frequency has been changed to 6.25 MHz.

Other values of related parameters have changed

accordingly.

Table 21-4, Parameters 1 and 1A of the Device

Data Sheet are amended in part, as follows

(changes and additions in bold):

TABLE 21-4: EXTERNAL CLOCK TIMING REQUIREMENTS

Note: Footnotes in original table omitted for the sake of brevity.

Param.

No. Symbol Characteristic Min Max Units Conditions

1A FOSC External CLKIN

Frequency DC 40 MHz XT osc (Industrial)

DC 25 MHz XT osc (Extended)

DC 40 MHz HS osc (Industrial)

DC 25 MHz HS osc (Extended)

4 10 MHz HS + PLL osc (Industrial)

4 6.25 MHz HS + PLL osc (Extended)

6.25

MHz

LP osc (Industrial)

LP osc (Extended)

EC, ECIO (Industrial)

EC, ECIO (Extended)

Oscillator Frequency DC 4 MHz RC osc (Industrial, Extended)

0.1 4 MHz XT os c (Industrial, Extended)

440

25 MHz

MHz HS osc (Industrial)

HS osc (Extended)

4 10 MHz HS + PLL osc (Industrial)

4 6.25 MHz HS + PLL osc (Extended)

5 200 kHz LP osc mode (Industrial,

Extended)

OSC External CLKIN Period 25

40 —

—ns

ns XT osc (Industrial)

XT osc (Extended)

25 —ns HS osc (Industrial)

40 — ns HS osc (Extended)

100 250 ns HS + PLL osc (Industrial)

160 250 ns HS + PLL osc (Extended)

250

—

LP osc (Industrial, Ex tended)

EC, ECIO (Industrial)

EC, ECIO (Extended)

Oscillator Period 250 —ns RC osc (Industrial, Extended)

250 —ns XT osc (Industrial, Extended)

100

160

—

250

HS osc (Industrial)

HS osc (Extended)

HS + PLL osc (Industrial)

HS + PLL osc (Extended)

5—µsLP osc (Industrial)

 2002 Microchip Technology Inc. DS80058H-page 7

PIC18CXX2

4. Module: Electrical Specifications

(Continued)

Figure 21-3 (below), reflecting the voltage-

frequency performance of extended temperature

devices, is added to the Device Data Sheet:

FIGURE 21-3: PIC18CXX2 VOLTAGE-FREQUENCY GRAPH (EXTENDED)

In addition, the title of Figure 21-1 is amended to

read:

“PIC18CXX2 Voltage-Fr equency Graph

(Industrial)”

Frequency

Voltage

6.0V

5.5V

4.5V

4.0V

2.0V

25 MHz

5.0V

3.5V

3.0V

2.5V

PIC18CXX2-E

4.2V

PIC18CXX2

DS80058H-page 8  2002 Microchip Technology Inc.

5. Module: Interrupts

The operation of t he GIE/GIEH bit (INTCON<7>) is

clarified as follows: when the bit is cleared, all

interrupts are disabled. This is regardless of the

stat e of the IPEN bit (RCON<7>), the p riority of the

interrupt, or whether or not the interrupt is

unmasked. This varies from the original descrip-

tion, in which clearing the bit when IPEN = ’1’

would only disable high priority interrupts.

The seventh paragraph in Section 7.0 of the

Device Data Sheet (beginning “When an interrupt

is responded to....”) is amended by adding the fol-

lowing sentence to the end:

“It is important to note, however, that clearing the

GIE/GIEH bit, regardless of the state of the IPEN

bit, will disable all interrupts.”

The chan ges to the bi t descrip tions in Reg ister 7-1

in the De vice Dat a Shee t are sho wn in the ex cerpt

below (changes in bold).

Also, th e inter rupt logic funne l sho wn in F igure 7-1

of the Device Data Sheet is amended with the

addition of a GIE/GIEH control line, as shown in

Figure 1 (new material in bold line).

FIGURE 1: INTERRUPT LOGIC (EXCERPT)

bit 7 GIE/GIEH: Global Interrupt Enable bit

When IPEN (RCON<7>) = 0:

1 = Enables all unmasked interrupts

0 = Disables all interrupts

When IPEN (RCON<7>) = 1:

1 = Enables all high priority interrupts

0 = Disables all interrupts

INT2IF

INT2IE

INT2IP

INT1IF

INT1IE

INT1IP

TMR0IF

TMR0IE

TMR0IP

RBIF

RBIE

RBIP GIEL/PEIE

Interrupt to CPU

Vector to Location

0018h

Peripheral Interrupt Flag bit

Peripheral Interrupt Enable bit

Peripheral Interrupt Priority bit

TMR1IF

TMR1IE

TMR1IP

Low Priority Interrupt Generation

XXXXIF

XXXXIE

XXXXIP

Additional Peripheral Interrupts

GIE/GEIH

 2002 Microchip Technology Inc. DS80058H-page 9

PIC18CXX2

6. Module: USART

The operation of the USART Transmit Interrupt

flag bit TXIF (PIR1<4 >) is clarifi ed as fol lows :

TXIF is n ot cle ared immedi atel y upo n load ing da ta

into the transmit buffer TXREG. The flag bit

becom es valid i n the second in structi on cycle fol -

lowing the load instruction (see Example 1). Poll-

ing TXIF immediately following a load of TXREG

will give invalid results (Example 2).

This clarification applies to all USART transmis-

sion modes (master or slave, synchronous or

asynchronous, 8-bit or 9-bit).

EXAMPLE 1: CORRECTLY POLLING

THE TXIF BIT

EXAMPLE 2: POLLING THE TXIF BIT

IMMEDIATELY AFTER

LOADING THE TRANSMIT

BUFFER

movwf TXREG ;load the register

nop :first instruction--

;just a placeholder, it

;could be any instruction

btfss PIR1,TXIF ;second instruction--

;now TXIF is valid

movwf TXREG ;load the register

btfss PIR1,TXIF ;first instruction--

;reading TXIF now will

;give invalid results

PIC18CXX2

DS80058H-page 10  2002 Microchip Technology Inc.

REVISION HISTORY

Rev H Document

Under Clarifications/Corrections to the Data

Sheet, added Interrupt issue for GIE/GIEH bit

(page 8, item 5).

Added USART issue (page 9, issue 6).

Rev G Document

Added Interrupt issue (page 4, item 12)

Under Clarifications/Corrections to the Data

Sheet, added Electrical Specifications issue for

extended temperature devices (pages 6 and 7,

item 4).

Rev F Document

Added I/O Port (PORTB - Interrupt-on-Change)

issue (page 4, item 11).

Rev E Document

Added Parallel Slave Port issue (page 2, item 6).

Added MSSP issue (page 3, item 7).

Added Interrupts issue (page 3, item 8).

Added Watchdog Timer (CLRWDT) issue (page 3,

item 9).

Added WDT (o sc modes) issue (page 3, item 10).

Under Clarifications/Corrections to the Data

Sheet, added Timer1 issue (page 5, item 3).

Rev D Document

Added Corrections to BOR and LVD modules

(page 3, items 1 and 2).

Rev C Document

Added ICSP issue (page 1, issue 3).

Added CCP (Compare mode) issue

(page 2, issue 4).

Added Timer issue (page 2, issue 5).

Rev B Document

Added CCP silicon issue (page 1, issue 2).

Rev A Document

1st revision of this document.

 2002 Microchip Technology Inc. DS80058H - page 11

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporated with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

use or otherwise. Use of Microchip’s products as critical com-

ponents in life support systems is not authorized except with

express written approval by Microchip. No licenses are con-

veyed, implicitly or otherwise, under any intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART,

PRO MATE, SEEVAL and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microID,

microPort, Migratable Memory, MPASM, MPLIB, MPLINK,

MPSIM, MXDEV, PICC, PICD EM, PICDEM.net, rf PIC, Select

Mode and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A.

Serialized Quick Term Programming (SQTP) is a service mark

of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper .

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and T empe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

DS80058H-page 12  2002 Microchip Technology Inc.

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200 Fax: 480-792-7277

Technical Support: 480-792-7627

Web Address: http://ww w.microchip .com

Rocky Mountain

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7966 Fax: 480-792-7456

Atlanta

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 770 -6 40- 003 4 Fax: 770- 640 -03 07

Boston

2 Lan Drive, Suite 120

Westford, MA 01886

Tel: 978 -6 92- 384 8 Fax: 978- 692 -38 21

Chicago

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 630-285-0071 Fax: 630-285-0075

Dallas

4570 Westgrove Drive, Suite 160

Addison, TX 7500 1

Tel: 972 -8 18- 742 3 Fax: 972- 818 -29 24

Detroit

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250 Fax: 248-538-2260

Kokomo

2767 S. Albright Road

Kokomo, Indiana 46902

Tel: 765-864-8360 Fax: 765-864-8387

Los A n ge les

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 949 -2 63- 188 8 Fax: 949- 263 -13 38

New York

150 Motor Parkway , Suite 202

Hauppauge, NY 11788

Tel: 631 -2 73- 530 5 Fax: 631- 273 -53 35

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408 -4 36- 795 0 Fax: 408- 436 -79 55

Toronto

6285 Northam Drive, Suite 108

Mississ aug a, Ontario L4V 1X5, C ana da

Tel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFIC

Australia

Microchip Technology Australia Pty Ltd

Suite 22, 41 Rawson S treet

Epping 212 1, NSW

Australia

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

China - Beijing

Microchip Technology Consulting (Shanghai)

Co., Ltd., Beijing Liaison Office

Unit 915

Bei Hai Wa n Tai Bldg.

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10-85282100 Fax: 86-10-85282104

China - Chengdu

Microchip Technology Consulting (Shanghai)

Co., Ltd., Chengdu Liaison Office

Rm. 2401, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Cheng du 610 016 , Chi na

Tel: 86-28-6766200 Fax: 86-28-6766599

China - Fuzhou

Microchip Technology Consulting (Shanghai)

Co., Ltd., Fuzhou Liaison Office

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Fuzhou 350001, China

Tel: 86-591-7503506 Fax: 86-591-7503521

China - Shanghai

Microchip Technology Consulting (Shanghai)

Co., Ltd.

Room 701, Bldg. B

Far East Internatio nal Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Tel: 86-21-6275-5700 Fax: 86-21-6275-5060

China - Shenzhen

Microchip Technology Consulting (Shanghai)

Co., Ltd., Shenzhen Liaison Office

Rm. 1315, 13/F, Shenzhen Kerry Centre,

Renminnan Lu

Shenzhen 518001, China

Tel: 86-755-2350361 Fax: 86-755-2366086

Hong Kong

Microchip Technology Hongkong Ltd.

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200 Fax: 852-2401-3431

India

Microchip Technology Inc.

India Liaiso n Office

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O ’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

Microchip Technology Japan K.K.

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea

Microc hip Technolo gy Korea

168-1, You ng bo Bld g. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Ko re a 135- 88 2

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Singapore

Microchip Technology Singapore Pte Ltd.

200 Midd le Ro ad

#07-02 Prime Centre

Singapore, 188980

Tel: 65-334-8870 Fax: 65-334-8850

Taiwan

Microc hip Technolo gy Taiw an

11F-3, No . 207

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Denmark

Microchip Technology Nordic ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

France

Microc hip Technolo gy SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Et age

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30 -90-79

Germany

Microc hip Technolo gy GmbH

Gustav-Heinemann Ring 125

D-81739 Munich, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Microc hip Technolo gy SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

United Kingdom

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berksh ire, E ngla nd RG 41 5TU

Tel: 44 118 921 5869 Fax: 44-118 921-5820

01/18/02

WORLDWIDE SALES AND SERVICE