DS90C363,DS90CF364
DS90C363/DS90CF364 +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link - 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel
Display (FPD) Link - 65 MHz
Literature Number: SNLS123B
DS90C363/DS90CF364
April 7, 2011
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link - 65 MHz, +3.3V LVDS Receiver 18-Bit
Flat Panel Display (FPD) Link - 65 MHz
General Description
The DS90C363 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF364 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data through-
puts is 170 Mbytes/sec. The Transmitter is offered with pro-
grammable edge data strobes for convenient interface with a
variety of graphics controllers. The Transmitter can be pro-
grammed for Rising edge strobe or Falling edge strobe
through a dedicated pin. A Rising edge Transmitter will inter-
operate with a Falling edge Receiver (DS90CF364) without
any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
20 to 65 MHz shift clock support
Programmable Transmitter (DS90C363) strobe select
(Rising or Falling edge strobe)
Single 3.3V supply
Chipset (Tx + Rx) power consumption < 250 mW (typ)
Power-down mode (< 0.5 mW total)
Single pixel per clock XGA (1024×768) ready
Supports VGA, SVGA, XGA and higher addressability.
Up to 170 Megabyte/sec bandwidth
Up to 1.3 Gbps throughput
Narrow bus reduces cable size and cost
290 mV swing LVDS devices for low EMI
PLL requires no external components
Low profile 48-lead TSSOP package
Falling edge data strobe Receiver
Compatible with TIA/EIA-644 LVDS standard
ESD rating > 7 kV
Operating Temperature: −40°C to +85°C
Block Diagram
Application
1288614
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2011 National Semiconductor Corporation 12886 www.national.com
DS90C363/DS90CF364 +3.3V Programmable LVDS 18-Bit-Color Flat Panel Display (FPD)
Link - 65 MHz
DS90C363
1288601
Order Number DS90C363MTD
See NS Package Number MTD48
DS90CF364
1288624
Order Number DS90CF364MTD
See NS Package Number MTD48
www.national.com 2
DS90C363/DS90CF364
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)−0.3V to +4V
CMOS/TTL Input Voltage −0.3V to (VCC + 0.3V)
CMOS/TTL Output Voltage −0.3V to (VCC + 0.3V)
LVDS Receiver Input Voltage −0.3V to (VCC + 0.3V)
LVDS Driver Output Voltage −0.3V to (VCC + 0.3V)
LVDS Output Short Circuit
Duration Continuous
Junction Temperature +150°C
Storage Temperature −65°C to +150°C
Lead Temperature
(Soldering, 4 sec) +260°C
Maximum Package Power Dissipation Capacity @ 25°C
MTD48 (TSSOP) Package:
DS90C363 1.98 W
DS90CF364 1.89 W
Package Derating:
DS90C363 16 mW/°C above +25°C
DS90CF364 15 mW/°C above +25°C
ESD Rating
(HBM, 1.5 k, 100 pF) > 7 kV
Recommended Operating
Conditions
Min No
m
Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Operating Free Air
Temperature (TA) −40 +25 +85 °C
Receiver Input Range 0 2.4 V
Supply Noise Voltage (VCC) 100 mVPP
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Units
CMOS/TTL DC SPECIFICATIONS
VIH High Level Input Voltage 2.0 VCC V
VIL Low Level Input Voltage GND 0.8 V
VOH High Level Output Voltage IOH = −0.4 mA 2.7 3.3 V
VOL Low Level Output Voltage IOL = 2 mA 0.06 0.3 V
VCL Input Clamp Voltage ICL = −18 mA −0.79 −1.5 V
IIN Input Current VIN = VCC, GND, 2.5V or 0.4V ±5.1 ±10 μA
IOS Output Short Circuit Current VOUT = 0V −60 −120 mA
LVDS DC SPECIFICATIONS
VOD Differential Output Voltage RL = 100Ω 250 345 450 mV
ΔVOD Change in VOD between 35 mV
complimentary output states
VOS Offset Voltage (Note 4) 1.125 1.25 1.375 V
ΔVOS Change in V OS between 35 mV
complimentary output states
IOS Output Short Circuit Current VOUT = 0V, RL = 100Ω −3.5 −5 mA
IOZ Output TRI-STATE® Current PWR DWN = 0V, ±1 ±10 μA
VOUT = 0V or VCC
VTH Differential Input High Threshold VCM = +1.2V +100 mV
VTL Differential Input Low Threshold −100 mV
IIN Input Current VIN = +2.4V, VCC = 3.6V ±10 μA
VIN = 0V, VCC = 3.6V ±10 μA
TRANSMITTER SUPPLY CURRENT
ICCTW Transmitter Supply Current, Worst Case RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figures 1, 3 ), TA = −40°
C to +85°C
f = 32.5 MHz 31 45 mA
f = 37.5 MHz 32 50 mA
f = 65 MHz 42 55 mA
3 www.national.com
DS90C363/DS90CF364
Symbol Parameter Conditions Min Typ Max Units
ICCTG Transmitter Supply Current, 16 Grayscale RL = 100Ω,
CL = 5 pF,
16 Grayscale Pattern
(Figures 2, 3 ), TA = −40°C
to +85°C
f = 32.5 MHz 23 35 mA
f = 37.5 MHz 28 40 mA
f = 65 MHz 31 45 mA
ICCTZ Transmitter Supply Current PWR DWN = Low 10 55 μA
Power Down Driver Outputs in TRI-STATE® under
Power Down Mode
RECEIVER SUPPLY CURRENT
ICCRW Receiver Supply Current, Worst Case CL = 8 pF, Worst Case
Pattern (Figures 1, 4 ),
TA = −40°C to +85°C
f = 32.5 MHz 49 65 mA
f = 37.5 MHz 53 70 mA
f = 65 MHz 78 105 mA
ICCRG Receiver Supply Current, 16 Grayscale CL = 8 pF, 16 Grayscale
Pattern (Figures 2, 4 ),
TA = −40°C to +85°C
f = 32.5 MHz 28 45 mA
f = 37.5 MHz 30 47 mA
f = 65 MHz 43 60 mA
ICCRZ Receiver Supply Current PWR DWN = Low 10 55 μA
Power Down Receiver Outputs Stay Low during
Power Down Mode
Note 1: Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and T A = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ΔV OD).
Note 4: VOS previously referred as VCM.
Transmitter Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
LLHT LVDS Low-to-High Transition Time (Figure 3 ) 0.75 1.5 ns
LHLT LVDS High-to-Low Transition Time (Figure 3 ) 0.75 1.5 ns
TCIT TxCLK IN Transition Time (Figure 5 ) 5 ns
TCCS TxOUT Channel-to-Channel Skew (Figure 6 ) 250 ps
TPPos0 Transmitter Output Pulse Position for Bit 0 (Figure 17 ) f = 65 MHz −0.4 0 0.3 ns
TPPos1 Transmitter Output Pulse Position for Bit 1 1.8 2.2 2.5 ns
TPPos2 Transmitter Output Pulse Position for Bit 2 4.0 4.4 4.7 ns
TPPos3 Transmitter Output Pulse Position for Bit 3 6.2 6.6 6.9 ns
TPPos4 Transmitter Output Pulse Position for Bit 4 8.4 8.8 9.1 ns
TPPos5 Transmitter Output Pulse Position for Bit 5 10.6 11.0 11.3 ns
TPPos6 Transmitter Output Pulse Position for Bit 6 12.8 13.2 13.5 ns
TCIP TxCLK IN Period (Figure 7)15 T 50 ns
TCIH TxCLK IN High Time (Figure 7)0.35T 0.5T 0.65T ns
TCIL TxCLK IN Low Time (Figure 7)0.35T 0.5T 0.65T ns
TSTC TxIN Setup to TxCLK IN (Figure 7 ) f = 65 MHz 2.5 ns
THTC TxIN Hold to TxCLK IN (Figure 7 ) 0 ns
TCCD TxCLK IN to TxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 9 ) 3.0 3.7 5.5 ns
TPLLS Transmitter Phase Lock Loop Set (Figure 11 ) 10 ms
TPDD Transmitter Power Down Delay (Figure 15 ) 100 ns
www.national.com 4
DS90C363/DS90CF364
Receiver Switching Characteristics
Over recommended operating supply and −40°C to +85°C ranges unless otherwise specified
Symbol Parameter Min Typ Max Units
CLHT CMOS/TTL Low-to-High Transition Time (Figure 4 ) 2.2 5.0 ns
CHLT CMOS/TTL High-to-Low Transition Time (Figure 4 ) 2.2 5.0 ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 18 ) f = 65 MHz 0.7 1.1 1.4 ns
RSPos1 Receiver Input Strobe Position for Bit 1 2.9 3.3 3.6 ns
RSPos2 Receiver Input Strobe Position for Bit 2 5.1 5.5 5.8 ns
RSPos3 Receiver Input Strobe Position for Bit 3 7.3 7.7 8.0 ns
RSPos4 Receiver Input Strobe Position for Bit 4 9.5 9.9 10.2 ns
RSPos5 Receiver Input Strobe Position for Bit 5 11.7 12.1 12.4 ns
RSPos6 Receiver Input Strobe Position for Bit 6 13.9 14.3 14.6 ns
RSKM RxIN Skew Margin (Note 5) (Figure 19 ) f = 65 MHz 400 ps
RCOP RxCLK OUT Period (Figure 8)15 T 50 ns
RCOH RxCLK OUT High Time (Figure 8 ) f = 65 MHz 7.3 8.6 ns
RCOL RxCLK OUT Low Time (Figure 8)f = 65 MHz 3.45 4.9 ns
RSRC RxOUT Setup to RxCLK OUT (Figure 8 ) f = 65 MHz 2.5 6.9 ns
RHRC RxOUT Hold to RxCLK OUT (Figure 8 ) f = 65 MHz 2.5 5.7 ns
RCCD RxCLK IN to RxCLK OUT Delay @ 25°C, VCC = 3.3V (Figure 10 ) 5.0 7.1 9.0 ns
RPLLS Receiver Phase Lock Loop Set (Figure 12 ) 10 ms
RPDD Receiver Power Down Delay (Figure 16 ) 1 μs
Note 5: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions
(min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol
interference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
AC Timing Diagrams
1288602
FIGURE 1. “Worst Case” Test Pattern
5 www.national.com
DS90C363/DS90CF364
1288603
FIGURE 2. “16 Grayscale” Test Pattern (Note 6, Note 7, Note 8, Note 9)
Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 7: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 8: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 9: Recommended pin to signal mapping. Customer may choose to define differently.
1288615
FIGURE 3. DS90C363 (Transmitter) LVDS Output Load and Transition Times
www.national.com 6
DS90C363/DS90CF364
1288604
FIGURE 4. DS90CF364 (Receiver) CMOS/TTL Output Load and Transition Times
1288616
FIGURE 5. DS90C363 (Transmitter) Input Clock Transition Time
1288617
Measurements at Vdiff=0V
TCCS measured between earliest and latest LVDS edges
TxCLK Differential Low High Edge
FIGURE 6. DS90C363 (Transmitter) Channel-to-Channel Skew
1288618
FIGURE 7. DS90C363 (Transmitter) Setup/Hold and High/Low Times
7 www.national.com
DS90C363/DS90CF364
1288605
FIGURE 8. DS90CF364 (Receiver) Setup/Hold and High/Low Times
1288619
FIGURE 9. DS90C363 (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
1288606
FIGURE 10. DS90CF364 (Receiver) Clock In to Clock Out Delay
1288620
FIGURE 11. DS90C363 (Transmitter) Phase Lock Loop Set Time
www.national.com 8
DS90C363/DS90CF364
1288607
FIGURE 12. DS90CF364 (Receiver) Phase Lock Loop Set Time
1288609
FIGURE 13. Seven Bits of LVDS in One Clock Cycle
1288610
FIGURE 14. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
9 www.national.com
DS90C363/DS90CF364
1288621
FIGURE 15. Transmitter Power Down Delay
1288608
FIGURE 16. Receiver Power Down Delay
1288622
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
www.national.com 10
DS90C363/DS90CF364
1288625
FIGURE 18. Receiver LVDS Input Strobe Position
11 www.national.com
DS90C363/DS90CF364
1288611
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note Cycle-to-cycle jitter is less than 250 ps at 65 MHz. ) + ISI (Inter-symbol interference)
(Note ISI is dependent on interconnect length; may be zero. )
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Note 10: Cycle-to-cycle jitter is less than 250 ps at 65 MHz.
Note 11: ISI is dependent on interconnect length; may be zero.
FIGURE 19. Receiver LVDS Input Skew Margin
www.national.com 12
DS90C363/DS90CF364
DS90C363 Pin Descriptions — FPD
Link Transmitter
Pin Name I/O No
.
Description
TxIN I 21 TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME and
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+ O 3 Positive LVDS differentiaI data output.
TxOUT− O 3 Negative LVDS differential data output.
FPSHIFT IN I 1 TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
R_FB I 1 Programmable strobe select.
RTxCLK OUT+ O 1 Positive LVDS differential clock output.
TxCLK OUT− O 1 Negative LVDS differential clock output.
PWR DWN I 1 TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at power down.
V CC I 3 Power supply pins for TTL inputs.
GND I 4 Ground pins for TTL inputs.
PLL V CC I 1 Power supply pin for PLL.
PLL GND I 2 Ground pins for PLL.
LVDS V CC I 1 Power supply pin for LVDS outputs.
LVDS GND I 3 Ground pins for LVDS outputs.
DS90CF364 Pin Descriptions — FPD
Link Receiver
Pin Name I/O No
.
Description
RxIN+ I 3 Positive LVDS differentiaI data inputs.
RxIN− I 3 Negative LVDS differential data inputs.
RxOUT O 21 TTL level data outputs. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines—FPLINE, FPFRAME,
DRDY (also referred to as HSYNC, VSYNC, Data Enable).
RxCLK IN+ I 1 Positive LVDS differential clock input.
RxCLK IN− I 1 Negative LVDS differential clock input.
FPSHIFT OUT O 1 TTL Ievel clock output. The falling edge acts as data strobe. Pin name RxCLK OUT.
PWR DWN I 1 TTL level input. When asserted (low input) the receiver outputs are low.
V CC I 4 Power supply pins for TTL outputs.
GND I 5 Ground pins for TTL outputs.
PLL V CC I 1 Power supply for PLL.
PLL GND I 2 Ground pin for PLL.
LVDS V CC I 1 Power supply pin for LVDS inputs.
LVDS GND I 3 Ground pins for LVDS inputs.
13 www.national.com
DS90C363/DS90CF364
Pin Diagrams
DS90C363
1288623
DS90CF364
1288613
Truth Table
TABLE 1. Programmable Transmitter
Pin Condition Strobe Status
R_FB R_FB = VCC Rising edge strobe
R_FB R_FB = GND Falling edge strobe
Applications Information
The DS90C363 and DS90CF364 are backward compatible
with the existing 5V FPD Link transmitter/receiver pair
(DS90CF563 and DS90CF564). To upgrade from a 5V to a
3.3V system the following must be addressed:
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL V CC of both the transmitter
and receiver devices. This change may enable the
removal of a 5V supply from the system, and power may
be supplied from an existing 3V power source.
2. The DS90C363 (transmitter) incorporates a rise/fall
strobe select pin. This select function is on pin 14,
formerly a VCC connection on the 5V products. When the
rise/fall strobe select pin is connected to V CC, the part is
configured with a rising edge strobe. In a system
currently using a 5V rising edge strobe transmitter
(DS90CR563), no layout changes are required to
accommodate the new rise/fall select pin on the 3.3V
transmitter. The VCC signal may remain at pin 14, and the
device will be configured with a rising edge strobe.
When converting from a 5V falling edge transmitter
(DS90CF563) to the 3V transmitter a minimal board
layout change is necessary. The 3.3V transmitter will
not be configured with a falling edge strobe if VCC
remains connected to the select pin. To guarantee the
3.3V transmitter functions with a falling edge strobe pin
14 should be connected to ground OR left unconnected.
When not connected (left open) and internal pull-down
resistor ties pin 14 to ground, thus configuring the
transmitter with a falling edge strobe.
3. The DS90C363 transmitter input and control inputs
accept 3.3V TTL/CMOS levels. They are not 5V tolerant.
www.national.com 14
DS90C363/DS90CF364
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
Dimensions show in millimeters
Order Number DS90C363MTD and DS90CF364MTD
NS Package Number MTD48
15 www.national.com
DS90C363/DS90CF364
Notes
DS90C363/DS90CF364 +3.3V Programmable LVDS 18-Bit-Color Flat Panel Display (FPD)
Link - 65 MHz
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
www.national.com
Products Design Support
Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench
Audio www.national.com/audio App Notes www.national.com/appnotes
Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns
Data Converters www.national.com/adc Samples www.national.com/samples
Interface www.national.com/interface Eval Boards www.national.com/evalboards
LVDS www.national.com/lvds Packaging www.national.com/packaging
Power Management www.national.com/power Green Compliance www.national.com/quality/green
Switching Regulators www.national.com/switchers Distributors www.national.com/contacts
LDOs www.national.com/ldo Quality and Reliability www.national.com/quality
LED Lighting www.national.com/led Feedback/Support www.national.com/feedback
Voltage References www.national.com/vref Design Made Easy www.national.com/easy
PowerWise® Solutions www.national.com/powerwise Applications & Markets www.national.com/solutions
Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero
Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic
PLL/VCO www.national.com/wireless PowerWise® Design
University
www.national.com/training
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2011 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
Email: support@nsc.com
Tel: 1-800-272-9959
National Semiconductor Europe
Technical Support Center
Email: europe.support@nsc.com
National Semiconductor Asia
Pacific Technical Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Technical Support Center
Email: jpn.feedback@nsc.com
www.national.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TIs terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TIs standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Security www.ti.com/security
Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright ©2011, Texas Instruments Incorporated