1. Product profile
1.1 General description
Logic level enhancement mode N-cha nnel MOSFET in LFP AK33 p ackage. This product is
designed and qualified for use in a wide ran ge of industrial, communications and domestic
equipment.
1.2 Features and benefits
Low parasitic inductance and
resistance
Optimised for 4.5V Gate drive utilising
NextPower Superjunction technology
Ultra low QG, QGD, & QOSS for high
system efficiencies at low and high
loads
1.3 Applications
DC-to-DC converters
Load switching
Synchronous buck regulator
1.4 Quick reference data
PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33
using NextPower Technology
Rev. 4 — 15 June 2012 Product data sheet
LFPAK33
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDS drain-source voltage Tj = 25 °C - - 30 V
IDdrain current Tmb =2C; V
GS =10V; see Figure 1 --39A
Ptot total power dissipation Tmb =2C; see Figure 2 --38W
Tjjunction temperature -55 - 175 °C
Static characteristics
RDSon drain-source on-state
resistance VGS =4.5V; I
D=10A; T
j=2C;
see Figure 10 -14.6516.9m
VGS =10V; I
D=10A; T
j=2C;
see Figure 10 -11.813.6m
Dynamic characteristics
QGD gate-drain charge VGS =4.5V; I
D=10A; V
DS =15V;
see Figure 12 ; see Figure 13 -1-nC
QG(tot) total gate charge VGS =4.5V; I
D=10A; V
DS =15V;
see Figure 12 ; see Figure 13 -3.7-nC
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 2 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
2. Pinning information
3. Ordering information
4. Limiting values
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1Ssource
SOT1210 (LFPAK33)
2Ssource
3Ssource
4 G gate
mb D mounting base; connected to
drain
1432
S
D
G
mbb076
Table 3. Ordering informatio n
Type number Package
Name Description Version
PSMN013-30MLC LFPAK33 P lastic single ended surface mounted package (LFPAK33);
4 leads SOT1210
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VDS drain-source voltage Tj = 25 °C - 30 V
VGS gate-source voltage -20 20 V
IDdrain current VGS =10V; T
mb =2C; see Figure 1 -39A
VGS =10V; T
mb = 100 °C; see Figure 1 -28A
IDM peak drain current pulsed; tp10 µs; Tmb =2C;
see Figure 4 - 157 A
Ptot total power dissipation Tmb =2C; see Figure 2 -38W
Tstg storage temperature -55 175 °C
Tjjunction temperature -55 175 °C
Tsld(M) peak soldering temperature - 260 °C
VESD electrostatic discharge voltage MM (JEDEC JESD22-A115) 100 - V
Source-drain diode
ISsource current Tmb =2C - 34 A
ISM peak source current pulsed; tp10 µs; Tmb = 25 °C - 157 A
Avalanche ru ggedness
EDS(AL)S non-repetitive drain-source
avalanche energy VGS =10V; T
j(init) =2C; I
D=39A;
Vsup 30 V; RGS =50; unclamped;
see Figure 3
-5.6mJ
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 3 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
Fig 1. Continuous drain current as a function of
mounting base temperature Fig 2. Normalized total power dissipation as a
function of mounting ba s e temperature
Fig 3. Single pulse avalanche rating; avalanche current as a function of avalan che time
003aaj396
0
10
20
30
40
0 50 100 150 200
T
mb
(°C)
I
D
(A)
Tmb (°C)
0 20015050 100
03na19
40
80
120
Pder
(%)
0
003aaj397
10
-1
1
10
10
2
10
-3
10
-2
10
-1
1 10
t
AL
(ms)
I
AL
(A)
(1)
(2)
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 4 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
5. Thermal characteristics
Fig 4. Safe o perating area; continuous and peak drain currents as a function of drain-s ou rce voltage
003aaj398
10
-1
1
10
10
2
10
3
10
-1
1 10 10
2
V
DS
(V)
I
D
(A)
Lim it R
DSon
= V
DS
/ I
D
DC
100 μs
10 ms
t
p
=10 μs
100 ms
1 ms
Table 5. Thermal characteristics
Symbol Parameter Conditions Min Typ Max Unit
Rth(j-mb) thermal resistance from
junction to mounting base see Figure 5 - 3.8 3.99 K/W
Fig 5. Transient thermal impedance from junction to mounting base as a function of pulse duration
003aaj399
single shot
0.2
0.1
0.05
10
-2
10
-1
1
10
10
-5
10
-4
10
-3
10
-2
10
-1
1
t
p
(s)
Z
th(j-mb)
(K/W) δ = 0.5
0.02
10
-6
t
p
T
P
t
t
p
T
δ =
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 5 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
6. Characteristics
Table 6. Characteristics
Symbol Parameter Conditions Min Typ Max Unit
Static characteristics
V(BR)DSS drain-source
breakdown voltage ID=25A; V
GS =0V; T
j=25°C 30--V
ID=25A; V
GS =0V; T
j= -55 °C 27 - - V
VGS(th) gate-source threshold
voltage ID=1mA; V
DS =V
GS; Tj= 25 °C 1.3 1.66 1.95 V
VGS(th)/T gate-source threshold
voltage variation with
temperature
--4-mV/K
IDSS drain leakage current VDS =30V; V
GS =0V; T
j=25°C --1µA
VDS =30V; V
GS =0V; T
j= 150 °C - - 100 µA
IGSS gate leakage current VGS =16V; V
DS =0V; T
j= 25 °C - - 100 nA
VGS =-16V; V
DS =0V; T
j= 25 °C - - 100 nA
RDSon drain-source on-state
resistance VGS =4.5V; I
D=10A; T
j=2C;
see Figure 10 - 14.65 16.9 m
VGS =4.5V; I
D=10A; T
j=15C;
see Figure 10 ; see Figure 11 - - 28.75 m
VGS =10V; I
D=10A; T
j=2C;
see Figure 10 - 11.8 13.6 m
VGS =10V; I
D=10A; T
j= 150 °C;
see Figure 11 ; see Figure 10 - - 22.95 m
RG gate resistance f = 1 MHz 0.85 1.7 3.4
Dynamic characteristics
QG(tot) total gate charge ID=10A; V
DS =15V; V
GS =10V;
see Figure 12 ; see Figure 13 -8-nC
ID=10A; V
DS =15V; V
GS =4.5V;
see Figure 12 ; see Figure 13 -3.7-nC
ID=0A; V
DS =0V; V
GS =10V -7.4-nC
QGS gate-source charge ID=10A; V
DS =15V; V
GS =4.5V;
see Figure 12 ; see Figure 13 -1.2-nC
QGS(th) pre-threshold
gate-source charge -0.8-nC
QGS(th-pl) post-threshold
gate-source charge -0.4-nC
QGD gate-drain charge - 1 - nC
VGS(pl) gate-source plateau
voltage ID=10A; V
DS =15V; see Figure 12;
see Figure 13 -2.6-V
Ciss input capacitance VDS =15V; V
GS = 0 V; f = 1 MHz;
Tj=2C; see Figure 14 - 519 - pF
Coss output capacitance - 131 - pF
Crss reverse transfer
capacitance -37-pF
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 6 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
td(on) turn-on delay time VDS =15V; R
L=1.5; VGS =4.5V;
RG(ext) =5
-7-ns
trrise time - 9.8 - ns
td(off) turn-off delay time - 9.6 - ns
tffall time - 5.5 - ns
Qoss output charge VGS =0V; V
DS =15V; f=1MHz;
Tj=2C -3.7-nC
Source-drain diode
VSD source-drain voltage IS=10A; V
GS =0V; T
j=2C;
see Figure 15 - 0.86 1.1 V
trr reverse recovery time IS=10A; dI
S/dt = -100 A/ µs; VGS =0V;
VDS =15V - 13.4 - ns
Qrrecovered charge - 6.6 - nC
tareverse recovery rise
time VGS =0V; I
S=10A; dI
S/dt = -100 A/µs;
VDS =15V; see Figure 16 -8.6-ns
tbreverse recovery fall
time -4.8-ns
Table 6. Characteristics …continued
Symbol Parameter Conditions Min Typ Max Unit
Fig 6. Output characteristics; drain current as a
function of drain-source voltage; typical values Fig 7. Drain-source on-state resistance as a function
of gate-source voltage; typical values
003aaj400
0
10
20
30
40
01234
V
DS
(V)
I
D
(A)
V
GS
(V) =
2.6
2.8
3.5
4.5 10
2.4
2.2
3
003aaj401
0
10
20
30
40
50
0 4 8 12 16
V
GS
(V)
R
DSon
(mΩ)
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 7 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
Fig 8. Forward transconductance as a function of
drain current; typical values Fig 9. Tran sfer characteristics; drain current as a
function of gate-s ourc e vol tage; typical values
Fig 10. Drain-source on-state resistance as a function
of drain current; typical values Fig 11. Normalized drain-source on-state resistance
factor as a function of junction temperature
003aaj402
0
10
20
30
40
50
0 10203040
I
D
(A)
g
fs
(S)
003aaj403
0
10
20
30
40
01234
V
GS
(V)
I
D
(A)
T
j
= 25 °C
T
j
= 150 °C
003aaj406
0
10
20
30
40
50
515253545
I
D
(A)
R
DSon
(mΩ)
4.5
V
GS
(V) = 10
2.8 3
3.5
003aaj407
0
0.5
1
1.5
2
-60 0 60 120 180
T
j
(°C)
a
V
GS
=4.5V
10V
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 8 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
Fig 12. Gate charge waveform definitions Fig 13. Gate-source voltage as a function of gate
charge; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
Fig 15. Source current as a fu nction of source-drain
voltage; typical values
003aaa508
VGS
VGS(th)
QGS1 QGS2
QGD
VDS
QG(tot)
ID
QGS
VGS(pl)
003aaj408
0
2
4
6
8
10
0246810
Q
G
(nC)
V
GS
(V)
V
DS
=
24 V
6 V
15 V
003aaj409
10
10
2
10
3
10
-1
1 10 10
2
V
DS
(V)
C
(pF)
C
iss
C
rss
C
oss
003aaj410
0
10
20
30
40
0 0.3 0.6 0.9 1.2
V
SD
(V)
I
S
(A)
T
j
= 25 °C
T
j
= 150°C
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 9 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
Fig 16. Reverse recovery timing definition
003aaf 444
0
t (s)
I
D
(A)
I
RM
0.25 I
RM
t
rr
t
a
t
b
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 10 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
7. Package outline
Fig 17. Package outline SOT1210 (LFPAK33)
References
Outline
version
European
projection Issue date
IEC JEDEC JEITA
SOT1210
sot1210_po
11-12-19
12-03-12
Unit(1)
mm
max
nom
min
0.90 0.10 0.35 0.20 0.30 2.70
0.65
A
Dimensions
Note
1. Plastic or metal protrusions of 0.15 mm per side are not included.
Plastic single ended surface mounted package (LFPAK33); 8 leads SOT1210
A1b
0.35
b1cc
1D(1) θD1E(1) E1e
0.65
e1H
3.40 2.452.35 3.40
L
0.25
Lp
0.50
0.20 0.10
wy
3.20 2.000.80 0.00 0.25 0.10 0.20 2.500.25 0°
1.90 3.20 0.13 0.30
8°
0 5 mm2.5
scale
A
e1
eX
θ
wA
mounting
base
E1
c1
b1
b
A
E
L
D1
HD
detail X
Cc
A1
Lp C
y
14
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 11 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
8. Revision history
Table 7. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PSMN013-30MLC v.4 20120615 Product data sheet - PSMN013-30MLC v.3
Modifications: Status changed from objective to product.
Va rious changes to content.
PSMN013-30MLC v.3 20120607 Objective data sheet - PSMN013-30MLC v.2
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 12 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URLhttp://www.nxp.com.
9.2 Definitions
Preview — The document is a preview version only. The document is still
subject to formal approval, which may result in modificati ons or additions.
NXP Semiconductors does not give any representations or warranties as to
the accuracy or completeness of informati on included herein and shall have
no liability for the consequences of use of such info rmation.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specifica t io n The information and data provided in a Product
data sheet shall define the specification of the product as agreed be tween
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
9.3 Disclaimers
Limited warranty and liability — Information in this document is be lieved to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregat e and cumulative liabil ity towards
customer for the products described herein shall be limited in accordance
with theTerms and conditions of commercial sale of NXP Semicon ductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersed es an d r eplaces all inf ormation supplied pri or
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability rela ted to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — St ress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Document status[1] [2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [shor t] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
PSMN013-30MLC All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 4 — 15 June 2012 13 of 14
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the gener al terms and conditions of commercial
sale, as published athttp://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors product s by customer.
No offer to sell or license — Nothing in this document may b e interpreted or
construed as an of fer to sell product s that is op en for accept ance or the grant ,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) descri bed herein may
be subject to export control regulat i ons. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automo tive use. It i s neit her qualif ied nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product cl aims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated ) versio n of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
9.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
Adelante,Bitport,Bitsound,CoolFlux,CoReUse,DESFire,EZ-HV,FabKey,G
reenChip,HiPerSmart,HITAG,I²C-bus
logo,ICODE,I-CODE,ITEC,Labelution,MIFARE,MIFARE Plus,MIFARE
Ultralight,MoReUse,QLPAK,Silicon
Tuner,SiliconMAX,SmartXA,STARplug,TOPFET,TrenchMOS,TriMedia
andUCODE — are trademarks of NXP B.V.
HD Radio andHD Radio logo — are trademarks of iBiquity Digital
Corporation.
10. Contact information
For more information, please visit:http://www.nxp.com
For sales office addresses, please send an email to :salesaddresses@nxp.com
NXP Semiconductors PSMN013-30MLC
N-channel 30 V 13.6 m logic level MOSFET in LFPAK33 using NextPower Technology
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 15 June 2012
Document identifier: PSMN013-30MLC
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
11. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.1 General description . . . . . . . . . . . . . . . . . . . . . .1
1.2 Features and benefits. . . . . . . . . . . . . . . . . . . . .1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . .2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . .2
4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2
5 Thermal characteristics . . . . . . . . . . . . . . . . . . .4
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5
7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
8 Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11
9 Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
9.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
9.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
9.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . .1 2
9.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
10 Contact information. . . . . . . . . . . . . . . . . . . . . .1 3