60 GHz Millimeterwave
Transmitter, 57 GHz to 64 GHz
Data Sheet
HMC6300
Rev. C Document Feedback
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FEATURES
Frequency band: 57 GHz to 64 GHz
RF signal bandwidth: up to 1.8 GHz
Output power for 1 dB compression: 15 dBm
Gain: 5 dB to 35 dB
Digital and analog RF and IF gain control
Integrated frequency synthesizer
Integrated image reject filter
Partially external loop filter
Support for external local oscillator (LO)
On-chip temperature sensor
Support for 256 QAM modulation
Integrated minimum shift keying (MSK) modulator
Universal analog I/Q baseband interface
3-wire serial digital interface
65-ball, RoHS compliant, wafer level ball grid array
APPLICATIONS
Small cell backhaul
60 GHz industrial, scientific, and medical (ISM) band
data transfer
Multiple Gbps data communication
WiGig/802.11ad radio
High definition video transmission
Radar/high resolution imaging
GENERAL DESCRIPTION
The HMC6300 is a complete millimeterwave transmitter
integrated circuit in a 6 mm × 4 mm RoHS compliant wafer
level ball grid array (WLBGA) that operates from 57 GHz to
64 GHz with up to 1.8 GHz modulation bandwidth.
An integrated synthesizer provides tuning in 250 MHz,
500 MHz, or 540 MHz steps with excellent phase noise to
support up to 64 QAM modulation. Optionally, an external LO
can be injected allowing for user selectable LO characteristics or
phase coherent transmit and receive operation, as well as
modulation up to 256 QAM. Support for a wide variety of
modulation formats is provided through a universal analog
baseband I/Q interface. The transmitter chip optionally
supports dedicated frequency-shift keying (FSK), minimum
shift keying (MSK), and on-off keying (OOK) modulation
formats for lower cost and lower power serial data links without
the need for high speed data converters.
A differential output provides up to 15 dBm linear output
power into a 100 Ω load. Single-ended operation is also
supported up to 12 dBm. Together with the HMC6301, a
complete 60 GHz transceiver chipset is provided for multiple
Gbps operation in the unlicensed 60 GHz ISM band.
FUNCTIONAL BLOCK DIAGRAM
REFCLK_P
RFOUT_P
BB_QN
BB_QP
BB_IM
BB_IP
FM_MQ
FM_PQ
FM_MI
FM_PI
RFOUT_N
REFCLK_N
DET
OUT
EXTLO_P
EXTLO_N
DRIVER
×3
÷2
IF AMP
DIV
LPF CP PFD
MUX
HMC6300
MSK
MOD
90°
180°
SCANOUT
CLK
DATA
INTERFACE
SERIAL
PA
14423-001
Figure 1.
HMC6300 Data Sheet
Rev. C | Page 2 of 25
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Specifications, 57 GHz to 63 GHz ............................ 3
Electrical Specifications, 63 GHz to 64 GHz ............................ 4
Recommended Operating Conditions ...................................... 5
Power Consumption .................................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions ..............................8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 13
Register Array Assignment and Serial Interface .................... 13
Transmitter Register Array Assignments ................................ 15
Synthesizer Settings .................................................................... 20
Applications Information .............................................................. 22
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
REVISION HISTORY
6/2017—Rev. B to Rev. C
Change to Figure 17 ....................................................................... 14
Changes to Table 7 .......................................................................... 15
12/2016—Rev. A to Rev. B
Changes to Figure 11 and Figure 14 ............................................. 11
Changes to Ordering Guide .......................................................... 25
9/2016—v00.0716 to Rev. A
Updated Format .................................................................. Universal
Added Minimum Gain Parameter, Table 1 ................................... 3
Changes to Recommended Operating Conditions, Table 3 ....... 5
Changes to Figure 17 ...................................................................... 14
Added Ordering Guide Section .................................................... 25
7/2016—Revision v00.0716: Initial Version
Data Sheet HMC6300
Rev. C | Page 3 of 25
SPECIFICATIONS
TA = 25°C, reference frequency = 71.4286 MHz, IF bandwidth = maximum, input impedance = 100 Ω differential, output impedance =
100 Ω differential, input signal level (high modulator gain) = −36 dBm on each of the four baseband inputs, power amplifier
configuration is differential, unless otherwise noted.
ELECTRICAL SPECIFICATIONS, 57 GHz TO 63 GHz
Table 1. Electrical Specifications, 57 GHz to 63 GHz
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
FREQUENCY STEP SIZE With 71.4286 MHz reference clock 250 MHz
With 142.857 MHz reference clock 500 MHz
With 154.2857 MHz reference clock 540 MHz
MODULATION BANDWIDTH Full I/Q bandwidth 1.8 GHz
GAIN
Minimum Gain 5 dB
Maximum Gain 32.5 35 dB
Modulator Gain Control High and low gain settings 9 dB
IF Gain Control 14 dB
RF Gain Control 22 dB
OUTPUT POWER
Output Power for 1 dB Compression (P1dB) Balanced into 100 Ω 15 dBm
Saturated Output Power (PSAT) Balanced into 100 Ω 13.9 17 dBm
Output Power for 1 dB Compression (P1dB) Singled-ended into 50 Ω 12 dBm
Saturated Output Power (PSAT) Singled-ended into 50 Ω 14 dBm
Detector Power Range
−10 to +15
dBm
TEMPERATURE SENSOR RANGE Four levels −40 +85 °C
SUPPRESSION AND REJECTION
Sideband Suppression 15 30 dBc
Image Rejection 40 dBc
LO Suppression At 6/7 of RF carrier frequency (3 × LO) 10 20 dBc
Carrier Suppression Without calibration 30 dBc
PHASE
Phase Noise
@ 100 kHz Offset −75 dBc/Hz
@ 1 MHz Offset −93 dBc/Hz
@ 10 MHz Offset −114 dBc/Hz
@ 100 MHz Offset −122 dBc/Hz
Phase-Locked Loop (PLL) Bandwidth Using internal filter 300 kHz
POWER DISSIPATION
Balanced 1.0 W
Single-Ended 0.88 W
Balanced, External LO 0.75 W
HMC6300 Data Sheet
Rev. C | Page 4 of 25
ELECTRICAL SPECIFICATIONS, 63 GHz TO 64 GHz
Table 2. Electrical Specifications, 63 GHz to 64 GHz
Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY STEP SIZE
With 71.4286 MHz reference clock
250
MHz
With 142.857 MHz reference clock 500 MHz
With 154.2857 MHz reference clock 540 MHz
MODULATION BANDWIDTH
Full I/Q bandwidth
1.8
GHz
GAIN
Maximum Gain 30.5 32 dB
Modulator Gain Control High and low gain settings 9 dB
IF Gain Control 14 dB
RF Gain Control 22 dB
OUTPUT POWER
Output Power for 1 dB Compression (P1dB) Balanced into 100 Ω 15 dBm
Saturated Output Power (PSAT) Balanced into 100 Ω 13.9 17 dBm
Output Power for 1 dB Compression (P1dB) Singled-ended into 50 Ω 12 dBm
Saturated Output Power(P
SAT
)
Singled-ended into 50 Ω
14
dBm
Detector Power
−10 to +15
dBm
TEMPERATURE SENSOR RANGE Four levels −40 +85 °C
SUPPRESSION AND REJECTION
Sideband Suppression 15 30 dBc
Image Rejection 40 dBc
LO Suppression At 6/7 of RF carrier frequency (3 × LO) 10 20 dBc
Carrier Suppression
Without calibration
30
dBc
PHASE
Phase Noise @ 100 kHz Offset
−75
dBc/Hz
Phase Noise @ 1 MHz Offset −93 dBc/Hz
Phase Noise @ 10 MHz Offset −114 dBc/Hz
Phase Noise @ 100 MHz Offset −122 dBc/Hz
PLL Bandwidth Using internal filter 300 kHz
POWER DISSIPATION
Balanced 1.0 W
Single-Ended 0.88 W
Balanced, External LO) 0.75 W
Data Sheet HMC6300
Rev. C | Page 5 of 25
RECOMMENDED OPERATING CONDITIONS
Table 3.
Parameter Symbol Min Typ Max Unit
POWER SUPPLY
Power Amplifier VCCPAN, VCCPAP 3.9 4 4.1 V dc
VDDPA 2.565 2.7 2.835 V dc
Driver VCCDRV 2.565 2.7 2.835 V dc
Divider VCCDIV 2.565 2.7 2.835 V dc
Mixer VCCMIX 2.565 2.7 2.835 V dc
Intermediate Frequency VCCIF 2.565 2.7 2.835 V dc
Radio Frequency Variable Gain Amplifier VCCRFVGA 2.565 2.7 2.835 V dc
Tripler VCCTRIP 2.565 2.7 2.835 V dc
VCO VCCVCO 2.565 2.7 2.835 V dc
Digital Circuit VDDD 1.3 1.35 1.48 V dc
Synthesizer VDDSYN 1.3 1.35 1.48 V dc
INPUT VOLTAGE RANGE
Serial Digital Interface DATA, ENABLE, CLK, RESET
Logic High
0.9
1.2
1.4
V
Logic Low −0.05 +0.1 +0.3 V
REFERENCE CLOCK
Reference Clock, Positive REFCLK_P 3.3 V or 2.5 V LVPECL/LVDS, V
1.2 V CMOS V
Reference Clock, Negative REFCLK_N 3.3 V or 2.5 V LVPECL/LVDS, V
1.2 V CMOS V
BASEBAND I/Q
In-Phase Baseband Input
Negative BB_IM 5 100 750 mV p-p
Positive BB_IP 5 100 750 mV p-p
Quadrature Baseband Input
Negative BB_QN 5 100 750 mV p-p
Positive BB_QP 5 100 750 mV p-p
BASEBAND I/Q, COMMON MODE
In-Phase Baseband Input
Negative BB_IM 1.6 V
Positive BB_IP 1.6 V
Quadrature Baseband Input
Negative BB_QN 1.6 V
Positive BB_QP 1.6 V
MSK DATA
MSK In-Phase Input
Negative (Minus) FM_MI 200 500 750 mV p-p
Positive FM_PI 200 500 750 mV p-p
MSK Quadrature Input
Negative (Minus) FM_MQ 200 500 750 mV p-p
Positive
FM_PQ
200
500
750
mV p-p
MSK COMMON MODE 1.1 V
ANALOG GAIN CONTROL
RF Variable Gain Amplifier ANARFVGA 0.1 1.1 2.5 V
IF Variable Gain Amplifier ANAIFVGA 0.1 1.1 2.5 V
EXTERNAL LO
Positive EXTLO_P 0 3 5 dBm
Negative EXTLO_N 0 3 5 dBm
HMC6300 Data Sheet
Rev. C | Page 6 of 25
Parameter Symbol Min Typ Max Unit
DRAIN CURRENT
1.35 V 10 mA
2.7 V 277 mA
4.0 V (Balanced) 58 mA
4.0 V (Singled-Ended)
29
mA
POWER CONSUMPTION
Table 4.
Parameter
Voltage (V)
Typical Current (mA)
Typical Power Consumption (mW)
VCCPAN 4.0 29 116
VCCPAP 4.0 29 116
VCCDRV 2.7 32 86
VCCDIV 2.7 46 124
VCCMIX 2.7 32 86
VCCIF 2.7 31 84
VCCRFVGA 2.7 20 54
VCCTRIP 2.7 56 151
VCCVCO 2.7 52 140
VCCPA 2.7 8 22
VCCD 1.35 0.08 0.1
VCCSYN 1.35 10 13
Data Sheet HMC6300
Rev. C | Page 7 of 25
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
VCCDRV 2.85 V
VCCDIV 2.85 V
VCCPAN, VCCPA P 4.2 V
VCCVCO 2.85 V
VCCRFVGA 2.85 V
VCCIF 2.85 V
VCCMIX 2.85 V
VCC
TRIP
2.85 V
VDDSYN 1.6 V
VDDPA 2.85 V
VDDD 1.6 V
Serial Digital Interface Input Voltage 1.5 V
Thermal Resistance (R
TH
), Junction to
Ground Paddle
9.57°C
Baseband Inputs: BB, FM (Each) 0.75 V p-p
Storage Temperature −55°C to +150°C
Operating Temperature −40°C to 85°C
Reflow Temperature (Maximum Peak) 260°C
ESD Sensitivity, Charged Device Model
(CDM)
Class C3 (250 V)
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
HMC6300 Data Sheet
Rev. C | Page 8 of 25
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
HMC6300
TOP VIEW
(BAL L SIDE DOWN)
A
B
C
D
E
F
G
H
12345678910 11 12
GRO UND ARE A
DET
OUT
REF
OUT
VCC
DRV
BB_QN BB_QP BB_IM BB_IP FM_MQ FM_PQ FM_MI FM_PI VCC
DIV
VCC
PAP
RFB VCC
MIX
VCCIF GND GND GND GND EXTFIL_P EXTFIL_N VCC
DIV
VCC
DIV
GND VSS
DIV
VSS
LPF_BIAS_PLL
RFOUT_P VSS
CP_PFD
REFCLK_P
REFOUT_N VSS
REF_DIG
REFCLK_N
GND VREG
OUT
VDD
SYN
VCC
PAN
VDD
PA
VCC
RFVGA
SCANOUT VDD
D
RESET VCC
TRIP
VSS
VCO
VSS
VCO
VCC
VCO
VCC
VCO
VCO
RCAP
VCC
DRV
ANA
RFVGA
DATA ENABLE CLK ANA
IFVGA
VSS
VCO
EXTLO_N EXTLO_P VSS
VCO
VSS
VCO
VSS
VCO
14423-002
Figure 2. Pin Configuration Diagram
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
A1 DETOUT Detector Output (0.6 V dc to 2.6 V dc).
A2 REFOUT Detector Reference Output (0.6 V dc).
A3, H1 VCCDRV Driver Power Supply (2.7 V dc).
A4 BB_QN Quadrature Negative Baseband Input. This pin is dc-coupled and matched to 50 Ω.
A5 BB_QP Quadrature Positive Baseband Input. This pin is dc-coupled and matched to 50 Ω.
A6 BB_IM In-Phase Negative Baseband Input. This pin is dc-coupled and matched to 50 Ω.
A7 BB_IP In-Phase Positive Baseband Input. This pin is dc-coupled and matched to 50 Ω.
A8 FM_MQ FSK Negative (Minus) Quadrature Input. This pin is dc-coupled and matched to 50 Ω.
A9 FM_PQ FSK Positive Quadrature Input. This pin is dc-coupled and matched to 50 Ω.
A10 FM_MI FSK Negative (Minus) In-Phase Input. This pin is dc-coupled and matched to 50 Ω.
A11 FM_PI FSK Positive In-Phase Input. This pin is dc-coupled and matched to 50 Ω.
A12, B11, B12 VCCDIV Divider Power Supply (2.7 V dc).
B1 VCCPAP Power Amplifier Power Supply (4.0 V dc).
B2
RFB
Detector Circuit Feedback.
B3 VCCMIX Mixer Power Supply (2.7 V dc).
B4 VCCIF IF Power Supply (2.7 V dc).
B5 to B8, C1, F1 GND Analog Ground Connect.
Data Sheet HMC6300
Rev. C | Page 9 of 25
Pin No. Mnemonic Description
B9 EXTFIL_P External PLL Filter (Positive).
B10 EXTFIL_N External PLL Filter (Negative).
C11 VSSDIV Digital Ground for the Synthesizer.
C12 VSSLPF_BIAS_PLL Digital Ground for Synthesizer.
D1
RFOUT_P
Radio Frequency Output (Positive). This pin is ac-coupled and is differentially matched to
100 Ω. This output port is disabled when single-ended output is selected.
D11 VSSCP_PFD Digital Ground for Synthesizer.
D12 REFCLK_P External Reference Clock (Positive). This pin can be dc or ac matched to 50 Ω.
E1 RFOUT_N Radio Frequency Output (Negative). This pin is ac coupled and is diff matched to 100 Ω.
This pin is used if single-ended output is selected.
E11 VSSREF_DIG Digital Ground for Synthesizer.
E12 REFCLK_N External Reference Clock (Negative). This pin can be dc or ac matched to 50 Ω.
F11 VREGOUT VCO Regulator Output.
F12 VDDSYN Synthesizer Power Supply (1.3 V dc).
G1 VCCPA N Power Amplifier Power Supply (4.0 V dc).
G2 VDDPA Power Amplifier Power Supply (2.7 V dc).
G3 VCCRFVGA RF VGA Power Supply (2.7 V dc).
G4 SCANOUT Serial Digital Interface Output (1.2 V CMOS).
G5 VDDD Digital Circuits Power Supply (1.3 V dc).
G6 RESET Serial Digital Interface Reset (1.2 V CMOS).
G7 VCCTRIP Tripler Power Supply (2.7 V dc).
G8, G9, H7, H10 to H12
VSS
VCO
Digital Ground for the VCO.
G10, G11 VCCVCO VCO Power Supply (2.7 V dc).
G12 VCORCAP External Capacitor Connection for the VCO Regulator.
H2 ANARFVGA 0.1 V to 2.4 V RF VGA Analog Control. Connect Pin H2 to 2.7 V dc for digital control.
H3 DATA Serial Digital Interface Data (1.2 V CMOS).
H4 ENABLE Serial Digital Interface Enable (1.2 V CMOS).
H5 CLK Serial Digital Interface Clock (1.2 V CMOS).
H6 ANAIFVGA 0.1 V to 2.4 V IF VGA Analog Control. Connect Pin H6 to 2.7 V dc for digital control.
H8 EXTLO_N External LO (Negative) Input.
H9 EXTLO_P External LO (Positive) Input.
HMC6300 Data Sheet
Rev. C | Page 10 of 25
TYPICAL PERFORMANCE CHARACTERISTICS
50
10
20
15
25
35
45
30
40
57 58 59 6160 63
62 64
GAI N ( dB)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
14423-003
Figure 3. Maximum Gain vs. Frequency over Temperature, IF and RF
Attenuation = 0 dBm
24
22
20
18
16
14
12
10
8
6
4
2
0
00.30.50.81.01.31.51.82.02.2
ATTENUAT ION ( dB)
ANALOG CONTROL VOLTAGE (V)
+85°C
+25°C
–40°C
14423-004
Figure 4. RF Attenuation vs. Analog Control Voltage over Temperature,
Measurement Taken at 60 GHz, IF Attenuation = 0 dBm
18
0
4
10
14
16
8
2
6
12
0 1 2 5 7 9 113 4 6 8 10 12 13 14 15
ATTENUATION ( dB)
DIGITAL SETTING
+85°C
+25°C
–40°C
14423-005
Figure 5. RF Attenuation vs. Digital Setting over Temperature,
Measurement Taken at 60 GHz, IF Attenuation = 0 dBm
–2
14
10
4
0
6
12
8
2
00.501.001.50 0.250.751.251.752.00
ATTENUAT ION ( dB)
ANALOG CONTROL VOLTAGE (V)
+85°C
+25°C
–40°C
14423-006
Figure 6. IF Attenuation vs. Analog Control Voltage over Temperature,
Measurement Taken at 60 GHz, RF Attenuation = 0 dBm
18
0
4
10
14
16
8
2
6
12
0 1 2 5 7 9 113 4 6 810 12 13 14 15
ATTENUATION ( dB)
DIGITAL SETTING
+85°C
+25°C
–40°C
14423-007
Figure 7. IF Attenuation vs. Digital Setting over Temperature,
Measurement Taken at 60 GHz, RF Attenuation = 0 dBm
20
18
16
14
12
10
8
6
4
2
057 58 59 60 61 62 63 64
P1dB (dBm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
14423-008
Figure 8. Output P1dB vs. Frequency over Temperature, IF and RF
Attenuation = 0 dBm
Data Sheet HMC6300
Rev. C | Page 11 of 25
25
23
21
19
17
15
13
11
9
7
557 58 59 60 61 62 63 64
P
SAT
(d Bm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
14423-009
Figure 9. Output Saturated Power (PSAT) vs. Frequency over Temperature,
IF and RF Attenuation = 0 dBm
–25
–30
–35
–40
–45
–50
–55
–6057 58 59 60 61 62 63 64
CARRIER S UP P RE S S ION ( dBc)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
14423-010
Figure 10. Carrier Suppression vs. Frequency over Temperature, IF and RF
Attenuation = 0 dBm
–60
–140
–120
–130
–110
–90
–70
–100
–80
1k 10k 100K 1M 100M
10M 1G
PHASE NOISE (dBc/Hz)
FRE Q UE NCY ( Hz )
+85°C
+25°C
–40°C
14423-011
Figure 11. Phase Noise vs. Frequency Offset over Temperature, Internal
LO, Measurement Taken at 60 GHz
25
20
10
15
5
057 58 59 60 61 62 63 64
OI P 3 ( dBm)
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
14423-012
Figure 12. OIP3 vs. Frequency over Temperature, Total POUT = 0 dBm, IF
and RF Attenuation = 0 dBm
–25
–30
–35
–40
–45
–50
–55
–60
SIDE BAND S UP P RE S S ION ( dBc)
57 58 59 60 61 62 63 64
FREQUENCY ( GHz)
+85°C
+25°C
–40°C
14423-013
Figure 13. Sideband Suppression vs. Frequency over Temperature, IF and
RF Attenuation = 0 dBm
–60
–140
–120
–130
–110
–90
–70
–100
–80
PHASE NOISE (dBc/Hz)
FRE Q UE NCY ( Hz )
+85°C
+25°C
–40°C
14423-014
1k 10k 100K 1M 100M10M 1G
Figure 14. Phase Noise vs. Frequency Offset over Temperature, External
LO, Measurement Taken at 60 GHz
HMC6300 Data Sheet
Rev. C | Page 12 of 25
10
0.01
1
0.1
0 2 46810 12 14 16 18 20
OUTPUT VOLTAGE (V)
OUT P UT PO WER (dBm)
+85°C
+25°C
–40°C
14423-015
Figure 15. Detector Output Voltage vs. Output Power over Temperature,
Measurement Taken at 60 GHz, and 1.15 kΩ Connecting DETOUT and RFB Pins
1
16
4
8
2
–40 –30 –20 10 30 50 70
–10 020 40 60 80 90
SENSOR READI NG
TEMPERATURE (°C)
14423-016
Figure 16. Temperature Sensor Reading vs. Temperature
Data Sheet HMC6300
Rev. C | Page 13 of 25
THEORY OF OPERATION
An integrated frequency synthesizer creates a low phase noise LO
between 16.3 GHz and 18.3 GHz. The step size of the synthesizer
equates to 250 MHz steps at RF when used with a 71.42857 MHz
reference crystal or 500 MHz if used with a 142.857 reference
crystal. To support IEEE channels (ISM band) with a 540 MHz
step size, use a 154.2857 MHz reference crystal.
If the chip is configured for I/Q baseband input, these signals
are quadrature modulated onto an 8 GHz to 9.1 GHz sliding IF
using the synthesized LO divided by two. There are also options
to input AM/FM/FSK/MSK waveforms directly to the on-chip
IF modulators. The IF signal is then filtered and amplified with
14 dB of variable gain, then mixed with three times the LO
frequency to upconvert to an RF frequency between 57 GHz
and 64 GHz.
Integrated notch filters attenuate the lower mixing product at
40 GHz to 46 GHz. Three RF amplifier stages provide gain to
allow up to 15 dBm of linear and differential output power with
22 dB of variable gain. IF and RF gain can be controlled using
either analog voltages or the digital SPI. For lower power consump-
tion, half of the power amplifier can be disabled to run in a
single-ended configuration; this drops the output power by 3 dB.
An on-chip power detector can be used to monitor the rms
output power. The detector output pin (DETOUT) is connected
through an external resistor to the RFB pin. A resistor value of
1.15 kΩ is recommended for optimal coverage up to the P1dB
point of the transmitter. The REFOUT pin provides the reference
voltage for the detector, and the difference between DETOUT and
REFOUT is used to estimate the output power.
The phase noise and quadrature balance of the on-chip synthesizer
is sufficient to support up to 64 QAM modulation. For higher
order modulation (up to 256 QAM or less than 250 MHz step
size), the HMC6300 can be operated using an external LO.
The HMC6300 transmitter is ideal for FDD operation together
with the HMC6301 receiver chip. However, both devices can
support TDD operation by enabling and disabling the circuits.
All of the enables are placed in register array, four of which
allow for full chip enable or disable in one SPI write.
There are no special power sequencing requirements for the
HMC6300; all voltages are to be applied simultaneously.
REGISTER ARRAY ASSIGNMENT AND SERIAL
INTERFACE
The register arrays for both the transmitter and receiver are
organized into 32 rows of 8 bits. Using the serial interface, the
arrays are written or read one row at a time, as shown in Figure 17
and Figure 18, respectively. Figure 17 shows the sequence of
signals on the ENABLE, CLK, and DATA lines to write one
8-bit row of the register array. The ENABLE line goes low, the
first of 18 data bits (Bit 0) is placed on the DATA line, and 2 ns
or longer after the DATA line stabilizes, the CLK line goes high
to clock in Data Bit 0. The DATA line should remain stable for
at least 2 ns after the rising edge of CLK.
A write operation requires 18 data bits and 18 clock pulses, as
shown in Figure 17. The 18 data bits contain the 8-bit register
array row data (LSB is clocked in first), followed by the register
array row address (ROW 0 through ROW 23, 000000 to 001111,
LSB first), the read/write bit (set to 1 to write), and finally the
Tx Chip Address 110, LSB first).
The Tx IC supports a serial interface running up to several
hundred megahertz, and the interface is 1.2 V CMOS levels.
Note that the register array row address is six bits, but only four
are used to designate 32 rows, the two MSBs are 0.
After the 18th clock pulse of the write operation, the ENABLE
line returns high to load the register array on the IC; prior to
the rising edge of the ENABLE line, no data is written to the
array. The CLK line should have stabilized in the low state at
least 2 ns prior to the rising edge of the ENABLE line.
HMC6300 Data Sheet
Rev. C | Page 14 of 25
ENABLE
TIME = 0
CLK
DATA
DATA ARRAY ADDRE S S CHIP
ADDRESS
R/W = 1
LSB
LSB
LSB
MSB
MSB
MSB
0
118
12345678910 11 12 13 14 15 16 17
14423-017
Figure 17.Timing Diagram for Writing a Row of the Transmitter Serial Interface
TIME = 0
ENABLE
CLK
DATA
SCAN OUT WRI TE DAT A =
(xxxxxxxx) ARRAY ADDRE SS READ DAT A
LSB
LSB
LSB
LSB
MSB
MSB
MSB
MSB
R/W = 0
127
CHIP
ADDRESS
012345678910 11 12 13 14 15 16 17
01234567
14423-018
Figure 18. Timing Diagram for Reading a Row of the Transmitter Serial Interface
Data Sheet HMC6300
Rev. C | Page 15 of 25
TRANSMITTER REGISTER ARRAY ASSIGNMENTS
In the following table, N/A means not applicable. All register arrays are read/write, unless otherwise indicated.
Table 7. Transmitter Register Array Assignments
Register Array Row
and Bit Internal Signal Name Signal Function
ROW0 N/A Not used.
ROW1
ROW1, Bit 7
pa_sel_vgbs<3>
Controls the regulator for the base voltage of the power amplifier output
transistors.
ROW1, Bits[7:3] = 1100 for normal operation.
ROW1, Bit 6
pa_sel_vgbs<2>
ROW1, Bit 5 pa_sel_vgbs<1>
ROW1, Bit 4 pa_sel_vgbs<0>
ROW1, Bit 3 pa_sel_vref<3> Controls the bias current for the power amplifier output transistors.
ROW1, Bits[3:0] = 1010 for normal operation.
ROW1, Bit 2 pa_sel_vref<2>
ROW1, Bit 1 pa_sel_vref<1>
ROW1, Bit 0 pa_sel_vref<0>
ROW2
ROW2, Bit 7
pa_sel_alc_dac<3>
Factory diagnostics; ROW2.
Bits[7:4] = 1111 for normal operation.
ROW2, Bit 6 pa_sel_alc_dac<2>
ROW2, Bit 5 pa_sel_alc_dac<1>
ROW2, Bit 4 pa_sel_alc_dac<0>
ROW2, Bit 3 pa_sep_pa_pwrdn_fast Active high for normal operation.
ROW2, Bit 2 pa_pwrdwn_fast Active high for normal operation.
ROW2, Bit 1 pa_se_sel Control for Tx output interface; active low for differential Tx output; active high for
Tx single-ended output.
ROW2, Bit 0 power_det_pwrdn Active low to enable Tx power detector.
ROW3
ROW3, Bit 7 driver_bias<2> Controls the bias current for the power amplifier driver.
ROW3, Bits[7:5] = 111 for normal operation.
ROW3, Bit 6 driver_bias<1>
ROW3, Bit 5 driver_bias<0>
ROW3, Bit 4 driver_bias2<2> Controls the bias current for the Power Amplifier Predriver 2.
ROW3, Bits[4:2] = 101 for normal operation.
ROW3, Bit 3 driver_bias2<1>
ROW3, Bit 2 driver_bias2<0>
ROW3, Bit 1 en_ifmix_HiCG Active high to enable high gain mode in IF mixer.
ROW3, Bit 0 en_tempflash Active high to enable temperature sensor.
ROW4
ROW4, Bit 7 driver_pwrdn Active high to power down the driver amplifier.
ROW4, Bit 6 upmixer_pwrdn Active high to power down the upmixer.
ROW4, Bit 5 ifvga_pwrdn Active high to power down the IF VGA.
ROW4, Bit 4 divider_pwrdn Active high to power down the divider.
ROW4, Bit 3 pa_pwrdn Active high to power down the power amplifier.
ROW4, Bit 2 rfvga_pwrdn Active high to power down the RF VGA.
ROW4, Bit 1 tripler_pwrdn Active high to power down the tripler.
ROW4, Bit 0 if_upmixer_pwrdn Active high to power down the IF upmixer.
ROW5
ROW5, Bit 7 tripler_bias<13> Controls bias of frequency tripler.
ROW5, Bits[7:0] = 11111111 for normal operation.
ROW5, Bit 6 tripler_bias<12>
ROW5, Bit 5 tripler_bias<11>
ROW5, Bit 4 tripler_bias<10>
ROW5, Bit 3 tripler_bias<9>
ROW5, Bit 2 tripler_bias<8>
ROW5, Bit 1
tripler_bias<7>
ROW5, Bit 0 tripler_bias<6>
HMC6300 Data Sheet
Rev. C | Page 16 of 25
Register Array Row
and Bit Internal Signal Name Signal Function
ROW6
ROW6, Bit 7 tripler_bias<5> Controls bias of frequency tripler.
ROW6, Bits[7:2] = 111011 for normal operation.
ROW6, Bit 6 tripler_bias<4>
ROW6, Bit 5 tripler_bias<3>
ROW6, Bit 4 tripler_bias<2>
ROW6, Bit 3
tripler_bias<1>
ROW6, Bit 2 tripler_bias<0>
ROW6, Bit 1
N/A
Not used.
ROW6, Bit 0
ROW7
ROW7, Bit 7 ifvga_vga_adj<3> IF variable gain amplifier gain control bits.
ROW7, Bits[7:4] = 0000 is highest gain and 1101 is lowest gain.
Attenuation is ≈ 1.3 dB per step, ≈ 17 dB maximum.
ROW7, Bit 6 ifvga_vga_adj<2>
ROW7, Bit 5 ifvga_vga_adj<1>
ROW7, Bit 4 ifvga_vga_adj<0>
ROW7, Bit 3 ifvga_tune<3> Controls the tuning of the IF filter for the variable gain amplifier.
ROW7, Bits[3:0] = 1111 for normal operation.
ROW7, Bit 2 ifvga_tune<2>
ROW7, Bit 1 ifvga_tune<1>
ROW7, Bit 0 ifvga_tune<0>
ROW8
ROW8, Bit 7
ifvga_bias<3>
Controls the bias current of the IF variable gain amplifier.
ROW8, Bits[7:4] = 1000 for normal operation.
ROW8, Bit 6 ifvga_bias<2>
ROW8, Bit 5 ifvga_bias<1>
ROW8, Bit 4 ifvga_bias<0>
ROW8, Bit 3 if_upmixer_tune<3> Controls the tuning of the IF filter for the IF to RF upmixer.
ROW8, Bits[3:0] = 1111 for normal operation.
ROW8, Bit 2 if_upmixer_tune<2>
ROW8, Bit 1 if_upmixer_tune<1>
ROW8, Bit 0 if_upmixer_tune<0>
ROW9
ROW9, Bit 7 ifvga_q_cntrl<2> Controls the Q of the IF filter in the baseband to IF upmixer.
ROW9, Bits[7:5] = 000 for the highest Q and highest gain.
To reduce Q and widen bandwidth, increment ROW9, Bits[7:5] in sequence, as
follows:
001
100
101
111
ROW9, Bit 6 ifvga_q_cntrl<1>
ROW9, Bit 5 ifvga_q_cntrl<0>
ROW9, Bit 4 N/A Not used.
ROW9, Bit 3
ROW9, Bit 2
ROW9, Bit 1
ROW9, Bit 0
ROW10
ROW10, Bit 7 enable_FM Active high to enable FSK/MSK modulation inputs.
0 = normal I/Q operation.
ROW10, Bit 6 if_refsel Reserved for diagnostic purposes.
ROW10, Bits[6:5] = 10 for normal operation.
ROW10, Bit 5 bg_monitor
ROW10, Bit 4 enDig_IFVGA_Gain_Control Active high to enable digital control of IFVGA gain.
ROW10, Bit 3
ipc_pwrdn
Active high to power down the chip current reference generator.
ROW10, Bit 2 if_bgmux_pwrdn Active high to power down one of three on-chip band gap references (IF) and
associated mux.
ROW10, Bit 1 upmix_cal_pwrdn Active high to power down upmixer calibration.
ROW10, Bit 0 TempSensor_pwrdn Active high to power down the temperature sensor.
ROW11
Data Sheet HMC6300
Rev. C | Page 17 of 25
Register Array Row
and Bit Internal Signal Name Signal Function
ROW11, Bit 7 RFVGAgain<3> RF variable gain amplifier control bits.
ROW11, Bits[7:4] gain settings as follows:
0000 = highest gain.
1111 = lowest gain.
Attenuation is ≈ 1.3 dB/step, ≈ 17 dB maximum.
ROW11, Bit 6 RFVGAgain<2>
ROW11, Bit 5 RFVGAgain<1>
ROW11, Bit 4 RFVGAgain<0>
ROW11, Bit 3 enRFVGA_Ana Active high to enable analog gain control of RFVGA.
ROW11, Bit 2 RFVGA_ICtrl<2> Controls bias current of RF variable amplifier.
ROW11, Bits[2:0] = 011 for normal operation.
ROW11, Bit 1 RFVGA_ICtrl<1>
ROW11, Bit 0 RFVGA_ICtrl<0>
ROW12
ROW12, Bit 7 upmix_cal<7> 3 × LO feedthrough calibration of RF upmixer.
ROW12, Bits[7:0] = 01100100 for uncalibrated operation.
ROW12, Bit 6 upmix_cal<7>
ROW12, Bit 5 upmix_cal<7>
ROW12, Bit 4 upmix_cal<7>
ROW12, Bit 3 upmix_cal<7>
ROW12, Bit 2 upmix_cal<7>
ROW12, Bit 1 upmix_cal<7>
ROW12, Bit 0 upmix_cal<7>
ROW13 N/A Not used.
ROW14
N/A
Not used.
ROW15 N/A Not used.
ROW16
ROW16, Bit 7
byp_synth_LDO
Factory diagnostics.
0 = normal operation.
ROW16, Bit 6 en_cpShort Factory diagnostics.
0 = normal operation.
ROW16, Bit 5 en_cpCMFB Enables CMFB circuit for charge pump, set to 1 when synthesizer is in use.
ROW16, Bit 4 en_cp_dump Enables auxiliary circuit for charge pump, set to 1 when synthesizer is in use.
ROW16, Bit 3 en_cpTRIST Factory Diagnostics.
0 = normal operation.
ROW16, Bit 2
en_cp
Enables charge pump, set to 1 when synthesizer is in use.
ROW16, Bit 1 en_synth_LDO Enables LDO for synthesizer, set to 1 when synthesizer is in use.
ROW16, Bit 0 enbar_synthBG Factory diagnostics.
0 = normal operation.
ROW17
ROW17, Bit 7
en_lockd_clk
Enables lock detector for synthesizer, set to 1 when synthesizer is in use.
ROW17, Bit 6 en_test_divOut Factory diagnostics.
0 = normal operation.
ROW17, Bit 5 en_vtune_flash Enables flash ADCs for VCO vtune port, set to 1 when synthesizer is in use.
ROW17, Bit 4
en_reBuf_DC
Enables dc coupling for reference clock buffer.
ROW17, Bit 3 en_refBuf Enables reference clock buffer, set to 1 when synthesizer is in use.
ROW17, Bit 2 en_stick_div Factory diagnostics.
0 = normal operation.
ROW17, Bit 1 en_FBDiv_cml2cmos Enables auxiliary circuit for the feedback divider chain, set to 1 when synthesizer is
in use.
ROW17, Bit 0 en_FBDiv Enables feedback divider chain, set to 1 when synthesizer is in use.
ROW18
ROW18, Bit 7 N/A Not used.
ROW18, Bit 6 en_nb250m Active high to enable, 250 MHz channel step size.
ROW18, Bit 5 byp_vco_LDO Factory diagnostics.
0 = normal operation.
ROW18, Bit 4 en_extLO Enables external LO, set to 0 when synthesizer is in use.
HMC6300 Data Sheet
Rev. C | Page 18 of 25
Register Array Row
and Bit Internal Signal Name Signal Function
ROW18, Bit 3 en_vcoPk Factory diagnostics.
0 = normal operation.
ROW18, Bit 2 en_vco Enables internal VCO, set to 1 when synthesizer is in use.
ROW18, Bit 1 en_vco_reg Enables internal regulator for VCO, set to 1 when synthesizer is in use.
ROW18, Bit 0 enbar_vcoGB Factory diagnostics.
0 = normal operation.
ROW19
ROW19, Bit 7 N/A Not used.
ROW19, Bit 6
ROW19, Bit 5
ROW19, Bit 4
ROW19, Bit 3
ROW19, Bit 2
ROW19, Bit 1 refsel_synthBG Factory diagnostics.
1 = normal operation.
ROW19, Bit 0 muxRef Factory diagnostics.
0 = normal operation.
ROW20
ROW20, Bit 7 N/A Not used.
ROW20, Bit 6
Fbdiv_code<6>
Feedback divider ratio for the integer-N synthesizer based on Table 8 to Table 10.
ROW20, Bit 5 Fbdiv_code<5>
ROW20, Bit 4 Fbdiv_code<4>
ROW20, Bit 3 Fbdiv_code<3>
ROW20, Bit 2 Fbdiv_code<2>
ROW20, Bit 1 Fbdiv_code<1>
ROW20, Bit 0 Fbdiv_code<0>
ROW21
ROW21, Bit 7 N/A Not used.
ROW21, Bit 6
ROW21, Bit 5
ROW21, Bit 4 refsel_vcoBG Factory diagnostics.
1 = normal operation.
ROW21, Bit 3 vco_biasTrim<3> Sets VCO tank bias current.
ROW21, Bit 2 vco_biasTrim<2> ROW21, Bits[3:0] = 0010 for normal operation.
ROW21, Bit 1 vco_biasTrim<1>
ROW21, Bit 0 vco_biasTrim<0>
ROW22
ROW22, Bit 7 N/A Not used.
ROW22, Bit 6
ROW22, Bit 5
ROW22, Bit 4 vco_bandSel<4> Set for desired frequency.
Table 8, Table 9, and Table 10 contain approximate band settings depending on
the reference clock frequency.
ROW22, Bits[4:0] = valid range 00000 to 10011.
ROW22, Bit 3 vco_bandSel<3>
ROW22, Bit 2 vco_bandSel<2>
ROW22, Bit 1 vco_bandSel<1>
ROW22, Bit 0 vco_bandSel<0>
Data Sheet HMC6300
Rev. C | Page 19 of 25
Register Array Row
and Bit Internal Signal Name Signal Function
ROW23
ROW23, Bit 7 ICP_BiasTrim<2> Sets charge pump current.
ROW23, Bit 6 ICP_BiasTrim<1> ROW23, Bits[7:5] = 011 for normal operation.
ROW23, Bit 5 ICP_BiasTrim<0>
ROW23, Bit 4 vco_offset<0> Sets internal VCO output swing.
ROW23, Bit 3 vco_offset<1> ROW23, Bits[4:0] = 00010 for normal operation.
ROW23, Bit 2 vco_offset<2>
ROW23, Bit 1
vco_offset<3>
ROW23, Bit 0 vco_offset<4>
ROW24 (Read Only)
ROW24, Bit 7 N/A Not used.
ROW24, Bit 6
ROW24, Bit 5
ROW24, Bit 4
ROW24, Bit 3 lockdet Monitor for lock detect.
1 = valid lock.
ROW24, Bit 2 dn Monitor VCO amplitude.
ROW24, Bit 1 up Monitor VCO amplitude.
ROW24, Bit 0 center Monitor VCO amplitude.
ROW25 (Read Only)
ROW25, Bit 7 vtune_flashp<7> VCO amplitude monitor (positive).
ROW25, Bit 6 vtune_flashp<6>
ROW25, Bit 5 vtune_flashp<5>
ROW25, Bit 4 vtune_flashp<4>
ROW25, Bit 3 vtune_flashp<3>
ROW25, Bit 2 vtune_flashp<2>
ROW25, Bit 1 vtune_flashp<1>
ROW25, Bit 0 vtune_flashp<0>
ROW26 (Read Only)
ROW26, Bit 7 vtune_flashn<7> VCO amplitude monitor (negative).
ROW26, Bit 6
vtune_flashn<6>
ROW26, Bit 5 vtune_flashn<5>
ROW26, Bit 4 vtune_flashn<4>
ROW26, Bit 3 vtune_flashn<3>
ROW26, Bit 2 vtune_flashn<2>
ROW26, Bit 1 vtune_flashn<1>
ROW26, Bit 0 vtune_flashn<0>
ROW27 (Read Only)
ROW27, Bit 7 N/A Not used.
ROW27, Bit 6
ROW27, Bit 5
ROW27, Bit 4 tempS<4> Thermometer encoded temperature reading.
ROW27, Bit 3 tempS<3> For ROW27, Bits[4:0], the temperature reading is as follows:
ROW27, Bit 2 tempS<2> 00000 = lowest temperature.
ROW27, Bit 1 tempS<1> 11111 = highest temperature.
ROW27, Bit 0 tempS<0>
ROW28 N/A Not used.
ROW29 N/A Not used.
ROW30 N/A Not used.
ROW31 N/A Not used.
HMC6300 Data Sheet
Rev. C | Page 20 of 25
SYNTHESIZER SETTINGS
Table 8. Synthesizer Settings, IEEE Channels Using 154.2857 MHz Reference
Frequency (GHz) IEEE Channel
Divider Setting, Fbdiv_Code<5:4>,
ROW20, Bits[5:0]
Typical Band Setting, vco_bandSel<4:0>,
ROW22, Bits[4:0]
57.24 001010 00001
57.78 001011 00010
58.32 Channel 1 001100 00010
58.86 001101 00010
59.40 001110 00011
59.94 001111 00011
60.48 Channel 2 010000 00100
61.02 010001 00100
61.56 010010 00101
62.10 010011 00101
62.64 Channel 3 010100 00101
63.18 010101 00110
63.72 010110 00110
64.26 010111 00110
64.8
Channel 4
011000
00111
65.34 011001 00111
65.88 011010 01000
Table 9. 500 MHz Channels Using 142.8571 MHz Reference
Frequency (GHz) Divider Setting Typical Band Setting
56.5 010001 00001
57 010010 00001
57.5 010011 00010
58 010100 00010
58.5 010101 00010
59 010110 00011
59.5 010111 00011
60 011000 00100
60.5 011001 00100
61 011010 00101
61.5 011011 00101
62 011100 00101
62.5 011101 00110
63 011110 00110
63.5 011111 00110
64 100000 00111
Data Sheet HMC6300
Rev. C | Page 21 of 25
Table 10. 250 MHz Channels Using 71.42857 MHz Reference
Frequency (GHz) Divider Setting Typical Band Setting
56.5 0100010 00001
56.75 0100011 00001
57 0100100 00010
57.25 0100101 00010
57.5 0100110 00011
57.75
0100111
00011
58
0101000
00100
58.25
0101001
00100
58.5
0101010
00101
58.75
0101011
00101
59
0101100
00110
59.25
0101101
00110
59.5
0101110
00111
59.75
0101111
00111
60
0110000
01000
60.25
0110001
01000
60.5
0110010
01001
60.75
0110011
01001
61
0110100
01010
61.25 0110101 01010
61.5
0110110
01011
61.75
0110111
01011
62 0111000 01100
62.25 0111001 01100
62.5 0111010 01101
62.75 0111011 01101
63 0111100 01110
63.25 0111101 01110
63.5 0111110 01111
63.75 0111111 01111
64 1000000 01111
HMC6300 Data Sheet
Rev. C | Page 22 of 25
APPLICATIONS INFORMATION
For more information about the HMC6300 evaluation kit, see
the EK1HMC6350 User Guide. The EK1HMC6350 contains all
that is required to set up a simplex 60 GHz millimeterwave link
using standard RF cable interfaces for baseband input and
output. The kit comes with two motherboard printed circuit
boards (PCBs) that provide on-board crystals, USB interface,
supply regulators, and SMA cables for connectorized I/Q
interfaces. Software is supplied to allow the user to read from
and write to all chip level registers using graphical user interface
(GUI) or to upload previously saved register settings.
14423-019
Figure 19. Evaluation PCB Daughter Board
Data Sheet HMC6300
Rev. C | Page 23 of 25
J4
QTH-030-01-F-D-A
GROUNDING
PS_4V_2 DATA
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
ENABLE
CLK
TX_SCANOUT
RESET
BB_QM
BB_QP
BB_IM
BB_IP
TX_REFCLKM
TX_REFCLKP
FMP_I
FMM_I
FMP_Q
FMM_Q
PS_4V_2 GND
GND
GND
GND
GND
GND
GND
ANA_RFVGA
ANA_RFVGA
TX_VCC_PA
TX_VCC_RFVGA
TX_VDDD
TX_VCC_TRIP
TX_VCC_TRIP
TX_VCC_VCO
TX_VCC_VCO
TX_VDD_SYN
NC
TX_VCC_DIV
TX_VCC_DIV
TX_VCC_IF
TX_VCC_MIX
TX_VCC_DRV
TX_VCC_DRV
REF_OUT
DECT_OUT
PS_4V_1
PS_4V_1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
HMC6300
U1
RFOUTN
RFOUTP
EXTFIL_P
EXTFIL_N
DET_OUT
REF_OUT
BB_QM
BB_QP
BB_IM
BB_IP
FMM_Q
FMP_Q
VREG_OUT
VCO_RCAP
VCC_MIX
VCC_IF
VCC_TRIP
VCC_RFVGA
VCC_PAp
VCC_PAn
VCC_DIV
VCC_DIV
VCC_DIV
EXTLO_N
EXTLO_P
FMM_I
FMP_I
RFB
SCANOUT
RESET
DATA
ENABLE
CLK
ANA_IFVGA
VSS_DIV
VSS_LPF_BIAS_PLL
VSS_CP_PFD
VSS_REF_DIG
VSS_VCO
VSS_VCO
VSS_VCO
VSS_VCO
VSS_VCO
VSS_VCO
VDD_PA
VDD_SYN
VDDD
GND
GND
GND
GND
GND
GND
VCC_DRV
VCC_DRV
VCC_VCO
VCC_VCO
RFOUTN
DECT_OUT
RFB
REF_OUT
BB_QM
BB_QP
BB_IM
BB_IP
FMM_Q TX_VCC_MIX
TX_VCC_IF
FMP_Q
TX_OUT
J1
RFOUTP
EXTLO_N
EXTLO_P
1
F1
4MIL-BALUN_60GHz
32
J3
SMA
SMA
J2
R1
1kΩ
C30
1nF
C29
100nF
C28
100nF
C26
1µF
DEPOP R4
1kΩ
FMP_I
FMM_I
RFB
TX_SCANOUT
RESET
DATA
ENABLE
CLK
ANA_IFVGA
TX_VCC_PA
TX_VDD_SYN
TX_VDDD
R5
0VSS_GND
C15
1nF
C24
1nF
C12
1nF
R3
1kΩ
C20
1nF
C21
1nF
TX_VCC_TRIP
TX_VCC_RFVGA
PS_4V_1
PS_4V_2
TX_VCC_DIV
TX_VCC_DRV
TX_VCC_VCO
C23
1nF
C14
1nF
C22
1nF
C16
1nF
C31
1nF
C32
1nF
C17
1nF
C27
100pF
E1 A1
A2
A4
A5
A6
A7
A8
A9
F11
G12
B3
B4
G7
G3
A12
B11
B1
G1
A3
H1
G10
G11
B5
B6
B7
B8
C1
F1
B12
D1
B9
B10
H8
H9
A10
A11
B2
G4
G6
H3
H4
H5
H6
ANA_RFVGA
ANA_RFVGA
H2
REF_CLKP
TX_REFCLKP
D12
REF_CLKN
TX_REFCLKN
E12
C11
D11
E11
C12
G8
H10
H7
H11
H12
G2
F12
G5
G9
DEPOP
DEPOP
DEPOP
92_MMPX-S50-0-1/111_NM-1
14423-020
Figure 20. Evaluation Daughter Board PCB Schematic
HMC6300 Data Sheet
Rev. C | Page 24 of 25
USB-LED
PWR-SUPPLY-LED
SEL1
MUX
USB
5V SUPPLY
EXT CLOCK
VOUT IP
VOUT IM
BB QP BB IM BB IP
VOUT QPVOUT QM
FMP Q FMM Q
FMM IFMP I
BB QM
600-01205-00-2
MUX
SEL0
12
12
RX MODULE
TX MODULE
DECT OUT
REF OUT
TX IFVGA
TX RFVGA
RX LNA CTL
RX IFVGA
60 GHz EVALUATION BOARD
1
260
59
+
+
+
+
++++
1
260
59
R155
C82
R159
R88 J28
C2
C9
J20
FB1
FB2 FB4
FB6
C1
C10
C11
C12
C13
C14
C21
C85 C88
C24
C25
C26
C28
C3
C86
C4
C42
C43
C44
C45
C46
C47
C48
C49
C5
C50C51
C52
C6
C63
C64
C65
C66
C67
C68
C69
C7
C70
C89
C8
C58
C93C90
C56
U3
U15
U16
D1
D4
D7
D8
J8
R119
R157
R161
R13 R15 R17 R19
R21
R22
R23
R24
R56
R57
R58
R69
R62
R63
R64
R65
R66
R68
R67
R70
R71
R72
R73
R131
R82
R85
R86
R87
R89
R90
R91
R92
R93
R94
R95
R96
R97
R98
R99
R167
R178
R123
R128
R129
R14 R16 R18 R20
R32
R59
R77
R103
R61
R79
J10
J11 J12
J13J14J15 J16 J17 J18 J19
J21 J9
U19
J26
J27
J1
Y1
R180
R166
R169
R168
R176
R183
R177
R172
R184
R181
R175
R174
R170
R171
C84 C87
Y4
Y3
U17
U18
U11
R153 R152
C79
R158
J30
C80
C81
C83
C91 C92 C95 C94
R130
R154
R156
R160
R162
R163
R60
R165
R173
R182
R179
R164
U22
J31
J32
J33
J34
J29
C102
C101
C110
C96
C105
C99
C108
C103
C97
C106
C100
C109
U27
U26
U23
U24
R186
R195
R188
R189
R187
R190
R191
R192 R193
U25
C104
C98
C107
R194
R185
14423-021
Figure 21. Evaluation PCB Motherboard
Data Sheet HMC6300
Rev. C | Page 25 of 25
OUTLINE DIMENSIONS
0.815
0.755
0.695
6.050
6.000
5.950
BOTTOM VIEW
(BAL L SIDE UP)
GROUND AREA
TOP VIEW
(BAL L SIDE DO WN)
SIDE VIEW
0.220
0.190
0.160
0.595
0.565
0.535
0.310
0.270
0.230
4.050
4.000
3.950
3.50
REF
5.50 REF
5.75 REF
COPLANARITY
0.10
SEATING
PLANE
01-25-2016-A
0.50
BSC
0.25
BSC 0.25 BSC
PKG-005029
0.50 BSC
0.858
0.425 0.406
1.115
0.455
0.075
1.258 1.03
BALLA1
IDENTIFIER
A
B
C
D
E
F
G
H
1
2
3
4
5
6
78
9
10
11
12
Figure 22. 65-Ball Wafer Level Ball Grid Array [WLBGA]
(BF-65-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
MSL Rating
1
Package Description
Package Option
Branding
2
HMC6300BG46 −40°C to +85°C MSL1 65-Ball Wafer Level Ball Grid Array [WLBGA] BF-65-1 BBFZ
#YYWW
XXXXXXXX-XX
EV1HMC6300BG46 Evaluation Board, PCB Only
EK1HMC6350 60 GHz SMT Transceiver Evaluation Kit
1 Maximum peak reflow temperature of 260°C. The peak reflow temperature must not exceed the maximum temperature for which the package is qualified according
to the moisture sensitivity level (MSL1).
2 BBFZ = RoHS Compliant Part, #YYWW indicates the year and week number, and the assembly lot number is indicated by XXXXXXXX-XX.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14423-0-6/17(C)
