FEATURES
14-bit resolution
3MPPS throughput rate (14-bits)
Functionally complete
Very low noise
Excellent Signal-to-Noise ratio
Edge triggered
Small, 40-pin, TDIP package
Low power, 500mW typical
Low cost
Programmable Analog Bandwidth
The ADCDS-1403 is an application-specifi c
video signal processor designed for electronic-
imaging applications that employ CCD's (charge
coupled devices) as their photodetector. The
ADCDS-1403 incorporates a "user confi gurable"
input amplifi er, a CDS (correlated double sampler)
and a sampling A/D converter in a single package,
providing the user with a complete, high perfor-
mance, low-cost, low-power, integrated solution.
The key to the ADCDS-1403's performance is
a unique, high-speed, high-accuracy CDS circuit,
which eliminates the effects of residual charge,
charge injection and "kT/C" noise on the CCD's
output fl oating capacitor, producing a "valid video"
output signal. The ADCDS-1403 digitizes this
resultant "valid video" signal using a high-speed,
low-noise sampling A/D converter.
The ADCDS-1403 requires only the rising edge
of start convert pulse to initiate its conversion
process. Additional features of the ADCDS-1403
include gain adjust, offset adjust, precision +2.4V
reference, and a programmable analog bandwidth
function.
PRODUCT OVERVIEW
4
3
2
26
INVERTING INPUT
DIRECT INPUT
OFFSET ADJUST
REFERENCE HOLD
27
32, 33 7, 35, 37
DATA VALID
DIGITAL GROUND ANALOG GROUND
25
23
10
24
6
START CONVERT
BIT 1 (MSB)
BIT 14 (LSB)
OUT-OF-RANGE
+2.4V REFERENCE OUTPU
T
+12V
A
–5V
A
+5V
A
+5V
D
39 38 36 34
TIMING
AND
CONTROL
SAMPLING
A/D
NON-INVERTING INPUT
75
9
523
9
0.01μF
5K
9
1 FINE GAIN ADJUST
5
INPUT AMPLIFIER
30 31
A1
CORRELATED
DOUBLE
SAMPLER
AØ
INPUT/OUTPUT CONNECTIONS
Pin Function Pin Function
1 FINE GAIN ADJUST 40 NO CONNECT
2 OFFSET ADJUST 39 +12V
3 DIRECT INPUT 38 –5VA
4 INVERTING INPUT 37 ANALOG GROUND
5 NON-INVERTING INPUT 36 +5VA
6 +2.4V REF. OUTPUT 35 ANALOG GROUND
7 ANALOG GROUND 34 +5VD
8 NO CONNECT 33 DIGITAL GROUND
9 NO CONNECT 32 DIGITAL GROUND
10 BIT 14 (LSB) 31 A1
11 BIT 13 30 AØ
12 BIT 12 29 NO CONNECT
13 BIT 11 28 NO CONNECT
14 BIT 10 27 DATA VALID
15 BIT 9 26 REFERENCE HOLD
16 BIT 8 25 START CONVERT
17 BIT 7 24 OUT-OF-RANGE
18 BIT 6 23 BIT 1 (MSB)
19 BIT 5 22 BIT 2
20 BIT 4 21 BIT 3
Figure 1. ADCDS-1403 Functional Block Diagram
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
31 Mar 2011 ADCDS-1403.B02 Page 1 of 9
ABSOLUTE MAXIMUM RATINGS
Functional Specifi cations
The following specifi cations apply over the operating temperature range, under the follow-
ing conditions: Vcc=+12V, +Vdd=+5V, Vee=–5V, fi n=98KHz, sample rate=3MHz.
PARAMETERS MIN. TYP. MAX. UNITS
+12V Supply (Pin 32) 0 — +14 Volts
–5V Supply (Pin 38) –6.5 — +0.3 Volts
+5V Supply (Pin 34, 36) –0.3 — +6.5 Volts
Digital Input (Pin 25, 26, 30, 31) –0.3 — Vdd+0.3V Volts
Analog Input (Pin 3,4,5) –6 — +6 Volts
Lead Temperature (10 seconds) — — 300 °C
ANALOG INPUT MIN. TYP. MAX. UNITS
Input Voltage Range
(externally confi gurable) 0.350 2.8 — Volts p-p
Input Resistance — 5000 — Ohm
Input Capacitance — 10 — pF
DIGITAL INPUTS
Logic Level
Logic 1 +3.5 — — Volts
Logic 0 — — +.80 Volts
Logic Loading
Logic 1 — — +10 uA
Logic 0 — — –10 uA
DIGITAL OUTPUTS
Logic Levels
Logic 1 (IOH = .5ma) +2.4 — — Volts
Logic 1 (IOH = 50μa) +4.5 — — Volts
Logic 0 (IOL = 1.6ma) — — +0.4 Volts
Logic 0 (IOL = 50ua) — — +0.1 Volts
Internal Reference
Voltage
(Fine gain adjust pin (1) grounded)
+25°C 2.35 2.4 2.45 Volts
0 to 70°C 2.35 2.4 2.45 Volts
–55 to +125°C 2.35 2.4 2.45 Volts
External Current — 1.0 — mA
STATIC PERFORMANCE
Differential Nonlinearity
(Histogram, 98kHz) +25°C –0.90 ±0.5 +.90 LSB
0 to 70°C –0.90 ±0.5 +.90 LSB
–55 to +125°C –1.0 ±0.6 +1.0 LSB
Integral Nonlinearity
+25°C — ±2.5 — LSB
0 to 70°C — ±2.5 — LSB
–55 to +125°C — ±2.5 — LSB
Guaranteed No Missing Codes
0 to 70°C 14 — — LSB
–55 to +125°C 14 — — LSB
DC Noise
+25°C — 1.0 1.6 LSB
0 to 70°C — 1.0 2.0 LSB
–55 to +125°C — 1.25 2.5 LSB
Offset Error
+25°C — ±0.6 ±1.25 %FSR
0 to 70°C — ±0.6 ±1.25 %FSR
–55 to +125°C — ±0.6 ±1.45 %FSR
Gain Error
+25°C — ±1.00 ±2.8 %FSR
0 to 70°C — ±1.35 ±2.8 %FSR
–55 to +125°C — ±1.35 ±2.8 %FSR
DYNAMIC PERFORMANCE MIN. TYP. MAX. UNITS
Reference Hold
Aquisition Time 100 — — ns
Droop
@ +25°C — 25 — mV/us
@ –55 to +125°C — 100 — mV/us
Peak Harmonic (SFDR)
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C — –76 — dB
@ 0 to +70°C — –76 — dB
@ –55 to +125°C — –74 — dB
Peak Harmonic (SFDR)
(Input on pin (5)
Input @ 98kHz)
@ +25 °C — –76 — dB
@ 0 to +70°C — –76 — dB
@ –55 to +125°C — –74 — dB
Total Harmonic Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C — –75 — dB
@ 0 to +70°C — –75 — dB
@ –55 to +125°C — –74 — dB
(Input on pin (5)
Input @ 98kHz)
@ +25 °C — –76 — dB
@ 0 to +70°C — –76 — dB
@ –55 to +125°C — –74 — dB
Signal-to-Noise Ratio
Without Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C 73 75 — dB
@ 0 to +70°C 73 75 — dB
@ –55 to +125°C 70 73 — dB
(Input on pin (5)
Input @ 98kHz)
@ +25 °C 73 75 — dB
@ 0 to +70°C 73 75 — dB
@ –55 to +125°C 70 73 — dB
Signal-to-Noise Ratio
With Distortion
(CDD-IN, input on pin (3)
Input @ 98kHz)
@ +25 °C — 71 — dB
@ 0 to +70°C — 71 — dB
@ –55 to +125°C — 70 — dB
(Input on pin (5)
Input @ 98kHz)
@ +25 °C — 71 — dB
@ 0 to +70°C — 71 — dB
@ –55 to +125°C — 70 — dB
SIGNAL TIMING
Conversion Rate
–55 to +125°C 3 — — MHz
Conversion Time — 200 — nsec
Start Convert Pulse Width 20 150 — nsec
POWER REQUIREMENTS
Power Supply Range
+12V Supply +11.4 +12.0 +12.6 Volts
+5V Supply +4.75 +5.0 +5.25 Volts
–5V Supply –4.75 –5.0 –5.25 Volts
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
31 Mar 2011 ADCDS-1403.B02 Page 2 of 9
TECHNICAL NOTES
1. Obtaining fully specifi ed performance from the ADCDS-1403 requires
careful attention to pc-card layout and power supply decoupling.
The device's analog and digital grounds are connected to each other
internally. Depending on the level of digital switching noise in the overall
CCD system, the performance of the ADCDS-1403 may be improved by
connecting all ground pins (7,32,33,35, 37) to a large analog ground
plane beneath the package. The use of a single +5V analog supply for
both the +5VA (pin 36) and +5VD (pin 34) may also be benefi cial.
2. Bypass all power supplies to ground with a 4.7μf tantalum capacitor in
parallel with a 0.1μf ceramic capacitor. Locate the capacitors as close to
the package as possible.
3. If using the suggested offset and gain adjust circuits
(Figure 3 & 5), place them as close to the ADCDS-1403's package as
possible.
4. A0 and A1 (pins 30, 31) should be bypassed with 0.1μf capacitors to
ground to reduce susceptibility to noise.
ADCDS-1403 Modes of Operation
The input amplifi er stage of the ADCDS-1403 provides the designer
with a tremendous amount of fl exibility. The architecture of the ADCDS-
1403 allows its input-amplifi er to be confi gured in any of the following
confi gurations:
• Direct Mode (AC coupled)
• Non-Inverting Mode
• Inverting Mode
When applying inputs which are less than 2.8Vp-p, a coarse gain
adjustment (applying an external resistor to pin 4) must be performed to
ensure that the full scale video input signal (saturated signal) produces a
2.8Vp-p signal at the input-amplifi er's output (Vout).
In all three modes of operation, the video portion of the signal at the
CDS input (i.e. input-amplifi er's Vout) must be more negative than its asso-
ciated reference level and Vout should
not exceed ±2.8V DC.
The ADCDS-1403 achieves it specifi ed accuracies without the need
for external calibration. If required, the device's small initial offset and
gain errors can be reduced to zero using the FINE GAIN ADJUST (pin1) and
OFFSET ADJUST (pin 2) features.
Figure 2a.
Figure 2b.
4
3
5
75
9
523
9
V
IN
NO CONNECT
V
OUT
= 2.8Vp-p
5k
9
0.01μF
Rext
4
3
5
75
9
523
9
V
IN
NO CONNECT V
OUT
= 2.8Vp-p
5k
9
0.01μF
Rext
Figure 2c.
4
3
5
75
9
523
9
V
IN
NO CONNECT
V
OUT
= 2.8Vp-p
5k
9
0.01μF
Direct Mode (AC Coupled)
This is the most common input confi guration as it allows the ADCDS-
1403 to interface directly to the output of the CCD with a minimum amount
of analog "front-end" circuitry. This mode of operation is used with full-
scale video input signals from 0.350Vp-p to 2.8Vp-p.
Figure 2a. describes the typical confi guration for applications using a
video input signal with a maximum amplitude of 0.350Vp-p. The coarse
gain of the input amplifi er is determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/75)), with all internal resistors having a 1%
tolerance. Additional fi ne gain adjustment can be accomplished using the
Fine Gain Adjust (pin 1 see Figure 5).
Figure 2b. describes the typical confi guration for applications using a
video input signal with an amplitude greater than 0.350Vp-p and less than
2.8Vp-p. Using a single external series resistor (see Figure 4.), the coarse
gain of the ADCDS-1403 can be set, with additional fi ne gain adjustments
being made using the Fine Gain Adjust function (pin 1 see Figure 5). The
coarse gain of the input amplifi er can be determined from the following
equation:
VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having
a 1% tolerance.
POWER REQUIREMENTS MIN. TYP. MAX. UNITS
Power Supply Current
+12V Supply — +13 +16 mA
Power Supply Current
+5V Supply — +40 +46 mA
–5V Supply — –27 –35 mA
Power Dissipation — 0.50 0.60 Watts
Power Supply Rejection
(5%) @ +25°C — ±0.02 ±0.03 %FSR/%V
ENVIRONMENTAL
Operating Temperature Range
ADCDS-1403 0 — +70 °C
ADCDS-1403EX –55 — +125 °C
Storage Temperature –65 — +150 °C
Package Type 40-pin, TDIP
Weight 16.10 grams
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
31 Mar 2011 ADCDS-1403.B02 Page 3 of 9
Inverting Mode
The inverting mode of operation can be used in applications where the
analog input to the ADCDS-1403 has a video input signal whose amplitude
is more positive than its associated reference level. The ADCDS-1403's
correlated double sampler (i.e. input amplifi er's VOUT) requires that the
video signal's amplitude be more negative than its reference level at
all times (see timing diagram for details). Using the ADCDS-1403 in the
inverting mode allows the designer to perform an additional signal inver-
sion to correct for any analog "front end" pre-processing that may have
occurred prior to the ADCDS-1403.
Figure 2e. describes the typical confi guration for applications using
a video input signal with a maximum amplitude of 0.350Vp-p. Additional
fi ne gain adjustments can be made using the Fine Gain Adjust function (pin
1). The coarse gain of this circuit can be determined from the following
equation:
VOUT = 2.8Vp-p = –VIN*(523/75), with all internal resistors having a 1%
tolerance.
Figure 2f. describes the typical confi guration used in applications
needing to invert video input signals whose amplitude is greater than
0.350Vp-p. Using a single external series resistor (see Figure 4.), the initial
gain of the ADCDS-1403 can be set, with additional fi ne gain adjustments
being made using the Fine Gain Adjust function (pin 1). The coarse gain of
this circuit can be determined from the following equation:
VOUT = 2.8Vp-p = –VIN*(523/75+Rext), with all internal resistors having a
1% tolerance.
Figure 4. Coarse Gain Adjustment Plot
Non-Inverting Mode
The non-inverting mode of the ADCDS-1403 allows the designer to
either attenuate or add non-inverting gain to the video input signal. This
confi guration also allows bypassing the ADCDS-1403's internal coupling
capacitor, allowing the user to provide an external capacitor of appropriate
value.
Figure 2c. describes the typical confi guration for applications using
video input signals with amplitudes greater than
0.350Vp-p and less than 2.8Vp-p (with common mode limit of ±2.5V DC).
Using a single external series resistor (see Figure 4.), the coarse gain of the
ADCDS-1403 can be set with additional fi ne gain adjustments being made
using the Fine Gain Adjust function (pin 1 see Figure 5). The coarse gain of
the circuit can be determined from the following equation:
VOUT = 2.8Vp-p = VIN*(1+(523/(75+Rext))), with all internal resistors having
a 1% tolerance.
Figure 2d. describes the typical confi guration for applications using a
video input signal whose amplitude is greater than 2.8Vp-p. Using a single
external series resistor (Rext 1) in conjunction with the internal 5K (1%)
resistor to ground, an attenuation of the input signal can be achieved.
Additional fi ne gain adjustments being made using the Fine Gain Adjust
function (pin 1). The coarse gain of this circuit can be determined from the
following equation:
VOUT = 2.8Vp-p = [VIN*(5000/(Rext1+5000))]*
[1+(523/(75+Rext2))], with all internal resistors having
a 1% tolerance.
Figure 2d.
Figure 2e.
4
3
5
75
9
523
9
NO CONNECT V
OUT
= 2.8Vp-
p
5k
9
0.01μF
Rext1
V
IN
Rext2
4
3
5
75
9
523
9
NO CONNECT V
OUT
= 2.8Vp-p
5k
9
0.01μf
–V
IN
4
3
5
75
9
523
9
NO CONNECT V
OUT
= 2.8Vp-
p
5k
9
0.01μf
–
V
IN
Rext
Figure 2f.
Figure 3. Offset Adjustment Circuit
Offset
Adjust
2
External
Series
Resistor
ADCDS-1403
+5V
–5V
20K
9
Coarse Gain Adjustment Plot
External Gain Resistor vs. Full Scale Video Input
10
100
1000
10000
0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3
Full Scale Video Signal (Volts)
External Gain Resistor (Ohms)
Inverting Mode
Direct Mode
& Non-Inverting
Mode
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
31 Mar 2011 ADCDS-1403.B02 Page 4 of 9
Figure 6. Offset Adjustment vs. External Series Resistor
Offset Adjustment vs. External Series Resistor
10
100
1000
10000
0 5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60
k
External Series Resistor (Ohm's)
±LSB's of Adjustment
Figure 5. Fine Gain Adjustment Circuit
ADCDS-1403
Fine
Gain
Adjust
1
+5V
–5V
2
0K
9
External Series Resistor Value
(
Ohms
)
0.01
0.1
1
10
100
0 5K 10K 15K 20K 25K 30K 35K 40K 45K 50K 55K 60K
Offset Adjustment Sensitivity
External Series Resistor vs. Output Variation (LSB's)
Output Variation (LSB's)
Peak-Peak
variation at
potentiometer
1mV
10mV
100mV
Figure 7. Offset Adjustment Sensitivity
Offset Adjustment
Manual offset adjustment for the ADCDS-1403 can be accomplished
using the adjustment circuit shown in Figure 3. A software controlled
D/A converter can be substituted for the 20K:potentiometer. The offset
adjustment feature allows the user to adjust the Offset/Dark Current level
of the ADCDS-1403 until the output bits are 00 0000 0000 0000 and the
LSB fl ickers between 0 and 1. Offset adjust should be performed before
gain adjust to avoid interaction. The ADCDS-1403's offset adjustment is
dependent on the value of the external series resistor used in the offset
adjust circuit (Figure 3). The Offset Adjustment graph (Figure 6) illustrates
the typical relationship between the external series resistor value and its
offset adjustment capability utilizing ±5V supplies.
Offset Adjustment Sensitivity
It should be noted that with increasing amounts of offset adjustment
(smaller values of external series resistors), the ADCDS-1403 becomes
more susceptible to power supply noise or voltage variations seen at the
wiper of the offset potentiometer.
For Example:
External 50KΩ resistor:
1. 10mV of noise or voltage variation at the potentiometer
will produce 0.25LSB's of output variation.
2. 100mV of noise or voltage variation at the potentiometer
will produce 2.5LSB's of output variation.
The Offset Adjustment Sensitivity graph (Figure 7) illustrates the offset
adjustment sensitivity over a wide range of external resistor and noise
values. If a large offset voltage is required, it is recommended that a very
low noise external reference be used in the offset adjust circuit in place
of power supplies. The ADCDS-1403's +2.4V reference output could be
confi gured to provide the reference voltage for this type of application.
Fine Gain Adjustment
Fine gain adjustment (pin 1) is provided to compensate for the toler-
ance of the external coarse gain resistor (Rext) and/or the unavailability of
exact coarse gain resistor (Rext) values. Note, the fi ne gain adjustment will
not change the expected input amplifi er's full scale VOUT (2.8Vp-p.) Instead,
the gain of the ADCDS-1403's internal A/D is adjusted allowing the actual
input amplifi er's full scale VOUT to produce an output code of all ones (11
1111 1111 1111).
Fine gain adjustment for the ADCDS-1403 is accomplished using
the adjustment circuit shown below (Figure 5). A software controlled D/A
converter can be substituted for the 20K:potentiometer. The fi ne gain
adjust circuit ensures that the video input signal (saturated signal) will be
properly scaled to obtain the desired Full Scale digital output of 11 1111
1111 1111, with the LSB fl ickering between 0 and 1. Fine gain adjust
should be performed following the offset adjust to avoid interaction. The
fi ne gain adjust provides ±256 codes of adjust when ±5V supplies are
used for the Fine Gain Adjust Circuit.
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
31 Mar 2011 ADCDS-1403.B02 Page 5 of 9
Table 1. Out-of-Range Conditions
Table 2. Output Coding
OUT OF
RANGE MSB OVER
RANGE UNDER RANGE INPUT SIGNAL
0 0 0 0 In Range
0 1 0 0 In Range
1 0 0 1 Underrrange
1 1 1 0 Overrange
Notes:
➀ Input Amplifi er VOUT = (Video Signal - Reference Level)
➁ The video portion of the differential signal (input-amplifi er's VOUT) must be more negative than its associated reference
level and VOUT should not exceed ±2.8V DC.
INPUT AMPLIFIER VOUT, ➀ (VOLTS P-P) SCALE DIGITAL OUTPUT OUT-OF-RANGE
Video Signal-Reference Signal > –2.80000 >Full Scale –1LSB 11 1111 1111 1111 1
–2.80000 Full Scale –1LSB 11 1111 1111 1111 0
–2.10000 3/4FS 11 0000 0000 0000 0
–1.40000 1/2FS 10 0000 0000 0000 0
–0.70000 1/4FS 01 0000 0000 0000 0
–0.35000 1/8FS 00 1000 0000 0000 0
–0.000171 1 LSB 00 0000 0000 0001 0
0 0 00 0000 0000 0000 0
Video Signal-Reference Signal <0➁<0 00 0000 0000 0000 1
Output Coding
The ADCDS-1403's output coding is Straight Binary as indicated in
Table 2. The table shows the relationship between the output data coding
and the difference between the reference signal voltage and its correspond-
ing video signal voltage. (These voltages are referred to the output of the
ADCDS-1403's input amplifi er's VOUT).
Programmable Analog Bandwidth Function
When interfacing to CCD arrays with very high-speed "read-out" rates,
the ADCDS-1403's input stage must have suffi cient analog bandwidth to
accurately reproduce the output signals of the CCD array. The amount of
analog bandwidth determines how quickly and accurately the "Reference
Hold" and the "CDS output" signals will settle. If only a single analog band-
width was offered, the ADCDS-1403's bandwidth would be set to acquire
and digitize CCD output signals to 14-bit accuracy, at maximum conversion
rate of 3MHz (333ns see Figure 11. for details). Applications not requiring
the maximum conversion rate would be forced to use the full analog band-
width at the possible expense of noise performance.
The ADCDS-1403 avoids this situation by offering a fully programmable
analog bandwidth function. The ADCDS-1403 allows the user to "bandwidth
limit" the input stage in order to realize the highest level of noise perfor-
mance for the application being considered. Table 3. describes how to select
the appropriate reference hold "aquisition time" and CDS output "settling
time" needed for a particular application. Each of the selections listed in
Table 3. have been optimized to provide only enough analog bandwidth to
acquire a full scale input step, to 14-bit accuracy, in a single conversion.
Increasing the analog bandwidth (using a faster settling and acquisition
time) would only serve to potentially increase the amount of noise at the
ADCDS-1403's output. The ADCDS-1403 uses a two bit digital word to
select four different analog bandwidths for the ADCDS-1403's input stage
(See Table 3. for details).
MSB
OUT-OF-RANGE
"OVERRANGE"
"UNDERRANGE"
Figure 8. Overrange/ Underrange Circuit
Out-of-Range Indicator
The ADCDS-1403 provides a digital Out-of-Range output
signal (pin 24) for situations when the video input signal (saturated signal)
is beyond the input range of the internal A/D converter. The digital output
bits and the Out-of-Range signal correspond to a particular sampled video
input voltage, with both of these signals having a common pipeline delay.
Using the circuit described in Figure 8., both overrange and under-
range conditions can be detected (see Table 1). When combined with a D/A
converter, digital detection and orrection can be performed for both the gain
and offset errors.
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
31 Mar 2011 ADCDS-1403.B02 Page 6 of 9
Table 3. Programmable Analog Bandwidth
REFERENCE HOLD
"ACQUISITION TIME"
CDS OUTPUT
"SETTLING TIME"
A0
(PIN 30)
A1
(PIN 31)
ADCDS-1403 MAXIMUM
CONVERSION RATE –3DB BW
100ns 120ns 0 0 3MHz 10.5MHz
200ns 250ns 1 0 2MHz 6.6MHz
450ns 500ns 0 1 1MHz 3.7MHz
600ns 1000ns 1 1 0.5MHz 2.5MHz
Note: See Figure 11. for timing details
Timing
The ADCDS-1403 requires two independently operated signals to accu-
rately digitize the analog output signal from the CCD array.
• Reference Hold (pin 26)
• Start Convert (pin 25)
The "Reference Hold" signal controls the operation of an internal
sample-hold circuit. A logic "1" places the sample-hold into the hold mode,
capturing the value of the CCD's reference signal. The Reference Hold
Signal allows the user to control the exact moment when the sample-hold
is placed into the "hold" mode. For optimal performance the sample-hold
Figure 9. ADCDS-1403 Connection Diagram
should be placed into the "hold" mode once the reference signal has fully
settled from all switching transients to the desired accuracy (user defi ned).
Once the reference signal has been "held" and the video portion of
the CCD's analog output signal appears at the ADCDS-1403's input, the
ADCDS-1403's correlated double sampler produces a "CDS Output" signal
(see Figure 11.) which is the difference between the "held" reference level
and its associated video level. When the "CDS Output" signal has settled
to the desired accuracy (user defi ned), the A/D conversion process can be
initiated with the rising edge of a single start convert (Pin 25) signal.
+ + +
+12V +5VD –5VA
4.7F
0.1F
39 36 38
1
20KΩ
+5V
–5V
5
4
3
23
22
21
20
19
18
17
16
15
14
13
12
11
10
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14 (LSB)
6
24
27
+2.4V REFERENCE OUT
OUT-OF-RANGE
DATA VALID
ADCDS-1403
4.7F
0.1F
4.7F
0.1F
ANALOG GROUND
NON-INVERTING INPUT
INVERTING INPUT
DIRECT INPUT
+5VA
36
7, 35, 37
+
4.7F
0.1F
26
25
REF. HOLD
START CONVERT
2
20KΩ
+5V
–5V
OFFSET ADJUST
FINE GAIN ADJUST
External Series
Resistor
32, 33 DIGITAL GROUND
30
31
A1
A
0.1F
0.1F
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
31 Mar 2011 ADCDS-1403.B02 Page 7 of 9
Figure 11. ADCDS-1403 Timing Diagram
Figure 10. Reference Hold Timing
Once the A/D conversion has been initiated, Reference Hold (Pin 26)
can be placed back into the "Acquisition" mode in order to begin aquiring
the next reference level. For optimal performance the ADCDS-1403's
internal sample-hold should be placed back into the "Aquisition" mode
(Reference Hold to logic "0") during the CCD's "Reference Quiet Time"
("Reference Quiet Time" is defi ned as the period when the CCD's reference
signal has settled from all switching transients to the desired accuracy
(see Figure 10.)). Placing the sample-hold back into the "aquisition" mode
during the "Reference Quiet Time" prevents the ADCDS-1403's internal
amplifi ers from unecessarily tracking (reproducing) the large switching
transients that occur during the CCD's reset to reference transition.
Reset N Reset N+1 Reset N+2 Reset N+3 Reset N+4
Note: As described in Figure 10, the 60ns min. is dependant on the quality of the CCD's Reference when the ADCDS-1403 is switched back into the track mode
CCD
OUTPUT
START
CONVERT
REFERENCE
HOLD IN
CDS
OUTPUT
DATA
OUTPUT
100ns min.
133ns min
120ns min settling line
Full Scale
Step
150ns min
DATA N-4 VALID DATA N-3 VALID DATA N-2 VALID DATA N-1 VALID DATA N VALID
20ns min
N
Ref N
Video N
Ref. N+1
Video N+1
100ns min.
333ns min.
120ns min. settling time
150ns typ.
20ns max
Ref. N
Video N
Video N+1
Ref. N+2 Video N+1Video N+2 Ref. N+3
Video N+1Video N+3
Ref. N+4
N+2 N+3
NN+1 N+2 N+3
Hold
Acquisition
Time
N+1
Invalid data
30ns min., 50ns max.
DATA VALID
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
®®
DATEL • 11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: help@datel.com
31 Mar 2011 ADCDS-1403.B02 Page 8 of 9
ORDERING INFORMATION
OPERATING 40-PIN
MODEL TEMPERATURE RANGE PACKAGE
ADCDS-1403 0 to 70°C TDIP
ADCDS-1403EX –55 to 125°C TDIP
0.100 TYP.
(2.540)
2.24 TYP.
(56.90)
0.900 ±0.010
(22.86)
1.900 ±0.008
(48.260)
0.23 TYP.
(5.84)
1.27 TYP.
(32.25)
®®
ADCDS-1403
14-BIT, 3MHz
IMAGING SIGNAL PROCESSOR
Made in USA
ADCDS-1403
14-Bit, 3 Megapixels/Second Imaging Signal Processor
. makes no representation that the use of its products in the circuits described herein, or the use of other
technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not
imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change
without notice.
www.datel.com • e-mail: help@datel.com
®®
DATEL
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA
ITAR and ISO 9001/14001 REGISTERED
31 Mar 2011 ADCDS-1403.B02 Page 9 of 9