ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECL FANOUT BUFFER General Description Features The ICS85311 is a low skew, high perfor- mance 1-to-2 Differential-to-2.5V/3.3V ECL/LVPECL HiPerClockSTM Fanout Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels.The ICS85311 is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and part-to-part skew characteristics make the ICS85311 ideal for those clock distribution applications demanding well defined performance and repeatability. * * * Two differential 2.5V/3.3V LVPECL / ECL outputs * * Maximum output frequency: 1GHz * * * * * Output skew: 15ps (maximum) * ECL mode operating voltage supply range: VCC = 0V, VEE = -2.375V to -3.465V * * 0C to 70C ambient operating temperature ICS Block Diagram CLK Pulldown nCLK Pullup One CLK, nCLK input pair CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL Translates any single ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input Part-to-part skew: 100ps (maximum) Propagation delay: 1.4ns (maximum) Additive phase jitter, RMS: 0.14ps (typical), 3.3V LVPECL mode operating voltage supply range: VCC = 2.375V to 3.465V, VEE = 0V Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment Q0 nQ0 Q0 nQ0 Q1 nQ1 Q1 nQ1 1 2 3 4 8 7 6 5 VCC CLK nCLK VEE ICS85311 8-Lead SOIC 3.90mm x 4.903mm x 1.37mm package body M Package Top View IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 1 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Table 1. Pin Descriptions Number Name Type Description 1, 2 Q0, nQ0 Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5 VEE Power Negative supply pin. 6 nCLK Input Pullup 7 CLK Input Pulldown 8 VCC Power Inverting differential clock input. Non-inverting differential clock input. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER Test Conditions 2 Minimum Typical Maximum Units ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA Storage Temperature, TSTG -65C to 150C Package Thermal Impedance, JA 112C/W (0 lfpm) DC Electrical Characteristics Table 3A. Power Supply DC Characteristics, VCC = 3.3V5% or 2.5V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions VCC Positive Supply Voltage IEE Power Supply Current Minimum Typical Maximum Units 3.135 3.3 3.465 V 2.375 2.5 2.625 V 25 mA Maximum Units Table 3B. Differential DC Characteristics, VCC = 3.3V5% or 2.5V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Cureent VPP Peak-to-Peak Input Voltage; NOTE 1 VCMR Common Mode Input Voltage; NOTE 1, 2 Minimum Typical nCLK VCC = VIN = 3.465V or 2.625V 5 A CLK VCC = VIN = 3.465V or 2.625V 150 A nCLK VCC = 3.465V or 2.625V, VIN = 0V -150 A CLK VCC = 3.465V or 2.625V, VIN = 0V -5 A 0.15 1.3 V VEE + 0.5 VCC - 0.85 V NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 3 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Table 3C. LVPECL DC Characteristics, VCC = 3.3V5% or 2.5V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units VCC - 1.4 VCC - 0.9 V VCC - 2.0 VCC - 1.7 V 0.65 1.0 V NOTE1: Outputs terminated with 50 to VCC - 2V. AC Electrical Characteristics Table 4A. AC Characteristics, VCC = 3.3V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions Minimum 0.9 Typical Maximum Units 1 GHz 1.4 ns fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 1GHz tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 156.25MHz, Integration Range (12kHz - 20MHz) tsk(o) Output Skew; NOTE 2, 4 15 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps tR / tF Output Rise/Fall Time 300 700 ps odc Output Duty Cycle 48 52 % 20% to 80% @ 50MHz 0.14 ps NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has been reached under these conditions. All parameters are measured 500MHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Table 4B. AC Characteristics, VCC = 2.5V5%, VEE = 0V, TA = 0C to 70C Symbol Parameter Test Conditions Minimum fMAX Maximum Output Frequency tPD Propagation Delay; NOTE 1 1GHz 0.9 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section 156.25MHz, Integration Range (12kHz - 20MHz) tsk(o) Output Skew; NOTE 2, 4 15 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 100 ps tR / tF Output Rise/Fall Time 300 700 ps odc Output Duty Cycle 48 52 % 20% to 80% @ 50MHz Typical Maximum Units 1 GHz 1.4 ns 0.135 ps See Table 5A for NOTES. IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 4 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Additive Phase Jitter (3.3V) The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz Additive Phase Jitter @ 156.25MHz 12kHz to 20MHz = 0.14ps (typical) Offset Frequency (Hz) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 5 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Parameter Measurement Information 2V 2V VCC Qx SCOPE VCC LVPECL Qx SCOPE LVPECL nQx nQx VEE VEE -1.3V 0.165V -0.5V 0.125V 2.5V Core/ 2.5V LVPECL Output Load AC Test Circuit 3.3V Core/ 3.3V LVPECL Output Load AC Test Circuit VCC nQx Qx nCLK V Cross Points PP V nQy CMR CLK Qy tsk(o) VEE Output Skew Differential Input Level Par t 1 nQx nCLK Qx CLK nQy Par t 2 nQ[0:1] Qy Q[0:1] tPD tsk(pp) Part-to-Part Skew IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER Propagation Delay 6 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Parameter Measurement Information, continued nQ[0:1] nQ[0:1] 80% 80% Q[0:1] VSW I N G t PW t odc = PERIOD t PW 20% 20% Q[0:1] tF tR x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Output Rise/Fall Time Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K Figure 1. Single-Ended Signal Driving Differential Input IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 7 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK CLK Zo = 50 nCLK Zo = 50 nCLK HiPerClockS Input LVHSTL R1 50 IDT HiPerClockS LVHSTL Driver HiPerClockS Input LVPECL R2 50 R1 50 R2 50 R2 50 Figure 2A. HiPerClockS CLK/nCLK Input Driven by an IDT Open Emitter HiPerClockS LVHSTL Driver Figure 2B. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 3.3V 3.3V 3.3V R3 125 3.3V R4 125 3.3V Zo = 50 Zo = 50 CLK CLK R1 100 Zo = 50 nCLK HiPerClockS Input LVPECL R1 84 R2 84 Figure 2C. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V nCLK Zo = 50 Receiver LVDS Figure 2D. HiPerClockS CLK/nCLK Input Driven by a 3.3V LVDS Driver 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50 R4 120 Zo = 60 CLK CLK Zo = 50 Zo = 60 nCLK nCLK HCSL *R4 33 R1 50 R2 50 HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional - R3 and R4 can be 0 Figure 2F. HiPerClockS CLK/nCLK Input Driven by a 2.5V SSTL Driver Figure 2E. HiPerClockS CLK/nCLK Input Driven by a 3.3V HCSL Driver IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 8 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Recommendations for Unused Output Pins Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 3.3V Zo = 50 125 FOUT FIN 125 Zo = 50 Zo = 50 FOUT 50 1 RTT = Z ((VOH + VOL) / (VCC - 2)) - 2 o Zo = 50 VCC - 2V RTT 84 Figure 3A. 3.3V LVPECL Output Termination IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER FIN 50 84 Figure 3B. 3.3V LVPECL Output Termination 9 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Termination for 2.5V LVPECL Outputs ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C. Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to 2.5V VCC = 2.5V 2.5V 2.5V VCC = 2.5V R1 250 R3 250 50 + 50 + 50 - 50 2.5V LVPECL Driver - R1 50 2.5V LVPECL Driver R2 62.5 R2 50 R4 62.5 R3 18 Figure 4A. 2.5V LVPECL Driver Termination Example Figure 4B. 2.5V LVPECL Driver Termination Example 2.5V VCC = 2.5V 50 + 50 - 2.5V LVPECL Driver R1 50 R2 50 Figure 4C. 2.5V LVPECL Driver Termination Example IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 10 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS85311. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85311 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 25mA = 86.6mW * Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.3V, with all outputs switching) = 86.6mW + 60mW = 146.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 5 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.147W * 103.3C/W = 85.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 5. Thermal Resistance JA for 24 Lead TSSOP, Forced Convection JA vs. Air Flow Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W 128.5C/W 115.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7C/W 103.3C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 11 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCC Q1 VOUT RL 50 VCC - 2V Figure 5. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of VCC - 2V. * For logic high, VOUT = VOH_MAX = VCC_MAX - 0.9V (VCC_MAX - VOH_MAX) = 0.9V * For logic low, VOUT = VOL_MAX = VCC_MAX - 1.7V (VCC_MAX - VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOH_MAX) = [(2V - (VCC_MAX - VOH_MAX))/RL] * (VCC_MAX - VOH_MAX) = [(2V - 0.9V)/50] * 0.9V = 19.8mW Pd_L = [(VOL_MAX - (VCC_MAX - 2V))/RL] * (VCC_MAX - VOL_MAX) = [(2V - (VCC_MAX - VOL_MAX))/RL] * (VCC_MAX - VOL_MAX) = [(2V - 1.7V)/50] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 12 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Reliability Information Table 6. JA vs. Air Flow Table for a 8 Lead SOIC JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 153.3C/W 128.5C/W 115.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 112.7C/W 103.3C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. Transistor Count The transistor count for ICS85311 is: 225 Package Outline and Package Dimensions Package Outline - M Suffix for 8 Lead SOIC Table 7. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 Basic H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 0 8 Reference Document: JEDEC Publication 95, MS-012 150 il (N B d ) SOIC IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 13 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Ordering Information Table 8. Ordering Information Part/Order Number 85311AM 85311AMT 85311AMLF 85311AMLFT Marking 85311AM 85311AM 85311ALF 85311ALF Package 8 Lead SOIC 8 Lead SOIC "Lead-Free" 8 Lead SOIC "Lead-Free" 8 Lead SOIC Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ragnes, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 14 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Revision History Sheet Rev Table A Page Added Termination for LVPECL Outputs section. 5/30/02 5 9/23/02 7 3.3V Output Load Test Circuit Diagram - corrected VEE equation to read -1.3V 0.165V from 0.135V. Updated Output Rise/Fall Time Diagram. 1 2 3 3 5 6 7 8 13 Add Lead-Free bullet in Features section. Pin Characteristics table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings, updated Outputs rating. Combined 3.3V & 2.5V Power tables and Differential DC Characteristics tables. Updated Parameter Measurement Information. Updated Single Ended Signal Driving Differential Input diagram. Added Termination for 2.5V LVPECL Output section. Added Differential Clock Input Interface section. Ordering Information table - added Lead Free part number. 6/17/04 T8 7 13 Added Recommendations for Unused Input and Output Pins. Ordering Information Table - corrected Lead-Free marking and added Lead-Free Note. 7/28/05 T3 3 LVPECL DC Characteristics Table -corrected VOH max. from VCC - 1.0V to VCCO 0.9V; and VSWING max. from 0.9V to 1.0V. Power Considerations - corrected power dissipation to reflect VOH max in Table 3C. 4/11/07 Added 2.5V AC Characteristics Table. Added Additive Phase Jitter spec to both AC Tables. Added Additive Phase Jitter plot. Updated Differential Input Clock Interface section. 10/22/08 T2 B T8 C 9 - 10 T4A - T4B D Date 8 A B Description of Change 4 5 8 IDTTM / ICSTM LVPECL/ECL FANOUT BUFFER 15 ICS85311AM REV. D OCTOBER 22, 2008 ICS85311 LOW SKEW, 1-TO-2, DIFFERENTIAL-TO-LVPECL/ECLFANOUT BUFFER Contact Information: www.IDT.com www.IDT.com Sales Technical Support 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT netcom@idt.com +480-763-2056 Corporate Headquarters Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) (c) 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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