2
RF Device Data
Freescale Semiconductor, Inc.
AFT09S200W02NR3 AFT09S200W02GNR3
Table 1. Maximum Ratings
Rating Symbol Value Unit
Drain--Source Voltage VDSS --0.5, +70 Vdc
Gate--Source Voltage VGS --6.0, +10 Vdc
Operating Voltage VDD 32, +0 Vdc
Storage Temperature Range Tstg --65 to +150 C
Case Operating Temperature Range TC--40 to +125 C
Operating Junction Temperature Range (1,2) TJ--40 to +225 C
Table 2. Thermal Characteristics
Characteristic Symbol Value (2,3) Unit
Thermal Resistance, Junction to Case
Case Temperature 80C, 56 W CW, 28 Vdc, IDQ = 1400 mA, 940 MHz
RJC 0.35 C/W
Table 3. ESD Protection Characteristics
Test Methodology Class
Human Body Model (per JESD22--A114) 2
Machine Model (per EIA/JESD22--A115) B
Charge Device Model (per JESD22--C101) IV
Table 4. Moisture Sensitivity Level
Test Methodology Rating Package Peak Temperature Unit
Per JESD22--A113, IPC/JEDEC J--STD--020 3260 C
Table 5. Electrical Characteristics (TA=25C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
Off Characteristics
Zero Gate Voltage Drain Leakage Current
(VDS =70Vdc,V
GS =0Vdc)
IDSS — — 10 Adc
Zero Gate Voltage Drain Leakage Current
(VDS =28Vdc,V
GS =0Vdc)
IDSS — — 5 Adc
Gate--Source Leakage Current
(VGS =5Vdc,V
DS =0Vdc)
IGSS — — 1 Adc
On Characteristics
Gate Threshold Voltage
(VDS =10Vdc,I
D= 729 Adc)
VGS(th) 1.0 1.5 2.0 Vdc
Gate Quiescent Voltage
(VDS =28Vdc,I
D= 1400 mA)
VGS(Q) —2.15 —Vdc
Fixture Gate Quiescent Voltage (4)
(VDD =28Vdc,I
D= 1400 mA, Measured in Functional Test)
VGG(Q) 3.2 4.3 5.2 Vdc
Drain--Source On--Voltage
(VGS =10Vdc,I
D=4.1Adc)
VDS(on) 0.1 0.2 0.3 Vdc
1. Continuous use at maximum temperature will affect MTTF.
2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF
calculators by product.
3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf. Select
Documentation/Application Notes -- AN1955.
4. VGG =2.0VGS(Q). Parameter measured on Freescale Test Fixture, due to resistor divider network on the board. Refer to Test Fixture Layout.
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