M12L64322A-5TG - Elite Semiconductor Memory Technology Inc

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 1/47

Revision History

Revision 0.1(Dec. 28 1998)

-Original

Revision 0.2(Jan. 29 1999)

-Add page 45 "Packing Dimension"

Revision 0.3(Apr. 20 2000)

-Modify 6 tss from 2 to 1.5ns.(Page 7)

Revision 0.4(May. 09 2001)

- 64ms refresh period (4K cycle) --> 15.6μs refresh interval (P.1)

- Add Packing Dimension Title 86-LEAD TSOP(II) DRAM(400mil).

- Modify P.39

Revision 1.0(Jun. 08 2001)

- Modify ICC2NS, ICC6, tRDL, tOH spec

Revision 1.1(Oct. 21 2002)

- Add –5 spec, Delete -8 spec

Revision 1.2(Nov. 11 2002)

- Modify tCH, tCL spec

Revision 1.3(Dec. 24 2002)

- Delete -5 spec (AC/DC)

Revision 1.4(Jan. 17 2003)

- Modify tRDL to meet currently spec in the market

Revision 1.5(Feb. 17 2003)

- Typing error

Revision 1.6(Oct. 29 2003)

- Modify refresh period.

Revision 1.7(May. 10 2004)

- M12L64322A-6T tRDL=12ns

- M12L64322A-7T tRDL=14ns

Revision 1.8(May. 02 2005)

- Add pb-free to ordering information

- Recommend to add 4096 auto refresh before and after self refresh

Revision 1.9(Nov. 04 2005)

- Modify tCC / tRCD spec

Revision 2.0(Dec. 08 2005)

- Add –5T speed g rade

Revision 2.1(Mar. 08 2006)

- Modify Inch Dimension Max. A2 from 0.011 to 0.041

Revision 2.2(Nov. 27 2006)

- Add BGA 90 b all 8x13mm package

Revision 2.3(Mar. 02 2007)

- Delete BGA ball name of packing dimensions

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 2/47

SDRAM 512K x 32 Bit x 4 Banks

Synchronous DRAM

FEATURES

y JEDEC standard 3.3V power supply

y LVTTL compatible with multiplexed address

y Four banks operation

y MRS cycle with address key programs

- CAS Latency ( 2 & 3 )

- Burst Length ( 1, 2, 4, 8 & full page )

- Burst Type ( Sequential & Interleave )

y All inputs are sampled at the positive going edge of the

system clock

y DQM for masking

y Auto & self refresh

y 15.6μs refresh interval

ORDERING INFORMATION

86 Pin TSOP (TypeII)

(400mil x 875mil)

Product No. MAX FREQ. PACKAGE COMMENTS

M12L64322A-5TG 200MHz TSOPII Pb-free

M12L64322A-6TG 166MHz TSOPII Pb-free

M12L64322A-7TG 143MHz TSOPII Pb-free

M12L64322A-5BG 200MHz 90BGA Pb-free

M12L64322A-6BG 166MHz 90BGA Pb-free

M12L64322A-7BG 143MHz 90BGA Pb-free

GENERAL DESCRIPTION

The M12L64322A is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits.

Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.

Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a

variety of high bandwidth, high performance memory system applications.

PIN ARRANGEMENT Top View

1

2

3

4

5

6

7

8

9

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

86

85

84

83

82

81

80

79

78

66

65

64

63

62

61

60

59

58

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

10

11

12

13

14

15

16

17

18

19

20

DQ5

DQ6

VSSQ

DQ7

NC

VDD

DQM0

WE

CAS

RAS

CS

77

76

75

74

73

72

71

70

69

68

67

DQ10

DQ9

VDDQ

DQ8

NC

VSS

DQM1

NC

CLK

CKE

NC

DQ31

VDDQ

DQ30

DQ29

VSSQ

DQ28

DQ27

VDDQ

DQ26

DQ25

VSSQ

DQ24

VSS

21

22

23

24

25

26

27

28

29

NC

BA0

BA1

A10/AP

A0

A1

A2

DQM2

VDD

30

31

32

33

34

35

36

37

38

39

NC

DQ16

VSSQ

DQ17

DQ18

VDDQ

DQ19

DQ20

VSSQ

DQ21

DQ22 40

41

42

43

VDDQ

DQ23

VDD

A9

A8

A7

A6

A5

A4

A3

DQM3

VSS

57

56

55

54

53

52

51

50

49

48

47

46

45

44

86Pin TSOP(II)

(400mil x 875mil)

(0.5mm Pin pitch)

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 3/47

PIN ARRANGEMENT

90 Ball FBGA

1 2 3 4 5 6 7 8 9

A DQ26 DQ24 VSS VDD DQ23 DQ21

B DQ28 VDDQ VSSQ VDDQ VSSQ DQ19

C VSSQ DQ27 DQ25 DQ22 DQ20 VDDQ

D VSSQ DQ29 DQ30 DQ17 DQ18 VDDQ

E VDDQ DQ31 NC NC DQ16 VSSQ

F VSS DQM3 A3 A2 DQM2 VDD

G A4 A5 A6 A10 A0 A1

H A7 A8 NC NC BA1 NC

J CLK CKE A9 BA0 CS RAS

K DQM1 NC NC CAS WE DQM0

L VDDQ DQ8 VSS VDD DQ7 VSSQ

M VSSQ DQ10 DQ9 DQ6 DQ5 VDDQ

N VSSQ DQ12 DQ14 DQ1 DQ3 VDDQ

P DQ11 VDDQ VSSQ VDDQ VSSQ DQ4

R DQ13 DQ15 VSS VDD DQ0 DQ2

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 4/47

DQM0~3

DQ

Mode

Register

Control Logic

Column

Address

Buffer

&

Refresh

Counter

Row

Address

Buffer

&

Refresh

Counter

Bank D

Row Decoder

Bank A

Bank B

Bank C

Sense Amplifier

Column Decoder

Data Control Circuit

Latch Circuit

Input & Output

Buffer

Address

Clock

Generator

CLK

CKE

Command Decoder

CS

RAS

CAS

WE

BLOCK DIAGRAM

PIN DESCRIPTION

PIN NAME INPUT FUNCTION

CLK System Clock Active on the positive going edge to sample all inputs

CS Chip Select Disables or enables device operation by masking or enabling all

inputs except CLK , CKE and DQM0-3.

CKE Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior new command.

Disable input buffers for power down in standby.

A0 ~ A10 Address Row / column address are multiplexed on the same pins.

Row address : RA0~RA10, column address : CA0~CA7

BA0 , BA1 Bank Select Address Selects bank to be activated during row address latch time.

Selects bank for read / write during column address latch time.

RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with

RAS low.

Enables row access & precharge.

CAS Column Address Strobe

Latches column address on the positive going edge of the CLK with

CAS low.

Enables column access.

WE Write Enable Enables write operation and row precharge.

Latches data in starting from CAS , WE active.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 5/47

PIN NAME INPUT FUNCTION

DQM0~3 Data Input / Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.

Blocks data input when DQM active.

DQ0 ~ DQ31 Data Input / Output Data inputs / outputs are multiplexed on the same pins.

VDD / VSS Power Supply / Ground Power and ground for the input buffers and the core logic.

VDDQ / VSSQ Data Output Power / Ground Isolated power supply and ground for the output buffers to provide

improved noise immunity.

N.C No Connection This pin is recommended to be left No Connection on the device.

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to VSS VIN, VOUT -1.0 ~ 4.6 V

Voltage on VDD supply relative to VSS VDD, VDDQ -1.0 ~ 4.6 V

Storage temperature TSTG -55 ~ +150 C°

Power dissipation PD 1 W

Short circuit current IOS 50 mA

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITION

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70 C°)

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD, VDDQ 3.0 3.3 3.6 V

Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1

Input logic low voltage VIL -0.3 0 0.8 V 2

Output logic high voltage VOH 2.4 - - V IOH = -2mA

Output logic low voltage VOL - - 0.4 V IOL = 2mA

Input leakage current IIL -5 - 5 μA 3

Output leakage current IOL -5 - 5 μA 4

Note: 1. VIH(max) = 4.6V AC for pulse width ≤ 10ns acceptable.

2. VIL(min) = -1.5V AC for pulse width ≤ 10ns acceptable.

3. Any input 0V ≤ VIN

≤

VDD + 0.3V, all other pins are not under test = 0V.

4. Dout is disabled , 0V

≤

VOUT ≤ VDD.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 6/47

CAPACITANCE (VDD = 3.3V, TA = 25 C°, f = 1MHZ)

Parameter Symbol Min Max Unit

Input capacitance (A0 ~ A10, BA0 ~ BA1) CIN1 2 4 pF

Input capacitance

(CLK, CKE, CS , RAS , CAS , WE & DQM) CIN2 2 4 pF

Data input/output capacitance (DQ0 ~ DQ31) COUT 2 5 pF

DC CHARACTERISTICS

Recommended operating condition unless otherwise noted，TA = 0 to 70 C°

Version

Parameter Symbol Test Condition CAS

Latency -5 -6 -7 Unit Note

Operating Current

(One Bank Active) I

CC1

Burst Length = 1

tRC ≥tRC(min)

IOL = 0 mA

180 160 140 mA 1,2

ICC2P CKE ≤VIL(max), tcc = 15ns 2

Precharge Standby Current

in powe

r

-down mode I

CC2PS CKE & CLK

≤

VIL(max), tcc =

∞

2

mA

ICC2N CKE ≥VIH(min), CS ≥ VIH(min), tcc = 15ns

Input signals are changed one time during 30ns 30

Precharge Standby Current

in non power-down mode

I

CC2NS CKE ≥VIH(min), CLK

≤

VIL(max), tcc =

∞

input signals are stable 10

mA

ICC3P CKE ≤VIL(max), tcc = 15ns 10

Active Standby Current

in powe

r

-down mode ICC3PS CKE & CLK

≤

VIL(max), tcc =

∞

10

mA

ICC3N CKE ≥VIH(min), CS ≥VIH(min), tcc = 15ns

Input signals are changed one time during 30ns

40 mA

Active Standby Current

in non power-down mode

(One Bank Active) I

CC3NS CKE ≥VIH(min), CLK

≤

VIL(max), tcc =

∞

input signals are stable 10 mA

3 280 250 220

Operating Current

(Burst Mode)

I

CC4 IOL = 0 mA

Page Burst

2 Banks activated 2 220 200 180

mA

1,2

Refresh Current ICC5 tRC ≥tRC(min) 330 310 285 mA

Self Refresh Current ICC6 CKE

≤

0.2V 2 mA

Note : 1. Measured with outputs open.

2. Input signals are changed one time during 2 CLKS.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 7/47

AC OPERATING TEST CONDITIONS (VDD = 3.3V ±0.3V ，TA = 0 to 70 C°)

Parameter Value Unit

Input levels (Vih/Vil) 2.4/0.4 V

Input timing measurement reference level 1.4 V

Input rise and fall-time tr/tf = 1/1 ns

Output timing measurement reference level 1.4 V

Output load condition See Fig. 2

(Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Version

Parameter Symbol

-5 -6 -7 Unit Note

Row active to row active delay tRRD(min) 10 12 14 ns 1

RAS to CAS delay t

RCD(min) 15 18 20 ns 1

Row precharge time tRP(min) 15 18 20 ns 1

tRAS(min) 40 42 42 ns 1

Row active time

t

RAS(max) 100 us

Row cycle time @ Operating tRC(min) 55 60 63 ns 1

Last data in to col. address delay tCDL(min) 1 CLK 2

Last data in to row precharge tRDL(min) 2 CLK 2

Last data in to burst stop tBDL(min) 1 CLK 2

Output

870

VOH (DC) =2.4V , IOH = -2 mA

VOL (DC) =0.4V , IOL = 2 mA Output

30pF

Z0 =50

30pF

50

Vtt = 1.4V

3.3V

1200 Ω

Ω

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 8/47

Version

Parameter Symbol

-5 -6 -7 Unit Note

Col. address to col. address delay tCCD(min) 1 CLK 3

CAS latency = 3 2

Number of valid

Output data CAS latency = 2 1

ea 4

Note : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

AC CHARACTERISTICS (AC operating condition unless otherwise noted)

-5 -6 -7

Parameter Symbol Min Max Min Max Min Max

Unit Note

CAS latency = 3 5 6 7

CLK cycle time

CAS latency = 2

tCC

10

1000

10

1000

10

1000 ns 1

CAS latency = 3 4.5 5.5 6 CLK to valid

output delay CAS latency = 2

tSAC

10 6 6

ns 1,2

CAS latency = 3 2 2 2 Output data

hold time CAS latency = 2

tOH

2 2 2

ns 2

CLK high pulsh width tCH 2 2.5 2.5 ns 3

CLK low pulsh width tCL 2 2.5 2.5 ns 3

Input setup time tSS 1.5 1.5 2 ns 3

Input hold time tSH 1 1 1 ns 3

CLK to output in Low-Z tSLZ 1 1 1 ns 2

CAS latency = 3 4.5 5.5 6 CLK to output

in Hi-Z CAS latency = 2

tSHZ

6 6 6

ns

Note : 1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns. (tr/2 - 0.5) ns should be considered.

3. Assumed input rise and fall time (tr & tf) =1ns.

If tr & tf is longer than 1ns. transient time compensation should be considered.

i.e., [(tr + tf)/2 – 1] ns should be added to the parameter.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 9/47

FREQUENCY vs. AC PARAMETER RELATIONSHIP TABLE

M12L64322A-5TG (Unit : number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

Frequency CAS

Latency 55ns 40ns 15ns 10ns 15ns 5ns 5ns 10ns

200 MHZ(5.0ns ) 3 11 8 3 2 3 1 1 2

166 MHZ(6.0ns ) 3 10 7 3 2 3 1 1 2

143 MHZ(7.0ns ) 3 8 6 3 2 3 1 1 2

125 MHZ(8.0ns ) 2 7 5 2 2 2 1 1 2

100 MHZ(10.4ns ) 2 6 4 2 1 2 1 1 1

M12L64322A-6TG (Unit : number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

Frequency CAS

Latency 60ns 42ns 18ns 12ns 18ns 6ns 6ns 12ns

166 MHZ(6.0ns ) 3 10 7 3 2 3 1 1 2

143 MHZ(7.0ns ) 3 9 6 3 2 3 1 1 2

125 MHZ(8.0ns ) 2 9 6 3 2 3 1 1 2

100 MHZ(10.0ns ) 2 7 5 2 2 2 1 1 1

83 MHZ(12.0ns ) 2 6 4 2 1 2 1 1 1

M12L64322A-7TG (Unit : number of clock)

tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL

Frequency CAS

Latency 63ns 42ns 20ns 14ns 18ns 7ns 7ns 14ns

143 MHZ(7.0ns ) 3 9 6 3 2 3 1 1 2

125 MHZ(8.0ns ) 3 9 6 3 2 3 1 1 2

100 MHZ(10.0ns ) 2 7 5 2 2 2 1 1 1

83 MHZ(12.0ns ) 2 6 4 2 2 2 1 1 1

75 MHZ(13.4ns ) 2 6 4 2 2 2 1 1 1

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 10/47

SIMPLIFIED TRUTH TABLE

COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A9~A0 Note

Register Mode Register set H X L L L L X OP CODE 1,2

Auto Refresh H 3

Entry H L L L L H X X 3

L H H H X 3

Refresh Self

Refresh

Exit L H H X X X X X 3

Bank Active & Row Addr. H X L L H H X V Row Address

Auto Precharge Disable L 4

Read &

Column Address Auto Precharge Enable

H X L H L H X V

H

Column

Address

(A0~A7) 4,5

Auto Precharge Disable L 4

Write &

Column Address Auto Precharge Enable

H X L H L L X V

H

Column

Address

(A0~A7) 4,5

Burst Stop H X L H H L X X 6

Bank Selection V L

Precharge

All Banks

H X L L H L X

X H

X

H X X X

Entry H L

L V V V

X

Clock Suspend or

Active Power Down

Exit L H

X X X X X

X

H X X X

Entry H L

L H H H

X

H X X X

Precharge Power Down Mode

Exit L H

L V V V

X

DQM H X V X 7

H X X X

No Operating Command H X

L H H H

X X

(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )

Note : 1.OP Code : Operating Code

A0~A10 & BA0~BA1 : Program keys. (@ MRS)

2.MRS can be issued only at all banks precharge state.

A new command can be issued after 2 CLK cycles of MRS.

3.Auto refresh functions are as same as CBR refresh of DRAM.

The automatical precharge without row precharge of command is meant by “Auto”.

Auto/self refresh can be issued only at all banks precharge state.

4.BA0~BA1 : Bank select addresses.

If both BA1 and BA0 are “Low” at read ,write , row active and precharge ,bank A is selected.

If both BA1 is “Low” and BA0 is “High” at read ,write , row active and precharge ,bank B is selected.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 11/47

If both BA1 is “High” and BA0 is “Low” at read ,write , row active and precharge ,bank C is selected.

If both BA1 and BA0 are “High” at read ,write , row active and precharge ,bank D is selected

If A10/AP is “High” at row precharge , BA1 and BA0 is ignored and all banks are selected.

5.During burst read or write with auto precharge. new read/write command can not be issued.

Another bank read/write command can be issued after the end of burst.

New row active of the associated bank can be issued at tRP after the end of burst.

6.Burst stop command is valid at every burst length.

7.DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (write DQM latency is 0), but

makes Hi-Z state the data-out of 2 CLK cycles after.(Read DQM latency is 2)

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address BA0~BA1 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function RFU RFU W.B.L TM CAS Latency BT Burst Length

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT = 0 BT = 1

0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1

0 1 Reserved 0 0 1 Reserved 1 Interleave 0 0 1 2 2

1 0 Reserved 0 1 0 2 0 1 0 4 4

1 1 Reserved 0 1 1 3

0 1 1 8 8

Write Burst Length 1 0 0 Reserved 1 0 0 Reserved Reserved

A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved

1 Single Bit 1 1 1 Reserved

1 1 1 Full Page Reserved

Full Page Length : 256

POWER UP SEQUENCE

1.Apply power and start clock, Attempt to maintain CKE = ”H”, DQM = ”H” and the other pin are NOP condition at the inputs.

2. Maintain stable power , stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue mode register set command to initialize the mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Note : 1. RFU(Reserved for future use) should stay “0” during MRS cycle.

2. If A9 is high during MRS cycle, “ Burst Read single Bit Write” function will be enabled.

3. The full column burst (256 bit) is available only at sequential mode of burst type.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 12/47

BURST SEQUENCE (BURST LENGTH = 4)

Initial Address

A1 A0 Sequential Interleave

0 0 0 1 2 3 0 1 2 3

0 1 1 2 3 0 1 0 3 2

1 0 2 3 0 1 2 3 0 1

1 1 3 0 1 2 3 2 1 0

BURST SEQUENCE (BURST LENGTH = 8)

Initial

A2 A1 A0 Sequential Interleave

0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6

0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5

0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4

1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3

1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2

1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1

1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 13/47

DEVICE OPERATIONS

CLOCK (CLK)

The clock input is used as the reference for all SDRAM

operations.All operations are synchronized to the positive

going edge of the clock. The clock transitions must be

monotonic between VIL and VIH. During operation with CKE

high all inputs are assumed to be in valid state (low or high) for

the duration of setup and hold time around positive edge of the

clock for proper functionality and Icc specifications.

CLOCK ENABLE(CKE)

The clock enable (CKE) gates the clock onto SDRAM. If CKE

goes low synchronously with clock (set-up and hold time same

as other inputs), the internal clock suspended from the next

clock cycle and the state of output and burst address is frozen

as long as the CKE remains low. All other inputs are ignored

from the next clock cycle after CKE goes low. When all banks

are in the idle state and CKE goes low synchronously with

clock, the SDRAM enters the power down mode from the next

clock cycle. The SDRAM remains in the power down mode

ignoring the other inputs as long as CKE remains low. The

power down exit is synchronous as the internal clock is

suspended. When CKE goes high at least “1CLK + tSS” before

the high going edge of the clock, then the SDRAM becomes

active from the same clock edge accepting all the input

commands.

BANK A DDRESSES (BA0~BA1)

This SDRAM is organized as four independent banks of

524,288 words x 32 bits memory arrays. The BA0~BA1 inputs

are latched at the time of assertion of RAS and CAS to

select the bank to be used for the operation. The banks

addressed BA0~BA1 are latched at bank active, read, write,

mode register set and precharge operations.

ADDRESS INPUTS (A0~A10)

The 19 address bits are required to decode the 524,288 word

locations are multiplexed into 11 address input pins (A0~A10).

The 11 row addresses are latched along with RAS and

BA0~BA1 during bank active command. The 8 bit column

addresses are latched along with CAS , WE and BA0~BA1

during read or with command.

NOP and DEVICE DESELECT

When RAS , CAS and WE are high , The SDRAM

performs no operation (NOP). NOP does not initiate any new

operation, but is needed to complete operations which require

more than single clock cycle like bank activate, burst read,

auto refresh, etc. The device deselect is also a NOP and is

entered by asserting CS high. CS high disables the

command decoder so that RAS , CAS , WE and all the

address inputs are ignored.

POWER-UP

1.Apply power and start clock, Attempt to maintain CKE =

“H”, DQM = “H” and the other pins are NOP condition at

the inputs.

2.Maintain stable power, stable clock and NOP input

condition for minimum of 200us.

3.Issue precharge commands for both banks of the

devices.

4.Issue 2 or more auto-refresh commands.

5.Issue a mode register set command to initialize the

mode register.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the

various operating modes of SDRAM. It programs the

CAS latency, burst type, burst length, test mode and

various vendor specific options to make SDRAM useful

for variety of different applications. The default value of

the mode register is not defined, therefore the mode

register must be written after power up to operate the

SDRAM. The mode register is written by asserting low

on CS , RAS , CAS and WE (The SDRAM should

be in active mode with CKE already high prior to writing

the mode register). The state of address pins A0~A10

and BA0~BA1 in the same cycle as CS , RAS , CAS

and WE going low is the data written in the mode

register. Two clock cycles is required to complete the

write in the mode register. The mode register contents

can be changed using the same command and clock

cycle requirements during operation as long as all

banks are in the idle state. The mode register is divided

into various fields into depending on functionality. The

burst length field uses A0~A2, burst type uses A3, CAS

latency (read latency from column address) use A4~A6,

vendor specific options or test mode use A7~A8,

A10/AP and BA0~BA1, A7~A9, A10/AP and BA0~BA1

must be set to low for normal SDRAM operation. Refer

to the table for specific codes for various burst length,

burst type and CAS latencies.

BANK ACTIVATE

The bank activate command is used to select a random

row in an idle bank. By asserting low on RAS and

CS with desired row and bank address, a row access

is initiated. The read or write operation can occur after a

time delay of tRCD (min) from the time of bank activation.

tRCD is the internal timing parameter of SDRAM,

therefore it is dependent on operating clock frequency.

The minimum number of clock cycles required between

bank activate and read or write command should be

calculated by dividing tRCD (min) with cycle time of the

clock and then rounding of the result to the next higher

integer.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 14/47

DEVICE OPERATIONS (Continued)

The SDRAM has four internal banks in the same chip and

shares part of the internal circuitry to reduce chip area,

therefore it restricts the activation of four banks

simultaneously. Also the noise generated during sensing of

each bank of SDRAM is high requiring some time for power

supplies to recover before another bank can be sensed

reliably. tRRD (min) specifies the minimum time required between

activating different bank. The number of clock cycles required

between different bank activation must be calculated similar to

tRCD (min) specification. The minimum time required for the bank

to be active to initiate sensing and restoring the complete row

of dynamic cells is determined by tRAS (min). Every SDRAM bank

activate command must satisfy tRAS (min) specification before a

precharge command to that active bank can be asserted. The

maximum time any bank can be in the active state is

determined by tRAS (max) and tRAS (max) can be calculated

similar to tRCD specification.

BURST READ

The burst read command is used to access burst of data on

consecutive clock cycles from an active row in an active bank.

The burst read command is issued by asserting low on CS

and RAS with WE being high on the positive edge of the

clock. The bank must be active for at least tRCD (min) before the

burst read command is issued. The first output appears in CAS

latency number of clock cycles after the issue of burst read

command. The burst length, burst sequence and latency from

the burst read command is determined by the mode register

which is already programmed. The burst read can be initiated

on any column address of the active row. The address wraps

around if the initial address does not start from a boundary

such that number of outputs from each I/O are equal to the

burst length programmed in the mode register. The output

goes into high-impedance at the end of burst, unless a new

burst read was initiated to keep the data output gapless. The

burst read can be terminated by issuing another burst read or

burst write in the same bank or the other active bank or a

precharge command to the same bank. The burst stop

command is valid at every page burst length.

BURST WRITE

The burst write command is similar to burst read command

and is used to write data into the SDRAM on consecutive clock

cycles in adjacent addresses depending on burst length and

burst sequence. By asserting low on CS , CAS and WE

with valid column address, a write burst is initiated. The data

inputs are provided for the initial address in the same clock

cycle as the burst write command. The input buffer is

deselected at the end of the burst length, even though the

internal writing can be completed yet. The writing can be

complete by issuing a burst read and DQM for blocking data

inputs or burst write in the same or another active bank. The

burst stop command is valid at every burst length. The write

burst can also be terminated by using DQM for blocking data

and procreating the bank tRDL after the last data input to be

written into the active row. See DQM OPERATION also.

DQM OPERATION

The DQM is used mask input and output operations. It

works similar to OE during operation and inhibits writing

during write operation. The read latency is two cycles from

DQM and zero cycle for write, which means DQM masking

occurs two cycles later in read cycle and occurs in the

same cycle during write cycle. DQM operation is

synchronous with the clock. The DQM signal is important

during burst interrupts of write with read or precharge in

the SDRAM. Due to asynchronous nature of the internal

write, the DQM operation is critical to avoid unwanted or

incomplete writes when the complete burst write is

required. Please refer to DQM timing diagram also.

PRECHARGE

The precharge is performed on an active bank by

asserting low on clock cycles required between bank

activate and clock cycles required between bank activate

and CS , RAS , WE and A10/AP with valid BA0~BA1

of the bank to be procharged. The precharge command

can be asserted anytime after tRAS (min) is satisfy from the

bank active command in the desired bank. tRP is defined

as the minimum number of clock cycles required to

complete row precharge is calculated by dividing tRP with

clock cycle time and rounding up to the next higher

integer. Care should be taken to make sure that burst

write is completed or DQM is used to inhibit writing before

precharge command is asserted. The maximum time any

bank can be active is specified by tRAS (max). Therefore,

each bank activate command. At the end of precharge,

the bank enters the idle state and is ready to be activated

again. Entry to power-down, Auto refresh, Self refresh and

Mode register set etc. is possible only when all banks are

in idle state.

AUTO PRECHARGE

The precharge operation can also be performed by using

auto precharge. The SDRAM internally generates the

timing to satisfy tRAS (min) and “tRP” for the programmed

burst length and CAS latency. The auto precharge

command is issued at the same time as burst write by

asserting high on A10/AP, the bank is precharge command

is asserted. Once auto precharge command is given, no

new commands are possible to that particular bank until

the bank achieves idle state.

ALL BANKS PRECHARGE

Four banks can be precharged at the same time by using

Precharge all command. Asserting low on CS , RAS ,

and WE with high on A10/AP after all banks have

satisfied tRAS (min) requirement, performs precharge on all

banks. At the end of tRP after performing precharge all, all

banks are in idle state.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 15/47

DEVICE OPERATIONS (Continued)

AUTO REFRESH

The storage cells of SDRAM need to be refreshed every 64ms

to maintain data. An auto refresh cycle accomplishes refresh of

a single row of storage cells. The internal counter increments

automatically on every auto refresh cycle to refresh all the

rows. An auto refresh command is issued by asserting low on

CS , RAS and CAS with high on CKE and WE . The auto

refresh command can only be asserted with all banks being in

idle state and the device is not in power down mode (CKE is

high in the previous cycle). The time required to complete the

auto refresh operation is specified by tRC (min). The minimum

number of clock cycles required can be calculated by driving

tRC with clock cycle time and them rounding up to the next

higher integer. The auto refresh command must be followed by

NOP’s until the auto refresh operation is completed. The auto

refresh is the preferred refresh mode when the SDRAM is

being used for normal data transactions. The auto refresh

cycle can be performed once in 15.6us.

SELF REFRESH

The self refresh is another refresh mode available in the

SDRAM. The self refresh is the preferred refresh mode for

data retention and low power operation of SDRAM. In self

refresh mode, the SDRAM disables the internal clock and

all the input buffers except CKE. The refresh addressing

and timing is internally generated to reduce power

consumption.

The self refresh mode is entered from all banks idle state

by asserting low on CS , RAS , CAS and CKE with

high on WE . Once the self refresh mode is entered, only

CKE state being low matters, all the other inputs including

clock are ignored to remain in the refresh.

The self refresh is exited by restarting the external clock

and then asserting high on CKE. This must be followed by

NOP’s for a minimum time of tRC before the SDRAM

reaches idle state to begin normal operation. It is

recommended to use burst 40% auto refresh cycles

immediately before and after self refresh.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 16/47

COMMANDS

Mode register set command

(

CS , RAS , CAS , WE = Low)

The M12L64322A has a mode register that defines how the device operates. In

this command, A0 through A10 and BA0~BA1 are the data input pins. After power on,

the mode register set command must be executed to initialize the device.

The mode register can be set only when all banks are in idle state.

During 2CLK following this command, the M12L64322A cannot accept any other

commands.

Activate command

(CS , RAS = Low, CAS , WE = High)

The M12L64322A has four banks, each with 2,048 rows.

This command activates the bank selected by BA1 and BA0 and a row address

selected by A0 through A10.

This command corresponds to a conventional DRAM’s RAS falling.

Precharge command

(CS , RAS , WE = Low, CAS = High )

This command begins precharge operation of the bank selected by BA1 and BA0.

When A10 is High, all banks are precharged, regardless of BA1 and BA0. When A10

is Low, only the bank selected by BA1 and BA0 is precharged.

After this command, the M12L64322A can’t accept the activate command to the

precharging bank during tRP (precharge to activate command period).

This command corresponds to a conventional DRAM’s RAS rising.

CLK

CKE

CS

RAS

WE

BA0, BA1

(Bank select)

A10

Add

CAS

H

Row

Fig. 1 Mode register set

command

Fig. 2 Row address stroble and

bank active command

CLK

CKE

BA0, BA1

(Bank select)

A10

(Precharge select)

Add

H

Fig. 3 Precharge command

BA0, BA1

(Bank select)

CS

RAS

WE

CAS

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M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 17/47

Write command

(

CS , CAS , WE = Low, RAS = High)

If the mode register is in the burst write mode, this command sets the burst start

address given by the column address to begin the burst write operation. The first

write data in burst can be input with this command with subsequent data on following

clocks.

Read command

(

CS , CAS = Low, RAS , WE = High)

Read data is available after CAS latency requirements have been met.

This command sets the burst start address given by the column address.

CBR (auto) refresh command

(

CS , RAS , CAS = Low, WE , CKE = High)

This command is a request to begin the CBR refresh operation. The refresh

address is generated internally.

Before executing CBR refresh, all banks must be precharged.

After this cycle, all banks will be in the idle (precharged) state and ready for a

row activate command.

During tRC period (from refresh command to refresh or activate command), the

M12L64322A cannot accept any other command.

CLK

CKE

CS

RAS

WE

BA0, BA1

(Bank select)

BA0, BA1

(Bank select)

A10

Add

CAS

H

Col.

Fig. 4 Column address and

write command

Fig. 5 Column address and

read command

CLK

CKE

BA0, BA1

(Bank select)

A10

Add

H

Fig. 6 Auto refresh command

Col.

CS

RAS

WE

CAS

CS

RAS

WE

CAS

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 18/47

Self refresh entry command

(

CS , RAS , CAS , CKE = Low , WE = High)

After the command execution, self refresh operation continues while CKE

remains low. When CKE goes to high, the M12L64322A exits the self refresh mode.

During self refresh mode, refresh interval and refresh operation are performed

internally, so there is no need for external control.

Before executing self refresh, all banks must be precharged.

Burst stop command

(

CS , WE = Low, RAS , CAS = High)

This command terminates the current burst operation.

Burst stop is valid at every burst length.

No operation

(CS = Low , RAS , CAS , WE = High)

This command is not a execution command. No operations begin or terminate by

this command.

CLK

CKE

CS

RAS

WE

BA0, BA1

(Bank select)

A10

Add

CAS

CLK

CKE

BA0, BA1

(Bank select)

A10

Add

H

Fig. 7 Self refresh entry

command

Fig. 8 Burst stop command

CLK

CKE

BA0, BA1

(Bank select)

A10

Add

H

Fig. 9 No operation

CS

RAS

WE

CAS

CS

RAS

WE

CAS

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 19/47

BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. CLOCK Suspend

2. DQM Operation

*Note : 1. CKE to CLK disable/enable = 1CLK.

2. DQM masks data out Hi-Z after 2CLKs which should masked by CKE ”L”.

3. DQM masks both data-in and data-out.

CLK

CMD

CKE

Internal

CLK

DQ(CL2)

DQ(CL3)

RD

Q2

Q0 Q1 Q3

Q2

Q0 Q1 Q3D0 D1 D2 D3

D1 D2 D3

D0

WR

Masked by CKE

1) Clock Suspended Du

r

ing W

r

ite (BL=4) 2) Clock Suspended During Read (BL=4)

Not Written Suspended Dout

CLK

CMD

DQM

DQ(CL2)

DQ(CL3)

RD

Q0 Q2 Q3

Q1 Q2 Q3

D0 D1 D3

D1 D3

D0

WR

Masked by DQM

Masked b y DQ M

CLK

CMD

DQM

DQ(CL2)

DQ(CL3)

CKE

RD

Q0 Q2 Q4

Hi-Z Hi-Z Hi-Z Q6 Q7 Q8

Q5 Q6 Q7

Q1 Q3

Hi-Z Hi-Z Hi-Z

Hi-Z

1)Write Mask (BL=4) 2)Read Mask (BL=4)

DQM to Data-in Mask=0 DQM to Data-out Mask=2

3)DQM with clcok suspended (Full Page Read)

*Note2

Internal

CLK

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 20/47

3. CAS Interrupt (I)

*Note : 1. By “interrupt” is meant to stop burst read/write by external before the end of burst.

By ” CAS interrupt ”, to stop burst read/write by CAS access ; read and write.

2. tCCD : CAS to CAS delay. (=1CLK)

3. tCDL : Last data in to new column address delay. (=1CLK)

CLK

CMD

ADD

DQ(CL2)

DQ(CL3)

RD

QB0 QB2

QA0

CLK

CMD

ADD

DQ

WR

DA0 DB0 DB1

RD

A B

QB1 QB3

QB0 QB2

QA0 QB3

QB1

tCCD

*Note 2

WR

tCCD *Note 2

AB

tCDL

*Note 3

WR RD

tCCD *Note 2

AB

DA0 DQ0 DQ1

tCDL

*Note 3

DA0 DQ0 DQ1

DQ(CL3)

DQ(CL2)

1)Read interrupted by Read (BL=4)

2)Write interrupted by Write (BL=2) 3)Write interrupted by Read (BL=2)

*Note1

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 21/47

4. CAS Interrupt (II) : Read Interrupted by Write & DQM

CLK

i)CMD

DQM

DQ D1 D3

D0 D2

WR

ii)CMD

DQM

DQ

iii)CMD

DQM

DQ

iv)CMD

DQM

DQ

D1 D3

D0 D2

RD WR

D1 D3

D0 D2

D1 D3

D0 D2

RD WR

Hi-Z

Q0

*Note1

Hi-Z

(a)CL=2,BL=4

RD

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 22/47

*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.

5. Write Interrupted by Precharge & DQM

*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.

2. To inhibit invalid write, DQM should be issued.

3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt

but only another bank precharge of four banks operation.

CLK

i)CMD

ii)CMD

iii)CMD

iv)CMD

DQM

DQ

D1 D3

D1

D0 D2

D3

D0 D2

WR

(b)CL=3,BL=4

RD WR

D1 D3

D0 D2

D1 D3

D0 D2

RD WR

Hi-Z

D1 D3

D0 D2

Q0

*Note1

v)CMD

DQM

DQ

RD WR

Hi-Z

RD

CLK

CMD

DQM

DQ D0 D1 D2

WR

*Note3

*Note2

Masked by DQM

D3

1

)

No

r

mal W

r

ite

(

BL=4

)

tRDL(min)

PRE

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 23/47

6. Precharge

.

7. Auto Precharge

*Note : 1. tRDL : Last data in to row precharge delay.

2. Number of valid output data after row precharge : 1,2 for CAS Latency = 2,3 respectively.

3. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of other activated bank can be issued from this point.

At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.

CLK

CMD

DQ D0 D1 D2 D3

WR

CLK

CMD

DQ(CL2) Q0 Q1 Q2 Q3

RD

DQ(CL3)

*Note3

Auto Precharge starts

Q0 Q1 Q2 Q3

*Note3

Auto Precharge starts

1

)

No

r

mal W

r

ite

(

BL=4

)

2

)

No

r

mal Read

(

BL=4

)

tRDL

CLK

DQ D0 D1 D2 D3

WR

tRDL

*Note1

CLK

CMD

DQ(CL2) Q0 Q1 Q2

2*Note2

1*Note2

Q3

RD PRE

DQ(CL3) Q0 Q1 Q2 Q3

PRE

1)Normal Write (BL=4) 2)No

r

mal Read (BL=4)

CL=2

PRE CL=3

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 24/47

8. Burst Stop & Interrupted by Precharge

9. MRS

*Note: 1. tRDL : 2 CLK; Last data in to Row Precharge.

2. t

BDL : 1 CLK ; Last data in to burst stop delay.

3. Number of valid output data after burst stop : 1,2 for CAS latency = 2,3 respectiviely.

4. PRE : All banks precharge, if necessary.

MRS can be issued only at all banks precharge state.

CLK

CMD PRE

*Note4

MRS ACT

tRP 2CLK

1

)

Mod e Re

g

iste

r

Set

CLK

CMD

DQ(CL2)

DQ(CL3)

CLK

CMD

DQM

DQ D0 D1 D2 D3

WR STOP

*Note2

Q0 Q1

RD STOP

*Note3

1)W rite Burst Stop (BL=8)

2)Read Burst Stop (BL=4)

D5D4

CLK

CMD

CLK

CMD

DQM

DQ D0 D1 Mask

WR

RD PRE

1)Write interrupted b

y

precharge (BL=4)

2)Read interrupted by precharge (BL=4)

PRE

*Note1

tRDL

tBDL

D2

DQ(CL3)

Q0 Q1

DQ(CL2)

Q1Q0

*Note3

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 25/47

10. Clock Suspend Exit & Power Down Exit

11. Auto Refresh & Self Refresh

*Note : 1. Active power down : one or more banks active state.

2. Precharge power down : all banks precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.

No precharge commands are required after auto refresh command.

During tRC from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, all banks must be idle state.

5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh entry, refresh interval and refresh operation are performed internally.

After self refresh entry, self refresh mode is kept while CKE is low.

During self refresh entry, all inputs expect CKE will be don’t cared, and outputs will be in Hi-Z state.

For the time interval of tRC from self refresh exit command, any other command can not be accepted.

Before/After self refresh mode, burst auto refresh (40% cycles) is recommended.

CLK

CKE

Internal

CLK

CMD RD

tSS

*Note1

CLK

CKE

Internal

CLK

CMD ACT

tSS

*Note2

NOP

1)Clock Susp end(=

A

ctive Powe

r

Down)Exit 2)Powe

r

Down (=P

r

echa

r

ge Powe

r

Down)

CLK

CMD PRE AR

CKE

CMD

tRP tRC

*Note 5

*Note 4

CLK

CMD PRE SR

CKE

CMD

tRP tRC

*Note 4

1)Auto Refresh & Self Refresh *Note3

2)Self Refresh *Note8

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 26/47

12. About Burst Type Control

Sequential Counting

At MRS A3 = “0”. See the BURST SEQUENCE TABLE. (BL = 4,8)

BL = 1, 2, 4, 8 and full page.

Basic

MODE

Interleave Counting At MRS A3 = “1”. See the BURST SEQUENCE TABLE. (BL = 4,8)

BL = 4, 8 At BL =1, 2 interleave Counting = Sequential Counting

Random

MODE

Random Column Access

tCCD = 1 CLK

Every cycle Read/Write Command with random column address can realize Random

Column Access.

That is similar to Extended Data Out (EDO) Operation of conventional DRAM.

13. About Burst Length Control

1 At MRS A210 = “000”

At auto precharge . tRAS should not be violated.

2 At MRS A210 = “001”

At auto precharge . tRAS should not be violated.

4 At MRS A210 = “010”

8 At MRS A210 = “011”

Basic

MODE

Full Page At MRS A210 = “111”

At the end of the burst length , burst is warp-around.

Random

MODE Burst Stop t

BDL = 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.

Using burst stop command, any burst length control is possible.

RAS Interrupt

(Interrupted by

Precharge)

Before the end of burst. Row precharge command of the same bank stops read /write burst

with auto precharge.

t

RDL = 1 with DQM , Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.

During read/write burst with auto precharge, RAS interrupt can not be issued.

Interrupt

MODE

CAS Interrupt

Before the end of burst, new read/write stops read/write burst and starts new read/write

burst.

During read/write burst with auto precharge, CAS interrupt can not be issued.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 27/47

FUNCTION TURTH TABLE (TABLE 1)

Current

State CS RAS CAS WE BA ADDR ACTION Note

H X X X X X NOP

L H H H X X NOP

L H H L X X ILLEGAL 2

IDLE L H L X BA CA, A10/AP ILLEGAL 2

L L H H BA RA Row (&Bank) Active ; Latch RA

L L H L BA A10/AP NOP 4

L L L H X X Auto Refresh or Self Refresh 5

L L L L OP code OP code Mode Register Access 5

H X X X X X NOP

L H H H X X NOP

L H H L X X ILLEGAL 2

Row L H L H BA CA, A10/AP Begin Read ; latch CA ; determine AP

Active L H L L BA CA, A10/AP Begin Write ; latch CA ; determine AP

L L H H BA RA ILLEGAL 2

L L H L BA A10/AP Precharge

L L L X X X ILLEGAL

H X X X X X NOP (Continue Burst to End Æ Row Active)

L H H H X X NOP (Continue Burst to End Æ Row Active)

L H H L X X Term burst Æ Row active

Read L H L H BA CA, A10/AP Term burst, New Read, Determine AP

L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3

L L H H BA RA ILLEGAL 2

L L H L BA A10/AP Term burst, Precharge timing for Reads

L L L X X X ILLEGAL

H X X X X X NOP (Continue Burst to End Æ Row Active)

L H H H X X NOP (Continue Burst to End Æ Row Active)

L H H L X X Term burst Æ Row active

Write L H L H BA CA, A10/AP Term burst, New Read, Determine AP 3

L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3

L L H H BA RA ILLEGAL 2

L L H L BA A10/AP Term burst, Precharge timing for Writes 3

L L L X X X ILLEGAL

H X X X X X NOP (Continue Burst to End Æ Precharge)

Read with L H H H X X NOP (Continue Burst to End Æ Precharge)

Auto L H H L X X ILLEGAL

Precharge L H L X BA CA, A10/AP ILLEGAL

L L H X BA RA, RA10 ILLEGAL 2

L L L X X X ILLEGAL

H X X X X X NOP (Continue Burst to End Æ Precharge)

Write with L H H H X X NOP (Continue Burst to End Æ Precharge)

Auto L H H L X X ILLEGAL

Precharge L H L X BA CA, A10/AP ILLEGAL

L L H X BA RA, RA10 ILLEGAL 2

L L L X X X ILLEGAL

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 28/47

Current

State CS RAS CAS WE BA ADDR ACTION Note

H X X X X X NOP Æ Idle after tRP

L H H H X X NOP Æ Idle after tRP

Precharging L H H L X X ILLEGAL 2

L H L X BA CA ILLEGAL 2

L L H H BA RA ILLEGAL 2

L L H L BA A10/AP NOP Æ Idle after tRDL 4

L L L X X X ILLEGAL

H X X X X X NOP Æ Row Active after tRCD

L H H H X X NOP Æ Row Active after tRCD

Row L H H L X X ILLEGAL 2

Activating L H L X BA CA ILLEGAL 2

L L H H BA RA ILLEGAL 2

L L H L BA A10/AP ILLEGAL 2

L L L X X X ILLEGAL

H X X X X X NOP Æ Idle after tRC

L H H X X X NOP Æ Idle after tRC

Refreshing L H L X X X ILLEGAL

L L H X X X ILLEGAL

L L L X X X ILLEGAL

H X X X X X NOP Æ Idle after 2clocks

Mode L H H H X X NOP Æ Idle after 2clocks

Register L H H L X X ILLEGAL

Accessing L H L X X X ILLEGAL

L L X X X X ILLEGAL

Abbreviations : RA = Row Address BA = Bank Address

NOP = No Operation Command CA = Column Address AP = Auto Precharge

*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.

2. Illegal to bank in specified state ; Function may be legal in the bank indicated by BA, depending on the state of the

bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharge or in idle state. May precharge bank indicated by BA (and A10/AP).

5. Illegal if any bank is not idle.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 29/47

FUNCTION TRUTH TABLE (TABLE2)

Current

State CKE

( n-1 ) CKE

n CS RAS CAS WE ADDR ACTION Note

H X X X X X X INVALID

L H H X X X X Exit Self Refresh Æ Idle after tRC (ABI) 6

Self L H L H H H X Exit Self Refresh Æ Idle after tRC (ABI) 6

Refresh L H L H H L X ILLEGAL

L H L H L X X ILLEGAL

L H L L X X X ILLEGAL

L L X X X X X NOP (Maintain Self Refresh)

H X X X X X X INVALID

All L H H X X X X Exit Self Refresh Æ ABI 7

Banks L H L H H H X Exit Self Refresh Æ ABI 7

Precharge L H L H H L X ILLEGAL

Power L H L H L X X ILLEGAL

Down L H L L X X X ILLEGAL

L L X X X X X NOP (Maintain Low Power Mode)

H H X X X X X Refer to Table1

H L H X X X X Enter Power Down 8

H L L H H H X Enter Power Down 8

All H L L H H L X ILLEGAL

Banks H L L H L X X ILLEGAL

Idle H L L L H H RA Row (& Bank) Active

H L L L L H X Enter Self Refresh 8

H L L L L L OP Code Mode Register Access

L L X X X X X NOP

Any State H H X X X X X Refer to Operations in Table 1

other than H L X X X X X Begin Clock Suspend next cycle 9

Listed L H X X X X X Exit Clock Suspend next cycle 9

above L L X X X X X Maintain Clock Suspend

Abbreviations : ABI = All Banks Idle, RA = Row Address

*Note : 6.CKE low to high transition is asynchronous.

7.CKE low to high transition is asynchronous if restart internal clock.

A minimum setup time 1CLK + tSS must be satisfy before any command other than exit.

8.Power down and self refresh can be entered only from the all banks idle state.

9.Must be a legal command.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 30/47

Single Bit Read-Write-Read Cycle(Same Page) @ CAS Latency = 3,Burst Length = 1

: D o n ' t C a r e

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA0,BA1

tCH

tCL

tCC

tRAS

tRC

tSH

tSS

tRCD

tSH

tSS

tSH

tSS

Row Active Read Write Read Row Active

Precharge

*Note2

tRP

tSS

Ra

tSH

Rb

tSH

tSS

tSH

tSS

tOH

tSLZ

tSAC

*Note3

*Note4*Note2,3

*Note2,3

BS BS BS

Cb Cc

*Note3

Db

Qa

*Note3 *Note4

tSH

BS

BS BS

*Note1

HIGH

tCCD

Ra

*Note2

Ca

Qc

Rb

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 31/47

Note : 1. All input expect CKE & DQM can be don’t care when CS is high at the CLK high going edge.

2. Bank active @ read/write are controlled by BA0~BA1.

BA1 BA0 Active & Read/Write

0 0 Bank A

0 1 Bank B

1 0 Bank C

1 1 Bank D

3. Enable and disable auto precharge function are controlled by A10/AP in read/write command

A10/AP BA1 BA0 Operating

0 0 Disable auto precharge, leave A bank active at end of burst.

0 1 Disable auto precharge, leave B bank active at end of burst.

1 0 Disable auto precharge, leave C bank active at end of burst.

0

1 1 Disable auto precharge, leave D bank active at end of burst.

0 0 Enable auto precharge , precharge bank A at end of burst.

0 1 Enable auto precharge , precharge bank B at end of burst.

1 0 Enable auto precharge , precharge bank C at end of burst.

1

1 1 Enable auto precharge , precharge bank D at end of burst.

4. A10/AP and BA0~BA1 control bank precharge when precharge is asserted.

A10/AP BA1 BA0 Precharge

0 0 0 Bank A

0 0 1 Bank B

0 1 0 Bank C

0 1 1 Bank D

1 X X All Banks

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 32/47

Power Up Sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

tRP

Key RAa

BA1

BA0

RAa

High-Z

Precharge

(All Banks)

Auto Refresh Auto Refresh Mode Register Set

Row Active

(A-Bank)

: Don't care

tRC tRC

High level is necessary

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 33/47

Read & Write Cycle at Same Bank @ Burst Length = 4

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row

precharge. Last valid output will be Hi-Z (tSHZ) after the clock.

3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)

tRCD

tRC

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA0

BA1

CL=2

CL=3

`

Ra Ca Rb Cb

Ra Rb

tOH

tSAC

tSHZ

Read

Row Active Precharge

(A-Bank)

Precharge

(A-Bank)

Write

(A-Bank)

Row Active

(A-Bank)

*Note3

: Don't care

*Note1

Qa0 Qa1

Qa2 Qa3

Db0 Db3

Db1 Db2

Qa0 Qa1

Qa2 Qa3

Db0 Db3

Db1 Db2

HIGH

*Note2

tRDL

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 34/47

Page Read & Write Cycle at Same Bank @ Burst Length = 4

Note : 1. To Write data before burst read ends. DQM should be asserted three cycle prior to write command to avoid bus

contention.

2. Row precharge will interrupt writing. Last data input , tRDL before row precharge , will be written.

3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input

data after Row precharge cycle will be masked internally.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA1

BA0

CL =2

CL =3

*Note3

Row Active

( A - Bank )

Read

( A - Bank )

Read

( A - Bank )

Write

( A - Bank )

Write

( A - Bank )

Precharge

(A - Bank)

: D o n ' t C a r e

Qa0 Qa1 Qb0 Qb1 Dd0 Dd1

tCDL

Dc1

Dc0

Qa1 Qb0 Qb1 Qb2 Dc1 Dd0 Dd1

Dc0

Qa0

Ra

Cc Cd

Ra Ca Cb

*Note1

HIGH

tRCD

tRDL

*Note2

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 35/47

Page Read Cycle at Different Bank @ Burst Length = 4

Note: 1. CS can be don’t cared when RAS , CAS and WE are high at the clock high going edge.

2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

R o w A c t i v e

( A - B a n k )

R o w A c t i v e

( B - B a n k )

R e a d

( A - B a n k )

R o w A c t i v e

( C - B a n k )

R e a d

( B - B a n k )

P r e c h a r g e

( A - B a n k )

R o w A c t i v e

( D - B a n k )

R e a d

( C - B a n k )

P r e c h a r g e

( B - B a n k )

R e a d

( D - B a n k )

P r e c h a r g e

( C - B a n k )

P r e c h a r g e

( D - B a n k )

: D o n ' t C a r e

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1819

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

CL=2

DQM

A10/AP

BA1

BA0

CL=3

RBb CAa RCc CBb RDd CCc CDd

*Note1

*Note2

RAa

RDd

QBb0 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1

QDd2

QAa1

QAa0 QAa2 QBb1

QAa0 QAa1 QAa2 QBb0 QCc1 QCc2 QDd0 QDd2

QDd1QBb1 QCc0

QBb2

RAa RBb RCc

HIGH

DQ

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 36/47

Page Write Cycle at Different Bank @ Burst Length = 4

*Note : 1. To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data.

2. To interrupt burst write by Row precharge , both the write and the precharge banks must be the same.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA1

BA0

: Don't care

*Note1

RAa RBb CAa CBb RDd CCc

RCc CDd

*Note2

DAa1DAa0 DBb0 DBb1 DBb3 DDd0 DDd1

DAa2 DBb2 DCc0 DCc1

RAa RBb RCc RDd

DAa3 CDd2

tCDL

R o w A c t i v e

( A - Bank )

R o w A c t i v e

( B - B a n k )

W r i t e

( A - B a n k )

W r i t e

( B - B a n k )

R o w A c t i v e

( C - B a n k )

W r i t e

( C - B a n k )

P r e c h a r g e

( A l l B a n k s )

R o w A c t i v e

( D - B a n k )

W r i t e

( D - B a n k )

HIGH

tRDL

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 37/47

Read & Write Cycle at Different Bank @ Burst Length = 4

*Note : 1. tCDL should be met to complete write.

2. tRCD should be met.

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA1

BA0

CL =2

CL =3

Row Active

(A-Bank)

Read

(B-Bank)

: D o n ' t C a r e

QAa1 QAa2 QAa3 Ddb1 DDb2 DDd3

DDb0

QAa0

RAa

CBcRAa CAa

QAa1 QAa2 QAa3 Ddb1 DDb2 DDd3

DDb0

QAa0

Write

(D-Bank)

HIGH

RDb CDb RBc

RBb RAc

QBc0 QBc1 QBc2

QBc0 QBc1

Read

(A-Bank)

Row Active

(D-Bank)

Precharge

(A-Bank)

Row Active

(B-Bank)

tCDL

tRCD

*Note1*Note2

192103 4 5 6 7 8 11 12 13 14 1715 18

16 19

0

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 38/47

Read & Write cycle with Auto Precharge @ Burst Length = 4

*Note : 1. tCDL should be controlled to meet minimum tRAS before internal precharge start.

(In the case of Burst Length = 1 & 2)

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA0

BA1

CL =2

CL =3

Row Active

( A - Bank )

Row Active

( D - Bank )

Read with

Auto Precharge

( A - Bank )

Auto Precharge

Start Point

(D-Bank)

: D o n ' t C a r e

QAa1 QAa2 QAa3 Ddb1 DDb2 DDd3

DDb0

QAa0

Ra

Cb

Ra Ca

Rb

QAa1 QAa2 QAa3 Ddb1 DDb2 DDd3

DDb0

QAa0

Auto Precharge

Start Point

Write with

Auto Precharge

(D-Bank)

HIGH

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 39/47

Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4

*Note : 1. DQM is needed to prevent bus contention.

2. tRCD should be met.

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA1

BA0

Ra Ca Cb Cc

Ra

Qa0 Qa1 Qa2 Qa3

tSHZ

Qb1Qb0

tSHZ

Dc0 Dc2

*Note1

Row Active Read Clock

Supension

Read

Read DQM

Write

DQM

Clock

Suspension

Write

DQM

:Don't Care

19210

345678 11 12 13 14 17

15 1816 19

0

tRCD

*Note2

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 40/47

Read interrupted by Precharge Command & Read Burst Stop Cycle @ Burst Length = Full page

*Note : 1. About the valid DQs after burst stop, it is same as the case of RAS interrupt.

Both cases are illustrated above timing diagram. See the lable 1,2 on them.

But at burst write, Burst stop and RAS interrupt should be compared carefully.

Refer the timing diagram of “Full page write burst stop cycles”.

2. Burst stop is valid at every burst length.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA1

BA0

RAa CAa CAb

RAa

QAa0 QAa1 QAb1

QAb0 QAb2

Row Active

(A-Bank)

Read

(A-Bank)

Burst Stop Read

(A-Bank)

:Don't Care

HIGH

CL=2

CL=3

QAa2 QAa3 QAa4 QAb3 QAb4 QAb5

QAa0 QAa1 QAb1

QAb0 QAb2

QAa2 QAa3 QAa4 QAb3 QAb4 QAb5

11

22

Precharge

(A-Bank)

*Note2

*Note1 *Note1

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 41/47

Write interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length = Full page

*Note : 1. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by

AC parameter of tRDL.

DQM at write interrupted by precharge command is needed to prevent invalid write.

DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input

data after Row precharge cycle will be masked internally.

2. Burst stop is valid at every burst length.

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA1

BA0

RAa CAa CAb

RAa

DAa0 DAa1 DAb1DAb0 DAb2

Row Active

(A-Bank)

Write

(A-Bank)

Burst Stop Write

(A-Bank)

:Don't Care

HIGH

DAa2 DAa3 DAa4 DAb3 DAb4 DAb5

Precharge

(A-Bank)

tBDL tRDL

*Note1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 42/47

Active/Precharge Power Down Mode @ CAS Latency = 2, Burst Length = 4

*Note: 1. Both banks should be in idle state prior to entering precharge power down mode.

2. CKE should be set high at least 1CLK + tSS prior to Row active command.

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA0

Active

Power-down

Exit

Precharge

: Don't care

*Note3

*Note2

*Note1

tSS tSS tSS

Ra

Qa0 Qa1 Qa2

tSHZ

Precharge

Power-Down

Entry Precharge

Power-Down

Exit

Row Active

Active

Power-down

Entry

Read

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Ca

BA1

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 43/47

Self Refresh Entry & Exit Cycle

*Note : TO ENTER SELF REFRESH MODE

1. CS , RAS & CAS with CKE should be low at the same clock cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don’t care except for CKE.

3. The device remains in self refresh mode as long as CKE stays “Low”.

cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.

TO EXIT SELF REFRESH MODE

4. System clock restart and be stable before returning CKE high.

5. CS starts from high.

6. Minimum tRC is required after CKE going high to complete self refresh exit.

7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst

refresh.

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

A10/AP

BA0,BA1

Self Refresh Entry Auto Refresh

: Don't care

*Note2

*Note1

tSS

*Note3

*Note4 tRC

min

*Note6

Self Refresh Exit

Hi-Z Hi-Z

*Note5

*Note7

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 44/47

Mode Register Set Cycle Auto Refresh Cycle

All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE

*Note : 1. CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register.

2. Minimum 2 clock cycles should be met before new RAS activation.

3. Please refer to Mode Register Set table.

CLOCK

CKE

CS

RAS

CAS

ADDR

WE

DQ

DQM

:Don't Care

HIGH

0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 8 9 10

HIGH

Key Ra

HI-Z HI-Z

*Note2

*Note1

*Note3

tRC

MRS New

Command Auto Refresh New Command

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 45/47

PACKING DIMENSIONS

86 - LEAD TSOP(II) DRAM(400mil)

Symbol Dimension in mm Dimension in inch

Min Norm Max Min Norm Max

A 1.20 0.047

A1 0.05 0.10 0.15 0.002 0.004 0.006

A2 0.95 1.00 1.05 0.037 0.039 0.041

b 0.17 0.27 0.007 0.018

b1 0.17 0.20 0.23 0.007 0.008 0.009

c 0.12 0.21 0.005 0.008

c1 0.10 0.127 0.16 0.004 0.005 0.006

D 22.22 BSC 0.875 BSC

ZD 0.61 REF 0.024 REF

E 11.76 BSC 0.463 BSC

E1 10.16 BSC 0.400 BSC

L 0.40 0.50 0.60 0.016 0.020 0.024

L1 0.80 REF 0.031 REF

e 0.50 BSC 0.020 BSC

R1 0.12 0.005

R2 0.12 0.25 0.005 0.010

θ °0 °8 °0 °8

θ1 °0 °0

θ2 °10 °15 °20 °10 °15 °20

θ3 °10 °15 °20 °10 °15 °20

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 46/47

PACKING DIMENSIONS

90-BALL SDRAM ( 8x13 mm )

Symbol Dimension in mm Dimension in inch

Min Norm Max Min Norm Max

A

1.00

0.039

A1 0.30 0.35 0.40 0.012 0.014 0.016

A2

0.586 0.023

øb 0.40 0.45 0.50 0.016 0.018 0.020

D 7.90 8.00 8.10 0.311 0.315 0.319

E 12.90 13.00 13.10 0.508 0.512 0.516

D1

6.40

0.252

E1

11.20 0.441

e

0.80

0.031

Controlling dimension : Millimeter.

ESMT

M12L64322A

Elite Semiconductor Memo ry Technology Inc. Publication Date: Mar. 2007

Revision: 2.3 47/47

Important Notice

No part of this document may be reproduced or duplicated in any form or by any

means without the prior permission of ESMT.

The contents contained in this document are believed to be accurate at the time of

publication. ESMT assumes no responsibility for any error in this document, and

reserves the right to change the products or specification in this document without

notice.

The information contained herein is presented only as a guide or examples for the

application of our products. No responsibility is assumed by ESMT for any

infringement of patents, copyrights, or other intellectual property rights of third

parties which may result from its use. No license, either express , implied or

otherwise, is granted under any patents, copyrights or other intellectual property

rights of ESMT or others.

Any semiconductor devices may have inherently a certain rate of failure. To minimize

risks associated with customer's application, adequate design and operating

safeguards against injury, damage, or loss from such failure, should be provided by

the customer when making application designs.

ESMT's products are not authorized for use in critical applications such as, but not

limited to, life support devices or system, where failure or abnormal operation may

directly affect human lives or cause physical injury or property damage. If products

described here are to be used for such kinds of application, purchaser must do its

own quality assurance testing appropriate to such applications.