TOSHIBA Octal D-Type Latch with 3-State Output TC74HC563A Inverted TC74HC573A Non-inverting The TC74HC563A and TC74HC573A4 are high speed CMOS OCTAL LATCH with 3-STATE OUTPUT fabricated with silicon gate CMOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. These 8-bit D-type latches are controlled by a latch enable input (LE) and output enable input OE). When the OE input is high, the eight outputs are in a high impedance state. The TC74HC563A has inverting outputs, and TC74HC573A has non-inverting outputs. All inputs are equipped with protection circuits against static discharge or transient excess voitage. Features High Speed: tg = 13ns (Typ.) at Voc = 5V * Low Power Dissipation: I, = 4yA(Max.) at Ta = 25C High Noise Immunity: Viiq = Va = 28% Vec (Min) * Output Drive Capability: 15 LSTTL Loads * Symmetrical Output Impedance: Ilo4l = le, = 4mA(Min.) * Balanced Propagation Delays: toy = tha * Wide Operating Voltage Range: Vec(opr) = 2V ~ 6V Pin and Function Compatible with 74LS563/573 TC74HC563AP/AF TC74HC573AP/AF/AFW A ne TC74HC563A TC74HC573A OE 1 2 Vee Et 2 Vee oo 2 19 Go bo 2 19 QO Di 3 1 @& Di 3 18 Q1 02 4 17 G2 O02 4 17 Q2 03 5 1% 03 D3 5 16 a3 O4 6 iS G4 04 6 1 4 06 7 4 05 05 7 14 05 ps 6 13, 08 08 8 13 Q6 o7 9 12 07 D7 9 12.97 GND 10 11 Le = GND 10 11 Le Pin Assignment Truth Table inputs Outputs OE LE D Q(HC573A) | U(HCS563A) H x Xx Z z L L X Qn th L H L L H L H H H L X: Dont Care Z: High Impedance Q,(@,): Q@) outputs are latched at the time when the input is taken to a low logic level. TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 545 TC74HC563AP/AF TC74HC573AP/AF/AFW C?MOS Logic TC74HC/HCT Series TC74HCS63A TC74HC573A EN OE EN cl LE cl a0 D0 a D1 Q2 02 rox} D3 a4 D4 a5 D5 a6 D6 a7 07 JEC Logic Symbol! TC74HC563A D0 ol p2 03 D4 D5 D D7 L- wales ba ls Da wa lies 5) fo) fo) Cay EE lep a Gi a 4 o ch 4 ] o& q> t t t T T T a al Q2 G3 oO a ro. a TC74HCS73A o0 o1 p2 D3 Ds DS D6 D7 Let borg bien bes bog beg ber bs toh Loh | 10 La La La Lap, | 1a > Td ao Ql 02 Q3 a4 os a6 Q7 Logic Diagram 546 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. TC74HC563AP/AF C2MOS Logic TC74HC/HCT Series TC74HC573AP/AF/AFW Absolute Maximum Ratings Parameter Symbol Vatue Unit Supply Voltage Range Voc 05-7 V DC Input Voltage Vin 0.5 ~Voo+ 05 V DC Output Voltage Vout -0.5 ~ Veg + 0.5 V input Diode Current lik +20 mA Outpul Diode Current lox 20 mA DC Output Current lout 335 mA DC Voc/Ground Current lec 5 mA Power Dissipation Pp 500(DIP)*/180(MFP) mW Storage Temperature Tyig ~65 ~ 150 C Lead Temperature 10sec Tr 300 C *500mW in the range of Ta = -40C ~ 65C. From Ta = 68C to 85C a derating factor of -10mWAC shall be applied until 300mW. Recommended Operating Conditions Parameter Symbol Value Unit Supply Voltage Voc 2~6 V Input Voltage Vin 0-Veo v Output Voltage Vout 0-Veo v Operating Temperature Tope -40 - 85 0-1000(Vgc = 2.0V) \nput Rise and Fall Time ty 0 ~ 500(Vgc = 4.5V) ns 0 ~ 400(Veg = 6.0V) DC Electrical Characteristics Ta = 25C Ta = -40 ~ 85C Parameter Symbol Test Condition Unit Veco | Min. Typ. Max. Min. Max. . 2.0 156 - - 15 - High-Level _ Input Voltage Vin - . - _ O _ V 2.0 - - 05 - 05 Low-Level Vi - 45 | - - 135 - 136 V Input Voltage 60 _ _ 18 _ 18 2.0 19 2.0 ~ 19 - / low =-20pA 45 44 45 - 44 - High-Level y Vin = 60 | 58 6.0 - 59 - v OH Output Voltage Vi OF Va lon =-6 MA 45 4.18 431 - 4.13 - lon = -7.8mA 6.0 5.68 5.80 - 5.63 - 2.0 - 0.0 04 - 04 lop = 20pA 45 - 0.0 04 - 01 Low-Level Vo. Vin = 6.0 - 0.0 o4 - o4 V Output Voltage Vi OF Vip lop=6mA 45 - 0.17 0.26 - 0.33 loc = 7.8mA 6.0 - 0.18 0.26 - 0.33 3-State Output Vin = Viq OF Vip _ _ . Off-State Current lez Vout = Vee or GND 60 #5 60 Input Leakage Current lin Vin = Voc oF GND 6.0 - - 1 - 41.0 pA Quiescent Supply Current lec Vin = Voc of GND 6.0 - - 40 - 40.0 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. 547 TC74HC563AP/AF TC74HC573AP/AF/AFW C?MOS Logic TC74HC/HCT Series Timing Requirements (Input t, = t, = 6ns) Ta = 25C Ta = -40 ~ 85C Parameter Symbol | Test Condition Unit Vee Typ. Limit Limit Minimum Pulse Width tw 20 - 8 % (Le) ' ~ 45 - 45 19 wu 6.0 - 13 16 Minimum Setup Time 20 ~ 30 8 (Data) l, - 45 - 10 13 ns 60 - 9 11 Minimum Removal Time 20 ~ 5 5 (Data) hy - 45 - 5 5 6.0 - 5 5 AC Electrical Characteristics (C, = 50pF, Input t, = t, = 6ns) Ta = 25C Ta = -40 ~ 85C Parameter Symbol Test Condition Unit CL | Vee Min. Typ. Max. Min. Max. : 20 - 20 60 - 75 Output Transition Time it - 50 45 - 6 12 - 15 THE 6.0 - 5 10 - 13 2.0 - 50 115 - 145 tot 50 45 - 15 23 - 29 Propagation Delay Time _ 6.0 - 13 20 = 5 (LE-0,0) 20 - 60 155 - 195 tone 150 | 45 - 20 3t - 39 6.0 - 7 26 - 33 2.0 - 42 110 ~ 140 foun 50 45 - 14 22 - 28 Propagation Delay Time _ 6.0 - 12 19 - 24 18 (0-00) 20 - 57 150 - 190 toa 180 | 45 - 19 30 - 38 6.0 - 16 26 - 32 2.0 ~ 55 140 - 75 tor 50 45 - 7 28 - 35 6.0 - 14 24 - 30 Qutput Enable Time R= 1kQ 2.0 - 66 180 - 225 tzH 150 | 45 - 22 36 - 45 6.0 - 19 31 - 38 t 20 - 40 125 - 155 Output Disable Time Pe R,=1kQ 50 | 45 - 7 25 - 31 HZ 6.0 ~ 15 21 ~ 26 Input Capacitance Cw - - 5 10 - 10 Output Capacitance Cour - - 10 - - - c oo TC74HC563A - 4g ~ - ~ P Power Dissipation Capacitance Cpp (1) TC74HC5734 - 51 ~ - - Note (1) Average operating current can be obtained by the equation: locwopy = Crp * Voc * fin + Ioo/8(per Latch) And the total Cpp when n pcs. of Latch operate can be gained by the following equation: Cpp (total) = 33 + 16 * n (TC74HC563A) Cpp(total) = 33 + 18 n (TC74HC573A) 548 TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC. Cpp is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.