HV256 32-Channel High-Voltage Amplifier Array Features General Description * * * * * * * * * The HV256 is a 32-channel, high-voltage amplifier array integrated circuit. It operates on a single high-voltage supply, up to 300V, and two low-voltage supplies, VDD and VNN. Thirty-two Independent High-voltage Amplifiers 300V Operating Voltage 295V Output Voltage 2.2V/s Typical Output Slew Rate Adjustable Output Current Source Limit Adjustable Output Current Sink Limit Internal Closed-loop Gain of 72V/V 12 M Feedback Impedance Layout Ideal for Die Applications The input voltage range is from 0V to 4.096V. The internal closed-loop gain is 72V/V, giving an output voltage of 295V when 4.096V is applied. Input voltages of up to 5V can be applied but will cause the output to saturate. The maximum output voltage swing is 5V below the VPP high-voltage supply. The outputs can drive capacitive loads of up to 3000 pF. Applications * Microelectromechanical Systems (MEMS) Driver * Piezoelectric Transducer Driver * Optical Crosspoint Switches (Using MEMS Technology) The maximum output source and sink currents can be adjusted by using two external resistors. An external RSOURCE resistor controls the maximum sourcing current, and an external RSINK resistor controls the maximum sinking current. The current limit is approximately 12.5V divided by the external resistor value. The setting is common for all 32 outputs. A low-voltage silicon junction diode is made available to help monitor the die temperature. Package Type 100-lead MQFP (Top view) 100 1 See Table 3-1 for pin information. 2017 Microchip Technology Inc. DS20005826A-page 1 HV256 Functional Block Diagram BYP-VPP BYP-VDD To internal VPP bus To internal VDD bus BYP-VNN To internal VNN bus RSOURCE RSINK Output Current Source Limiting for all HVOUT Output Current Sink Limiting for all HVOUT VPP VDD VIN0 + HVOUT0 71R VNN VDD VPP VIN1 R + HVOUT1 VNN 71R R VDD VPP VIN31 + HVOUT31 71R GND R VNN Anode Cathode DS20005826A-page 2 2017 Microchip Technology Inc. HV256 Typical Application Circuit Micro Processor DAC DAC DAC DAC VPP HV256 VIN0 HVOUT0 VIN0 HVOUT1 VIN0 VIN0 VIN30 VIN31 High Voltage Op-Amp Array RSINK DAC RSOURCE DAC VDD HVOUT2 y x x y HVOUT3 MEMS Array HVOUT30 HVOUT31 AGND VNN 2017 Microchip Technology Inc. DS20005826A-page 3 HV256 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings High-voltage Supply, VPP ....................................................................................................................................... 310V Analog Low-voltage Positive Supply, AVDD ................................................................................................................ 8V Digital Low-voltage Positive Supply, DVDD ................................................................................................................. 8V Analog Low-voltage Negative Supply, AVNN ............................................................................................................ -7V Digital Low-voltage Negative Supply, DVNN ............................................................................................................ -7V Logic Input Voltage ................................................................................................................................. -0.5V to DVDD Analog Input Signal, VIN ................................................................................................................................... 0V to 6V Maximum Junction Temperature, TJ ..................................................................................................................... 150C Storage Temperature, TS .................................................................................................................... -65C to +150C Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Sym. Min. Typ. Max. Unit High-voltage Positive Supply VPP 125 -- 300 V Low-voltage Positive Supply VDD 6 -- 7.5 V Conditions Low-voltage Negative Supply VNN -4.5 -- -6.5 V VPP Supply Current IPP -- -- 0.8 mA VPP = 300V, All HVOUT = 0V, No load VDD Supply Current IDD -- -- 5 mA VDD = 6V to 7.5V VNN Supply Current INN -6 -- -- mA VNN = -4.5V to -6.5V Operating Temperature Range TJ -10 -- 85 C DS20005826A-page 4 2017 Microchip Technology Inc. HV256 DC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over operating conditions unless otherwise noted. Parameter HVOUT Voltage Swing Sym. Min. Typ. Max. Unit HVOUT 0 -- VPP-5 V Input Voltage Range VIN 0 -- 5 V Input Voltage Offset VINOS -- -- 50 mV RFB 9.6 12 -- M Feedback Resistance from HVOUT to Ground HVOUT Capacitive Load HVOUT Sourcing Current Limiting Range HVOUT Sinking Current Limiting Range External Resistance Range for Setting Maximum Current Source External Resistance Range for Setting Maximum Current Sink Conditions Input referred CLOAD 0 -- 3000 pF ISOURCE 385 550 715 A RSOURCE = 25 k ISINK 385 550 715 A RSINK = 25 k RSOURCE 25 -- 250 k RSINK 25 -- 250 k AC ELECTRICAL CHARACTERISTICS Electrical Specifications: Over operating conditions unless otherwise noted Parameter HVOUT Slew Rate Rise HVOUT Slew Rate Fall Sym. SR Min. Typ. Max. Unit Conditions -- 2.2 -- V/s No load -- 2 -- V/s No load VPP = 300V HVOUT -3 dB Channel Bandwidth BW -- 4 -- kHz Open-loop Gain AO 70 100 -- dB Closed-loop Gain AV 68.4 72 75.6 V/V DC Channel-to-channel Crosstalk CTDC -80 -- -- dB Power Supply Rejection Ratio for VPP, VDD and VNN PSRR -40 -- -- dB Peak Inverse Voltage PIV -- -- 5 V Cathode to anode Forward Diode Drop VF -- 0.6 -- V IF = 100 A, anode to cathode at TA = 25C Forward Diode Current IF -- -- 100 A Anode to cathode VF Temperature Coefficient TC -- -2.2 -- Min. Typ. Max. TEMPERATURE DIODE mV/C Anode to cathode TEMPERATURE SPECIFICATIONS Parameter Sym. Unit Conditions TEMPERATURE RANGE Maximum Junction Temperature TJ -- -- +150 C Storage Temperature TS -65 -- +150 C JA -- 39 -- C/W PACKAGE THERMAL RESISTANCE 100-lead MQFP 2017 Microchip Technology Inc. DS20005826A-page 5 HV256 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore outside the warranted range. (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) (VPP = 300V, VDD = 6.5V, VNN = 5.5V ) 3.5 600 3.0 500 2.5 2.0 Input Offset (mV) ISINK (A) 400 300 200 max 100 Offset at 25OC Offset at 85OC -2.0 -2.5 -3.0 min 0 Offset at -10OC 1.5 -3.5 25 150 250 -4.0 RSINK (k) -4.5 0 1.0 2.0 3.0 4.0 VIN (Volts) FIGURE 2-1: ISINK vs. RSINK. Input Offset vs. VIN and FIGURE 2-4: Temperature. (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 600 (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC) 73.97 73.96 500 73.94 Gain ISOURCE (A) 73.95 400 300 73.93 72.73 200 72.72 72.71 max 100 72.70 72.69 min 0 25 150 0 1 2 3 4 VIN (Volts) 250 RSOURCE (k) FIGURE 2-2: ISOURCE vs. RSOURCE. FIGURE 2-5: Gain vs. VIN. (VPP = 300V, VDD = 6.5V, VNN = 5.5V) 700 -10OC -50 25OC -40 min Vf (mV) max 500 min 85OC max min 400 VPP PSRR (dB) max 600 -30 -20 -10 0 10 300 0 20 40 60 80 (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) 100 1k 10k 100k 1M Frequency (Hz) 100 Diode Biasing Current (A) FIGURE 2-3: Temperature. DS20005826A-page 6 Temperature Diode vs. FIGURE 2-6: VPP PSRR vs. Frequency. 2017 Microchip Technology Inc. HV256 (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) VDD PSRR (dB) -50 -40 -30 -20 -10 0 10 100 1K 10K 100K 1M Frequency (Hz) FIGURE 2-7: (VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC) -50 VNN PSRR (dB) VDD PSRR vs. Frequency. -40 -30 -20 -10 0 10 100 1k 10k 100k 1M Frequency (Hz) FIGURE 2-8: VNN PSRR vs. Frequency. 2017 Microchip Technology Inc. DS20005826A-page 7 HV256 3.0 PIN DESCRIPTION The details on the pins of HV256 are listed on Table 3-1. Refer to Package Type for the location of pins. TABLE 3-1: PIN FUNCTION TABLE Pin Number Pin Name 1 HVOUT31 Amplifier output 2 HVOUT30 Amplifier output 3 HVOUT29 Amplifier output 4 HVOUT28 Amplifier output 5 HVOUT27 Amplifier output 6 HVOUT26 Amplifier output 7 HVOUT25 Amplifier output 8 HVOUT24 Amplifier output 9 HVOUT23 Amplifier output 10 HVOUT22 Amplifier output 11 HVOUT21 Amplifier output 12 HVOUT20 Amplifier output 13 HVOUT19 Amplifier output 14 HVOUT18 Amplifier output 15 HVOUT17 Amplifier output 16 HVOUT16 Amplifier output 17 HVOUT15 Amplifier output 18 HVOUT14 Amplifier output 19 HVOUT13 Amplifier output 20 HVOUT12 Amplifier output 21 HVOUT11 Amplifier output 22 HVOUT10 Amplifier output 23 HVOUT9 Amplifier output 24 HVOUT8 Amplifier output 25 HVOUT7 Amplifier output 26 HVOUT6 Amplifier output 27 HVOUT5 Amplifier output 28 HVOUT4 Amplifier output 29 HVOUT3 Amplifier output 30 HVOUT2 Amplifier output 31 HVOUT1 Amplifier output 32 HVOUT0 Amplifier output 33 VPP High-voltage positive supply. There are two pads in the die pad diagram. 34 NC No connect 35 NC No connect DS20005826A-page 8 Description 2017 Microchip Technology Inc. HV256 TABLE 3-1: PIN FUNCTION TABLE (CONTINUED) Pin Number Pin Name 36 NC No connect 37 NC No connect 38 NC No connect 39 GND Digital ground. There are four pads in the die pad diagram. 40 VNN Analog low-voltage negative supply. There are four pads in the die pad diagram. 41 NC 42 VDD Analog low-voltage positive supply. There are four pads in the die pad diagram. 43 GND Digital ground. There are four pads in the die pad diagram. 44 VNN Analog low-voltage negative supply. There are four pads in the die pad diagram. 45 VDD Analog low-voltage positive supply. There are four pads in the die pad diagram. 46 NC No connect 47 NC No connect 48 VIN0 Amplifier input 49 VIN1 Amplifier input 50 VIN2 Amplifier input 51 VIN3 Amplifier input 52 VIN4 Amplifier input 53 VIN5 Amplifier input 54 VIN6 Amplifier input 55 VIN7 Amplifier input 56 VIN8 Amplifier input 57 VIN9 Amplifier input 58 VIN10 Amplifier input 59 VIN11 Amplifier input 60 VIN12 Amplifier input 61 VIN13 Amplifier input 62 VIN14 Amplifier input 63 VIN15 Amplifier input 64 VIN16 Amplifier input 65 VIN17 Amplifier input 66 VIN18 Amplifier input 67 VIN19 Amplifier input 68 VIN20 Amplifier input 69 VIN21 Amplifier input 70 VIN22 Amplifier input 71 VIN23 Amplifier input 72 VIN24 Amplifier input 73 VIN25 Amplifier input 74 VIN26 Amplifier input 2017 Microchip Technology Inc. Description No connect DS20005826A-page 9 HV256 TABLE 3-1: PIN FUNCTION TABLE (CONTINUED) Pin Number Pin Name 75 VIN27 Amplifier input 76 VIN28 Amplifier input 77 VIN29 Amplifier input 78 VIN30 Amplifier input 79 VIN31 Amplifier input 80 NC No connect 81 NC No connect 82 NC No connect 83 NC No connect 84 NC No connect 85 NC No connect 86 GND Digital ground. There are four pads in the die pad diagram. 87 VDD Analog low-voltage positive supply. There are four pads in the die pad diagram. 88 VNN Analog low-voltage negative supply. There are four pads in the die pad diagram. 89 GND Digital ground. There are four pads in the die pad diagram. 90 NC 91 VDD Analog low-voltage positive supply. There are four pads in the die pad diagram. 92 BYP-VNN A low-voltage 1 nF to 10 nF decoupling capacitor across VNN and BYP-VNN is required. 93 BYP-VDD A low voltage 1 nF to 10 nF decoupling capacitor across VDD and BYP-VDD is required. 94 VNN Analog low-voltage negative supply. There are four pads in the die pad diagram. 95 ANODE 96 CATHODE 97 RSINK The external resistor from RSINK to VNN that sets the output current sinking limit. The current limit is approximately 12.5V divided by the RSINK resistor value. 98 RSOURCE The external resistor from RSOURCE to VNN that sets the output current sourcing limit. The current limit is approximately 12.5V divided by the RSOURCE resistor value. 99 BYP-VPP 100 VPP DS20005826A-page 10 Description No connect The anode side of a low-voltage silicon diode that can be used to monitor die temperature The cathode side of a low-voltage silicon diode that can be used to monitor die temperature A low-voltage 1 nF to 10 nF decoupling capacitor across VPP and BYP-VPP is required. High-voltage positive supply. There are four pads in the die pad diagram. 2017 Microchip Technology Inc. HV256 3.1 Pad Configuration Do not bond. Leave floating. VDD GND VNN GND VDD BYP-VNN VNN Anode BYP-VDD Do not bond. For testing only Cathode RSINK RSOURCE BYP-VPP VPP HVOUT31 Do not bond. Leave floating. HVOUT30 HVOUT29 VIN31 HVOUT28 VIN30 VIN29 HVOUT27 VIN28 HVOUT26 VIN27 HVOUT25 VIN26 HVOUT24 VIN25 HVOUT23 VIN24 HVOUT22 VIN23 HVOUT21 VIN22 HVOUT20 VIN21 VIN20 HVOUT19 VIN19 HVOUT18 VIN18 HVOUT17 VIN17 HVOUT16 VIN16 HVOUT15 VIN15 HVOUT14 HVOUT13 VIN14 HVOUT12 VIN13 HVOUT11 VIN12 HVOUT10 VIN11 HVOUT9 VIN10 HVOUT8 VIN9 HVOUT7 VIN8 HVOUT6 VIN7 HVOUT5 VIN6 HVOUT4 VIN5 VIN4 HVOUT3 VIN3 HVOUT2 VIN2 HVOUT1 VIN1 HVOUT0 VIN0 VPP VDD VNN GND VDD VNN GND FIGURE 3-1: Pad Configuration Drawing. 2017 Microchip Technology Inc. DS20005826A-page 11 HV256 TABLE 3-2: TABLE 3-2: PAD COORDINATES PAD COORDINATES (CONTINUED) Chip Size: 17160 m X 5830 m Center of Die: 0,0 Chip Size: 17160 m X 5830 m Center of Die: 0,0 Pad Name X (m) Y (m) Pad Name X (m) Y (m) VPP -8338.5 2708.5 GND 8047 -1424 HVOUT0 -7895 2305.5 VNN 8066.5 -1590 VDD 8066.5 -1958.5 HVOUT1 -7448.5 2305.5 HVOUT2 -7001.5 2305.5 GND 7867 -2192 2305.5 VIN31 5043.5 -2686 4638.5 -2686 HVOUT3 -6554.5 HVOUT4 -6107.5 2305.5 VIN30 HVOUT5 -5660.5 2305.5 VIN29 4233.5 -2686 3828.5 -2686 HVOUT6 -5213.5 2305.5 VIN28 HVOUT7 -4776.5 2305.5 VIN27 3423.5 -2686 2305.5 VIN26 3018.5 -2686 2613.5 -2686 HVOUT8 -4319.5 HVOUT9 -3872.5 2305.5 VIN25 HVOUT10 -3425.5 2305.5 VIN24 2208.5 -2686 1803.5 -2686 HVOUT11 -2978.5 2305.5 VIN23 HVOUT12 -2513.5 2305.5 VIN22 1398.5 -2686 2305.5 VIN21 993.5 -2686 588.5 -2686 HVOUT13 -2084.5 HVOUT14 -1637.5 2305.5 VIN20 HVOUT15 -1190.5 2305.5 VIN19 183.5 -2686 -221.5 -2686 HVOUT16 -743.5 2305.5 VIN18 HVOUT17 -296.5 2305.5 VIN17 -626.5 -2686 2305.5 VIN16 -1031.5 -2686 -1436.5 -2686 HVOUT18 150 HVOUT19 597.5 2305.5 VIN15 HVOUT20 1044.5 2305.5 VIN14 -2412.5 -2686 -2817 -2686 HVOUT21 1491.5 2305.5 VIN13 HVOUT22 1938.5 2305.5 VIN12 -3222 -2686 2305.5 VIN11 -3627 -2686 -4032 -2686 HVOUT23 2385.5 HVOUT24 2832.5 2305.5 VIN10 HVOUT25 3279.5 2305.5 VIN9 -4437 -2686 -4842 -2686 HVOUT26 3726.5 2305.5 VIN8 HVOUT27 4173.5 2305.5 VIN7 -5247 -2686 2305.5 VIN6 -5652 -2686 -6052 -2686 HVOUT28 4620.5 HVOUT29 5067.5 2305.5 VIN5 HVOUT30 5514.5 2305.5 VIN4 -6462 -2686 -6867 -2686 HVOUT31 5961.5 2305.5 VIN3 VPP 6659 2709 VIN2 -7272 -2686 2709 VIN1 -7677 -2686 -8082 -2686 BYP-VPP 7045 RSOURCE 7489 2709 VIN0 RSINK 7969 2709 VDD -8373 -2250.5 -8373 -1949 CATHODE 8366 2709 VNN ANODE 8366 2709 GND -8367 -1561 VNN 8047 425 VDD -8387 -1143 -8338.5 577.5 -8341 916.5 BYP-VDD 8047 125.5 VNN BYP-VNN 8047 -135.5 GND VDD 8047 -704.5 DS20005826A-page 12 2017 Microchip Technology Inc. HV256 4.0 FUNCTIONAL DESCRIPTION 4.1 Power-up/Power-down Sequence 4.1.1 EXTERNAL DIODE PROTECTION 4.1.2 The device can be damaged due to improper powerup/power-down sequence. To avoid this, please follow the acceptable power-up and power-down sequences in Table 4-1 and Table 4-2 and add two external diodes as shown in Figure 4-1. The first diode is a high-voltage diode across VPP and VDD where the anode of the diode is connected to VDD and the cathode of the diode is connected to VPP. Any low-current high-voltage diode such as a 1N4004 will be adequate. The second diode is a Schottky diode across VNN and DGND where the anode of the Schottky diode is connected to VNN and the cathode is connected to DGND. Any low-current Schottky diode such as a 1N5817 will be sufficient. VDD RECOMMENDED POWER-UP/POWER-DOWN SEQUENCE The HV256 needs all power supplies to be fully up and all channels refreshed with VSIG = 0V to force all high-voltage outputs to 0V. Before that time, the high-voltage outputs may have temporary voltage excursions above or below GND level, depending on selected power-up sequence. To minimize the excursions, the VDD and VNN power supplies should be applied at the same time (or within a few nanoseconds). In addition, the suggested VPP ramp-up speed should be 10 milliseconds or longer and the ramp-down should be 1 millisecond or longer. VPP 1N4004 or similar VNN DGND 1N5817 or similar FIGURE 4-1: Diode Configuration. TABLE 4-1: ACCEPTABLE POWER-UP SEQUENCES Option 2 Option 1 Step 1 2 3 4 Description VPP VNN VDD Inputs and Anode TABLE 4-2: Step 1 2 3 4 Step 4 VNN VDD VPP Inputs and Anode Step 1 2 3 4 Description VDD and VNN Inputs VPP Anode ACCEPTABLE POWER-DOWN SEQUENCES Option 2 Option 1 1 2 3 Description Option 3 Description Inputs and Anode VDD VNN VPP 2017 Microchip Technology Inc. Step 1 2 3 4 Description Inputs and Anode VPP VDD VNN Option 3 Step 1 2 3 4 Description Anode VPP Inputs VNN and VDD DS20005826A-page 13 HV256 300V VPP 0V VDD 6.5V 0V VNN -5.5V 0V 0V VIN GND +/- V offset X 72 0V HVOUT FIGURE 4-2: Recommended Power-up/Power-down Timing. VDD Before VNN VNN Before VDD VPP 0V VPP 0V VDD 6.5V 0V VDD 6.5V 0V VNN 0V -5.5V VNN 0V -5.5V HVOUT 0V -5.5V HVOUT 6.5V 0V FIGURE 4-3: DS20005826A-page 14 HVOUT Level at Power-up. 2017 Microchip Technology Inc. HV256 4.2 RSINK/RSOURCE The VDD_BYP, VDD_BYP and VNN_BYP pins are internal high-impedance-current mirror gate nodes, brought out to maintain stable opamp biasing currents in noisy power supply environments. When 0.1 F/25V bypass capacitors are added from between VPP_BYP and VPP, between VDD_BYP and VDD, and between VNN_BYP and VNN, they will force the high-impedance gate nodes to follow the fluctuation of power lines. The expected voltages at the VDD_BYP and VNN_BYP pins are typically 1.5V from their respectful power supply. The expected voltage at VPP_BYP is typically 3V below VPP. VPP Current limit BYP_VPP Cap 0.1F/25V BYP_VPP Set by RSOURCE BYP_VDD To internal biasing BYP_VDD Cap 0.1F/25V HVOpamp HVOUT0 HVOpamp HVOUT31 VDD BYP_VNN Set by RSINK Current limit BYP_VNN Cap 0.1F/25V VNN FIGURE 4-4: Internal Reference Current Diagram. 2017 Microchip Technology Inc. DS20005826A-page 15 HV256 5.0 PACKAGE MARKING INFORMATION 5.1 Packaging Information 100-lead MQFP Example XXXXXXX e3 YYWWNNN HV256FG e3 1738120 Legend: XX...X Y YY WW NNN e3 * Note: DS20005826A-page 16 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. 2017 Microchip Technology Inc. HV256 100-Lead MQFP Package Outline (FG) 20.00x14.00mm body, 3.15mm height (max), 0.65mm pitch, 3.20mm footprint D D1 E E1 Note 1 (Index Area E1/4 x D1/4) 100 1 1 e b Top View View B A A2 L L1 Seating Plane A1 Gauge Plane L2 Side View Seating Plane View B Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. Note: 1. $3LQLGHQWLHUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWLHUFDQEHDPROGHGPDUNLGHQWLHUDQHPEHGGHGPHWDOPDUNHURU a printed indicator. Symbol A MIN A1 A2 b 2.50* 0.00 2.50 0.22 Dimension NOM 2.70 (mm) MAX 3.15 0.25 2.90 0.40 D D1 E E1 22.95* 19.80* 16.95* 13.80* 0.65 1.60 0.25 14.00 0.88 BSC REF BSC 14.20* 1.03 23.20 20.00 17.20 23.45* 20.20* 17.45* e L L1 L2 0.73 0O 5O - - 7O 16O JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996. 7KLVGLPHQVLRQLVQRWVSHFLHGLQWKH-('(&GUDZLQJ Drawings are not to scale. S D # DSPD 100MQFPFG V i F041309 2017 Microchip Technology Inc. DS20005826A-page 17 HV256 NOTES: DS20005826A-page 18 2017 Microchip Technology Inc. HV256 APPENDIX A: REVISION HISTORY Revision A (August 2017) * Converted Supertex Doc# DSFP-HV256 to Microchip DS20005826A * Changed the part marking format * Made minor text changes throughout the document 2017 Microchip Technology Inc. DS20005826A-page 19 HV256 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. PART NO. Device XX - Package Options X - Environmental X Media Type Device: HV256 = 32-Channel High-Voltage Amplifier Array Package: FG = 100-lead MQFP Environmental: G = Lead (Pb)-free/RoHS-compliant Package Media Type: (blank) = 66/Tray for an FG Package DS20005826A-page 20 Example: a) HV256FG-G: 32-Channel High-Voltage Amplifier Array, 100-lead MQFP, 66/Tray 2017 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. 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Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2017, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-2116-0 == ISO/TS 16949 == 2017 Microchip Technology Inc. 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