2017 Microchip Technology Inc. DS20005826A-page 1
HV256
Features
• Thirty-two Independent High-voltage Amplifiers
• 300V Operating Voltage
• 295V Output Voltage
• 2.2V/µs Typical Output Slew Rate
• Adjustable Output Current Source Limit
• Adjustable Output Current Sink Limit
• Internal Closed-loop Gain of 72V/V
• 12 MΩ Feedback Impedance
• Layout Ideal for Die Applications
Applications
• Microelectromechanical Systems (MEMS) Driver
• Piezoelectric Transducer Driver
• Optical Crosspoint Switches
(Using MEMS Technology)
General Description
The HV256 is a 32-channel, high-voltage amplifier
array integrated circuit. It operates on a single
high-voltage supply, up to 300V, and two low-voltage
supplies, VDD and VNN.
The input voltage range is from 0V to 4.096V. The
internal closed-loop gain is 72V/V, giving an output
voltage of 295V when 4.096V is applied. Input voltages
of up to 5V can be applied but will cause the output to
saturate. The maximum output voltage swing is 5V
below the VPP high-voltage supply. The outputs can
drive capacitive loads of up to 3000 pF.
The maximum output source and sink currents can be
adjusted by using two external resistors. An external
RSOURCE resistor controls the maximum sourcing
current, and an external RSINK resistor controls the
maximum sinking current. The current limit is
approximately 12.5V divided by the external resistor
value. The setting is common for all 32 outputs. A
low-voltage silicon junction diode is made available to
help monitor the die temperature.
Package Type
100-lead MQFP
(Top view)
1
100
See Table 3-1 for pin information.
32-Channel High-Voltage Amplifier Array
HVOUT0
HVOUT31
HVOUT1
GND
VPP
VNN
-
+
R
71R
VDD
VPP
-
+
VIN0
VPP
-
+
Output Current Source
Limiting for all HVOUT
RSOURCE
R
R
RSINK Output Current Sink
Limiting for all HVOUT
71R
71R
Anode
Cathode
To internal VPP busBYP-VPP
BYP-VDD
BYP-VNN To internal VNN bus
To internal VDD bus
VIN1
VIN31
VDD
VDD
VNN
VNN
HV256
DS20005826A-page 2 2017 Microchip Technology Inc.
Functional Block Diagram
2017 Microchip Technology Inc. DS20005826A-page 3
HV256
Typical Application Circuit
VIN0
VIN0
VIN0
VIN0
HVOUT0
HVOUT1
HVOUT2
HVOUT3
HV256
AGND
MEMS
Array
y
y
x x
HVOUT30
HVOUT31
VNN
VDD VPP
VIN30
VIN31
Micro
Processor
DAC
DAC
DAC
DAC
DAC
DAC
High Voltage
Op-Amp
Array
RSOURCE
RSINK
HV256
DS20005826A-page 4 2017 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
High-voltage Supply, VPP ....................................................................................................................................... 310V
Analog Low-voltage Positive Supply, AVDD ................................................................................................................ 8V
Digital Low-voltage Positive Supply, DVDD ................................................................................................................. 8V
Analog Low-voltage Negative Supply, AVNN ............................................................................................................ –7V
Digital Low-voltage Negative Supply, DVNN ............................................................................................................ –7V
Logic Input Voltage ................................................................................................................................. –0.5V to DVDD
Analog Input Signal, VIN ................................................................................................................................... 0V to 6V
Maximum Junction Temperature, TJ..................................................................................................................... 150°C
Storage Temperature, TS .................................................................................................................... –65°C to +150°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
High-voltage Positive Supply VPP 125 —300 V
Low-voltage Positive Supply VDD 6 — 7.5 V
Low-voltage Negative Supply VNN –4.5 —–6.5 V
VPP Supply Current IPP — — 0.8 mA VPP = 300V, All HVOUT = 0V, No load
VDD Supply Current IDD — — 5 mA VDD = 6V to 7.5V
VNN Supply Current INN –6 — — mA VNN = –4.5V to –6.5V
Operating Temperature Range TJ–10 —85 °C
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise noted.
Parameter Sym. Min. Typ. Max. Unit Conditions
HVOUT Voltage Swing HVOUT 0 — VPP–5 V
Input Voltage Range VIN 0 — 5 V
Input Voltage Offset VINOS — — ±50 mV Input referred
Feedback Resistance from HVOUT
to Ground RFB 9.6 12 — MΩ
HVOUT Capacitive Load CLOAD 0 — 3000 pF
HVOUT Sourcing Current Limiting Range ISOURCE 385 550 715 µA RSOURCE = 25 kΩ
HVOUT Sinking Current Limiting Range ISINK 385 550 715 µA RSINK = 25 kΩ
External Resistance Range
for Setting Maximum Current Source RSOURCE 25 —250 kΩ
External Resistance Range for Setting
Maximum Current Sink RSINK 25 —250 kΩ
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Over operating conditions unless otherwise noted
Parameter Sym. Min. Typ. Max. Unit Conditions
HVOUT Slew Rate Rise SR —2.2 —V/µs No load
HVOUT Slew Rate Fall — 2 — V/µs No load
HVOUT –3 dB Channel Bandwidth BW — 4 — kHz VPP = 300V
Open-loop Gain AO70 100 —dB
Closed-loop Gain AV68.4 72 75.6 V/V
DC Channel-to-channel Crosstalk CTDC –80 — — dB
Power Supply Rejection Ratio for VPP
,
VDD and VNN
PSRR –40 — — dB
TEMPERATURE DIODE
Peak Inverse Voltage PIV — — 5 V Cathode to anode
Forward Diode Drop VF—0.6 — V
IF = 100 µA,
anode to
cathode at TA = 25°C
Forward Diode Current IF— — 100 µA Anode to cathode
VF Temperature Coefficient TC—–2.2 —mV/°C Anode to cathode
TEMPERATURE SPECIFICATIONS
Parameter Sym. Min. Typ. Max. Unit Conditions
TEMPERATURE RANGE
Maximum Junction Temperature TJ— — +150 °C
Storage Temperature TS–65 —+150 °C
PACKAGE THERMAL RESISTANCE
100-lead MQFP JA —39 —°C/W
2017 Microchip Technology Inc. DS20005826A-page 5
HV256
HV256
DS20005826A-page 6 2017 Microchip Technology Inc.
2.0 TYPICAL PERFORMANCE CURVES
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
RSINK (kΩ)
ISINK (µA)
min
max
600
500
400
300
200
100
0
25 150 250
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 2-1: ISINK vs. RSINK.
min
max
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
RSOURCE (kΩ)
ISOURCE (µA)
600
500
400
300
200
100
0
25 150 250
FIGURE 2-2: ISOURCE vs. RSOURCE.
700
600
500
400
300
Diode Biasing Current (μA)
V
f
(mV)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V)
-10OC
85OC
25OC
min
max
min
max
min
max
0 20 40 60 80 100
FIGURE 2-3: Temperature Diode vs.
Temperature.
FIGURE 2-4: Input Offset vs. VIN and
Temperature.
3.5
3.0
2.5
2.0
1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
0 1.0 2.0 3.0 4.0
VIN (Volts)
Input Offset (mV)
Offset at -10OC
Offset at 25OC
Offset at 85OC
(VPP = 300V, VDD = 6.5V, VNN = 5.5V )
0 1 2 3 4
V
IN
(Volts)
Gain
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = -10O, +25O, +85OC)
73.97
73.96
73.95
73.94
73.93
72.73
72.72
72.71
72.70
72.69
FIGURE 2-5: Gain vs. VIN.
Frequency (Hz)
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
VPP PSRR (dB)
(VPP = 300V, VDD = 6.5V, VNN = 5.5V, TA = 25OC)
FIGURE 2-6: VPP PSRR vs. Frequency.
2017 Microchip Technology Inc. DS20005826A-page 7
HV256
FIGURE 2-7:
VDD PSRR vs. Frequency.
Frequency (Hz)
V
NN
PSRR (dB)
(V
PP
= 300V, V
DD
= 6.5V, V
NN
= 5.5V, T
A
= 25
O
C)
-50
-40
-30
-20
-10
0
10 100 1k 10k 100k 1M
FIGURE 2-8: VNN PSRR vs. Frequency.
HV256
DS20005826A-page 8 2017 Microchip Technology Inc.
3.0 PIN DESCRIPTION
The details on the pins of HV256 are listed on
Table 3-1. Refer to Package Type for the location of
pins.
TABLE 3-1: PIN FUNCTION TABLE
Pin Number Pin Name Description
1HVOUT31 Amplifier output
2HVOUT30 Amplifier output
3HVOUT29 Amplifier output
4HVOUT28 Amplifier output
5HVOUT27 Amplifier output
6HVOUT26 Amplifier output
7HVOUT25 Amplifier output
8HVOUT24 Amplifier output
9HVOUT23 Amplifier output
10 HVOUT22 Amplifier output
11 HVOUT21 Amplifier output
12 HVOUT20 Amplifier output
13 HVOUT19 Amplifier output
14 HVOUT18 Amplifier output
15 HVOUT17 Amplifier output
16 HVOUT16 Amplifier output
17 HVOUT15 Amplifier output
18 HVOUT14 Amplifier output
19 HVOUT13 Amplifier output
20 HVOUT12 Amplifier output
21 HVOUT11 Amplifier output
22 HVOUT10 Amplifier output
23 HVOUT9 Amplifier output
24 HVOUT8 Amplifier output
25 HVOUT7 Amplifier output
26 HVOUT6 Amplifier output
27 HVOUT5 Amplifier output
28 HVOUT4 Amplifier output
29 HVOUT3 Amplifier output
30 HVOUT2 Amplifier output
31 HVOUT1 Amplifier output
32 HVOUT0 Amplifier output
33 VPP High-voltage positive supply. There are two pads in the die pad diagram.
34 NC No connect
35 NC No connect
2017 Microchip Technology Inc. DS20005826A-page 9
HV256
36 NC No connect
37 NC No connect
38 NC No connect
39 GND Digital ground. There are four pads in the die pad diagram.
40 VNN Analog low-voltage negative supply. There are four pads in the die pad diagram.
41 NC No connect
42 VDD Analog low-voltage positive supply. There are four pads in the die pad diagram.
43 GND Digital ground. There are four pads in the die pad diagram.
44 VNN Analog low-voltage negative supply. There are four pads in the die pad diagram.
45 VDD Analog low-voltage positive supply. There are four pads in the die pad diagram.
46 NC No connect
47 NC No connect
48 VIN0 Amplifier input
49 VIN1 Amplifier input
50 VIN2 Amplifier input
51 VIN3 Amplifier input
52 VIN4 Amplifier input
53 VIN5 Amplifier input
54 VIN6 Amplifier input
55 VIN7 Amplifier input
56 VIN8 Amplifier input
57 VIN9 Amplifier input
58 VIN10 Amplifier input
59 VIN11 Amplifier input
60 VIN12 Amplifier input
61 VIN13 Amplifier input
62 VIN14 Amplifier input
63 VIN15 Amplifier input
64 VIN16 Amplifier input
65 VIN17 Amplifier input
66 VIN18 Amplifier input
67 VIN19 Amplifier input
68 VIN20 Amplifier input
69 VIN21 Amplifier input
70 VIN22 Amplifier input
71 VIN23 Amplifier input
72 VIN24 Amplifier input
73 VIN25 Amplifier input
74 VIN26 Amplifier input
TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
HV256
DS20005826A-page 10 2017 Microchip Technology Inc.
75 VIN27 Amplifier input
76 VIN28 Amplifier input
77 VIN29 Amplifier input
78 VIN30 Amplifier input
79 VIN31 Amplifier input
80 NC No connect
81 NC No connect
82 NC No connect
83 NC No connect
84 NC No connect
85 NC No connect
86 GND Digital ground. There are four pads in the die pad diagram.
87 VDD Analog low-voltage positive supply. There are four pads in the die pad diagram.
88 VNN Analog low-voltage negative supply. There are four pads in the die pad diagram.
89 GND Digital ground. There are four pads in the die pad diagram.
90 NC No connect
91 VDD Analog low-voltage positive supply. There are four pads in the die pad diagram.
92 BYP-VNN A low-voltage 1 nF to 10 nF decoupling capacitor across VNN and BYP-VNN is
required.
93 BYP-VDD A low voltage 1 nF to 10 nF decoupling capacitor across VDD and BYP-VDD is
required.
94 VNN Analog low-voltage negative supply. There are four pads in the die pad diagram.
95 ANODE The anode side of a low-voltage silicon diode that can be used to monitor die
temperature
96 CATHODE The cathode side of a low-voltage silicon diode that can be used to monitor die
temperature
97 RSINK The external resistor from RSINK to VNN that sets the output current sinking limit.
The current limit is approximately 12.5V divided by the RSINK resistor value.
98 RSOURCE
The external resistor from RSOURCE to VNN that sets the output current
sourcing limit. The current limit is approximately 12.5V divided by the RSOURCE
resistor value.
99 BYP-VPP A low-voltage 1 nF to 10 nF decoupling capacitor across VPP and BYP-VPP is
required.
100 VPP High-voltage positive supply. There are four pads in the die pad diagram.
TABLE 3-1: PIN FUNCTION TABLE (CONTINUED)
Pin Number Pin Name Description
2017 Microchip Technology Inc. DS20005826A-page 11
HV256
3.1 Pad Configuration
HVOUT0
HVOUT1
HVOUT2
HVOUT3
HVOUT4
HVOUT5
HVOUT6
HVOUT7
HVOUT8
HVOUT9
HVOUT10
HVOUT11
HVOUT12
HVOUT13
HVOUT14
HVOUT15
HVOUT16
HVOUT17
HVOUT18
HVOUT19
HVOUT20
HVOUT21
HVOUT22
HVOUT23
HVOUT24
HVOUT25
HVOUT26
HVOUT27
HVOUT28
HVOUT29
HVOUT30
HVOUT31
VPP
VPP
BYP-VPP
RSOURCE
RSINK
VDD
VNN
GND
GND
VDD
VNN
VDD
VNN
GND
VDD
VNN
GND
BYP-VNN
BYP-VDD
Do not bond.
For testing only
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
VIN16
VIN17
VIN18
VIN19
VIN20
VIN21
VIN22
VIN23
VIN24
VIN25
VIN26
VIN27
VIN28
VIN29
VIN30
VIN31
Do not bond.
Leave floating.
Cathode
Anode
Do not bond.
Leave floating.
FIGURE 3-1: Pad Configuration Drawing.
TABLE 3-2: PAD COORDINATES
Chip Size: 17160 µm X 5830 µm
Center of Die: 0,0
Pad Name X (µm) Y (µm)
VPP –8338.5 2708.5
HVOUT0 –7895 2305.5
HVOUT1 –7448.5 2305.5
HVOUT2 –7001.5 2305.5
HVOUT3 –6554.5 2305.5
HVOUT4 –6107.5 2305.5
HVOUT5 –5660.5 2305.5
HVOUT6 –5213.5 2305.5
HVOUT7 –4776.5 2305.5
HVOUT8 –4319.5 2305.5
HVOUT9 –3872.5 2305.5
HVOUT10 –3425.5 2305.5
HVOUT11 –2978.5 2305.5
HVOUT12 –2513.5 2305.5
HVOUT13 –2084.5 2305.5
HVOUT14 –1637.5 2305.5
HVOUT15 –1190.5 2305.5
HVOUT16 –743.5 2305.5
HVOUT17 –296.5 2305.5
HVOUT18 150 2305.5
HVOUT19 597.5 2305.5
HVOUT20 1044.5 2305.5
HVOUT21 1491.5 2305.5
HVOUT22 1938.5 2305.5
HVOUT23 2385.5 2305.5
HVOUT24 2832.5 2305.5
HVOUT25 3279.5 2305.5
HVOUT26 3726.5 2305.5
HVOUT27 4173.5 2305.5
HVOUT28 4620.5 2305.5
HVOUT29 5067.5 2305.5
HVOUT30 5514.5 2305.5
HVOUT31 5961.5 2305.5
VPP 6659 2709
BYP-VPP 7045 2709
RSOURCE 7489 2709
RSINK 7969 2709
CATHODE 8366 2709
ANODE 8366 2709
VNN 8047 425
BYP-VDD 8047 125.5
BYP-VNN 8047 –135.5
VDD 8047 –704.5
GND 8047 –1424
VNN 8066.5 –1590
VDD 8066.5 –1958.5
GND 7867 –2192
VIN31 5043.5 –2686
VIN30 4638.5 –2686
VIN29 4233.5 –2686
VIN28 3828.5 –2686
VIN27 3423.5 –2686
VIN26 3018.5 –2686
VIN25 2613.5 –2686
VIN24 2208.5 –2686
VIN23 1803.5 –2686
VIN22 1398.5 –2686
VIN21 993.5 –2686
VIN20 588.5 –2686
VIN19 183.5 –2686
VIN18 –221.5 –2686
VIN17 –626.5 –2686
VIN16 –1031.5 –2686
VIN15 –1436.5 –2686
VIN14 –2412.5 –2686
VIN13 –2817 –2686
VIN12 –3222 –2686
VIN11 –3627 –2686
VIN10 –4032 –2686
VIN9 –4437 –2686
VIN8 –4842 –2686
VIN7 –5247 –2686
VIN6 –5652 –2686
VIN5 –6052 –2686
VIN4 –6462 –2686
VIN3 –6867 –2686
VIN2 –7272 –2686
VIN1 –7677 –2686
VIN0 –8082 –2686
VDD –8373 –2250.5
VNN –8373 –1949
GND –8367 –1561
VDD –8387 –1143
VNN –8338.5 577.5
GND –8341 916.5
HV256
DS20005826A-page 12 2017 Microchip Technology Inc.
TABLE 3-2: PAD COORDINATES
(CONTINUED)
Chip Size: 17160 µm X 5830 µm
Center of Die: 0,0
Pad Name X (µm) Y (µm)
2017 Microchip Technology Inc. DS20005826A-page 13
HV256
4.0 FUNCTIONAL DESCRIPTION
4.1 Power-up/Power-down Sequence
4.1.1 EXTERNAL DIODE PROTECTION
The device can be damaged due to improper power-
up/power-down sequence. To avoid this, please follow
the acceptable power-up and power-down sequences
in Tab l e 4-1 and Table 4-2 and add two external diodes
as shown in Figure 4-1. The first diode is a high-voltage
diode across VPP and VDD where the anode of the
diode is connected to VDD and the cathode of the diode
is connected to VPP
. Any low-current high-voltage
diode such as a 1N4004 will be adequate. The second
diode is a Schottky diode across VNN and DGND where
the anode of the Schottky diode is connected to VNN
and the cathode is connected to DGND. Any low-current
Schottky diode such as a 1N5817 will be sufficient.
VDD VPP
1N4004 or similar
VNN DGND
1N5817 or similar
FIGURE 4-1: Diode Configuration.
4.1.2 RECOMMENDED
POWER-UP/POWER-DOWN
SEQUENCE
The HV256 needs all power supplies to be fully up and
all channels refreshed with VSIG = 0V to force all
high-voltage outputs to 0V. Before that time, the
high-voltage outputs may have temporary voltage
excursions above or below GND level, depending on
selected power-up sequence. To minimize the
excursions, the VDD and VNN power supplies should be
applied at the same time (or within a few
nanoseconds). In addition, the suggested VPP ramp-up
speed should be 10 milliseconds or longer and the
ramp-down should be 1 millisecond or longer.
TABLE 4-1: ACCEPTABLE POWER-UP SEQUENCES
Option 1 Option 2 Option 3
Step Description Step Description Step Description
1 VPP 1 VNN 1 VDD and VNN
2 VNN 2 VDD 2Inputs
3VDD 3VPP 3VPP
4Inputs and Anode 4Inputs and Anode 4Anode
TABLE 4-2: ACCEPTABLE POWER-DOWN SEQUENCES
Option 1 Option 2 Option 3
Step Description Step Description Step Description
1Inputs and Anode 1Inputs and Anode 1Anode
2 VDD 2 VPP 2 VPP
3VNN 3VDD 3Inputs
4 VPP 4 VNN 4 VNN and VDD
0V
V
NN
0V
300V
0V
HV
OUT
0V
V
IN
GND +/- V offset X 72
0V
6.5V
-5.5V
V
DD
V
PP
HV256
DS20005826A-page 14 2017 Microchip Technology Inc.
FIGURE 4-2: Recommended Power-up/Power-down Timing.
VNN Before VDD
6.5V
0V
0V
-5.5V
0V
-5.5V
0V
6.5V
0V
6.5V
0V
0V
-5.5V
VPP
VDD
VNN
HVOUT
0V
VDD Before VNN
VPP
VDD
VNN
HVOUT
FIGURE 4-3: HVOUT Level at Power-up.
2017 Microchip Technology Inc. DS20005826A-page 15
HV256
4.2 RSINK/RSOURCE
The VDD_BYP, VDD_BYP and VNN_BYP pins are
internal high-impedance-current mirror gate nodes,
brought out to maintain stable opamp biasing currents
in noisy power supply environments. When 0.1 µF/25V
bypass capacitors are added from between VPP_BYP
and VPP
, between VDD_BYP and VDD, and between
VNN_BYP and VNN, they will force the high-impedance
gate nodes to follow the fluctuation of power lines. The
expected voltages at the VDD_BYP and VNN_BYP pins
are typically 1.5V from their respectful power supply.
The expected voltage at VPP_BYP is typically 3V below
VPP
.
BYP_VPP
HVOpamp
VDD
VPP
BYP_VNN
VNN
Set by RSOURCE
Set by RSINK
HVOUT0
BYP_VNN Cap
0.1µF/25V
Current limit
Current limit
To internal biasing HVOpamp
HVOUT31
BYP_VDD Cap
0.1µF/25V
BYP_VPP Cap
0.1µF/25V
BYP_VDD
FIGURE 4-4: Internal Reference Current Diagram.
HV256
DS20005826A-page 16 2017 Microchip Technology Inc.
5.0 PACKAGE MARKING INFORMATION
5.1 Packaging Information
Legend: XX...X Product Code or Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
3
e
3
e
XXXXXXX
YYWWNNN
e3
HV256FG
1738120
e3
100-lead MQFP Example
100-Lead MQFP Package Outline (FG)
20.00x14.00mm body, 3.15mm height (max), 0.65mm pitch, 3.20mm footprint
Symbol A A1 A2 b D D1 E E1 e L L1 L2 șș
Dimension
(mm)
MIN 2.50* 0.00 2.50 0.22 22.95* 19.80* 16.95* 13.80* 0.65
BSC
0.73 1.60
REF
0.25
BSC
0O5O
NOM - - 2.70 - 23.20 20.00 17.20 14.00 0.88 - -
MAX 3.15 0.25 2.90 0.40 23.45* 20.20* 17.45* 14.20* 1.03 7O16O
JEDEC Registration MS-022, Variation GC-2, Issue B, Dec. 1996.
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Drawings are not to scale.
SD#DSPD 100MQFPFG V i F041309
1
100
Top View
Seating
Plane
Gauge
Plane
θ
L
L1
L2
View B
View B
θ1
b
e
Side View
A2
A
A1
E
E1
DD1
Seating
Plane
Note 1
(Index Area
E1/4 x D1/4)
Note:
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a printed indicator.
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2017 Microchip Technology Inc. DS20005826A-page 17
HV256
HV256
DS20005826A-page 18 2017 Microchip Technology Inc.
NOTES:
2017 Microchip Technology Inc. DS20005826A-page 19
HV256
APPENDIX A: REVISION HISTORY
Revision A (August 2017)
• Converted Supertex Doc# DSFP-HV256
to Microchip DS20005826A
• Changed the part marking format
• Made minor text changes throughout the
document
HV256
DS20005826A-page 20 2017 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
Example:
a) HV256FG-G: 32-Channel High-Voltage
Amplifier Array, 100-lead MQFP,
66/Tray
PART NO.
Device
Device: HV256 = 32-Channel High-Voltage Amplifier Array
Package: FG = 100-lead MQFP
Environmental: G = Lead (Pb)-free/RoHS-compliant Package
Media Type: (blank) = 66/Tray for an FG Package
XX
Package
-
X - X
Environmental
Media Type
Options
2017 Microchip Technology Inc. DS20005826A-page 21
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEELOQ,
KEELOQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-2116-0
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITYMANAGEMENTS
YSTEM
CERTIFIEDBYDNV
== ISO/TS16949==
DS20005826A-page 22 2017 Microchip Technology Inc.
AMERICAS
Corporate Office
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
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EUROPE
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Worldwide Sales and Service
11/07/16