DATASHEET RAA210833 FN9348 Rev.1.00 Feb 8, 2019 Pin-Configurable 33A DC/DC Power Module with PMBus Interface The RAA210833 is a pin-strap-configurable 33A step-down PMBus-compliant DC/DC power supply module that integrates a digital PWM controller, synchronous MOSFETs, power inductor, and passive components. Only input and output capacitors are needed to finish the design. Because of its thermally enhanced HDA packaging technology, the module can deliver up to 33A of continuous output current without the need for airflow or additional heat sinking. The RAA210833 simplifies configuration and control of Renesas digital power technology while offering an upgrade path to full PMBus configuration through the pin-compatible ISL8278M. The RAA210833 uses ChargeModeTM control architecture, which responds to a transient load within a single switching cycle. The RAA210833 comes with a preprogrammed configuration for operating in a pin-strap mode. Output voltage, switching frequency, input UVLO, soft-start/stop delay and ramp times, and the device SMBus address can be programmed with external pin-strap resistors. A standard PMBus interface addresses fault management, as well as real-time full telemetry and point-of-load monitoring. The RAA210833 is available in a 41 Ld compact 17mmx19mm HDA module with a very low profile height of 3.6mm, suitable for automated assembly by standard surface mount equipment. The RAA210833 is RoHS compliant by exemption. Features * 33A single channel output current * Wide VIN range: 4.5V to 14V * Programmable output voltage * 0.6V to 5V output voltage settings * 1.2% accuracy over line/load/temperature * PMBus Interface and/or Pin-strap mode * Pin-strap mode for standard settings * VOUT, switching frequency, input UVLO, soft-start/stop, and external sync * Real time telemetry for VIN, VOUT, IOUT, temperature, duty cycle, and switching frequency. * ChargeMode control loop architecture * 296kHz to 1.06MHz fixed switching frequency operations * No compensation required * Fast single clock cycle transient response * Complete input and output over/undervoltage, output current, and temperature protections with fault logging * PowerNavigator supported * Thermally enhanced HDA package Applications * Server, telecom, storage, and datacom * Industrial/ATE and networking equipment * General purpose power for ASIC, FPGA, DSP, and memory Related Literature For a full list of related documents, visit our website * RAA210833 product page VIN CIN VIN VOUT VDD VSEN+ VSEN- VDRVIN COUT VR55 VDRVOUT 10F VOUT VCC 10F 10F 17 RAA210833 ENABLE SCL SDA SALRT EN SGND PMBus Interface m m PGND Note: 1. Only bulk input and output capacitors are required to finish the design. Figure 1. A Complete Digital Switch-Mode Power Supply FN9348 Rev.1.00 Feb 8, 2019 3.6mm m 19m Figure 2. A Small Package for High Power Density Page 1 of 57 RAA210833 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1 1.2 1.3 1.4 1.5 2. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RAA210833 Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 8 9 9 Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 2.2 2.3 2.4 3. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 12 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 3.2 3.3 4. Efficiency Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Transient Response Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Derating Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 5. SMBus Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soft-Start Delay and Ramp Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Frequency and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Module Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Prebias Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Overcurrent Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Overload Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Spreading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitoring Through SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Snapshot Parameter Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 19 21 22 22 23 24 25 26 26 27 28 28 28 29 PCB Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.1 5.2 5.3 5.4 5.5 5.6 Thermal Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PCB Layout Pattern Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stencil Pattern Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reflow Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FN9348 Rev.1.00 Feb 8, 2019 31 31 31 31 31 32 Page 2 of 57 RAA210833 6. PMBus Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1 6.2 PMBus Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PMBus Use Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7. PMBus Commands Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.1 8.2 9. Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Datasheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 FN9348 Rev.1.00 Feb 8, 2019 Page 3 of 57 RAA210833 1. Overview 1.1 Typical Application Circuit (Note 4) 3LQ6WUDS5HVLVWRUV (Note 2) &)* 6689/2 6<1& $6&5 5 6$ 5 30%XV ,QWHUIDFH 5 (1 555 N 9$8; 9WR9 96(7 5 5 5 5 5 5 ) 95 96:+ 3+$6( 9'59,1 & & 96(1 96(1 9,1 6*1' 9'' ) 3*1' 5 9,1 9WR9 9&& 95 9'59287 & ) (Note 5) 95 5$$ & 9 9''& 6&/ 6'$ 6$/57 & ) 9287 & & [) [) & 326&$3 5 [) [) 9287 9$ (Note 3) Notes: 2. R3 and R4 are not required if the PMBus host already has I2C pull-up resistors. 3. R2 is optional but recommended to sink possible ~100A back-flow current from the VSEN+ pin. Back-flow current is present only when the module is in a disabled state with power still available at the VDD pin. 4. R6 through R11 can be selected according to the tables for the pin-strap resistor setting in this document. 5. Internal reference supply pins (V25, VDDC, VR5, VR6) do not need external capacitors and can be no connect. Refer to "PCB Layout Guidelines" on page 30 for more information. Figure 3. Typical Single-Phase Application Circuit for 1.2V/33A Output Table 1. RAA210833 Design Guide Matrix and Output Voltage Response VIN (V) VOUT (V) Input Capacitors Output Capacitors ASCR ASCR Frequency Gain Residual (kHz) (Note 7) (Note 7) (Note 9) VOUT Dev Peak-to-Peak (mV) (Note 8) 5 0.7 3x22F Ceramic + 2x150F POS 12x100F Ceramic + 6x470F POS 350 100 296 75 5 0.7 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 6x470F POS 400 90 615 73 12 0.7 3x22F Ceramic + 2x150F POS 12x100F Ceramic + 6x470F POS 350 100 296 78 12 0.7 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 6x470F POS 500 90 615 72 5 0.8 3x22F Ceramic + 2x150F POS 12x100F Ceramic + 6x470F POS 350 100 296 74 5 0.8 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 6x470F POS 400 80 615 73 12 0.8 3x22F Ceramic + 2x150F POS 12x100F Ceramic + 6x470F POS 350 100 296 75 FN9348 Rev.1.00 Feb 8, 2019 Page 4 of 57 RAA210833 Table 1. RAA210833 Design Guide Matrix and Output Voltage Response (Continued) VIN (V) VOUT (V) Input Capacitors Output Capacitors ASCR ASCR Frequency Gain Residual (kHz) (Note 7) (Note 7) (Note 9) VOUT Dev Peak-to-Peak (mV) (Note 8) 12 0.8 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 6x470F POS 400 80 615 73 5 0.9 3x22F Ceramic + 2x150F POS 12x100F Ceramic + 5x470F POS 350 90 364 75 5 0.9 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 5x470F POS 300 70 615 84 12 0.9 3x22F Ceramic + 2x150F POS 12x100F Ceramic + 5x470F POS 350 80 364 85 12 0.9 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 5x470F POS 400 80 615 84 5 1 3x22F Ceramic + 2x150F POS 12x100F Ceramic + 4x470F POS 350 90 364 81 5 1 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 4x470F POS 350 80 615 89 12 1 3x22F Ceramic + 2x150F POS 12x100F Ceramic + 4x470F POS 350 90 364 85 12 1 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 4x470F POS 350 80 615 90 5 1.2 3x22F Ceramic + 2x150F POS 10x100F Ceramic + 4x470F POS 250 90 364 100 5 1.2 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 3x470F POS 300 80 727 103 12 1.2 3x22F Ceramic + 2x150F POS 10x100F Ceramic + 4x470F POS 250 90 364 110 12 1.2 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 3x470F POS 300 80 727 110 5 1.5 3x22F Ceramic + 2x150F POS 7x100F Ceramic + 2x470F POS 250 90 471 130 5 1.5 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 2x470F POS 350 90 727 125 12 1.5 3x22F Ceramic + 2x150F POS 7x100F Ceramic + 2x470F POS 250 90 471 147 12 1.5 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 2x470F POS 350 90 727 130 5 1.8 3x22F Ceramic + 2x150F POS 6x100F Ceramic + 2x470F POS 200 90 471 155 5 1.8 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 2x470F POS 210 80 727 155 12 1.8 3x22F Ceramic + 2x150F POS 6x100F Ceramic + 2x470F POS 200 90 471 160 12 1.8 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 2x470F POS 210 80 727 160 5 2.5 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 1x470F POS 190 100 615 215 12 2.5 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 1x470F POS 190 100 615 226 FN9348 Rev.1.00 Feb 8, 2019 Page 5 of 57 RAA210833 Table 1. RAA210833 Design Guide Matrix and Output Voltage Response (Continued) VIN (V) VOUT (V) Input Capacitors Output Capacitors ASCR ASCR Frequency Gain Residual (kHz) (Note 7) (Note 7) (Note 9) VOUT Dev Peak-to-Peak (mV) (Note 8) 12 3.3 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 1x470F POS 190 100 615 236 12 5 3x22F Ceramic + 2x150F POS 4x100F Ceramic + 1x470F POS 160 100 727 278 Notes: 6. CIN bulk capacitor is optional only for energy buffer from the long input power supply cable. 7. ASCR gain and residual are selected to ensure that the phase margin is higher than 60 at ambient room temperature (+25C). 8. Peak-to-peak voltage deviation is measured under 0% - 50% load transient and slew rate = 15A/s. 9. Frequency is selected to achieve best efficiency at full load. Higher frequency can be selected because less output capacitance is required to meet the transient response specification. Table 2. Recommended I/O Capacitor in Table 1 Vendors Value Part Number Murata, Input Ceramic 22F, 25V, 1210 GRM32ER71E226KE15L Taiyo Yuden, Input Ceramic 22F, 25V, 1210 TMK325BJ226MM-T Murata, Output Ceramic 100F, 6.3V, 1210 GRM32EC80J107ME20L TDK, Output Ceramic 100F, 6.3V, 1210 C3225X5R0J107M Sanyo POSCAP, Input Bulk 150F, 16V 16TQC150MYF Sanyo POSCAP, Output Bulk 470F, 6.3V 6TPE470MI FN9348 Rev.1.00 Feb 8, 2019 Page 6 of 57 RAA210833 OT/UT OC/UC ASCR SS/UVLO VSET OV/UV VIN LDO Power Management Interleave VIN SS EN PG CFG Regulator FB VDRVOUT VDRVIN VCC V25 VR5 VR55 VR6 VDD RAA210833 Internal Block Diagram VDDC 1.2 Snapshot PLL 0.24H VOUT Logic SYNC SYNC OUT PWM OUT D-PWM PGND NVM Supervisor Driver and FETs ChargeMode Control Protection CSA 332: ADC-10 VSEN+ VSA VSEN- ADC-10 VDD VDRVOUT SCL SDA SALRT 2 PMBus/I C Interface INTERNAL TEMP SENSOR SA SGND PGND SGND Digital Controller Figure 4. Internal Block Diagram FN9348 Rev.1.00 Feb 8, 2019 Page 7 of 57 RAA210833 1.3 Ordering Information Part Number (Notes 10, 11, 12) Part Marking Temp Range (C) Tape and Reel (Units) (Note 1) Package (RoHS Compliant) RAA2108332GLG#AG0 RAA2108332 -40 to +85 - RAA2108332GLG#HG0 RAA2108332 -40 to +85 500 41 Ld 17x19 HDA Y41.17x19 RAA2108332GLG#MG0 RAA2108332 -40 to +85 100 41 Ld 17x19 HDA Y41.17x19 RTKA2108332H00000BU Evaluation Board 41 Ld 17x19 HDA Pkg. Dwg. # Y41.17x19 Notes: 10. Refer to TB347 for details about reel specifications. 11. These Pb-free plastic packaged products are RoHS compliant by EU exemption 7C-I and 7A. They employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate-e4 termination finish, which is compatible with both SnPb and Pb-free soldering operations. Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 12. For Moisture Sensitivity Level (MSL), see the RAA210833 device page. For more information about MSL, see TB363. Table 3. Key Differences between Family of Parts Part Number Description VIN Range (V) VOUT Range (V) IOUT (A) RAA210833 33A DC/DC single channel Power Module 4.5 - 14 0.6 - 5 33 RAA210825 25A DC/DC single channel Power Module 4.5 - 14 0.6 - 5 25 RAA210850 50A DC/DC single channel Power Module 4.5 - 14 0.6 - 5 50 RAA210870 70A DC/DC single channel Power Module 4.5 - 14 0.6 - 2.5 70 RAA210925 25A/25A DC/DC dual channel Power Module 4.5 - 14 0.6 - 5 25/25 Table 4. Comparison of Simple Digital and Full Digital Parts ISL8278M RAA210833 VIN (V) 4.5 - 14 4.5 - 14 VOUT (V) 0.6 - 5 0.6 - 5 33 33 IOUT (Max) (A) fSW (kHz) Digital PMBus Programmablility for Configuration of Modules 296 - 1067 All PMBus commands, NVM access to store module configuration 296 - 1067 Configuration of modules supported by pin-strap resistors. Digital programmability supports configuration changes during run-time operation with a subset of PMBus commands. No NVM access to store module configuration Power Navigator Support Yes Yes SYNC Capability Yes Yes Current Sharing Multi-Modules No No DDC Pin (Inter-Device Communication) Yes No Note: For a full comparison of all the RAA210XXX and ISL827XM product offerings, visit the simple-digital module family page. FN9348 Rev.1.00 Feb 8, 2019 Page 8 of 57 RAA210833 1.4 Pin Configuration NC 5 VSEN+ 6 VSEN - 7 VDRVOUT 8 VDRVIN 99 SALRT SDA SCL EN VDD 26 25 24 23 22 21 20 19 18 17 16 28 PG SYNC 39 29 SS/UVLO 38 VDDC 4 27 V25 NC SA 3 NC NC PGND 2 CFG ASCR VSET 1 NC NC SGND 41 LD HDA Top View 37 40 SGND 15 VIN 11 VR6 10 35 VR55 34 PHASE VCC VR5 41 30 36 SGND PGND 33 NC 31 32 NC VOUT 14 PGND 1.5 VSWH 13 12 PGND Pin Descriptions Pin Number Label Type Description 2 ASCR I ChargeMode control ASCR parameters selection pin. Used to set ASCR gain and residual values. 6 VSEN+ I Differential output voltage sense feedback. Connect to the positive output regulation point. 7 VSEN- I Differential output voltage sense feedback. Connect to the negative output regulation point. 8 VDRVOUT PWR Output of internal regulator for powering internal MOSFET driver. Connect a 10F bypass capacitor to this pin. The regulator output is dedicated to powering internal MOSFET drivers. Do not use this regulator for any other purpose. For applications with VIN less than 5.2V, use an external 5V supply or connect this pad to VIN. 9 VDRVIN 10 VCC PWR Bias pin for internal regulator. Connect the VCC pad to the VR55 pin directly with a short loop trace. Not recommended to power external circuit. 11 VIN PWR Main input supply. Refer to "PCB Layout Guidelines" on page 30 for the decoupling capacitor's placement from VIN to PGND. FN9348 Rev.1.00 Feb 8, 2019 PWR Input supply to internal regulator for powering internal MOSFET drivers. Connect this pad to VIN. Page 9 of 57 RAA210833 Pin Number Label Type Description 12, 23, 31, 34 PGND PWR Power ground. Refer to "PCB Layout Guidelines" on page 30 for the PGND pad connections and decoupling capacitor's placement. 13 VSWH PWR Switch node. Refer to "PCB Layout Guidelines" on page 30 for connecting VSWH pads to electrically isolate the PCB copper island to dissipate internal heat. 14 VOUT PWR Power supply output. Range: 0.6V to 5V. Refer to "Derating Curves" on page 17 for maximum recommended output current at various output voltages. 15, 27, 40 SGND PWR Controller signal ground. Refer to "PCB Layout Guidelines" on page 30 for the SGND pad connections. 16 VDD PWR Input supply to digital controller. Connect the VDD pad to the VIN supply. 17 EN I 18 SCL I/O Serial clock input. A pull-up resistor is required for this application. 19 SDA I/O Serial data. A pull-up resistor is required for this application. 20 SALRT O Serial alert. A pull-up resistor is required for this application. 21 SA I Serial bus address select pin. Refer to Table 11 on page 25 for list of resistor values to set various serial bus address. 24 CFG I Clock source configuration. If the clock source is internal, set the internal FREQUENCY_SWITCH according to the SYNC pin resistor setting. If the clock source is external, the internal FREQUENCY_SWITCH is set according to CFG pin resistor. Refer to Table 8 on page 23 for more details. 25 VSET I Output voltage selection pin. Refer to Table 5 on page 19 for list of resistor values to set various output voltages. 28 PG O Power-good output. The power-good is configured as an open-drain output. 29 SS/UVLO I Soft-start/stop and undervoltage lockout selection pin. Used to set turn on/off delay and ramp time as well as input UVLO threshold levels. Refer to Table 6 on page 21 and Table 10 on page 24 for a list of resistors. 30 PHASE 35 VR6 PWR 6V internal reference supply voltage. 36 VR5 PWR 5V internal reference supply voltage. 37 VDDC 38 V25 39 SYNC 41 VR55 1, 3, 4, 5, 22, 26, 32, 33 NC FN9348 Rev.1.00 Feb 8, 2019 External enable input. Logic high enables the module. PWR Switch node pad for DCR sensing. Electrically shorted inside to VSWH, but for higher current sensing accuracy connect the PHASE pad to the VSWH pad externally. Refer to "PCB Layout Guidelines" on page 30. PWR VDD clean. Noise at the VDD pin is filtered by an internal ferrite bead and capacitor. For VDD > 6V, leave this pin as no connect. For 5.5 VDD 6V, connect the VDDC pin to the VR6 pin. For 4.5 VDD < 5.5V, connect the VDDC pin to VR6 and the VR5 pin. PWR 2.5V internal reference supply voltage. I/O Clock synchronization input. Sets the frequency of the internal switch clock, or synchronizes to an external clock. If using external synchronization, the external clock must be active before enable. Refer to Table 7 on page 22 for a list of resistor values to program various switching frequencies. PWR Internal 5.5V bias for internal regulator use only. Connect the VR55 pin directly to theVCC pin. Not recommended to power external circuit. These are test pins and are not electrically isolated. Leave these pins as no connect. Page 10 of 57 RAA210833 2. Specifications 2.1 Absolute Maximum Ratings Parameter Minimum Maximum Unit Input Supply Voltage, VIN Pin -0.3 +17 V Input Supply Voltage for Controller, VDD, VDDC Pin -0.3 +17 V Input Gate Driver Supply Voltage, VDRVIN Pin -0.3 +17 V Output Gate Driver Supply Voltage, VDRVOUT Pin -0.3 +6 V Output Voltage, VOUT Pin -0.3 +6 V Switch Node Referenced to PGND Pin, VSWH Pin -0.3 +25 V Switch Node for DCR Sensing Referenced to SGND Pin, PHASE Pin -0.3 +25 V Input Bias Voltage for Internal Regulator, VCC Pin -0.3 +6.5 V 6V Internal Reference Supply Voltage, VR6 Pin -0.3 +6.6 V Internal Reference Supply Voltage, VR5, VR55 Pin -0.3 +6.5 V 2.5V Internal Reference Supply Voltage, V25 Pin -0.3 +3 V Logic I/O Voltage for DDC, EN, CFG, PG, ASCR, SA, SCL, SDA, SALRT, SYNC, SS/UVLO, VSET -0.3 +6 V VSEN+, XTEMP+ -0.3 6 V VSEN-, XTEMP- -0.3 0.3 V Analog Input Voltages for ESD Rating Human Body Model (Tested per JS-001-2017) Value Unit 2 kV Machine Model (Tested per JESD22-A115C) 200 V Charged Device Model (Tested per JS-002-2014) 750 V Latch-Up (Tested per JESD78E; Class 2, Level A) 100 mA 2.2 Thermal Information Thermal Resistance (Typical) 41 Ld HDA Package (Notes 13, 14) JA (C/W) JC (C/W) 7.5 2.2 Notes: 13. JA is measured in free air with the module mounted on an 8-layer evaluation board 4.7x4.8inch in size with 2oz Cu on all layers and multiple via interconnects as specified in the RTKA2108332H00000BU evaluation board user guide. 14. For JC, the "case temp" location is the center of the package underside. Parameter Minimum Maximum Junction Temperature (Plastic Package) Storage Temperature Range Pb-Free Reflow Profile FN9348 Rev.1.00 Feb 8, 2019 -55 Maximum Unit +125 C +150 C Refer to Figure 29 on page 32 Page 11 of 57 RAA210833 2.3 Recommended Operating Conditions Minimum Maximum Unit Input Supply Voltage Range, VIN Parameter 4.5 14 V Input Supply Voltage Range for Controller, VDD 4.5 14 V Output Voltage Range, VOUT 0.6 5 V Output Current Range, IOUT(DC) (Note 17) 0 33 A Operating Junction Temperature Range, TJ -40 +125 C 2.4 Electrical Specifications VIN = VDD = 12V, fSW = 533kHz, COUT = 1340F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply across the operating temperature range, -40C to +85C. Parameter Symbol Test Conditions Min (Note 15) Typ Max (Note 15) Unit 40 50 mA 6.1 6.6 V Input and Supply Characteristics Input Supply Current for Controller IDD 6V Internal Reference Supply Voltage VR6 Internal Regulator Output Voltage VDRVOUT 5V Internal Reference Supply Voltage VR5 2.5V Internal Reference Supply Voltage V25 5.5V Internal Reference Supply Voltage VR55 Input Supply Voltage for Controller Read Back Resolution VDD_READ_RES Input Supply Voltage for Controller Read Back Total Error (Note 18) VDD_READ_ERR VIN = VDD = 12V, VOUT = 0V, module not enabled 5.5 VCC connected to VR55 IVR5 < 5mA 5.2 V 4.5 5.2 5.5 V 2.25 2.50 2.75 V VDD > 6V; 0A to 80mA PMBus read 5.7 V 20 mV 2 %FS Output Characteristics Output Voltage Adjustment Range VOUT_RANGE VIN > VOUT + 1.8V Output Voltage Set-Point Range VOUT_RES Configured using PMbus Output Voltage Set-Point Accuracy (Notes 16, 18) VOUT_ACCY Includes line, load, and temperature (-20C TA +85C) Output Voltage Readback Resolution VOUT_READ_RES Output Voltage Readback Total Error (Note 18) VOUT_READ_ERR Output Current Readback Resolution IOUT_READ_RES 0.54 5.5 0.025 -1.2 % +1.2 20 PMBus read -2 IOUT_RANGE Output Current Readback Total Error IOUT_READ_ERR PMBus read at max load at ambient room temperature tON_DELAY Configured using pin-strap resistor or PMBus %FS mV +2 10 Output Current Range (Note 17) V %FS Bits 33 3 A A Soft-Start and Sequencing Delay Time From Enable to VOUT Rise FN9348 Rev.1.00 Feb 8, 2019 2 300 ms Page 12 of 57 RAA210833 VIN = VDD = 12V, fSW = 533kHz, COUT = 1340F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply across the operating temperature range, -40C to +85C. (Continued) Parameter tON_DELAY Accuracy Symbol tON_RISE Output Voltage Ramp-Up Time Accuracy tON_RISE_ACCY tOFF_DELAY Accuracy Output Voltage Fall Time Output Voltage Fall Time Accuracy Min (Note 15) tON_DELAY_ACCY Output Voltage Ramp-Up Time Delay Time From Disable to VOUT Fall Test Conditions tOFF_DELAY Max (Note 15) Unit 120 ms 2 Configured using pin-strap resistor or PMBus 0.5 ms 250 Configured using pin-strap resistor or PMBus 2 tOFF_DELAY_ACCY tOFF_FALL Typ s 300 2 Configured using pin-strap resistor or PMBus 0.5 ms ms 120 ms tON_FALL_ACCY 250 s VPG_DELAY 4 ms Power-Good Power-Good Delay Temperature Sense Temperature Sense Range TSENSE_RANGE Configured using PMBus -50 150 C Internal Temperature Sensor Accuracy INT_TEMPACCY Tested at +100C -5 +5 C 4.18 16 V Fault Protection VDD Undervoltage Threshold Range VDD_UVLO_RANGE Measured internally VDD Undervoltage Threshold Accuracy (Note 18) VDD_UVLO_ACCY 2 %FS VDD Undervoltage Response Time VDD_UVLO_DELAY 10 s VOUT Overvoltage Threshold Range VOUT_OV_RANGE Factory default Configured using pin-strap resistor or PMBus VOUT Undervoltage Threshold Range VOUT_UV_RANGE Factory default Configured using pin-strap resistor or PMBus VOUT OV/UV Threshold Accuracy (Note 16) VOUT_OV/UV_ACCY VOUT OV/UV Response Time VOUT_OV/UV_DELAY Output Current Limit Set-Point Accuracy (Note 18) ILIMIT_ACCY Tested at IOUT_OC_FAULT_LIMIT = 40A Output Current Fault Response Time (Note 19) ILIMIT_DELAY TJUNCTION Over-Temperature Protection Threshold (Controller Junction Temperature) Thermal Protection Hysteresis 1.15 x VOUT % VOUT_MAX 1.05VOUT 0.85 x VOUT % % 0 0.95VOUT % -2 +2 % 10 s 10 %FS Factory default 3 tSW Factory default 115 C Configured using PMBus -40 125 15 TJUNCTION_HYS C C Oscillator and Switching Characteristics Switching Frequency Range Switching Frequency Set-Point Accuracy FN9348 Rev.1.00 Feb 8, 2019 fSW_RANGE fSW_ACCY Configured using pin-strap resistor or PMBus 296 1067 kHz -5 +5 % Page 13 of 57 RAA210833 VIN = VDD = 12V, fSW = 533kHz, COUT = 1340F, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C. Boldface limits apply across the operating temperature range, -40C to +85C. (Continued) Parameter Minimum Pulse Width Required from External SYNC Clock Symbol Min (Note 15) Typ Max (Note 15) Unit Measured at 50% amplitude 150 EXT_SYNCDRIFT External SYNC clock equal to 500kHz is not supported -10 +10 % Bias Current at the Logic Input Pins ILOGIC_BIAS EN, CFG, PG, SA, SCL, SDA, SALRT, SYNC, UVLO, VSET -100 +100 nA Logic Input Low Threshold Voltage VLOGIC_IN_LOW 0.8 V Logic Input High Threshold Voltage VLOGIC_IN_HIGH Drift Tolerance for External SYNC Clock EXT_SYNCPW Test Conditions ns Logic Input/Output Characteristics 2.0 Logic Output Low Threshold Voltage VLOGIC_OUT_LOW 2mA sinking Logic Output High Threshold Voltage VLOGIC_OUT_HIGH 2mA sourcing V 0.5 2.25 V V PMBus Interface Timing Characteristic PMBus Operating Frequency fSMB 100 400 kHz Notes: 15. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. 16. VOUT measured at the termination of the VSEN+ and VSEN- sense points. 17. The MAX load current is determined by the thermal "Derating Curves" on page 17. 18. "FS" stands for Full Scale of recommended maximum operation range. 19. "tSW" stands for time period of operation switching frequency. FN9348 Rev.1.00 Feb 8, 2019 Page 14 of 57 RAA210833 3. Typical Performance Curves 3.1 Efficiency Performance 100 100 95 95 90 90 Efficiency (KHz) Efficiency (%) Operating condition: TA = +25C, No air flow. COUT = 1340F. Typical values are used unless otherwise noted. 85 80 75 70 5Vout 1.8Vout 1Vout 65 3.3Vout 1.5Vout 0.9Vout 2.5Vout 1.2Vout 0.8Vout 85 80 75 70 65 60 3.3Vout 2.5Vout 1.8Vout 1.5Vout 1.2Vout 1Vout 0.9Vout 0.8Vout 0.7Vout 60 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 33 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 33 IOUT (A) IOUT (A) Figure 6. Efficiency vs Output Current at VIN = 5V and fSW = 364kHz for Various Output Voltages 95 95 90 90 Efficiency (%) Efficiency (%) Figure 5. Efficiency vs Output Current at VIN = 12V and fSW = 364kHz for Various Output Voltages 85 80 75 70 0.7Vout 1Vout 1.8Vout 5Vout 0.8Vout 1.2Vout 2.5Vout 0.9Vout 1.5Vout 3.3Vout 80 75 0.7Vout 1Vout 1.8Vout 0.8Vout 1.2Vout 2.5Vout 0.9Vout 1.5Vout 3.3Vout 70 Switching Frequency (kHz) Figure 7. Efficiency vs Switching Frequency at VIN = 12V and IOUT = 33A for Various Output Voltages FN9348 Rev.1.00 Feb 8, 2019 85 Switching Frequency (kHz) Figure 8. Efficiency vs Switching Frequency at VIN = 5V and IOUT = 33A for Various Output Voltages Page 15 of 57 RAA210833 3.2 Transient Response Performance Operating conditions: Step load = 0 to 16.5A, IOUT slew rate = 15A/s, TA = +25C, OLFM airflow. Typical values are used unless otherwise noted. VOUT (50mV/Div) VOUT (50mV/Div) ASCR Gain = 350 Residual = 90 ASCR Gain = 270 Residual = 90 IOUT (10A/Div) IOUT (10A/Div) 100s/Div 100s/Div Figure 9. 5VIN to 0.9VOUT, fSW = 364kHz, COUT = 12x100F Ceramic + 5x470F POSCAP Figure 10. 5VIN to 1.2VOUT, fSW = 364kHz, COUT = 10x100F Ceramic + 4x470F POSCAP VOUT (100mV/Div) VOUT (50mV/Div) ASCR Gain = 350 Residual = 80 ASCR Gain = 250 Residual = 90 IOUT (10A/Div) IOUT (10A/Div) 100s/Div Figure 11. 12VIN to 1VOUT, fSW = 615kHz, COUT = 4x100F Ceramic + 4x470F POSCAP VOUT (50mV/Div) Figure 12. 12VIN to 1.5VOUT, fSW = 471kHz, COUT = 7x100F Ceramic + 2x470F POSCAP VOUT (100mV/Div) ASCR Gain = 200 Residual = 100 ASCR Gain = 200 Residual = 90 IOUT (10A/Div) IOUT (10A/Div) 100s/Div Figure 13. 12VIN to 1.8VOUT, fSW = 471kHz, COUT = 6x100F Ceramic + 2x470F POSCAP FN9348 Rev.1.00 Feb 8, 2019 100s/Div 100s/Div Figure 14. 12VIN to 3.3VOUT, fSW = 615kHz, COUT = 4x100F Ceramic + 1x470F POSCAP Page 16 of 57 RAA210833 3.3 Derating Curves 35 35 30 30 Load Current (A) Load Current (A) All of the following curves were plotted at TJ = +120C 25 20 15 10 0 LFM 5 200 LFM 25 20 15 0 LFM 400 LFM 10 200 LFM 5 400 LFM 0 0 20 30 40 50 60 70 80 90 100 110 20 30 40 50 Temperature (C) 35 30 30 25 25 Load Current (A) Load Current (A) 35 20 15 10 5 80 90 100 110 20 15 10 200 LFM 0 LFM 5 400 LFM 0 200 LFM 400 LFM 0 20 30 40 50 60 70 80 90 100 110 20 30 40 50 Temperature (C) 60 70 80 90 100 110 100 110 Temperature (C) Figure 18. 12VIN to 1.2VOUT, 364kHz Figure 17. 5VIN to 1.2VOUT, 364kHz 35 35 30 30 25 Load Current (A) Load Current (A) 70 Figure 16. 12VIN to 1VOUT, 364kHz Figure 15. 5VIN to 1VOUT, 364kHz 0 LFM 60 Temperature (C) 20 15 10 0 LFM 5 25 20 15 10 200 LFM 0 LFM 5 400 LFM 200 LFM 400 LFM 0 0 20 30 40 50 60 70 80 90 Temperature (C) Figure 19. 5VIN to 1.8VOUT, 471kHz FN9348 Rev.1.00 Feb 8, 2019 100 110 20 30 40 50 60 70 80 90 Temperature (C) Figure 20. 12VIN to 1.8VOUT, 471kHz Page 17 of 57 RAA210833 35 35 30 30 Load Current (A) Load Current (A) All of the following curves were plotted at TJ = +120C (Continued) 25 20 15 10 0 LFM 5 25 20 15 10 200 LFM 0 LFM 5 400 LFM 400 LFM 0 200 LFM 0 20 30 40 50 60 70 80 90 100 110 20 30 40 50 Temperature (C) 35 30 30 25 25 Load Current (A) Load Current (A) 35 20 15 10 5 70 80 90 100 110 Figure 22. 12VIN to 2.5VOUT, 615kHz Figure 21. 5VIN to 2.5VOUT, 615kHz 0 LFM 60 Temperature (C) 20 15 10 200 LFM 0 LFM 5 400 LFM 200 LFM 400 LFM 0 0 20 30 40 50 60 70 80 90 100 110 20 30 40 Temperature (C) 50 60 70 80 90 100 110 Temperature (C) Figure 24. 12VIN to 3.3VOUT, 615kHz Figure 23. 5VIN to 3.3VOUT, 615kHz 35 Load Current (A) 30 25 20 15 10 0 LFM 5 200 LFM 400 LFM 0 20 30 40 50 60 70 80 90 100 110 Temperature (C) Figure 25. 12VIN to 5VOUT, 727kHz FN9348 Rev.1.00 Feb 8, 2019 Page 18 of 57 RAA210833 4. Functional Description 4.1 SMBus Communications The RAA210833 provides an SMBus digital interface that enables you to configure the module operation and monitor the input and output parameters. You can use the RAA210833 with any SMBus host device. In addition, the module is compatible with PMBus Power System Management Protocol Specification Parts I and II version 1.2. The RAA210833 accepts most standard PMBus commands. When controlling the device with PMBus commands, it is recommended that the enable pin be tied to SGND. The SMBus device address is the only parameter that must be set by external pins. 4.2 Output Voltage Selection The output voltage can be set to a voltage between 0.6V and 5V if the input voltage is higher than the output voltage by an amount sufficient to maintain regulation. The VSET pin sets the output voltage to any values between 0.6V and 5V as shown in Table 5. The RSET resistor is placed between the VSET pin and SGND. A standard 1% resistor is recommended. Table 5. Output Voltage Resistor Settings VOUT(V) VSET_GROUP (Set by SA Pin) RSET (k) 0.600 Group 0 10 0.650 Group 0 11 0.675 Group 0 12.1 0.690 Group 0 13.3 0.700 Group 0 14.7 0.710 Group 0 16.2 0.720 Group 0 17.8 0.730 Group 0 19.6 0.740 Group 0 21.5 0.750 Group 0 23.7 0.760 Group 0 26.1 0.770 Group 0 28.7 0.780 Group 0 31.6 0.790 Group 0 34.8 0.800 Group 0 38.3 0.810 Group 0 42.2 0.820 Group 0 46.4 0.830 Group 0 51.1 0.840 Group 0 56.2 0.850 Group 0 61.9 0.860 Group 0 68.1 0.870 Group 0 75 0.880 Group 0 82.5 0.890 Group 0 90.9 0.900 Group 0 100 0.910 Group 0 110 FN9348 Rev.1.00 Feb 8, 2019 Page 19 of 57 RAA210833 Table 5. Output Voltage Resistor Settings (Continued) VOUT(V) VSET_GROUP (Set by SA Pin) RSET (k) 0.920 Group 0 121 0.930 Group 0 133 0.940 Group 0 147 0.950 Group 0 162 0.960 Group 0 178 0.970 Group 0 Connect to SGND 0.980 Group 0 OPEN 0.990 Group 0 Connect to V25 1.000 Group 1 Connect to SGND 1.030 Group 1 10 1.050 Group 1 11 1.100 Group 1 12.1 1.120 Group 1 13.3 1.150 Group 1 14.7 1.200 Group 1 OPEN 1.250 Group 1 16.2 1.300 Group 1 17.8 1.350 Group 1 19.6 1.400 Group 1 21.5 1.500 Group 1 23.7 1.600 Group 1 26.1 1.650 Group 1 28.7 1.700 Group 1 31.6 1.800 Group 1 34.8 1.850 Group 1 38.3 1.900 Group 1 42.2 2.000 Group 1 46.4 2.100 Group 1 51.1 2.200 Group 1 56.2 2.300 Group 1 61.9 2.400 Group 1 68.1 2.500 Group 1 Connect to V25 2.600 Group 1 75 2.700 Group 1 82.5 2.800 Group 1 90.9 2.900 Group 1 100 3.000 Group 1 110 3.200 Group 1 121 3.300 Group 1 133 3.400 Group 1 147 3.600 Group 1 162 FN9348 Rev.1.00 Feb 8, 2019 Page 20 of 57 RAA210833 Table 5. Output Voltage Resistor Settings (Continued) VOUT(V) VSET_GROUP (Set by SA Pin) RSET (k) 5.000 Group 1 178 By default, VOUT_MAX is set 110% higher than VOUT by the pin-strap resistor, which can be changed to any value up to 5.5V with the PMBus Command VOUT_MAX. 4.3 Soft-Start Delay and Ramp Times The RAA210833 follows an internal start-up procedure after power is applied to the VDD pin. The module requires approximately 60ms to 70ms to check for specific values stored in its internal memory and programmed by pin-strap resistors. After this process is complete, the device is ready to accept commands through the PMBus interface and the module is ready to be enabled. If the module is to be synchronized to an external clock source, the clock frequency must be stable before asserting the EN pin. It may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. In addition, you may want to precisely set the time required for VOUT to ramp to its target value after the delay period has expired. These features can be used as part of an overall inrush current management strategy or to precisely control how fast a load IC is turned on. The RAA210833 gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. The soft-start delay period begins when the EN pin is asserted and ends when the delay time expires. The soft-start delay (TON_DELAY) and ramp-up time (TON_RISE) can be set to custom values with pin-strap resistors or PMBUS. When the delay time is set to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). When the soft-start ramp period is set to 0ms, the output ramps up as quickly as the output load capacitance and loop settings allow. It is generally recommended to set the soft-start ramp to a value greater than 500s to prevent inadvertent fault conditions due to excessive inrush current. Similar to the soft-start delay and ramp-up time, the delay (TOFF_DELAY) and ramp-down time (TOFF_FALL) for soft-stop/off can be set to custom values with pin-strap resistors or PMBUS. In addition, the module can be configured as "immediate off" with the command ON_OFF_CONFIG, so that the internal MOSFETs are turned off immediately after the delay time expires. Use the SS/UVLO pin to set the soft-start/stop delay time and ramp time to some typical values as shown in Table 6. A standard 1% resistor is required. Table 6. Soft-Start/Stop and Input UVLO Resistor Settings Resistor (k) UVLO (V) Delay Time (ms) Ramp Time (ms) Open 4.2 5 5 Connect to V25 4.5 10 10 Connect to SGND 4.5 5 2 12.1 4.5 5 2 13.3 4.5 5 5 14.7 4.5 5 10 16.2 4.5 10 2 17.8 4.5 10 5 19.6 4.5 10 10 21.5 4.5 20 5 23.7 4.5 20 10 26.1 4.2 5 2 28.7 4.59 5 5 31.6 5.06 5 10 FN9348 Rev.1.00 Feb 8, 2019 Page 21 of 57 RAA210833 Table 6. Soft-Start/Stop and Input UVLO Resistor Settings (Continued) 4.4 Resistor (k) UVLO (V) Delay Time (ms) Ramp Time (ms) 34.8 5.57 10 2 38.3 6.13 10 5 42.2 6.75 10 10 46.4 7.42 20 5 51.1 8.18 20 10 56.2 10.8 5 2 61.9 10.8 5 5 68.1 10.8 5 10 75 10.8 10 2 82.5 10.8 10 5 90.9 10.8 10 10 100 10.8 20 5 110 10.8 20 10 Power-Good The RAA210833 provides a Power-Good (PG) signal that indicates that the output voltage is within a specified tolerance of its target level and no fault condition exists. By default, the PG pin asserts if the output is within 10% of the target voltage. These limits and the polarity of the pin can be changed with PMBus command POWER_GOOD_ON. A PG delay period is defined as the time from when all conditions within the RAA210833 for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of using an external reset controller to control external digital logic. A fixed PG delay of 4ms is programmed for the RAA210833. 4.5 Switching Frequency and PLL Set the device's switching frequency from 296kHz to 1067kHz using the pin-strap method as shown in Table 7, or by using the PMBus command FREQUENCY_SWITCH. Table 7. Switching Frequency Resistor Settings fSW(kHz) RSET (k) 296 14.7, or connect to SGND 320 16.2 348 17.8 364 19.6 400 21.5 421 23.7 471 26.1 516 28.7 533 31.6, or OPEN 615 34.8 640 38.3 696 42.2 727 46.4 800 51.1 FN9348 Rev.1.00 Feb 8, 2019 Page 22 of 57 RAA210833 Table 7. Switching Frequency Resistor Settings (Continued) fSW(kHz) RSET (k) 842 56.2 889 61.9 1067 68.1,orconnecttoV25 The RAA210833 incorporates an internal Phase-Locked Loop (PLL) to clock the internal circuitry. The PLL can also be driven by an external clock source connected to the SYNC pin. Connect a resistor to the CFG pin to set this configuration. If the clock source is set to internal, the internal frequency is set according to the SYNC pin resistor settings. If the clock source is set to external, the internal frequency is set according to the resistor connected to the CFG pin as shown in Table 8. The external clock frequency should be within 10% of the listed options. Table 8. External Frequency SYNC Settings Clock Source Internal Frequency Switch (kHz) RSET (k) Internal Determined by SYNC resistor 10, or OPEN External 296 11 External 340 12.1 External 390 13.3 External 444 14.7 External 516 16.2, or connect to SGND External 593 17.8 External 696 19.6 External 800 21.5 External 941 23.7 External 1067 26.1, or Connect to V25 The external clock signal must not vary more than 10% from its initial value, should be stable, and should have a minimum pulse-width of 150ns. Note: if the pin-strap method is used, a standard 1% resistor is required. 4.6 Loop Compensation The module loop response is programmable using the pin-strap method or the PMBus command ASCR_CONFIG according to Table 9. A standard 1% resistor is required. The RAA210833 uses the ChargeMode control algorithm that responds to output current changes within a single PWM switching cycle, achieving a smaller total output voltage variation with less output capacitance than traditional PWM controllers. Table 9. ASCR Resistor Settings ASCR Gain ASCR Residual RSET (k) 190 60 10 200 60 11 90 65 12.1 80 70 13.3 120 70 Connect to SGND 160 70 14.7 200 70 OPEN 250 70 16.2 300 70 17.8 FN9348 Rev.1.00 Feb 8, 2019 Page 23 of 57 RAA210833 Table 9. ASCR Resistor Settings (Continued) ASCR Gain ASCR Residual RSET (k) 120 80 19.6 190 80 21.5 210 80 23.7 250 80 26.1 300 80 28.7 350 80 31.6 400 80 34.8 110 90 38.3 160 90 42.2 200 90 46.4 250 90 51.1 350 90 56.2 400 90 61.9 500 90 68.1 600 90 75 300 95 82.5 120 100 90.9 160 100 100 190 100 110 220 100 121 250 100 Connect to V25 350 100 133 400 100 147 500 100 162 600 100 178 4.7 Input Undervoltage Lockout (UVLO) The Input Undervoltage Lockout (UVLO) prevents the RAA210833 from operating when the input falls below a preset threshold, indicating that the input supply is out of its specified range. The UVLO threshold (VUVLO) can be set between 4.18V and 16V or by using the pin-strap method as shown in Table 10, or by using the PMBus command VIN_UV_FAULT_LIMIT. A standard 1% resistor is required. The module shuts down immediately when the UVLO threshold is reached. The fault needs to be cleared for the module to restart. Table 10. UVLO Resistor Settings FN9348 Rev.1.00 Feb 8, 2019 UVLO (V) Resistor (k) 4.2 Open 4.5 Connect to V25 4.5 Connect to SGND 4.5 12.1 4.5 13.3 4.5 14.7 Page 24 of 57 RAA210833 Table 10. UVLO Resistor Settings (Continued) 4.8 UVLO (V) Resistor (k) 4.5 16.2 4.5 17.8 4.5 19.6 4.5 21.5 4.5 23.7 4.2 26.1 4.59 28.7 5.06 31.6 5.57 34.8 6.13 38.3 6.75 42.2 7.42 46.4 8.18 51.1 10.8 56.2 10.8 61.9 10.8 68.1 10.8 75 10.8 82.5 10.8 90.9 10.8 100 10.8 110 SMBus Module Address Selection Each module must have its own unique serial address to distinguish between other devices on the bus. The module address is set by connecting a resistor between the SA pin and SGND. This pin can also be used to make VSET_Group selection as shown in Table 11. A standard 1% resistor is required. Table 11. SMBus Address Resistor Selection RSET (k) SMBus Address VSET_GROUP 10 19h Group 0 11 1Ah Group 0 12.1 1Bh Group 0 13.3 1Ch Group 0 14.7 1Dh Group 0 16.2 1Eh Group 0 17.8 1Fh Group 0 19.6 20h Group 0 21.5 21h Group 0 23.7 22h Group 0 26.1 23h Group 0 28.7 24h Group 0 31.6 25h Group 0 FN9348 Rev.1.00 Feb 8, 2019 Page 25 of 57 RAA210833 Table 11. SMBus Address Resistor Selection (Continued) RSET (k) SMBus Address VSET_GROUP 34.8 26h Group 0 38.3 27h Group 0 42.2 28h Group 0 46.4 29h Group 0 51.1 19h Group 1 56.2 1Ah Group 1 61.9 1Bh Group 1 68.1 1Ch Group 1 75 1Dh Group 1 82.5 1Eh Group 1 90.9 1Fh Group 1 100 20h Group 1 110 21h Group 1 121 22h Group 1 133 23h Group 1 147 24h Group 1 162 25h Group 1 Connect to SGND 26h Group 1 178 27h Group 1 OPEN 28h Group 1 4.9 Output Overvoltage Protection The RAA210833 offers an internal output overvoltage protection circuit that can be used to protect sensitive load circuitry from being subjected to a voltage higher than its prescribed limits. A hardware comparator is used to compare the actual output voltage (seen at the VSEN+ and VSEN- pins) to a threshold set to 15% higher than the target output voltage (the default setting). Fault threshold can be programmed to a desired level with PMBus command VOUT_OV_FAULT_LIMIT. If the VSEN+ voltage exceeds this threshold, the module initiates an immediate shutdown without retry. Internal to the module, a 332 resistor is populated from VOUT to VSEN+ to protect from overvoltage conditions in case of open at VSENSE pin and differential remote sense traces due to assembly error. As long as the differential remote sense traces have low resistance, VOUT regulation accuracy is not sacrificed. 4.10 Output Prebias Protection An output prebias condition exists when an externally applied voltage is present on a power supply's output before the power supply's control IC is enabled. Certain applications require that the converter not be allowed to sink current during start-up if a prebias condition exists at the output. The RAA210833 provides prebias protection by sampling the output voltage before initiating an output ramp. If a prebias voltage lower than the target voltage exists after the preconfigured delay period has expired, the target voltage is set to match the existing prebias voltage, and both drivers are enabled. The output voltage is then ramped to the final regulation value at the preconfigured ramp rate. The actual time the output takes to ramp from the prebias voltage to the target voltage varies depending on the prebias voltage. However, the total time elapsed from when the delay period expires and when the output reaches its target value matches the preconfigured ramp time (see Figure 26 on page 27). FN9348 Rev.1.00 Feb 8, 2019 Page 26 of 57 RAA210833 If the prebias voltage is higher than the target voltage after the preconfigured delay period expires, the target voltage is set to match the existing prebias voltage, and both drivers are enabled with a PWM duty cycle that would ideally creates the prebias voltage. After the preconfigured soft-start ramp period expires, the PG pin is asserted (assuming the prebias voltage is not higher than the overvoltage limit). The PWM then adjusts its duty cycle to match the original target voltage and the output ramps down to the preconfigured output voltage. If a prebias voltage is higher than the overvoltage limit, the device does not initiate a turn-on sequence and declares an overvoltage fault condition. VOUT Desired Output Voltage Prebias Voltage Time Ton-Delay Ton-Rise VPREBIAS < VTARGET VOUT Prebias Voltage Desired Output Voltage Time Ton-Delay Ton-Rise VPREBIAS > VTARGET Figure 26. Output Responses to Prebias Voltages 4.11 Output Overcurrent Protection The RAA210833 can protect the power supply from damage if the output is shorted to ground or if an overload condition is imposed on the output. The average output overcurrent fault threshold can be programmed with the PMBus command IOUT_OC_FAULT_LIMIT. The module automatically programs the peak inductor current fault threshold by reading the real-time input voltage, switching frequency, and VOUT_COMMAND to calculate inductor ripple current. The default response from an overcurrent fault is an immediate shutdown with a continuous retry of 70ms delay. FN9348 Rev.1.00 Feb 8, 2019 Page 27 of 57 RAA210833 4.12 Thermal Overload Protection The RAA210833 includes a thermal sensor that continuously measures the internal temperature of the module and shuts down the controller when the temperature exceeds the preset limit. The default temperature limit is set to +115C in the factory, but can be changed with PMBus command OT_FAULT_LIMIT. The response from an over-temperature fault is an immediate shutdown without retry. 4.13 Phase Spreading When multiple point-of-load converters share a common DC input supply, adjust the clock phase offset of each device, so that not all devices start to switch simultaneously. Setting each converter to start its switching cycle at a different point in time can dramatically reduce input capacitance requirements and efficiency losses. Because the peak current drawn from the input supply is effectively spread out over a period of time, the peak current drawn at any given moment is reduced and the power losses proportional to the IRMS2 are reduced dramatically. To enable phase spreading, all converters must be synchronized to the same switching clock. The phase offset between devices is determined from the lower four bits of the SMBus address of each interleaved device.The phase offset of each device can be set to any value between 0 and 360 in 22.5 increments by setting the device address appropriately as shown in Table 12. This functionality can also be accessed using the PMBus command INTERLEAVE. Table 12. INTERLEAVE Settings from SA INTERLEAVE vs SA SA 4.14 SA in Binary Low 4-Bits INTERLEAVE Phase Shift () 19h 00011001 1001 9 202.5 1Ah 00011010 1010 10 225 1Bh 00011011 1011 11 247.5 1Ch 00011100 1100 12 270 1Dh 00011101 1101 13 292.5 1Eh 00011110 1110 14 315 1Fh 00011111 1111 15 337.5 20h 00100000 0000 0 0 21h 00100001 0001 1 22.5 22h 00100010 0010 2 45 23h 00100011 0011 3 67.5 24h 00100100 0100 4 90 25h 00100101 0101 5 112.5 26h 00100110 0110 6 135 27h 00100111 0111 7 157.5 28h 00101000 1000 8 180 29h 00101001 1001 9 202.5 Monitoring Through SMBus A system controller can monitor a wide variety of different RAA210833 system parameters with PMBus commands: * READ_VIN * READ_VOUT * READ_IOUT FN9348 Rev.1.00 Feb 8, 2019 Page 28 of 57 RAA210833 * READ_INTERNAL_TEMP * READ_DUTY_CYCLE * READ_FREQUENCY * MFR_READ_VMON 4.15 Snapshot Parameter Capture The RAA210833 offers a special feature to capture parametric data and some fault status following a fault. A detailed description is provided in "PMBus Commands Description" on page 36 under PMBus command SNAPSHOT and SNAPSHOT_CONTROL. FN9348 Rev.1.00 Feb 8, 2019 Page 29 of 57 RAA210833 5. PCB Layout Guidelines To achieve stable operation, low losses, and good thermal performance, some layout considerations are necessary. * For VDD > 6V, the recommended PCB layout is shown in Figure 27. Leave V25, VDDC, VR5, and VR6 as "No Connect". * For 5.5V VDD 6V, connect VDDC pin to VR6 pin. For 4.5 VDD < 5.5V, connect VDDC pin to VR6 and VR5 pin. An RC filter is required at the input of VDRVIN pin if input supply is shared with VIN pin. * Establish a separate SGND plane and PGND plane, then connect SGND to the PGND plane as shown in Figure 28 in the middle layer. For making connections between SGND/PGND on the top layer and other layers, use multiple vias for each pin to connect to the inner SGND/PGND layer. Do not connect SGND directly to PGND on a top layer. Connecting SGND directly to PGND without establishing an SGND plane bypasses the decoupling capacitor at internal reference supplies, making the controller susceptible to noise. * Place enough ceramic capacitors between VIN and PGND, and VOUT and PGND. Place bypass capacitors between VDD and the ground plane, as close to the module as possible to minimize high frequency noise. * Use large copper areas for the power path (VIN, PGND, VOUT) to minimize conduction loss and thermal stress. Use multiple vias to connect the power planes in different layers. Extra ceramic capacitors at VIN and VOUT can be placed on the bottom layer under the VIN and VOUT pads when multiple vias are used for connecting copper pads on top and bottom layers. * Connect differential remote-sensing traces to the regulation point to achieve a tight output voltage regulation. Route a trace from VSEN- and VSEN+ to the point-of-load where the tight output voltage is desired. Avoid routing any sensitive signal traces such as the VSENSE signal near VSWH pads. SGND SGND VR6 PHASE SGND SGND VR5 VR55 VDRVIN C A B C SGND VDDC SGND VDRVOUT C R UVLO VR25 C VDD SYNC PG Connect SGND to PGND in the Middle Layer CVDD NC ASCR NC NC NC VSEN+ VSEN - PGND SGND NC VSET CFG PGND NC SA SALRT SDA SCL EN SGND * For noise sensitive applications, it is recommended that the user connect the VSWH pads only on the top layer only (however, thermal performance gets sacrificed). External airflow might be required to keep module heat at desired level. For applications where switching noise is less critical, an excellent thermal performance can be achieved in the RAA210833 module by increasing copper mass attached to VSWH pad. To increase copper mass on the VSWH node, create copper islands in the middle and bottom layers under the VSWH pad, and connect them to the top layer with multiple vias. Make sure to shield the copper islands with a PGND layer to avoid any interference from noise sensitive signals. PGND PGND VCC NC PGND PGND PGND VSWH PGND CVIN VOUT NC VIN PGND CVOUT Figure 27. Recommended Layout - Top PCB Layer FN9348 Rev.1.00 Feb 8, 2019 Figure 28. Recommended Layout - Connect SGND to PGND in the Middle PCB Layer after Establishing Separate SGND and PGND Page 30 of 57 RAA210833 5.1 Thermal Considerations Experimental power loss curves, along with JA from thermal modeling analysis, can be used to evaluate the thermal consideration for the module. The derating curves are derived from the maximum power allowed while maintaining the temperature below the maximum junction temperature of +125C. In actual applications, other heat sources and design margins should be considered. 5.2 Package Description The structure of the RAA210833 belongs to the High Density Array (HDA) no-lead package. This package has advantages, such as good thermal and electrical conductivity, low weight, and small size. The HDA package is applicable for surface mounting technology and is being more readily used in the industry. The RAA210833 contains several types of devices, including resistors, capacitors, inductors, and control ICs. The RAA210833 is a copper leadframe based package with exposed copper thermal pads, which have good electrical and thermal conductivity. The copper leadframe and multi-component assembly is overmolded with polymer mold compound to protect these devices. The package outline, a typical PCB land pattern design, and a typical stencil opening edge position are shown in the Package Outline Drawing section starting on page 50. The module has a small size of 17mmx19mmx3.6mm. Figure 29 shows typical reflow profile parameters. These guidelines are general design rules. You can modify parameters according to your application. 5.3 PCB Layout Pattern Design The bottom of the RAA210833 is a lead-frame footprint, that is attached to the PCB by a surface mounting process. The PCB land pattern is shown in the "Package Outline Drawing" section starting on page page 50. The PCB layout pattern is an array of solder mask defined PCB lands that align with the perimeters of the HDA exposed pads and I/O termination dimensions. The thermal lands on the PCB layout also feature an array of solder mask defined lands and should match 1:1 with the package exposed die pad perimeters. The exposed solder mask defined PCB land area should be 50-80% of the available module I/O area. 5.4 Thermal Vias A grid of 1.0mm to 1.2mm pitch thermal vias, which drops down and connects to buried copper plane(s), should be placed under the thermal land. The vias should be about 0.3mm to 0.33mm in diameter with the barrel plated to about 1.0 ounce copper. Although adding more vias (by decreasing via pitch) improves the thermal performance, diminishing returns are seen as more and more vias are added. Use as many vias as practical for the thermal land size and that your board design rules allow. 5.5 Stencil Pattern Design Reflowed solder joints on the perimeter I/O lands should have about a 50m to 75m (2mil to 3mil) standoff height. The solder paste stencil design is the first step in developing optimized, reliable solder joints. The stencil aperture size to solder mask defined PCB land size ratio should typically be 1:1. The aperture width can be reduced slightly to help prevent solder bridging between adjacent I/O lands. A typical solder stencil pattern is shown in the "Package Outline Drawing" section starting on page page 50. Consider the symmetry of the whole stencil pattern when designing its pads. A laser cut, stainless steel stencil with electropolished trapezoidal walls is recommended. Electropolishing "smooths" the aperture walls resulting in reduced surface friction and better paste release, which reduces voids. Using a Trapezoidal Section Aperture (TSA) also promotes paste release and forms a "brick like" paste deposit that assists in firm component placement. A 0.1mm to 0.15mm stencil thickness is recommended for this large pitch (1.3mm) HDA. FN9348 Rev.1.00 Feb 8, 2019 Page 31 of 57 RAA210833 5.6 Reflow Parameters Due to the low mount height of the HDA, a "No Clean" Type 3 solder paste per ANSI/J-STD-005 is recommended. Nitrogen purge is also recommended during reflow. A system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the HDA. The profile given in Figure 29 is provided as a guideline to be customized for varying manufacturing practices and applications. 300 Peak Temperature ~+245C; Typically 60s-150s Above +217C Keep Less Than 30s within 5C of Peak Temperature Temperature (C) 250 200 Slow Ramp (3C/s Maximum) and Soak From +150C to +200C for 60s~180s 150 100 Ramp Rate 1.5C from +70C to +90C 50 0 0 100 150 200 250 300 350 Duration (s) Figure 29. Typical Reflow Profile FN9348 Rev.1.00 Feb 8, 2019 Page 32 of 57 RAA210833 6. PMBus Command Summary Command Code Command Name Description Type Data Format Default Value Default Setting Page 01h OPERATION Sets Enable and Disable modes. R/W Byte BIT 02h ON_OFF_CONFIG Configures the EN pin and PMBus commands to turn the unit ON and OFF. R/W Byte BIT 03h CLEAR_FAULTS Clears fault indications. SEND Byte 21h VOUT_COMMAND Sets the nominal value of the output voltage. R/W Word L16u Pin-strap 37 24h VOUT_MAX Sets the maximum possible value of VOUT. 110% of pin-strap VOUT. R/W Word L16u 1.1 x VOUT Pin-strap 37 33h FREQUENCY_SWITCH Sets the switching frequency. R/W Word L11 Pin-strap 37 37h INTERLEAVE Configures a phase offset between devices sharing a SYNC clock. R/W Word BIT Set based on PMBus Address 38 40h VOUT_OV_FAULT_LIMIT Sets the VOUT overvoltage fault threshold. R/W Word L16u 1.15 x VOUT Pin-strap 38 44h VOUT_UV_FAULT_LIMIT Sets the VOUT undervoltage fault threshold. R/W Word L16u 0.85 x VOUT Pin-strap 38 46h IOUT_OC_FAULT_LIMIT Sets the IOUT average overcurrent fault threshold. R/W Word L11 E280h 40A 38 4Bh IOUT_UC_FAULT_LIMIT Sets the IOUT average undercurrent fault threshold. R/W Word L11 E57Fh -40A 39 4Fh OT_FAULT_LIMIT Sets the over-temperature fault threshold. R/W Word L11 EB98h +115C 39 53h UT_FAULT_LIMIT Sets the under-temperature fault threshold. R/W Word L11 E530h -45C 39 55h VIN_OV_FAULT_LIMIT Sets the VIN overvoltage fault threshold. R/W Word L11 D3A0h 14.5V 39 59h VIN_UV_FAULT_LIMIT Sets the VIN undervoltage fault threshold. R/W Word L11 Pin-strap 40 5Eh POWER_GOOD_ON Sets the voltage threshold for Power-Good indication. R/W Word L16u 0.9 x VOUT Pin-strap 40 60h TON_DELAY Sets the delay time from ENABLE to start of VOUT rise. R/W Word L11 Pin-strap 40 61h TON_RISE Sets the rise time of VOUT after ENABLE and TON_DELAY. R/W Word L11 Pin-strap 40 64h TOFF_DELAY Sets the delay time from DISABLE to start of VOUT fall. R/W Word L11 Pin-strap 41 65h TOFF_FALL Sets the fall time for VOUT after DISABLE and TOFF_DELAY. R/W Word L11 Pin-strap 41 78h STATUS_BYTE Returns an abbreviated status for fast reads. Read Byte BIT 00h No Faults 41 79h STATUS_WORD Returns information with a summary of the units's fault condition. Read Word BIT 0000h No Faults 42 FN9348 Rev.1.00 Feb 8, 2019 36 16h Hardware Enable, soft-off 36 36 Page 33 of 57 RAA210833 Command Code Command Name Description Type Data Format Default Value Default Setting Page 7Ah STATUS_VOUT Returns the VOUT specific status. Read Byte BIT 00h No Faults 42 7Bh STATUS_IOUT Returns the IOUT specific status. Read Byte BIT 00h No Faults 43 7Ch STATUS_INPUT Returns status specific to the input. Read Byte BIT 00h No Faults 43 7Dh STATUS_TEMPERATURE Returns the temperature specific status. Read Byte BIT 00h No Faults 43 7Eh STATUS_CML Read Byte BIT 00h No Faults 44 80h STATUS_MFR_SPECIFIC Returns the VMON and External Sync clock specific status. Read Byte BIT 00h No Faults 44 88h READ_VIN Returns the input voltage reading. Read Word L11 44 8Bh READ_VOUT Returns the output voltage reading. Read Word L16u 45 8Ch READ_IOUT Returns the output current reading. Read Word L11 45 8Dh READ_INTERNAL_TEMP Returns the temperature reading internal to the device. Read Word L11 45 94h READ_DUTY_CYCLE Returns the duty cycle reading during the ENABLE state. Read Word L11 45 95h READ_FREQUENCY Returns the measured operating switch frequency. Read Word L11 45 DFh ASCR_CONFIG Configures the ASCR control loop. R/W Block CUS Pin-strap 46 E4h DEVICE_ID Returns the 16-byte (character) device identifier string. Read Block ASCII Reads Device Version 46 E5h MFR_IOUT_OC_FAULT_ RESPONSE Configures the IOUT overcurrent fault response. R/W Byte BIT B9h Disable and Retry with 70ms delay 46 E6h MFR_IOUT_UC_FAULT_ RESPONSE Configures the IOUT undercurrent fault response. R/W Byte BIT B9h Disable and Retry with 70ms delay 47 EAh SNAPSHOT Returns 32-byte read-back of parametric and status values. Read Block BIT 47 F3h SNAPSHOT_CONTROL Snapshot feature control command. R/W Byte BIT 48 F5h MFR_VMON_OV_FAULT_ Returns the VMON overvoltage LIMIT threshold. Read Word L11 CB00h 6V 48 F6h MFR_VMON_UV_FAULT_ Returns the VMON undervoltage LIMIT threshold. Read Word L11 CA00h 4V 48 F7h MFR_READ_VMON Read Word L11 FN9348 Rev.1.00 Feb 8, 2019 Returns the Communication, Logic, and Memory specific status. Returns the VMON voltage reading. VMON is used to monitor VDRVOUT (Pin 8) voltage through an internal 16:1 resistor divider. 48 Page 34 of 57 RAA210833 6.1 PMBus Data Formats * Linear-11 (L11) - The L11 data format uses a 5-bit two's complement exponent (N) and 11-bit two's complement mantissa (Y) to represent a real world decimal value (X). The relation between the real world decimal value (X), N, and Y is: X = Y * 2N Data Byte High 7 6 5 4 3 2 1 0 Exponent (N) Data Byte Low 7 6 5 4 3 2 1 0 Mantissa (Y) * Linear-16 Unsigned (L16u) - The L16u data format uses a fixed exponent (hard-coded to N = -13h) and a 16-bit unsigned integer mantissa (Y) to represent the real world decimal value (X). The relation between the real world decimal value (X), N and Y is: X = Y * 2-13 * Linear-16 Signed (L16s) - The L16s data format uses a fixed exponent (hardcoded to N = -13h) and a 16-bit two's complement mantissa (Y) to represent the real world decimal value (X). The relation between the real world decimal value (X), N, and Y is: X = Y * 2-13 * Bit Field (BIT) - An explanation of the Bit Field format is provided in PMBus on "PMBus Commands Description" on page 36. * Custom (CUS) - An explanation of the custom data format is provided in PMBus "PMBus Commands Description" on page 36. A combination of Bit Field and integer are common type of Custom data format. * ASCII (ASC) - A variable length string of text characters that uses the ASCII data format. 6.2 PMBus Use Guidelines The PMBus is a powerful tool that allows you to optimize circuit performance by configuring devices for your application. When configuring a device in a circuit, the device should be disabled whenever most settings are changed with PMBus commands. Some exceptions to this recommendation are OPERATION, ON_OFF_CONFIG, CLEAR_FAULTS, VOUT_COMMAND, and ASCR_CONFIG. While the device is enabled any command can be read. Many commands do not take effect until after the device has been re-enabled, hence the recommendation that commands that change device settings are written while the device is disabled. In addition, there should be a 2ms delay between repeated READ commands sent to the same device. When sending any other command, a 5ms delay is recommended between repeated commands sent to the same device. Commands not listed in the PMBus command summary are not allowed for customer use, and are reserved for factory use only. Issuing reserved commands may result in unexpected operation. FN9348 Rev.1.00 Feb 8, 2019 Page 35 of 57 RAA210833 7. PMBus Commands Description OPERATION (01h) Definition: Sets Enable and Disable settings. Data Length in Bytes: 1 Data Format: BIT Type: R/W Default Value: 40h Units: N/A Settings 00h Actions Immediate off 40h Soft off 80h On. ON_OFF_CONFIG (02h) Definition: Configures the interpretation and coordination of the OPERATION command and the ENABLE pin (EN). Data Length in Bytes: 1 Data Format: BIT Type: R/W Default Value: 16h (Device starts from ENABLE pin with soft off) Units: N/A Settings Actions 16h Device starts from ENABLE pin with soft off 17h Device starts from ENABLE pin with immediate off 1Ah Device starts from OPERATION command with soft off 1Bh Device starts from OPERATION command with immediate off CLEAR_FAULTS (03h) Definition: Clears all fault bits in all registers and releases the SALRT pin (if asserted) simultaneously. If a fault condition still exists, the bit reasserts immediately. This command does not restart a device if it has shut down, it only clears the faults. Data Length in Bytes: 0 Byte Data Format: N/A Type: Send only Default Value: N/A Units: N/A Reference: N/A FN9348 Rev.1.00 Feb 8, 2019 Page 36 of 57 RAA210833 VOUT_COMMAND (21h) Definition: Sets or reports the target output voltage. This command cannot set a value higher than either VOUT_MAX or 110% of the pin-strap VOUT setting. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: Pin-strap setting Units: Volts Range: 0V to VOUT_MAX VOUT_MAX (24h) Definition: Sets an upper limit on the output voltage the unit can command regardless of any other commands or combinations. This command provides a safeguard against a user accidentally setting the output voltage to a possibly destructive level rather than to be the primary output overprotection. The default value can be changed through PMBus. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: 1.10 x VOUT pin-strap setting Units: Volts Range: 0V to 5.5V FREQUENCY_SWITCH (33h) Definition: Sets the switching frequency of the device. The initial default value is defined by a pin-strap and this value can be overridden by writing this command through PMBus. If an external SYNC is used, this value should be set as close as possible to the external clock value. The output must be disabled when writing this command. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: kHz Range: 296kHz to 1067kHz FN9348 Rev.1.00 Feb 8, 2019 Page 37 of 57 RAA210833 INTERLEAVE (37h) Definition: Configures the phase offset of a device that is sharing a common SYNC clock with other devices. The phase offset of each device can be set to any value between 0 and 360 in 22.5 increments. Data Length in Bytes: 2 Data Format: BIT Type: R/W Default Value: Pin-strap setting of SA Units: kHz Bits Purpose Value 0 Description 15:8 Reserved Reserved 7:4 Group Number 0 to 15 Sets the number of rails in the group. A value of 0 is interpreted as 16. 3:0 Position in Group 0 to 15 Sets position of the device's rail within the group. VOUT_OV_FAULT_LIMIT (40h) Definition: Sets the VOUT overvoltage fault threshold. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: 1.15 x VOUT pin-strap setting Units: V Range: 0V to VOUT_MAX VOUT_UV_FAULT_LIMIT (44h) Definition: Sets the VOUT undervoltage fault threshold. This fault is masked during ramp or when disabled. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: 0.85 x VOUT pin-strap setting Units: V Range: 0V to VOUT_MAX IOUT_OC_FAULT_LIMIT (46h) Definition: Sets the IOUT average overcurrent fault threshold. The device automatically calculates the peak inductor overcurrent fault limit. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: E280h (40A) Units: A Range: -100A to 100A FN9348 Rev.1.00 Feb 8, 2019 Page 38 of 57 RAA210833 IOUT_UC_FAULT_LIMIT (4Bh) Definition: Sets the IOUT average undercurrent fault threshold. The device automatically calculates the valley inductor undercurrent fault limit. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: E57Fh (-40A) Units: A Range: -100A to 100A OT_FAULT_LIMIT (4Fh) Definition: Sets the temperature at which the device should indicate an over-temperature fault. Note that the temperature must drop below OT_FAULT_LIMIT to clear this fault. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: EB98h (+115C) Units: Celsius Range: 0C to +150C UT_FAULT_LIMIT (53h) Definition: Sets the temperature, in degrees Celsius, of the unit where it should indicate an under-temperature fault. Note that the temperature must rise above UT_FAULT_LIMIT to clear this fault. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: E530h (-45C) Units: Celsius Range: -55C to +25C VIN_OV_FAULT_LIMIT (55h) Definition: Sets the VIN overvoltage fault threshold. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: D3A0h (14.5V) Units: V Range: 0V to 16V FN9348 Rev.1.00 Feb 8, 2019 Page 39 of 57 RAA210833 VIN_UV_FAULT_LIMIT (59h) Definition: Sets the VIN undervoltage fault threshold. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: V Range: 0V to 12V POWER_GOOD_ON (5Eh) Definition: Sets the voltage threshold for Power-good indication. Power-good asserts after the output voltage exceeds POWER_GOOD_ON and deasserts when the output voltage is less than the VOUT_UV_FAULT_LIMIT. Renesas recommends setting POWER_GOOD_ON higher than the VOUT_UV_FAULT_LIMIT. Data Length in Bytes: 2 Data Format: L16u Type: R/W Default Value: 0.9 x VOUT pin-strap setting Units: V TON_DELAY (60h) Definition: Sets the delay time from when the device is enabled to the start of VOUT rise. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: ms Range: 2ms to 300ms TON_RISE (61h) Definition: Sets the rise time of VOUT after ENABLE and TON_DELAY. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: ms Range: 1ms to 120ms FN9348 Rev.1.00 Feb 8, 2019 Page 40 of 57 RAA210833 TOFF_DELAY (64h) Definition: Sets the delay time from DISABLE to the start of VOUT fall. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: ms Range: 2ms to 300ms TOFF_FALL (65h) Definition: Sets the fall time for VOUT after DISABLE and TOFF_DELAY. Data Length in Bytes: 2 Data Format: L11 Type: R/W Default Value: Pin-strap setting Units: ms Range: 0ms to 120ms STATUS_BYTE (78h) Definition: Returns one byte of information with a summary of the most critical faults. Data Length in Bytes: 1 Data Format: BIT Type: Read only Default Value: 00h Units: N/A Bit Number Status Bit Name Meaning 7 BUSY A fault was declared because the device was busy and unable to respond. 6 OFF This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 VOUT_OV_FAULT An output overvoltage fault occurred. 4 IOUT_OC_FAULT An output overcurrent fault occurred. 3 VIN_UV_FAULT An input undervoltage fault occurred. 2 TEMPERATURE A temperature fault occurred. 1 CML A communications, memory, or logic fault occurred. 0 NONE OF THE ABOVE A fault not listed in Bits 7:1 occurred. FN9348 Rev.1.00 Feb 8, 2019 Page 41 of 57 RAA210833 STATUS_WORD (79h) Definition: Returns two bytes of information with a summary of the unit's fault condition. Based on the information in these bytes, the host can get more information by reading the appropriate status registers. The low byte of the STATUS_WORD is the same register as the STATUS_BYTE (78h) command. Data Length in Bytes: 2 Data Format: BIT Type: Read only Default Value: 0000h Units: N/A Bit Number Status Bit Name Meaning 15 VOUT An output voltage fault has occurred. 14 IOUT/POUT An output current or output power fault occurred. 13 INPUT An input voltage, input current, or input power fault occurred. 12 MFG_SPECIFIC A manufacturer specific fault occurred. 11 POWER_GOOD# The POWER_GOOD signal, if present, is negated. 10 Reserved Reserved 9 OTHER A bit in STATUS_OTHER is set. 8 UNKNOWN A fault type not given in Bits 15:1 of the STATUS_WORD detected. 7 BUSY A fault was declared because the device was busy and unable to respond. 6 OFF This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. 5 VOUT_OV_FAULT An output overvoltage fault occurred. 4 IOUT_OC_FAULT An output overcurrent fault occurred. 3 VIN_UV_FAULT An input undervoltage fault occurred. 2 TEMPERATURE A temperature fault occurred. 1 CML A communications, memory, or logic fault occurred. 0 NONE OF THE ABOVE A fault not listed in Bits 7:1 occurred. STATUS_VOUT (7Ah) Definition: Returns one data byte with the status of the output voltage. Data Length in Bytes: 1 Data Format: BIT Type: Read only Default Value: 00h Units: N/A BIT NUMBER 7 6:5 4 3:0 FN9348 Rev.1.00 Feb 8, 2019 STATUS BIT NAME MEANING VOUT_OV_FAULT Indicates an output overvoltage fault. Reserved Reserved VOUT_UV_FAULT Indicates an output undervoltage fault. N/A These bits are not used. Page 42 of 57 RAA210833 STATUS_IOUT (7Bh) Definition: Returns one data byte with the status of the output current. Data Length in Bytes: 1 Data Format: BIT Type: Read only Default Value: 00h Units: N/A Bit Number 7 6:5 4 3:0 Status Bit Name Meaning IOUT_OC_FAULT An output overcurrent fault has occurred. Reserved Reserved IOUT_UC_FAULT An output undercurrent fault has occurred. N/A Not used. STATUS_INPUT (7Ch) Definition: Returns input voltage and input current status information. Data Length in Bytes: 1 Data Format: BIT Type: Read only Default Value: 00h Units: N/A Bit Number 7 6:5 4 3:0 Status Bit Name Meaning VIN_OV_FAULT An input overvoltage fault has occurred. Reserved Reserved VIN_UV_FAULT An input undervoltage fault has occurred. N/A Not used. STATUS_TEMPERATURE (7Dh) Definition: Returns one byte of information with a summary of any temperature related faults. Data Length in Bytes: 1 Data Format: BIT Type: Read only Default Value: 00h Units: N/A Bit Number 7 6:5 4 3:0 FN9348 Rev.1.00 Feb 8, 2019 Status Bit Name Meaning OT_FAULT An over-temperature fault has occurred. Reserved Reserved UT_FAULT An under-temperature fault has occurred. N/A These bits are not used. Page 43 of 57 RAA210833 STATUS_CML (7Eh) Definition: Returns one byte of information with a summary of any Communications, Logic, and/or Memory errors. Data Length in Bytes: 1 Data Format: BIT Type: Read only Default Value: 00h Units: N/A Bit Number Meaning 7 Invalid or unsupported PMBus command was received. 6 The PMBus command was sent with invalid or unsupported data. 5 Packet error was detected in the PMBus command. 4 Memory/logic fault has occurred. 3:2 Reserved 1 A PMBus command tried to write to a read only or protected command, or a communication fault other than the ones listed in this table has occurred. 0 Not used STATUS_MFR_SPECIFIC (80h) Definition: Returns one byte of information providing the status of the device's voltage monitoring and clock synchronization faults. Data Length in Bytes: 1 Data Format: BIT Type: Read only Default Value: 00h Units: N/A Bit Number 7:4 Field Name Meaning Reserved Reserved 3 External Switching Period Fault Loss of external clock synchronization occurred. 2 Reserved Reserved 1 VMON UV Fault The voltage on the VMON pin dropped below the level set by VMON_UV_FAULT. 0 VMON OV Fault The voltage on the VMON pin rose above the level set by VMON_OV_FAULT. READ_VIN (88h) Definition: Returns the input voltage reading. Data Length in Bytes: 2 Data Format: L11 Type: Read only Units: V FN9348 Rev.1.00 Feb 8, 2019 Page 44 of 57 RAA210833 READ_VOUT (8Bh) Definition: Returns the output voltage reading. Data Length in Bytes: 2 Data Format: L16u Type: Read only Units: V READ_IOUT (8Ch) Definition: Returns the output current reading. Data Length in Bytes: 2 Data Format: L11 Type: Read only Default Value: N/A Units: A READ_INTERNAL_TEMP (8Dh) Definition: Returns the controller junction temperature reading from the internal temperature sensor. Data Length in Bytes: 2 Data Format: L11 Type: Read only Units: C READ_DUTY_CYCLE (94h) Definition: Reports the actual duty cycle of the converter during the enable state. Data Length in Bytes: 2 Data Format: L11 Type: Read only Units: % READ_FREQUENCY (95h) Definition: Reports the actual switching frequency of the converter during the enable state. Data Length in Bytes: 2 Data Format: L11 Type: Read only Units: kHz FN9348 Rev.1.00 Feb 8, 2019 Page 45 of 57 RAA210833 ASCR_CONFIG (DFh) Definition: Allows you to configure the ASCR settings. ASCR gain is analogous to bandwidth and ASCR residual is analogous to damping. To improve load transient response performance, increase ASCR gain. To decrease transient response overshoot, increase ASCR residual. Increasing ASCR gain can result in increased PWM jitter and should be evaluated in the application circuit. Excessive ASCR gain can lead to excessive output voltage ripple. Increasing ASCR residual to improve transient response damping can result in slower recovery times, but does not affect the peak output voltage deviation. Data Length in Bytes: 4 Data Format: CUS Type: R/W Default Value: Pin-strap setting Bit Purpose 31:25 Not Used 24 Reserved Data Format Value 0000000h Description Not used Reserved 23:16 ASCR Residual Setting Integer 15:0 ASCR Gain Setting Integer DEVICE_ID (E4h) Definition: Returns the 16-byte (character) device identifier string. Data Length in Bytes: 16 Data Format: ASCII Type: Block Read Default Value: Part number/Die revision/Firmware revision MFR_IOUT_OC_FAULT_RESPONSE (E5h) Definition: Configures the IOUT overcurrent fault response as defined by the following table. The command format is the same as the PMBus standard fault responses except that it sets the overcurrent status bit in STATUS_IOUT. Data Length in Bytes: 1 Data Format: BIT Type: R/W Default Value: B9h (Disable and continuous retry with 70ms delay) Units: N/A Settings Actions 80h Disable with no retry. B9h Disable and continuous retry with 70ms delay. FN9348 Rev.1.00 Feb 8, 2019 Page 46 of 57 RAA210833 MFR_IOUT_UC_FAULT_RESPONSE (E6h) Definition: Configures the IOUT undercurrent fault response as defined by the following table. The command format is the same as the PMBus standard fault responses except that it sets the undercurrent status bit in STATUS_IOUT. Data Length in Bytes: 1 Data Format: BIT Type: R/W Default Value: B9h (Disable and continuous retry with 70ms delay) Units: N/A Settings Actions 80h Disable with no retry. B9h Disable and continuous retry with 70ms delay. SNAPSHOT (EAh) Definition: A 32-byte readback of parametric and status values. It allows monitoring and status data to be stored to flash following a fault condition. In case of a fault, the most recently updated values are stored to the flash memory. When SNAPSHOT STATUS Byte 22 is set stored, the device will no longer automatically captures parametric and status values following a fault until stored data are erased. Use the SNAPSHOT_CONTROL command to erase stored data and clear the status bit before the next ramp up. Data erased are not allowed when the module is enabled. Data Length in Bytes: 32 Data Format: Bit field Type: Block Read Byte Number 31:23 Value Pmbus Command Format Reserved Reserved 00h 22 Flash Memory Status Byte FF - Not Stored 00 - Stored NVM Status Byte Bit 21 Manufacturer Specific Status Byte STATUS_MFR_SPECIFIC (80h) Byte 20 CML Status Byte STATUS_CML (7Eh) Byte 19 Temperature Status Byte STATUS_TEMPERATURE (7Dh) Byte 18 Input Status Byte STATUS_INPUT (7Ch) Byte 17 IOUT Status Byte STATUS_IOUT (7Bh) Byte 16 VOUT Status Byte STATUS_VOUT (7Ah) Byte 15:14 Switching Frequency READ_FREQUENCY (95h) L11 13:12 Reserved Reserved 11:10 Internal Temperature READ_INTERNAL_TEMP (8Dh) L11 Duty Cycle READ_DUTY_CYCLE (94h) L11 7:6 Reserved Reserved L11 5:4 Output Current READ_IOUT (8Ch) L11 3:2 Output Voltage READ_VOUT (8Bh) L16u 1:0 Input Voltage READ_VIN (88h) 9:8 FN9348 Rev.1.00 Feb 8, 2019 L11 Page 47 of 57 RAA210833 SNAPSHOT_CONTROL (F3h) Definition: Writing a 01h causes the device to copy the current Snapshot values from NVRAM to the 32-byte Snapshot command parameter. Writing a 02h causes the device to write the current Snapshot values to NVRAM. Writing a 03h erases all Snapshot values from NVRAM. Write (02h) and Erase (03h) can only be used when the device is disabled. All other values are ignored. Data Length in Bytes: 1 Data Format: Bit field Type: R/W byte Value Description 01h Read Snapshot values from NVRAM. 02h Write Snapshot values to NVRAM. 03h Erase Snapshot values stored in NVRAM. MFR_VMON_OV_FAULT_LIMIT (F5h) Definition: Reads the VMON OV fault threshold. Data Length in Bytes: 2 Data Format: L11 Type: Read only Default Value: CB00h (6V) Units: V Range: 4V to 6V MFR_VMON_UV_FAULT_LIMIT (F6h) Definition: Reads the VMON UV fault threshold. Data Length in Bytes: 2 Data Format: L11 Type: Read only Default Value: CA00h (4V) Units: V Range: 4V to 6V MFR_READ_VMON (F7h) Definition: Reads the VMON voltage. Data Length in Bytes: 2 Data Format: L11 Type: Read only Default Value: N/A Units: V Range: 4V to 6V FN9348 Rev.1.00 Feb 8, 2019 Page 48 of 57 RAA210833 8. Revision History 8.1 Firmware Firmware Revision Code RAA210833--G0100 8.2 Change Description Note Initial release Datasheet Rev. Date 1.00 Feb 8, 2019 0.00 Aug 31, 2018 FN9348 Rev.1.00 Feb 8, 2019 Description Updated the description for PG pin 28 on page 10. Updated 80h action under OPERATION (01h) command on page 36. Initial release Page 49 of 57 RAA210833 9. Package Outline Drawing For the most recent package outline drawing, see Y41.17x19. Y41.17x19 41 I/O 17.0mm x 19.0mmx3.6mm HDA Module Rev 1, 5/16 PIN 1 INDICATOR DATUM A A 17.00 BSC SEE DETAIL A B 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L TERMINAL #A1 INDEX AREA 9.00 18.50 0.15 0.10 M C A B 0.475 19.00 BSC 2.975 1.300 1.350 0.10 C 2X P R T U V W DATUM B 12.00 0.30 REF 0.30 REF 0.10 C 2X M N 0.20 REF 16.50 0.15 0.10 M C A B TOP VIEW BOTTOM VIEW 2 1.00 BSC 0.20 REF 3.6 0.1 // 0.10 C 0.08 C C 0.20 REF SEATING PLANE 0.025 MAX SIDE VIEW 3 21 x 0.60 0.05 3 21 x 0.60 0.05 0.10 M C A B 1.00 BSC 0.05 M C 2 TERMINAL TIP DETAIL A NOTES: 1. All dimensions are in millimeters. 2. Represents the basic land grid pitch. 3. The total number of I/O (excluding dummy pads). 4. Unless otherwise specified, tolerance: decimal 0.10. 5. Dimensioning and tolerancing per ASME Y14.M-2009. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. FN9348 Rev.1.00 Feb 8, 2019 Page 50 of 57 RAA210833 0.60 2.50 5.10 2X 1.60 0.60 2X 0.60 1.50 1.60 5.10 7.60 1.00 0.60 4X 1.60 4X 0.80 0.80 1.40 1.00 1.30 0.60 2.00 1.50 0.60 2.00 0.60 0.60 4.90 2.70 1.50 8.20 8.20 3.00 1.50 1.80 2.00 3.05 3.50 0.70 3.00 0.70 5.80 4.80 10.00 SIZE DETAILS FOR THE 16 EXPOSED DAPS BOTTOM VIEW FN9348 Rev.1.00 Feb 8, 2019 Page 51 of 57 RAA210833 0.60 2.50 5.10 2X 1.60 0.60 2X 0.60 1.50 1.60 5.10 7.60 1.00 0.60 4X 1.60 0.80 1.40 1.00 0.60 2.00 4X 0.80 1.30 1.50 0.60 2.00 0.60 0.60 4.90 2.70 1.50 1.50 3.00 8.20 8.20 1.80 2.00 3.05 0.70 3.00 3.50 0.70 4.80 5.80 10.00 SIZE DETAILS FOR THE 16 EXPOSED DAPS TOP VIEW FN9348 Rev.1.00 Feb 8, 2019 Page 52 of 57 6.700 6.850 7.050 8.200 8.500 5.300 5.700 2.300 2.700 3.300 3.700 4.300 4.700 0.700 0.775 1.300 1.700 0.175 0.300 0.700 0.300 1.300 2.300 1.700 2.700 9.300 8.700 3.300 8.500 8.300 7.700 9.500 6.700 6.300 5.700 5.300 4.700 4.300 3.700 0.00 RAA210833 8.300 7.700 9.500 7.300 9.300 8.700 8.300 7.700 6.700 6.300 5.700 7.300 5.300 4.700 4.300 5.550 5.350 3.700 3.600 3.400 3.300 2.700 1.650 1.450 0.044 0.000 0.400 0.556 1.000 1.400 2.000 2.675 0.600 0.000 0.300 1.000 2.900 3.100 3.275 4.025 5.000 5.200 5.900 7.100 4.625 7.300 7.450 7.650 9.200 8.500 8.200 6.350 6.550 4.700 3.000 1.600 1.400 1.600 1.400 1.000 0.200 0.000 2.800 2.700 4.400 3.500 3.000 5.100 4.900 5.400 5.350 5.550 6.300 9.500 8.300 7.600 7.400 8.500 5.900 6.150 7.575 7.775 7.900 8.500 9.200 9.500 RECOMMENDED SOLDER MASK DEFINED PCB LAND PATTERN (1) TOP VIEW FN9348 Rev.1.00 Feb 8, 2019 Page 53 of 57 6.000 5.200 2.200 0.433 0.633 0.000 1.133 1.333 2.550 2.900 6.800 7.300 RAA210833 7.100 6.750 5.533 5.333 7.300 3.767 5.300 5.700 3.700 3.567 3.300 1.700 2.300 2.000 1.700 1.100 0.900 0.300 1.300 0.000 0.000 0.300 0.900 2.500 3.500 3.700 0.000 2.900 4.700 5.300 6.300 6.900 6.700 5.200 RECOMMENDED SOLDER MASK DEFINED PCB LAND PATTERN (2) TOP VIEW FN9348 Rev.1.00 Feb 8, 2019 Page 54 of 57 8.180 8.500 6.740 6.830 7.070 5.280 5.720 1.715 1.285 0.715 0.285 0.000 0.190 0.285 0.715 0.760 1.285 1.715 2.285 2.715 3.285 3.715 4.285 4.720 3.285 2.715 2.285 5.715 5.285 4.285 4.715 3.715 6.285 6.720 7.715 8.500 8.280 RAA210833 9.500 9.280 8.720 8.280 7.720 7.285 9.500 8.720 8.285 7.720 6.715 6.285 7.260 5.715 5.285 5.590 5.310 4.715 4.285 3.715 3.285 3.640 3.360 2.715 1.690 0.000 0.980 1.420 1.410 0.585 0.024 0.015 0.000 0.260 0.420 0.536 1.040 1.980 2.860 3.140 4.960 5.240 5.940 6.180 7.060 7.545 7.805 7.340 7.860 8.530 9.170 9.500 8.500 8.160 6.590 6.310 4.740 2.960 1.640 1.360 0.000 0.040 1.420 2.680 6.960 6.320 5.580 5.380 5.320 5.140 4.860 4.420 3.530 3.040 8.500 8.280 8.270 7.630 7.370 9.160 RECOMMENDED STENCIL PATTERN (90% PASTE TO PAD) (1) TOP VIEW FN9348 Rev.1.00 Feb 8, 2019 Page 55 of 57 7.060 5.970 5.230 2.160 0.673 0.393 1.093 1.373 2.533 2.860 6.330 7.270 6.830 7.730 8.270 RAA210833 7.270 6.733 5.730 5.573 5.293 5.270 3.807 3.730 3.527 2.270 2.040 1.730 1.070 3.270 1.730 1.270 0.930 0.000 0.270 0.270 0.870 2.530 2.690 3.260 3.470 3.740 4.040 4.610 5.160 5.930 7.420 7.680 1.585 1.370 1.015 0.230 1.630 4.660 2.940 2.770 5.340 6.660 6.330 6.940 8.260 9.170 RECOMMENDED STENCIL PATTERN (90% PASTE TO PAD) (2) TOP VIEW FN9348 Rev.1.00 Feb 8, 2019 Page 56 of 57 1RWLFH 'HVFULSWLRQVRIFLUFXLWVVRIWZDUHDQGRWKHUUHODWHGLQIRUPDWLRQLQWKLVGRFXPHQWDUHSURYLGHGRQO\WRLOOXVWUDWHWKHRSHUDWLRQRIVHPLFRQGXFWRUSURGXFWV DQGDSSOLFDWLRQH[DPSOHV<RXDUHIXOO\UHVSRQVLEOHIRUWKHLQFRUSRUDWLRQRUDQ\RWKHUXVHRIWKHFLUFXLWVVRIWZDUHDQGLQIRUPDWLRQLQWKHGHVLJQRI\RXU SURGXFWRUV\VWHP5HQHVDV(OHFWURQLFVGLVFODLPVDQ\DQGDOOOLDELOLW\IRUDQ\ORVVHVDQGGDPDJHVLQFXUUHGE\\RXRUWKLUGSDUWLHVDULVLQJIURPWKHXVHRI WKHVHFLUFXLWVVRIWZDUHRULQIRUPDWLRQ 5HQHVDV(OHFWURQLFVKHUHE\H[SUHVVO\GLVFODLPVDQ\ZDUUDQWLHVDJDLQVWDQGOLDELOLW\IRULQIULQJHPHQWRUDQ\RWKHUFODLPVLQYROYLQJSDWHQWVFRS\ULJKWVRU RWKHULQWHOOHFWXDOSURSHUW\ULJKWVRIWKLUGSDUWLHVE\RUDULVLQJIURPWKHXVHRI5HQHVDV(OHFWURQLFVSURGXFWVRUWHFKQLFDOLQIRUPDWLRQGHVFULEHGLQWKLV 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