128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 3.3V I/O, Burst Counter == Pipelined Outputs IDT71V3556S/XS IDT71V3558S/XS IDT71V3556SA/XSA IDT71V3558SA/XSA Features * 128K x 36, 256K x 18 memory configurations * Supports high performance system speed - 200 MHz (x18) (3.2 ns Clock-to-Data Access) * Supports high performance system speed - 166 MHz (x36) (3.5 ns Clock-to-Data Access) * ZBT Feature - No dead cycles between write and read cycles * Internally synchronized output buffer enable eliminates the need to control OE * Single RAV (READ/WRITE) control pin + Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications Description TheiDT71V3556/58are3 3V high-speed 4,718,592-bit (4.5 Mega- bit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBT, or Zero Bus Turnaround. Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write The IDT71V3556/58 contain data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outpuis at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V3556/58 * 4-word burst capability (interleaved or linear) to be suspended as long as necessary All synchronous inputs are * Individual byte write (BW1 - BW4) control (May tie active) ignored when (CEN) is high and the internal device registers wilt hold * Three chip enables for simple depth expansion their previous values _ _ * 3.3V power supply (25%), 3.3V /O Supply (Vopa) There are three chip enable pins (CE1, CE2, CE2) that allow the * Optional- Boundary Scan JTAG Interface (IEEE 1149.1 user to deselect the device when desired ifany one of these three are compliant) not asserted when ADV/LD is low, no new memery operation can be * Packaged in a JEDEC standard 100-pin plastic thin quad initiated However, any pending data transfers (reads or writes) will be flatpack (TQFP), 179 ball grid array (BGA) and 165 fine pitch | completed. The data bus will tri-state two cycles after chip is dese- ball grid array (fBGA)} | @ c i e d Pin Description Summary Ao-Ai7 Address Inputs Input Synchronous CEt, CE2, CE Chip Enables Input Synchronous OE Output Enable Input Asynchronous RW Read/Write Signat Input Synchronous CEN Clock Enable Input Synchronous BWi, Bite, Bs, BW: Individual Byte Write Selecis Input Synchronous CLK Clock Input NA ADV/LD Advance burst address / Load new address Input Synchronous LBO Linear / Intedeaved Burst Order Input Static TMS Tesi Mode Select Input Synchronous TDI Test Data Input Input Synchronous TCK Test Clock Input NA TDO Test Data Output Output Synchronous TRST JTAG Reset (Optional) Input Asynchronous Zz Sleep Mode Input Synchronous Go-O31, YOp1-/0Ps Data Input / Output O Synchronous Vop, Vora Core Power, /O Power Supply Static Vss Ground Supply Static 5281 (bl oF 2008 Integrated Device Technology. Inc All rights reserved Product specifications subject ta change without notice AUGUST 2008 OSC-S5281/10IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V /O, Burst Counter, and Pipelined Outputs Description continued of a write is initiated. The ID71V3556/58 has an on-chip burst counter. In the burst mode, the IDT713556/58 can provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the LBO input pin. The LBO pin selects between linear and Pin Definition Commercial and Industrial Temperature Ranges interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH) The iDT71V3556/58 SRAMs utilize IDT's Jatest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100-pin thin plastic quad flatpack (TQFP} as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). Symbol Pin Function V0 Active Description AgAt? Address Inputs NYA Synchronous Address inputs The address register is triggered by a combination of the rising edge of CLK, ADV/LD low, CEN low, and true chip enables. ADV/LD Advance / Load NYA ADVILD is a synchronous input thal is used to load the intemal registers wih new address and control when it is sampied low at the rising edge of clock with the chip selected When ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is sampied high then the intemal burst counter is advanced for any burst that was in progress The extemal addresses are ignored when ADV/LD is sampled high. Read / Write NIA F/W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access to the memory array. The dala bus activity jor the current cycle takes place two clock cycles later. ao mi = Clock Enable LOW Synchronous Ciock Enable Input, When CEN is sampled high, all other synchronous inputs, including clock are ignored and outputs remain unchanged The effect of CEN sampled high on the device outputs is as if the low to high clock transition did not occur For nomal operation, CEN must be sampled low at rising edge of clock. BWreBWas Individual Byte Write Enables LOW Synchronous byte write enables Each 9-bit byte has iis own active fow byte write enable On ioad write cycles (When RAW and ADV/D are sampled low) the appropriate byte write signal (BWi-BWa) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when AYW is sampled high The appropriate byte(s) of data are written into the device two cycles later BW:-BW can all be tied low if aways doing write to the entire 36-bit word. a a ral Mm Chip Enables LOW Synchronous active low chip enable. CE: and CEz are used with CE2to enable the IDT71va5se/58. (CE: or CE sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect cycle The ZBT has a two cycle deselect, Le., the data bus will ti-state two clock cycles after deselect is initiated. CE Chip Enable HIGH Synehronous active high chip enable CE2 is used with CE: and CE to enable the chip CE2 has inverted polarity but othenvise identical to CE1 and CE. CLK Clock NA This is the clock input to the IDT?#V3556/58 Except for GE, all liming references forthe device are made wih tespect to ihe nsing edge of CLK, Oo-O3+ VOpi-VOr4 Data InpufOutput vO NYA Synchronous data inpufoutput (YO} pins Both the data input path and data output palh are registered and triggered by the rising edge of CLK. [BO Linear Burst Order LOW Burst order selection input When 1B0 is high the interleaved burst sequence is selected When [BO is low the Linear burst sequence is selected. LBO is static input and it must not change during device operation. Output Enable LOW Asynchronous output enable OE must be low to read data from the 71355658, When OE is high the VO pins are in a high-impedance state OE does not need to he actively controlled for read and write cycles. In normal operation, OE can be tied low. TMS Test Mode Select NIA Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an intemal pullup. Tl Test Data Input NIA Serial input of registers placed between TDland TDO Sampied on tising edge of TCK. This pin has an intemal pullup. TCK Test Clock NA Clock input of TAP contoller Each TAP event is clocked. Test inputs are captured on rising edge of TCK while test outputs are driven fiom the falling edge of TCK. This pin has an intemal pullup. Test Data Output NIA Serial culput of registers placed between TDi and TDO. This output is active depending on the state of the TAP controller. | x 4 JTAG Reset (Optional) LOW Optional Asynchronous JTAG reset Can be used to reset the TAP contoifer, but not required. JTAG reset occurs automalically al power up and also resets using TMS and TCK per IEEE 1149.1 {not used TRST can be je# floating. This pin has an intemal pullup. Only available in BGA package. Sleep Mede HIGH Synchronous sleep mode input. ZZ HIGH will gate the CLK intemally and power down the IDT71V3556/3558 to its lowest power consumption level Data retention is guaranteed in Sleep Mode. This pin has an intemal pulldown. Power Supply NA NIA 3.3V care power supply. Power Supply NA NWA 3.3V YO Supply. Vss Ground NA NIA Ground. NOTE: 1. All synchronous inpuis must meet specified setup and hold timas with respect fo CLK BG HeIDF71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with 2BT Feature, 3.3V /O, Burst Counter, and Pipelined Outputs Functional Block Diagram LBO Address A [0:16] CEI, CE2, CE2 RW CEN ADV/LD BWx Clock TMS TDI TCK {optronal) Commercial and Industrial Temperature Ranges al 128Kx36 BIT MEMORY ARRAY D Qtr +) Address r _ DB QC -) Control _ 5 SP DI BO 15 Ly 5 am D oO; Control Logic Gik 7 Sel D mo Output Register ' |_| | Gate | y 5281 drw 01a | Data I/O [0:31], e| TAG VO Pf: (SA Version) TDO v0 [ 4] |IDT?1V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V i/O, Burst Counter, and Pipelined Outputs Functional Block Diagram LBO Address A [0:17] CE1, CE2, CE2 Clock *"] 256x18 BIT MEMORY ARRAY DB QRreo| w| Address |} D Q =! Control _ 5 | & DI DO 2 A rc a i mD Oo i Control Logic Clik A y Y Mux Sal j DB Oo Output Register 1 | Gate a | y 5281 drw Ofb > Data VO [0:15], | JAG | TOO HO P[1:2] (SA Version) Recommended DC Operating Conditions Symbol Parameter Min. Typ. Max, Unit Vop Core Supply Voliage 3.135 3.3 3.465 v Vooa | O Supply Voltage 3.136 33 3.465 Vv Vss | Supply Voltage a 0 0 V Ve Input High Voltage ~ Inputs 2.0 _ Vop +0.3 V Vin | Input High Voltage - VO 20 | Vona40.3 ] Vv Vi. } Input Low Voltage og | 0.8 V NOTES: ee 1 Vic {min ) =1.0 for pulse width less than teve/2, once per cycle 2 Vin {max ) = +6 OV for pulse width less than teyc/2, once per cycle Commercial and Industrial Temperature RangesIDT?71V3556, IDT71V3558, 128K x 36, 256K x.18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V /O, Burst Counter, and Pipelined Outputs Recommended Operating Temperature and Supply Voltage Grade Temperature Vss Voo Yooa Commercial OPC to +70C ov 345% | 33V+5% Industral AOE to +85C ov 3.3V+5% | 33V+5% NOTES: $281 bl 1 Tais the "Instant on case temperature. Pin Configuration - 128K x 36 Commercial and Industrial Temperature Ranges Ig - at i@eis > sag 228 ABBE 8 8S2Gwood 2 2 HOOP ARDODOOWOOnA DAA 99 98 97 96 95 94 93 92 91 50 89 88 6 86 85 B4 83 BP 81 = eo o vOp3L_]1 O 80 [J VOp2 vOrsL_]2 79 [J /01s VoiI-]3 7a {1 Ora VooeL_]4 77 {_] Vove vssE_]5 78 Vss VOrwL_Is 75 LJ ora vOisl_}7 74 |] vOu12 /O2oL_] 8 73 [J yon O21] 9 72] O10 VssL_J 190 7t 1 Vss VooeL_]11 701] Vobe /Qee_] 12 69 LJ] vo0 VOe3 J 13 68 [_] Os Voom [_} 14 a7 (_] vss Voo[_] 15 66 (_] Voptt: Voom] 16 65 L_] vop VesL_] 17 64 |] Yseyz7t3) Ce4L_4 18 a3 J yor 1/O25E] 19 62 [_} 1/08 Vopal_]e2o 61 [1] vopa vssC_jat 60 Vss VO2g 7] 22 59 L_] Os O27] 23 58 |_] 1/04 VOzeL_] 24 57 [_] |/Os /Oz9[_] 25 56 F 1/02 VssI_] 26 35(_] veg VopaL_]27 84 [] Yona O30 Tt 28 53 [_] vos 'O31L_] 29 52 {-_] Oo vOpal_] 30 5107 Ort 31 32 33 34 35 96 37 38 39 40 41 42 43 44 45 46 47 48 49 50 UU UUUOUUUUUOUUUUOUOO ex ence _ eo 2 ~S20O0 Onn UVDcsd K-Nnoaxety ow Brett te eee Bee e EEE ZEEE Top View 100 NOTES: TQFP 1 Pins 14 16 and 66 co not have to be connected directly to Veo as ong as the input voltage is = Vin. 2 Pins 83 and 84 are reserved for futuse 8M and 16M respectively. 3. Pin 64 does not have to be connected directly to Vss as long as the input voltage is < Vi; on the Jatest die revision this pin supports ZZ (sleep mode}IDT?71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with Fang ee eh Ose) Ore at eee el ae) le cl eg eae ee) Commercial and Industrial Temperature Ranges Pin Configuration - 256K x 18 Ia a S541 a M = Paid finaghanaanaranani ff \0 89 SB 97 6 95 94-93 5291 80 88 88 87 66 as BF 8 EP BI oO Nef so (J Ate no C7}e 79 ONC no LJs 74 LING Yooe [44 74] Vooa vse i_]s 6 Yess NG EJs 3 LIne no C27 74] VOR: vos DJs 73 LD vor vOs LJ9 7a Lol Os Vss [7] 10 7 Ves Vena 11 70] Yooa VOro L412 691] Os vor Loh13 es Lo) Os Vooth [714 s7 (J Vss Voo [J 1s 66 1) Veni Voom Z| 16 65 LJ] vo vss CCjir 4 vewrz) ene 18 a3 {_] vGa vors LJ i9 62 [J voe Vooo L_}20 61 (J Vove vss (Jat eo {_] vss vOra LJe2 sof] yO vous (423 sa [1 vOo vOee L_}24 sv LJ Nc nc [Jes 53 INC vss [Jee 55 [_] Vss Voce L_J27 s L_] Vora NG Tes 53 FJ NG nc CJ29 sJwne sil 4NcG 3132 23 34 35 36 37 36 39 40 41 47 43 44 45 46 47 48 49 50 Nc [30 Top 100 TQFP NOTES: 4283 dive 02a. 1. Pins 14, 16 and 66 do not have to be connected directly to Vop as long as the input voltage is = ViH 2 Pins 83 and 84 are reserved for future 8M and 16M respectively 3 Pin 64 does not have to be connected directly to Vss as long as the input voltage is < Vit; on the latest cle revision this pin supports 27 (sleep mode) 100 Pin TQFP Capacitance) (TA = +25 C, f = 1.0MHz) Absolute Maximum Ratings . Commercial & : Symbol Rating Industrial Values Unit Verve) Terminal Voltage with 0510446 V Respect to GND VrerM | Terminal Voltage with 05 to Voo V Respact to GND Vierm*) | Terminal Voltage with 05 to Vpn 40.5 Vv Respect to GND Vreav) | Terminal Voltage with -0.5 to Vong +05 V Respect to GND Commercial -0 to +70 C Tala Operating Temperature Industrial -40 to +85 C Operating Temperature TBIAS Temperature ~55 to +125 C Under Bias TsTa Storage 55 to +125 C Temperature PT Power Dissipation 20 Ww lour BC Output Current 50 mA NOTES: 5281 tbl 06 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functicnai operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure ta absolute maximum rating conditions for extended pericds may affect reliability Voo terminals only Vbpo terminals only Input terminals only VO terminals only. Om hwnm This is @ steady-state DC parameter that applies after the power supply has reached its nominal operating value Power sequencing is not necessary; however, the voitage on any input or /O pin cannot exceed Vone during power supply ramp Up 7 Tais the "instant on" case temperature 119 BGA Capacitance") (Ta = +25 C, f = 1.0MHz) Symbol Parameter! Conditions | Max. | Unit Symbol Parameter Conditions | Max. | Unit Cn input Capacitance Vin = 3dV 5 pF CN Input Capacitance Vin = 3dV 7 pF Cro VO Capacitance VouT = 3dV pF cro VO Capacitance Vout = 3d 7 pF 528t itl OF 5281 tH 07a 165 fBGA Capacitance") (TA = +25 C, f = 1.0MHz) Symbol Parameter Conditions Max. | Unit On Input Capacitance VIN = 3dV TBD | pF Cro | VO Capacitance Vout= 3dV TBD ] pF NOTE: 5281 tbl O7D 1. This parameter is guaranteed by device characterization, but not production tested1 2 3 4 5 6 Zz o Oo 0 oO o oO 0 Al Vooa AG Aa NC(2) AS Al VDDQ o oO oO o 0 Oo oO Bi NG CE2 A3 ADVLD As CE2 NG oO o oO oO o oO oO Cc NC A? Aa yoo Al2 AIS NC o oO oO Oo o Oo o D| vote vOP3 vss NC vss yOp2 vor 0 o oO oO o oO oO E| Wor yore VSS CEI vss vOrs O14 oO o oO oO o o F| vopa vOrg vss OE vss iQnz vba oO Oo oO Oo oO oO G Qed vet BW3 NC} Bwe Ost O10 o oo Oo O o oOo oO H cee vce3 vss RW VSS \fO9 VO8 oO o oO oO oO oO J} yeca VoD Ven(1) VDD VDDX1) vbo VECO o o oO 0 o o K} Gea oes VEs CLK VSS vO6 Or Oo o Oo oO oO oO LL] 1/0e5 O27 Bw NG BW VO4 Os oO Oo oO oO o oO Mj voDe ee vss CEN vss yvoa VDDO Oo Oo Oo oO oO Le) N vceo VOB0 ss Al VSS i702 Vor oO Oo oO oO o P} oat vOP4 Vss AO vss vor vOo oO oO oO oO o oO oO RAR} NC AS Tso VDD Vpot} Ata Nc o o oO oO oO T} NC NG Ato AN Als NC nezz(5} oO o 0 o o 0. UL_vopa NC/ATMS) NC/TDI) NC/TCKIS) NCvTDO) NC/TRSTA4) yooe S287 dew 134 Top View Pin Configuration - 256K x 18, 119 BGA 1 2 3 4 5 6 Z te & & wo 8 & @ Ds 6 4 NGi2) 3 16 DDG o oO oO o Oo 68 6 B NC CE2 AS ADV/LD Ag CE2 Nc o oO oO o Oo oO Cc NC Ar Ae YDD Als Aly NC 9 Oo Oo o o o oO Bi vcs NG vss NC VSS. voP1 NC o Oo oO Oo o oO o E NG l/O9 VSS CE1 V8S NC Wor oO oO o oO o oO o Fi Vea NG vss OE VSS VOe yoDa oO oO oO Oo o Oo oO G NC YOis Bwe NG(2) vss NC es} o Oo oO Oo o Oo oO H OU1 NG VSS RAW VSS WO Nc Oo oO Oo 0 0 oO oO J VoD Voo YODI1) VoD VOD(1) VDD VDDQ 0 0 oO Oo oO oO Qo K] NC vOI2 vss CLK vss NC Vos Qo oO o oO Oo 0 9 Li vo1a NC VSS NC Bw vow NC oO Oo o oO o oO oO Mj VobO vos vss CEN vss NG vpca o o o oO 9 o Oo N WO18 NC Yss Al ss VO1 Nc Oo o Oo oO o o 3 P NC YvOP2 V5S Ag SS NG Go oO Oo oO oO o o oO R NC AS TBO VbD Yop) Al2 NC oO oO oO o o o oO tT] ONC Ajo AMS NG Ald AN NGfzzi5 o Oo oO o o oC UL YOR NCATMS) NC/TDIS) NC/TCKS) NC/TDOG) NC/TRSTS4) yong S26ldnw 135 Top View NOTES: 1 J3, U5, and RS co not have to be directly connected to Vop as long as the input voltage is > Vin. 2. Gd and Ad are reserved for future 8M and 16M respectively. 3. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. 4 TRST is offered as an optional JTAG reset if required in the application if not needed, can be Ieft floating and will internally be pulled to Yop 5. Pin T7 does not have to be connected directly fo Vss as long as the input voltage is < Vit; an the latest die revision this pin supports ZZ (sieep mode). IDT71V3556, IDT71V3558, 428K x 36, 256K x 18, 3.3V Synchronous SRAMS with 2BT Feature, 3.3V VO, Burst Counter, and Pipelined Outputs Pin Configuration - 128K x 36, 119 BGA Commercial and Industria! Temperature RangesD7, UU 2 53 FR + TD HO 17 mM DODO |OAO wo FS IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchroncus SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Pin Configuration - 128K x 36, 165 fBGA Commercial and Industrial Temperature Ranges 1 2 3 4 5 6 7 8 g 10 i NC# A7 CET BWa BWe CE2 CEN ADV/LD NGa Ag NC NG AG CE2 BWa Bwi CLK RW OE NG Ag NCH VOP3 NC VDDG Vss Vss vss Vss Vss VdDQ NC VOp2 YOu VOrg Vopa VDD vss Vs5 Vss Vob Vong #O15 HO14 WO19 018 Vopa Yoo Vss Vss VSS Voo Vana VO13 VO12 voz VOzo Vooa VpD Vss Vs Vss Yop VpDa vOu O10 Oz3 O22 Vooq VoD Vs vss Vss VoD Vpba Og Os Vpptt Von) NG Vpo Vss vss Vss VoD NG NC NO/ZA O25 O24. Vobpa VoD ss Vss Vss VDD Vopa vO7 06 vO27 VO26 Vope Yop Vss Vss Vss Vob vpaQ O5 Oa VO29 O28 Vora Vpp Vss V8s ss Voo Vona O3 VO2 O34 Oza Vooa VoD Vs yss vss VoD Vppa VOr Oo VOP4 NC Yopa Vs NC/TRST34 NG Vpp vss Vopa NC OPI NC Nc AS A2 NCFDIS Ai NC/TDO Ato Al3 Ald NC LBO NC Ad A3 NC/TMS Ag NC/TCK $ Att Ate ANS Ate 5281 tbl 25 Pin Configuration - 256K x 18, 165 fBGA 1 2 3 4 5 6 7 8 9 19 i A NC A? CE BWe NC ce TEN ADVILD NC AB Aio B NC AG CE2 NC Bw CLK AW OE NC? Ag NC Cc NC NC Vppa Vss Vss Vss Vss Vss Voca NC VOPt D NC Os Voba VoD vss Vs Vss Vob Voo0 NG vor E NG Oa Vana Yop Vss. Vs vss Vpo Vong NC O6 F NG O10 VDDQ vop Vss vss Vss Von Vopa NC VOs G NC vou Yona Vop Vss Vss VSS VoD Vppa NG O4 H Yop" Vopl NC VoD VSS V85 VSS VDD NG NC NCizZz) J VO2 NG Voba Vop vss Vs vss Voo Voo0 Os NC K O13 NC Vapa Voo Vss VSS vss Vob vooa O2 NC L HOt NC VDcQ Yop Vss Vss Vss yoo Vopa fOr NC M VO15 NG VDDQ VpD Vss Vss Vss Voo VDDQ O0 NC N YOr2 NC Vopa Vss NOFFRSTE4 NC Vbpt VSS VoDa NG NG P NC NC AS Ag NC/TDIA Al NC/TDO Alt Atd Als NC R (a6 NC Aa A3 NCTMS Ag NC/TCK | Ata Al3 Ais Ad? NOTES: 5281 tbl 252 1. 2. 3 4 5. H1, H2, and N7 do not have to be directly connected to Von as long as the input voltage is = ViH. AQ, B9, B11, Al. R2 and P2 are reserved for future 9M, 18M, 36M, 72M, 144M and 288M respectively These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. TRSt is offered as an optional JTAG reset f required In the application If not needed, can be left floating and will internally be pulled to Von Pin H1 does not have to be connected directly to Vss as long as the input voltage is < ViL; on the latest die revision this pin supports ZZ (sleep mode).IDT71V3556, IDT?71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Synchronous Truth Table CEN RW Chip) ADVILD BWx ADDRESS PREVIOUS CYCLE CURRENT CYCLE 0 Enable USED {2 cycles later) L L Select L Valid External Xx LOAD WRITE pf L H Select L x Extemal x LOAD READ Qn L Xx X H Valid Intemal LOAD WRITE / BURST WRITE pe) BURST WRITE (Advance burst counten L Xx x H x Intemal LOAD READ / BURST READ Ql) BURST READ (Advance burst counter? L Xx Deselect L x xX x DESELECT or STOP HiZ L Xx X H X x DESELECT / NOOP NOOP HiZ H x X X X X X SUSPEND Previous Value $281 thi 08 NOTES: 1. L=Vit, H = Vin, X =Don't Care. 2 When ADV/LD signal is sampled high, the internal burst counter is incremented The R/W signat is ignored when the counter is advanced Therefore the nature of the burst cycle {Read or Write) is determined by the status of the RAV signal when the first address is loaded at the beginning of the burst cycle 3. Deselect cycle is initiated when either (CE1 or CE2 is sampled high or CE2 is sampled low} and ADV/LD is sampled low at rising edge of clock The data bus will tri-state two cycles after deselect is initiated 4 When CEN is sampled high at the rising adge of clock, that clack edge is blocked from prapogating through the part The state of all the internal registers and the /Os remains unchanged 5 To select the chip requires CE: = L, CE2 =L, CE2 = H on these chip enables Chip is deselected if any one of the chip enables is false o Partial Truth Table for Writes Device Outputs are ensured to be in High-Z aiter the first rising edge of clock upon power-up 7 Q- Data read from the device, D - data written te the device NOTES: 1 L=Vui,H= Vn, X =Den't Care 2, Multiple bytes may be selected during the same cycle 3 NVA for X18 configuration OPERATION RW Bw BW2 Bw? Bw? READ H X X x xX WRITE ALL BYTES L L L L L WRITE BYTE 1 (VO(0:7}, YOrs) L L H H H WRITE BYTE 2 (VO{8:15], /Op2)) L H L H H WRITE BYTE 3 (V0[16:23], YOps)@9) L H H L H WRITE BYTE 4 (VO[24:34}, VOp4\@) L H H H L NO WRITE L H H H H 5287 tht 08IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBI Feature, 3.3V lO, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Interleaved Burst Sequence Table (LBO=Vpp) Sequence 1 Sequence 2 Sequence 3 Sequence 4 Al AQ Al AO Al AQ Al AQ First Address 0 0 0 1 1 0 1 1 Second Address G 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address" i 1 1 0 0 1 0 0 5281 tht 10 NOTE: 1 Upon completion of the Burst sequence ihe counter wraps around to its initial state and continues counting Linear Burst Sequence Table (LBO=Vss) Sequence 1 Sequence 2 Sequence 3 Sequence 4 Al AO Al AO Al AQ Al AO First Address 0 & 0 1 1 0 1 1 Second Address a 1 1 A) 1 1 0 0 Third Address 1 0 1 } 0 0 0 1 Fourth Address") 1 1 0 0 0 1 j 0 S284 tbl tt NOTE: 1 Upon completion of the Burst sequence the counter wraps arcund to its initial state and continues counting Functional Timing Diagram CYCLE n+29 n+30 n+31 n+32 n+33 n+34 n+35 n+36 n+37 cLock f Lt Le LF LE Lt LE LE Le I (2) ADDRESS A29 A34 A3 A36 A37 (AQ A168) A30 ASI A32 A383 5 3 (2) CONTROL (RW, ADVILD, BW) c29 C30 C31 c32 C33 C34 C35 C36 C37 (2) DATA DiQ27 piaes Dae D DIQ32 B/Q33 D/Q34 DIQS5 Yo fot} VO PIt4 Q QO! yO29 O30 D/Q31 Q Q 5281 drw 03 NOTES: 1. This assumes CEN, CEi, CE2, CE2 are all true. 2 All Address, Controt and Data_In are only required to meet set-up and hold time with respect to the ising edge of clock Data_Outis valid after a clock-io-data dalay from the rising edge cf clockIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V /O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles (2) Cycle Address RAW | ADV/LD | Ge | CEN | BWx OQ |Comments x Load read ion L L n xX Burst read x ir m1 Qo | Load read rc Deselect or STOP NOOP Load read Mm Pm en fe Burst read Deselect or STOP Load write Load write Deselect or STOP NOOP mp pm pm po pope po Pop Pe | cp ek ] ml) oypr yr yey oye oy ae yeep cde fe Load write Load read rc As mo rT 7 - AT Load write x AB m8 X n+19 Ag Burs? write Load read Burst read sym pe Pom pm Pope Pa pee Pe Pep ac Kc Pol eK J oc] dl x7 mlx [ols x x x X x xX X x L L Burst write L x X L Xx L C x x L mae fof Qs | Load wite r rc S281 tol 12 NOTES: _ _ _ __ __ 1. CE=Lis defined as CE1 =L, CE2 = Land CE2 =H CE =H is defined as CE1 =H, CE2 =H or CE2=1 2 H=High; L = Low, X = Don't Care; Z = High Impedance Read Operation () Cycle | Address | RW | aDV/LD | Ge | CEN | BWx | OF vO | Comments tt Ao H L L EL x x Address and Control meet setup re+1 X Xx X X L xX X x Ciock Setup Valid n+2 x x x x x x L Qc | Contents of Address Ao Read Out 5281 bl 1 NOTES: 1. H=High; L =Low: X = Don't Care; Z = High Impedance. 2. CE=Lis defined as CE1 =L, CE2=L and CE2=H CE=H is defined as CE1 =H, CE2 =H or CE2=LIDT71V3556, 1IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Burst Read Operation 7 Cycte | Address | RAW | ADVLD | CH | CEN | BWx | OF VO | Comments n Ao H L L L x X x Address and Control meet seiup net xX x H x L x x x Clock Setup Valid, Advance Counter nt2 x x H x L x L Qo | Address Ao Read Out, Inc. Count n+3 x X H X L X L Qo+t | Address Ao+i Read Out, inc Count n+4 x X H x L x L Qo+2 | Address Ao+2 Read Out, Inc. Count m5 A H L L L x L Qo+3 | Address Ao+3 Read Out, Load Ai m6 x xX H x L x L Qo | Address Ao Raad Out, Inc Count m7 x x H x L x L Qt Address Ai Read Out, Inc. Count n+8 Ag H L L L X L Qu f Address Aisi Read Out, Load A2 NOTES: rai 1 H=High; L = Low; X = Dont Care; 2 = High Impedance _ _ 2. CE=Lis defined as CEi=L, CEe=LandCEa=H CE=His defined as CE: =H, CE2 =H or CE2=L Write Operation ( Cycle Address RW | ADV/LD | Ge | CEN | Bwx OE #Q |Comments n Ao L L L L x x Address and Control meet setup m1 x x X x L x x x Clock Setup Valid n+2 xX x X x L x x Do | Write to Address Ao NOTES: 5281 tht 15 1. H=High; L = Low; X = Don't Care; Z = High Impedance _ _ 2 CE=Lis defined as CEi=L CEe=LandCEa=H CE =H is defined as Chi =H, CE2 =H or CE2=L Burst Write Operation Cycle Address RW | aDWLD | Ge | CEN | BWx OE O | Comments n Ag L L L L L Xx X Address and Control meet setup m1 xX x H xX L L X X Clock Setup Valic, Inc Count n+2 xX x H x L L X Do | Address Ao Write, Ine. Count rH x x H x L L x Dot | Address Ao+1 Write, Inc. Count ne4 X H X L L x Dose | Address Ao+2 Write, Inc. Count ns Al L L L L L x Do+3 | Address Ao+3 Write, Load A: m6 x X H xX L L xX De | Address Ao Write, Inc. Gount n+7 x X H x L L xX Di | Address Ai Write, Inc. Count n+8 Az L L L L L x Divi | Address At+1 Write, Load Az NOTES: 5281 th! 16 1. H=High; L = Low; X = Don't Gare; ? = Don't Know; Z= High Impedance. _. 2. CE=Lisdefined as CE1=L, CE2=Land CEe=H CE =His defined as CE1 =H CEs =Hor GE2=LIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V iO, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Read Operation with Clock Enable Used Cycle Address RW | ADWLD | GE CEN BWx OE O |Comments n Ao H L L L x x x Address and Control meet setup re x xX x x H x Xx x Glock n+i Ignored n+2 At H L L L x x x Clock Valid n+3 xX x X X H X L Qo =| Glock Jgnored. Data Qo is on the bus. n4 x X xX xX H K L Qo =| Clock Ignored. Data Qois on the bus. nts Ae H L L L x L Qo | Address Ao Read out (bus trans.) nd Aa H L L L xX L GQ: | Address At Read out (bus trans.) m7 Aa H L L EL x L Q2 =| Address Az Read out (bus trans.} 5281 tbi 17 NOTES: 1 H-= High; L = Low; X = Dont Care; Z = High Impedance 2 CE=Lis defined as CE1 =L, CE2=LandCE2=H CE=H is defined as CE1 =H, CE2 = Hor CE2=L Write Operation with Clock Enable Used () Cycle Address RW | ADVLD | Ge? | CEN ; BWx | OE iG | Comments n Ao L L L L L x x Address and Control meet setup. m1 X X X x H xX x x Clock n+1 Ignored. n+2 Al L L L L L Xx x Clock Valid. n3 x x xX x H x x x Clock Ignored. nd x x Xx x H x x xX Clock Ignored nd Ae L L L L L Xx Do | Write Data De n+6 A3 L L L L L X Di | Write Data Di n+? Ad L L L L L x De | Write Data De 5281 wl 18 NOTES: 1. He High; L = Low; X = Don't Care; Z = High Impedance __ _ 2. CE =Lis defined asCE1=L C&2=L and CE2=H. CE=His defined as CE1 =H CE2=HorCEesLIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs MCLE mT ey (glam gota U) elect lee tla (a) Read Operation with CHIP Enable Used ) Cycle | Address | RW | ADVAD | CE? | CEN | BWx | OE | yom {Comments n X x L H L x x ? Deselected m4 x Xx L H L x x ? ~~ | Deselected n+2 Ao H L L L x x Z Address and Control meet setup n+3 X Xx L H L X x Z | Deselecied or STOP. n+4 Ai H L L L X L Qo | Address Ac Read out. Load At n+ xX x L H L X X Zz Deselected or STOP. ne6 x x L H L X L Qi } Address Ai Read out Deselected. nt+7 Ae H L L L X x Z Address and control meet setup n+8 x xX L H L X X Z =| Deselected or STOP. n+ Xx xX L H L x L Qe | Address Az Read out. Deselected. NOTES: 5281 | 19 1 H=High; L = Low; X = Don't Care; ? = Don't Know; Z= High impedance __ 2 CE=Lis defined as CEi =L, CEe=LandCEs=H CE=H is defined as CE: =H, CE2 =H or CE2=L 3 Device Outputs are ensured to be in High-Z atter the first rising edge of clock upon power-up Write Operation with Chip Enable Used () Cycle Address RW | ADWID | cee | CEN | BWx OE yoe) |Comments n X x L H L x X ? Deselected. nd x x L H L x x ? Deselecied. n+2 Ao L L L L L x Z Address and Control meet setup H3 xX x L H L x x Zz Deselected of STOP. n4 Ai L L L L L x Do | Address Do Write in Load Ai. ne x x L H L X x Zz Deseiected or STOP. n+6 x x L H L x x Di | Address Di Write in. Deselected. n+? Az L L L L L xX Zz Address and control meet setup n+8 x x L H L x xX Z | ODeselected or STOP. n+ X x L H L x x Ce { Address De Write in. Deselected. 5281 ib} 20 0 a ES: E =L is defined as CE1 =L, CEe =LandGEe=H CE=H is celined as CE: =H, CE2 =H or CE2=L N 1 H=High; L = Low; X = Dont Care; ? = Don't Know; Z = High Impedance 2IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V YO, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (Vop = 3.3V +/-5%) Symbol Parameter Test Conditions Min. Max. Unit |luif Input Leakage Current Yoo = Max , ViN = OV to Vop _ 5 pA thy LBO, JTAG and ZZ Input Leakage Current Von = Max., Vin = OV to Vop _ 30 pA [lo Output Leakage Current Vout = OV to Vooa, Device Deselected 5 HA VoL Oufput Low Voltage lo. = +8mA, Vop = Min. - 04 Vv VoH Output High Voltage loH = -8mA, VoD = Min. 24 _ V sea tol 21 NOTE: 1 TheLBO TMS, FDI, TCK and TRST pins wil be internally pulled to Voo and ZZ will be internally pulled if they are not actively driven in the application DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (von = 3.3V +/-5%) 200MHz* 166MHz 133MHz 100MHz Symbol Parameter Test Conditions Com Only | Com't | Ind | Coml | Ind | Com) | Ind | Unit 1D | Operating Power Device Selected, Outputs Open, 400 350 | 380 | 300 | 310 | 250 | 255 | mA Vin > VIN or < Vil, f= tax! Is8i | CMOS Standby Device Deselected, Outputs Open, 40 40 45 40 45 40 45 mA Power Supply Current | VoD = Max , Vin > VHD or < VIO, f = 923) Is82_ | Clock Running Power | Device Deselected, Outputs Open, 130 120 | 130 | #0 | 120 | 100 | 110 | mA Supply Curent Voo = Max, Vin > Vu or < Vio, f = Max? 9) Iss3_ dle Power Device Selected, Outputs Open, 40 4G 45 AQ 45 40 45 mA Supply Currant CEN 2 ViH, Vop = Max 1 Vin > VHD or < Vib, f= fmax9) NOTES: 5281 tbl 22 1 Allvalues are maximum guaranteed values 2 Atf=fmax, inputs are cycling at the maximum frequency of read cycles of Acyc; f=0 means no input lines are changing. 3 For /Os Vp = Vong 0.2V, Vip = 0 2V For other inpuis VHo = Yoo ~ 0 2V, Vip = 0.2V 4 Only available in 256K x 18 configuration AC Test Loads vorg2 AC Test Conditions (Vppa = 3.3V) Input Puls Levels 0 to 3V yoo 6+ < CE etawoa | Mput Rise/Fall Times 2ns 5+ Figure 1 AC Test Load input Timing Reference Leveis 15V at Output Timing Reference Levels 15Y AC Test Load See Figure 1 ACD 37 S267 tbl 23 Typicaf, ns (Typical, ns), | wt 1 5 4 L T 2030 50 80 100 200 Capacitance (pF) 5281 drw 05 Figure 2. Lumped Capacitive Load, Typicat DeratingIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ras ewe eee Oo leet mela Melt eM ad Tee eLtL ec) AC Electrical Characteristics (VoD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) Commercial and [Industrial Temperature Ranges 300MHz) 166MHz 133MHz 1OOMHz Symbol Parameter Min, Max. Min. Max, Min, Max. Min. Max, Unit Icrc Clock Cycle Time 5 _ 6 75 _ 10 _ ns te) Clock Frequence 200 166 133 10 MHz tcH) Clock High Pulse Width 18 18 22 32 ns te?) Clock Low Pulse Width 18 18 2.2 _ 32 _ ns Output Parameters ico Clock High to Valid Data 3.2 35 42 _ 5 ns icoc Clack High to Data Change 1 1 f 1 ns t1z8 44) Clock High fo Output Active 1 1 1 1 ns teHz#45) Clock High to Data High-Z 1 3 1 3 1 3 i 33 ns {ce Output Enable Access Time 32 _ 35 _ 42 5 ns ia Output Enable Low to Data Active G 0 0 0 ns touz8# Output Enable High to Data High-Z 35 35 42 ~ 5 ns Set Up Times Ise Clock Enable Setup Time 15 15 _ 17 _ 2.0 _ ns ISA Address Setup Time 1.5 _ 15 _ 17 20 _ ns iso Data In Setup Time 16 _ 1.6 17 _ 20 ns isw Read/Write (AW) Setup Time 15 15 17 2.0 ns sab Advance/Load (ADV/LD) Setup Time 15 _ 1.5 17 20 ns isc Chip Enable/Select Setup Time 1.5 15 17 2,0 _ ns iss Byte Write Enabie (BWx) Setup Time 15 15 17 29 ns Hold Times tHE Clack Enable Held Time 05 _ 05 - 05 a5 _ ns THA Address Hold Time 05 0.5 _ 05 _ 0.5 _ ns IHD Data In Hold Time 0.5 _ 0.6 _ 0.5 G5 _ ns tH Read/Write (RAW) Hold Time 05 0.5 05 05 _ ns tHaADV Advance/Load (ADV/LD) Hold Time 05 0.5 _ 05 _ 0.5 ns tHE Chip Enable/Select Hold Time 05 05 0.5 _ a5 ns THB Byte Write Enable (BW) Hold Time 05 0.5 0.5 05 ns NOTES: 5281 thl 24 1 tr= titeye 2. Meastired as HIGH above 0.6Vppa and LOW below 0 4Vona 3. Transition is measured +200mV irom steady-state 4. These parameters are guaranteed with the AC load (Figure 1) by device characterization They are not production tested 5. Toavoid bus contention, the output buffers are designed such that tchz (device turn-off} is about ins faster than tcLz (device tum-cn) ai a given temperature and voltage The specs as shown do not imply bus contention because tcLz is a Min. parameter that is worse case at totally different test conditions (0 deg C, 3.465V} than tcuz which is a Max, parameter (worse case at 70 deg. C, 3 135). 6. Commercial temperature range only. Only available in 256K x 18 configuration.AC Electrical Characteristics (VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges) IDT713556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous Wi ATLL) ZBT Feature, 3.3V VO, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 200MHz 166MHz 133MHz 100MHz Symbol Parameter Min. Max, Min, Max. Min. Max. Min Max. Unit ievc Clock Cycle Time 5 6 75 10 ns tr?) Clock Frequence 200 166 133 - 100 MHz ich?! Clock High Pulse Width 18 _ 18 22 32 ns te? Glock Low Pulse Width 18 18 22 32 ns Output Parameters tcp Clock High to Valid Data _ 32 35 _ 42 5 ns. icoc Clock High to Data Change 1 _ 1 _ 1 _ i ns torz845) Clock High to Output Active 1 _ 1 1 1 ns toHZ 45) Clock High to Data High-Z 1 3 1 3 1 3 1 33 ns toe Output Enable Access Time _ 32 _ 35 42 5 ns ia 284 Output Enable Low to Data Active 6 0 0 0 ns tonZ4) Output Enable High to Data High-2 35 35 ~~ 42 5 ns Set Up Times {se Clock Enable Setup Time 1.5 15 17 20 ~ ns isa Address Setup Time 15 15 _ 17 20 _ ns iso Data in Setup Time 15 _ 1.5 17 _ 20 ns tsw Read/Write (RW) Setup Time 1.5 15 1.7 20 ve ns isADV Advance/Load (ADV/LD) Setup Time 15 15 17 20 ns isc Chip Enable/Select Setup Time 1.5 _ 15 _ 17 20 ao ns {SB Byte Write Enable (BWx} Setup Time 15 15 1.7 ao 20 ns Hold Times tHE Clock Enable Hold Time 05 05 05 0.5 _ ns THA Addtess Hold Time 05 _ 05 _ 0.5 05 ns tHD Data In Hold Time a5 05 _ 05 05 _ ns tw Read/Write (R/W) Hold Time 05 _ 05 0.5 05 _ ns tHADV Advance/Load (ADV/LD} Hold Time 0.5 _ 05 0.5 a5 ns tHC Chip Enable/Select Hoid Time 0.5 _ 05 _ 05 0.5 _ ns {HB Byte Write Enable (BWx} Hold Time 0.5 0.5 o5 0.5 ns NOTES: 9281 tbl 24 1 tr = Itevce 2 Measured as HIGH above 0.6Va0q and LOW below 0.4Voo0. 3. Transition is measured =200mV from steady-state. 4. These parameters are guaranteed with the AC load (Figure 1} by device characterization. They are not production tested 5 Toaveid bus contention, the cutput buffers are designed such that tcnz (device turn-off) is about 1ns fastar than tcLz (device turn-on} at a given temperature and voltage. The specs as shown do not imply bus contention because tcLz is a Min. parameter that is worse case at totally different test conditions {0 deg C 3 465V) than tcuz which Is a Max parameier (worse case at 70 deg C, 3 735V) 6. Commercial temperature range only. Only available in 256K x 18 configuration.WVHS SU} O}U! paped| ae JO.QUOS PUB SSUPPe MBL LSYM [2UDIS AVY BU] JO B}E]S OU} Aq PAXy Si (BYLJAA 10 Peay) sseo0e jsing ay} jo eunzeu ay. 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MOT paldwes s! jeuBls jy UaUA PayENIU! S! B|9AO SYLMA Y SOLAS ayUM-]SNg PUR AyUM Ife UC PIA aq ysnut (XAG) S[eUBis OIA S1Ag JenplApuy y @Je]S SNOlAaad Jay UNB}Sd ||IM WHS Ol) Ul sJeys1Geu [euzeIUI [AY uNDo0 JOU Pip WORISUBY) YOO}D H-7 SU) 4! SB SABYSd | Led ey) WHS Ou) oI BujeBodord uroy yoo! eu) Jo LONISUBN) H-7] BU) YOO]q III YOO|O Jo Spe Busy ayy uo YBly poydwues usyA NAD e HO IH 8! 20 WuOJeAeA SI UD AQT ae 2399 pue Lag ueYyM e[dwexe JOJ -sjeudis 249 pue 1399 eu) 0} PeLaAU! Jn jeoyUsD! eve suoNIsuEN Buu z49 Zz ay Ssappe o} Buipuodsauco WyYYHS 84) 0} eyep Indu! ot) syuesazdeu (zy) q Hy Sselppe jeUaIXe ayy Woy} jndjno ysiij ay) Saseudar (Iy} O + S3LON 60 IP LBS Lnovivd NIWwLvd Commerciai and Industrial Temperature Ranges 30 bMS - LAN ead a9 ES a 2 4 jay 77) ra | 3 < =| a = Es it] % fa Ba} FR a = s ia) ie] @ = rT] r=) 7% =] = or a a S E 5 a) nan a 3 a =) Pg id ro) o = Fe f=} ci ri E faa N < ak wl < Qo on 0 in Q co. o = ta Ld 6 E hen a > 0 = 3) s E re ssaudav Ke 256K x 18, . 128K x 36 ayaay IDT71V3558, t W119 IDT71V3556.WHS 8u} o} peyuessud $] eyEp jenyoe ayy auojaq sapAo OM UI S@LUO9 UCH2ULOUI BUM SyAg ay) MOT paldues s) feubls AAzY VOY PeyENUI SI BOA Sym Y Se]OAO aILM4SING PUE AIIM |e UO PIA eq IsnW (XAtg) sleuBis syiAA alAg (enpiypU) y a]BIS SNOVAEIM JOU) UIEIEN HIM WHS Ou) Lt suaysiBe) (eusequl yy sn990 JOU plp UORISUEA 490]9 H-7 BYL j! SB eAEYeG IM Yed O41 WYYS 2l) o1UI BueBodoud Woy yoo}o ey] jo LORISURN H-"] Jeu 49010 jm 90/9 Jo aBpa Bulsy aun uo YBiy paldues ueYyr NAO e r= HBIH SI 230 WUOISARM SIL] UO AQ] G12 299 pul 199 UoYym ejduexe 104 s[eubis 239 pue 199 Su] 0} paysAU! Inq jLOyVED| eve suoIssueN BuRUI] z45 Zz 5 "ey Ssauppe 0} Hulpuodseu0s YS au] 0} BlEp Indul ay sjuaseudeu {ey} GQ Ly Ssouppe peule]xa ayy LOH IndIno ISI) ayy seserdal (Wy}o = S3LON F Fe OL MD LeZg ic = 3 3 1novyivd =] Fy | 2 NIVLYO Cy = F hd 30 P=} 3 on oa PAG - LAS a ram 2 2 vi 239 189 ae, 6 @ cameo 6 o3 Se no ed 8 ssaydayv 6 Ey 2 a oO or Pa 8 Avy & 5 i coches ay ie rao Ady oo. ry OD a > ey NBO 9 oi | 2 aa 6S 19 a4 = M ay | TIDT?71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs JTAG Interface Specification (SA Version only) Commercial and Industrial! Temperature Ranges tucyc tuF wR CL ; Ng fCH TOK / ee _ CUS Device Inputs")/ TDUTMS tupe ws] wy Device Outputs)/ TDO tURSR ticD TRST() M5281 drw 01 tJRST NOTES: 1 Device inputs = All device inputs except TDI, TMS and TRST 2 Device cutputs = All device outputs except TDO 3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset. JTAG AC Electrical Characteristics :2:3:4 Symboi Parameter Min. Max | Units . . y Scan Register Sizes ucve JTAG Clock Input Period 100 _ ns 1iCH STAG Clock HIGH zo | | ns Register Name Bit Size to. JTAG Clock Low 40 | | ns | |!nstuction (A) 4 UR JTAG Clock Rise Time Bt) ns Bypass (BYR) ' ur JTAG Clock Fall Time _ st} ns JTAG Identification (JIDR} 32 urs JTAG Reset so | | ns | [Boundary Soan (BSR) Note (1) 281 tb? 03 FSR JTAG Reset Recovery 50 _ ns NOTE: tien JTAG Data Output _ 99 ns 1. The Boundary Scan Descriptive Language (BSDL} file for this device is available by contacting your locat IDT sales representative WoC JTAG Data Output Hold 0 ns us JTAG Setup 25 ~_ ns WH JTAG Hold 25 ns 6281 tbl of NOTES: 1 Guaranteed by design 2 AC Test Load (Fig. 1) on external output signals 3. Refer to AC Test Conditions stated earlier in this document 4, JTAG operations occur at one speed ((OMHz} The base device may run at any speed specified in this datasheet.IDT74#V3558, IDT713558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS wiih 2BT Feature, 3.3V /O, Burst Counter, and Pipelined Outpuis ; JTAG identification Register Definitions (SA Version only) era UU Male eee cca Roti erste lem ature |e) Instruction Field Value Description Revision Number (34:28) 0x2 Reserved for version number. IDT Device ID (27:12) 0x208, Ox20A Defines IDT part number 71V3556SA and 71V3558SA, respectively. IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT. ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register. 5281 ibt 02 Available JTAG Instructions Instruction Description OPCODE EXTEST Forces contents of the boundary scan cells onto the device outpuis", 0000 Places the boundary scan register (BSR) between TDI and TDO. Places the boundary scan register (BSR) between TDI and TCO SAMPLE allows data from device inputs and outputs" to be capiured SAMPLE/PRELOAD in the boundary scan cells and shified seriaily through TDO. PRELOAD 0001 allows data to be input serially into the boundary scan cells via the TDI Loads the JTAG ID register (JIDR) with the vendor ID code and places DEVICE_ID the register between TDI and TDO 0010 HIGHZ Places the bypass register (BYR} between TDI and TOO. Forces all 0011 device output drivers to a High-Z state RESERVED 0700 RESERVED Several combinations ar reserved. Do notuse cedes other than those 0101 identfied for EXTEST, SAMPLE/PRELOAD, DEVICE_ID, HIGHZ, CLAMP, RESERVED VALIDATE and BYPASS instuctions O10 RESERVED oti CLAMP Uses BYR. Forces contents of the boundary scan cells onto the device 4000 oulpuis. Places the bypass register (BYR) between TDI and TDO. RESERVED 1001 RESERVED 1010 Same as above RESERVED 1011 RESERVED 1100 Automatically loaded into the instruction register whenever the TAP VALIDATE controller passes through the CAPTURE-IR state. The lower two bits 01' 1101 are mandated by the IEEE std. 1149.1 specification. RESERVED Same as above, 1110 BYPASS The BYPASS instruction is used to truncate the boundary scan register 41 as a single bit in length 5261 tbl 04 NOTES: 1. Device outputs = All device outputs except TDO. 2 Device inputs = Al device inputs except TDI, TMS, and TRST.-I1DT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feaiure, 3.3V [/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline me 4 P_ben lated Eat 5 T san | atrRato oo BA : m i Dye (e2] im EVEN LEAD SIDES OOD LEAD SIDES GA ARARAPHPAEPA RR ANGMAR AREA 7 oS ps tT coe { _f AEE cr SEE BELA A = bE aa ao _ aaa o ee a, a ES 4, ot |e EAS 1 \ge = ? DETAIL A =x aia ~~ Ay crm [1 a eS = co 1 uy ro vo : i wis i a * SEED 2 cA EDR TNTSaTD) . a EP qe PLANE Ee -~ SF Met 8 Tis af + 20 WIM = 4} wt gi be DEVAL _B Fm REE at STH PRA LL. sey, integrated Demce Technctays, Sy, 73 Bieede Feu: ers Shea, C4 OF Aas 016 AS hey) Me con Heats ; * a Fit. (ehgp segA 74 he Sat Se q NE AemRGvas | Gan 7 82 AK PACKAGE DUTUNE at EASE WETAE Bera Lt lonyrayes 14.0 X 20.0% 14 mm TOFP ae 1.097 +9 FORM DETAIL c _ SS q aw c | Psc-4045 i 02 ai Gtat Grand [eer to : i oes : ET SEarnee [ante 7 : i JEDEC VARIATION ; 4 Wl g Q uN wow [maa LAND PATTERN DIMENSIONS at - = 1.60 Al OS 10 15 j- P 1 2] 15 i 145 py D 2208 BSC + Dt 20.00 BSC aE E TED ESE : (ICOROCOIOUOORICSO0G02 0002000 El 400 BSC 5 = ae i ia = ST | ! D 30 = | NE 2 a ; 65 Bt = [ ee b | at aa ae ot? S = oil 22 30 JB aoa 3 + = mw ccc = 7 10 oS co ddd = - 15 cS [snaen j [ | = = ca : SS ca NOEES: 5 Ea Rl Wi uF Ty = ot l ALL SIMVENSIONNG AND TOLERANCING CONFORM 7O ANS! Y14 5W-19a2 ONDA NORAD DS ORACONGANNEE! i AS WP PACKACE MAY BE SHALLER THAN BOTTOM PACKAGE BY 15 mm te : AL TUS AND TO BE DETERMINED AT DATUM PLANE Jo 1 i AX OMENSIONS 0 AND E ARE 10 BE DETERWNED AT SFATNG PLANE i NIN MAL 2 @\ CIMERSIONS G1 AND. E1 20 NOT INCLUDE MOLD PROTRUSION, ALLOWABLE PT aa80 133.00 MOLD PROTRUSION 35 25 mm PER SDE. Ot ang 1 ARE WAUWLM BOOY mh aa SUE CWENSOMS INCLLOING MOLD WasMaTcH a at | 0b AX DETALS OF PIN 1 IDENTIFIER iS OPTIONS, RUT MUST BE LOCATED WOH [1680 | 7.00 THE ZDNE SMDICATED afl fi50 [14.00 AX DIMENSION b GOES NOT ANCLUOE DAMEAR PROTRUSION, ALOWMSLE CAUBAR ea} 1235 bt PROTRUSION (5 OB mim IN EXCESS OF THE & DIMENSION AT WACRANL x iw Ts MATERIAL EONEVTION. DAMBAR CANNOT SF LOCATED ON THC LOWER Sagas a 64 SSC oR THE Foot u 100 @\ EXACT SHAPE OF EACH CORRER 1S OPTIONAL EES sapere am Tuisgraied Davies Tenbaoigy, i, Ay THESE DNENSCNS APPLY TQ THE FLAT SECTION OF THE LEAD BETWEEN See aan \ et Sina aia see Gum ot anon HO AND 25 mia FRO THE LEAD BP ote 2 RRS LES rant. i800; FaT-an pe? Tis. (etdg wS-MP Cee pig deta mg TRE PK PACKAGE GUTLUNE if] ALL DIMENSIONS JRE iy MILLIVETERS, 140% 26.0.1 14 mm IOP It THG QUIUNE CONFORMS TG JEDEC FLSUCATIN $5 REGGIRATON WO-136 s 1.DO/A.10 FORM VARATON Gt AND BX war Tora Se, ty pe eb pse~ 4045 QoS Noe Seats isHTTIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V 1/O, Burst Counter, and Pipelined Outputs Commercial and industrial Temperature Ranges SVISENE oH 1 se= | ano ace] IMMA RELEASE [aofiafa7p har i BATH E 2 OMENS ONS [94/25 700} eg [i]---4 i 1 al 33 CORNER mS i "AS ID CORNER A 450 AK BREAK i am Koa I E ----- D oood00G ( 5 + Ooohoc0 | | B Gq oOoegooo i i ' 5 aoeba0o | : Ld D eoopoon | ! oC o0eoagou00o i i oocopooo | : : SoopoDo | Bi 7 T D in SS o t Fe i p Coogcoo | oa i p ooa@ace | > EEE 1 1 5 ooocooce LO feces tt i 1 B oo00000 [ | oooocd | | P oooepao0d | D D0OP000 | N--h-- D oooepoeo0g | (SU TeTaS SIE RI O15 BALL SHOWN) AL - ee A x aos : x AR San Sa [eee Srey Selagried Ewrise Tenbertsgy, fr (ANGLE AT: F WE Sherte: Fog, Sorte Soro, 14 E04 Fam GOS 4ET-24 WL Ho RE pereovnis [Sate | ATE BG PACKAGE OUTLINE AT FU aad 14.0 % 27.0 mm SOY RR SIE fONeMNG se REY ce pgo- 4063 ot De Sok SEALE SHAR Toucer 3s oF 2 RITES cn REY RESCRP TION: BATE I APPROVED WF am CORNER 60628 O3 INITIAL, REEEASE oh 97 Tv on BATCH & 0 MENS ONS 04/25/00 To wy pes paee a CHANGE PACKAGE THOKNESS 1a 05 x0} aoopoce eoogecosd 8 OGOP OCS c oacgoo0sg a . BDOhOOD t NOTES: CoOoPooO F 4 AIL REWENSIONING AND TOLERANCONG COMFORN 10 aNaEY14 5M- 1882 oookoes @y STATNC PLANE AND PREWARY DATUM ARE DEFINEO Gy THE TING F =~ u eeegooo SPPERICAL CROHNS OF THE SOLER BAILS ; ecaogcdea as 3a "YB" 35 THE BALL MATRIX SIZE Ni OTHE 1D" DIRECTION ME G THE BALL VATRIX SIZE IN THE "E DIRECTION Bo 5 q o 5 . "W" 1S THE MAME ALLOMAELE NUMBER OF SOLUER BALLS COoegnecs 4 PACKAGE MAY OCTEND TO EN6E PERIPEERY AND way ONSET OF coobooa F MOLDING COMPOUND, EPONY, METAL, CERAM 08 OTHER MATERIAL Gooooooa R AX DMENSION "b" 5 NEASURED AT_THE MAXIMUM SDLOEH GALL GAWETER OCOoCPd0o T PARALLEL 7 PRIMARY DATUM ocoo0o0 u eye Se AX 7A 10 CORKER WWST BE IDENTIIED IDENTFICATION MAY BZ GY MEANS \ OF CHAMFER, METALEZED OR INK WARK, INDENTATION OR OTHER FEATURE (719 BALL) OF THE PACKAGE BOY. MARK MLS JE VISIBLE FROM TOP SURFACE Z\ ACTON, SHAPE OF THIS FEATERE SS OPTIONAL S ALL GIVENSEONS ARE IN MILLIMETERS 2EDEC MARTE 4 9 THIS DRAWING CONFOSHS 10 JEDEC PUBLICATION 95 REGISTRATION NS-028, Fi a a -ARINTICN AA i Pun fnew Twa | ft A =~ fe he ag = 170 6 22.00 BS a 20.32 BSC E 1450 BBC El 7.62 BEC ub if a ME 7 3 x 415 a TF BSG b 50 15 0 5 c Sr as tet peers 400 - - 4 ice Ientegratact Teulon Tuebeslogy, tox bab = = A brew exe] 075 Sarda Yay, Sota Sora, CA BA eu = ie a fezEf eer doen) TO -ae c = - : pee, Fe Mi APO "RL IAEA 1072 ddd = = 0 lapercwals | cate {TLE a PACKAGE COTUNE ten - > Jo pve" FF beansy: 14.6 2 220 mm BCOY me PACA = [nena WS ray c PS0- 4063 02 DONDI RAE SERRE imu zor 7IDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V /O, Burst Counter, and Pipelined Outputs 165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline Commercial and Industrial Temperature Ranges 1 REVISIONS +s (ST ae larai Te |. Cia AV IB CORNER = Sf 2 =@ ed fib oo0ocadacaocoo |s D cococdaga0000 a ; 5D ooo0cgcoooad t _- ed b ecoo0agageaonago fs 4 D eoo0ocmvacaooo fe ) oooocogooco oc ' D oooocoa@Mwaooes c i D oSO-06 660-6 6-8-1 Ey oocoocgoaoooo0 0 ! D ooooac#woaco0o$9o * B) ooo0o ooooso E D oooocgacoosno 4 D ooo0oecogpoaooco0cos 4 b i-poOoooegacooof ? ri LEP Treo ooeceAaooO |r ao L ake a ie eae aL pst (165 BALL SHOWN} y LF WIT Tiere ARLE SH aM sean Fe [sire Enates SSronen integrated Device Technology, inc. aioe ARCULAR 7a) Seer Wey, Sarin Gees 2 a4e4 pate Flay (00) MO-RSTA The PDT TH aerrowS | cave | UTE BO PADXACE OUTUNE AM 70 loves 718 x 18.0 mm BOOT SRCRED FPEGA SGE | DeYEE Ko aay c PSC- 4086 oo OO mgt otaLe ORK [swear iorz E FEFRSONS i uN ireve DESCOIPAGH {sam | ARPROVD ee i fot ATA LAGE [cen Az oeo0ocoeoocodno ooocoo SoO000c 0 ooo0oo0oc@mooooo NOTES: oocooeooocao8 _ ooooOoOhv oOo 0o 1 DMENSIONINNG AND TOLERANCING COAFGRH TO ASHE Y14 5h-1 964 oo0a0o 00 aao 2 ene THE Basi SOLDER GALL ORIG PICH o00c~O 90000 i REPRESENTS THE MAXMUM SOLOER SALL ATR SZ ag 66-0 3 4 NW" REPRESENTS THE BALLCOWNT NuMasle oococeoooan . GUDSEN 1S MESURE ADE MAGA STEN Sk OAvETER oo0o00 ooo00 AX SEATING PLANE, aN Prauany paruM EL] are DERNED SY THE SPHERICAL CROWNS OF THE SEX GER BALLS. ocaoofoaodcaeo _. AX "Ae" 0 CORNER MUST GE SCENNFED BY CHAMFER, INK WARK, METALLIZEG oo0o0oco0a?rgooacdaa MARKING, NOENFATDN CR OTHER FEATURE ON PACKACE SOLY oo0o0on 20000 AX WAM" ID CORNER S ON PACKAGE BODY, MUST BE LOCATED WIA THE ZONE INDICATED oooc8 oo9000 3 AGL CHIENSIONS ARE IW MILENATTERS: oo0c0o0o 9o0a00 (165 BALL} 3 JEBEC VARWNTION k 3 NOT vet REciterED | & Q a A = 1.20 a Ad 3 55 id a 1300 BS E 100 ESC Mi XK 15 3 Hu 165 4 a 180 BSE etagriled Dawe Taconglogy mc [2 [45 bo }5 Femi tea) ee Te Be Wie NTE Fan Go) ETNA ME Gi2-310-7099 But MATER n/a peraewais [oars [TRE 69 PACKAGE GUILNE cane mp isnot 13.0 X 15.0 mre ECDN FP ata, GZE | ORANG Ne TRY c PSC4088 Lao SO 1p) Sar Peavey Beri 2IDT713556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V 1/0, Burst Counter, and Pipelined Outputs Timing Waveform of OE Operation Commercial and Industrial Temperature Ranges OE toe TOHZ folz DATAOUT j Valid 5281 drw 11 NOTE: 1 A read operation is assumed to be in progress Ordering Information (OT _XXXX XXX XX XX X x Device Power Speed Package Process/ Process/ ype Temperature Temperature Range Range Blank Commercial (0C to +76C} } Industrial (-40C to 485C} G Restricted Hazardous Substance Device PF** 100-pin Plastic Thin Quad Flatpack (TQFP) BG 419 Ball Grid Array BA) BQ 185 Fine Pitch Ball Grid Array (BGA) 200* 38 Clock Frequency in Megaheriz 100 8 Standard Power SA Standard Power with JFAG interlace | x X Generation Dia Step Optional | IDT71V3556 128Kx36 Pipelined ZBT SRAM with 3 3V I/O IDT71V3558 256Kx18 Pipelined ZBT SRAM with 3.3V 1/0 5281 dry i2 ' Commercial temperature range only. Only available in 256K x 18 configuration JTAG (SA Version) ts not available with 160-pin TOFP packageIDT71V3556, IDT71V3558, 128K x 36, 256K x 18, 3.3V Synchronous SRAMS with ZBT Feature, 3.3V 1/0, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Datasheet Document History 8/30/89 8/23/99 10/4/99 12/31/99 04/30/00 05/26/00 07/26/00 10/25/00 1/24/02 9/30 /04 10/18/06 08/1 1/08 Pg 4,5 Pg 6 Pg. 14 Pg 15 Pg. 22 Pg 24 Pg. 14 Pg 15 Pg.5,6 Pg 6 Pg 5,6, 7 Pg 21 Pg, 23 Pg 5-8 Pq 8 Pg. 23 Pg 8 Pg. 1-8, 15,22,23,27 Pg.7 Pg. 27 Pg. 1, 26 Pg 1, 15, 16, 27 Updated to new format Added Smart ZBT functionality Added Note 4 and changed Pins 38, 42, and 43 to DNU Changed U2-U6 to DNU Added Smart ZBT AC Electrical Characteristics Improved ica and toe(max} at 166MHz Revised tcuz(min) for f < 133 MHz Revised touz (max) for f < 133 MHz improved tcn, tet for f < 166 MHz Improved setup times for 100-200 MHz Added BGA package diagrams Added Datasheet Document History Revised AC Electrical Characteristics table Revised tcHz to match tcLz and tcpc at 133MHz and 100MHz Removed Smart functionality Added industrial Temperature range offerings at the 100 te 166MHz speed grades Insert clarification note to Recommended Operating Temperature and Absolute Max Ratings tables Add BGA capacitance table Add note to TQFP and BGA Pin Configurations; corrected typo in pinout Add 100pinTQFP package Diagram Cutline Add new package offering, 13 x 15mm 165 {BGA Correct 119BGA Package Diagram Outline Add ZZ sleep mode reference note to BG119, PK100 and BQ165 pinouts Update BQ165 pinout Update BG119 package diagram ouiline dimensions Remove Preliminary status Add note to pin N5 on BQ165, reserved for JTAG TRST Added JTAG "SA" version functionality Updated pin configuration for the 119 BGA-reordered 1/O signals on P6, P7 {128K x 36) and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18) Adding "Restricted hazardous substance device" to ardering information Added X generation die step to data sheet Remove 200MHz on 128K x 36 configuration. DIDT. ZBT? and Zero Bus Tumaround ate trademarks of Integrated Device Techn CORPORATE HEADQUARTERS 6024 Silver Creek Valley Rd San Jose, CA 95138 for SALES: for Tech Support: 800-345-7015 or 408-284-8200 sramhalp @idt.com fax: 408-284-2775 800-345-7015 or www idt.com 408/284-4555 The IDT toga is a registered trademark of Integrated Device Technotogy, Inc otog inc. and the architecture is suoported by Micron Technology and Motorola Inc. :