BSS138W N-Channel Logic Level Enhancement Mode Field Effect Transistor General Description Features These N-Channel enhancement mode field effect transistor. These products have been designed to minimize on-state resistance while provide rugged, reliable, and fast switching performance.These products are particularly suited for low voltage, low current applications such as small servo motor control, power MOSFET gate drivers, and other switching applications. * RDS(ON) = 3.5 @ VGS = 10V, ID = 0.22A RDS(ON) = 6.0 @ VGS = 4.5V, ID = 0.22A * High density cell design for extremely low RDS(ON) * Rugged and Reliable * Compact industry standard SOT-323 surface mount package D S G SOT-323 Marking : 138 Absolute Maximum Ratings Symbol TA = 25C unless otherwise noted Parameter Value Units VDSS Drain-Source Voltage 50 V VGSS Gate-Source Voltage 20 V 0.21 0.84 A A -55 to +150 C 300 C ID Drain Current TJ, TSTG TL - Continuous - Pulsed (Note1) Operating and Storage Junction Temperature Range Maximum Lead Temperature for Soldering Purposes, 1/16" from Case for 10 Seconds Thermal Characteristics Symbol PD RJA Value Units Maximum Power Dissipation Derate Above 25C Parameter (Note1) 340 2.72 mW mW/C Thermal Resistance, Junction to Ambient (Note1) 367 C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity 138 BSS138W 7'' 8mm 3000 units (c) 2010 Fairchild Semiconductor Corporation BSS138W Rev. A0 www.fairchildsemi.com 1 BSS138W -- N-Channel Logic Level Enhancement Mode Field Effect Transistor December 2010 Symbol TA = 25C unless otherwise noted Parameter Test Condition Min. Typ. Max. Units Off Characteristics BVDSS BVDSS TJ Drain-Source Breakdown Voltage VGS = 0V, ID = 250A 50 Breakdown Voltage Temperature ID = 250A, Referenced to 25C Coefficient V 71 mV/C IDSS Zero Gate Voltage Drain Current VDS = 50V, VGS = 0V VDS = 50V, VGS = 0V, TJ = 125C VDS = 30V, VGS = 0V 0.5 5 100 A A nA IGSS Gate-Body Leakage VGS = 20V, VDS = 0V 100 nA 1.5 V On Characteristics (Note2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = 1mA VGS(th) TJ Gate Threshold Voltage Temperature Coefficient ID = 1mA, Referenced to 25C -3.9 RDS(ON) Static Drain-Source On-Resistance VGS = 10V, ID = 0.22A VGS = 4.5V, ID = 0.22A VGS = 10V, ID = 0.22A, TJ=125C 1.17 1.36 2.16 On-State Drain Current VGS = 10V, VDS = 5V 0.2 A Forward Transconductance VDS = 10V, ID = 0.22A 0.12 S ID(ON) gFS 0.8 1.3 mV/C 3.5 6.0 5.8 Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Gate Resistance VDS = 25V, VGS = 0V, f = 1.0MHz VGS = 15mV, f = 1.0MHz 38 pF 5.9 pF 3.5 pF 11 Switching Characteristics (Note2) td(on) Turn-On Delay Time 2.3 5 tr Turn-On Rise Time 1.9 18 ns ns td(off) Turn-Off Delay Time 6.7 36 ns 6.5 14 ns tf Turn-Off Fall Time Qg Total Gate Change Qgs Gate-Source Change Qgd Gate-Drain Change VDD = 30V, ID = 0.29A, VGS = 10V, RGEN = 6 1.1 VDS = 25V, ID = 0.22A, VGS = 10V 0.12 nC nC 0.22 nC Drain-Source Diode Characteristics and Maximum Ratings IS VSD Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0V, IS = 0.44A (Note2) 0.22 A 1.4 V Notes: 1. 367C/W when mounted on a minimum pad. 2. Pulse Test: Pulse Width 300s, Duty Cycle 2.0% (c) 2010 Fairchild Semiconductor Corporation BSS138W Rev. A0 www.fairchildsemi.com 2 BSS138W -- N-Channel Logic Level Enhancement Mode Field Effect Transistor Electrical Characteristics Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 3.5 RDS(on), () Drain-Source On-Resistance ID. Drain-Source Current (A) 2.0 VGS = 10V 1.5 6V 4.5V 3.5V 1.0 3V 0.5 2.5V 3.0 2.5 4.5V 4V 3V VGS = 2.5V 2.0 3.5V 1.5 1.0 10V 6V 2V 0.0 0.0 0.5 1.0 1.5 2.0 2.5 0.5 0.0 3.0 0.2 0.4 Figure 3. On-Resistance Variation with Temperature. 1.0 4.0 ID = 110 mA VGS = 10V 3.5 ID = 220 mA RDS(on) () Drain-Source On-Resistance RDS(on) () Normalized Drain-Source On-Resistance 0.8 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 2.5 2.0 1.5 1.0 3.0 o TA = 125 C 2.5 2.0 1.5 o TA = 25 C 1.0 0.5 0.0 0.5 -50 0 50 100 0 150 2 4 o Figure 5. Drain-Source On Voltage with Temperature. 10 1000 VGS = 10V IS. Reverse Drain Current [mA] VGS = 0 V 1.6 o TA = 125( C) 1.2 o TA = 25( C) 0.8 0.4 o TA = -55( C) 0.1 0.2 0.3 0.4 0.5 o TA=150 C 100 o 10 TA=25 C 1 o TA=-55 C 0.1 0.0 0.6 ID. Drain Current (A) 0.2 0.4 0.6 0.8 1.0 1.2 VSD. Body Diode Forward Voltage [V] (c) 2010 Fairchild Semiconductor Corporation BSS138W Rev. A0 8 Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. 2.0 0.0 0.0 6 VGS. Gate to Source Voltage(V) TJ. Junction Temperature ( C) VDS. Drain-Source On Voltage (V) 0.6 ID. Drain-Source Current(A) VDS. Drain-Source Voltage (V) www.fairchildsemi.com 3 BSS138W -- N-Channel Logic Level Enhancement Mode Field Effect Transistor Typical Performance Characteristics Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 10 100 CISS, COSS, CRSS. Capacitance (pF) VGS. Gate-Source Voltage (V) ID = 220mA 8 VDS = 8V 6 VDS = 25V VDS = 30V 4 2 0 0.0 f = 1MHZ VGS = 0V 80 60 CISS 40 COSS 20 CRSS 0 0.2 0.4 0.6 0.8 1.0 1.2 0 10 Qg. Gate Charge (nC) 40 50 Figure 10. Single Pulse Maximum Power Dissipation. 1 10 P(pk), Peak Transient Power (W) 5 0 10 ID, Drain Current [A] 30 VDS. Voltage Bias (V) Figure 9. Maximum Safe Operating Area. 100s 1ms 10ms -1 10 100ms 1s DC RDS(on) Limit -2 10 VGS=10V Single Pulse o Rthja=367 C/W o Ta = 25 C -3 10 20 -1 0 10 1 10 4 3 2 1 0 1E-3 2 10 10 VDS, Drain-Source Voltage [V] Single Pulse o Rthja=367 C/W TA=25 0.01 0.1 1 10 100 t1, Time(sec) r(t), Normalized Transient Thermal Resistance Figure 11. Transient Thermal Response Curve. 1 50% Rthja(t)=r(t)*Rthja o Rthja=367 C/W 30% 0.1 10% 5% 2% D=1% Single Pulse 0.01 1E-4 1E-3 0.01 0.1 1 10 100 1000 t1, time(sec) (c) 2010 Fairchild Semiconductor Corporation BSS138W Rev. A0 www.fairchildsemi.com 4 BSS138W -- N-Channel Logic Level Enhancement Mode Field Effect Transistor Typical Performance Characteristics (Continued) 2.000.20 SYMM C L A 3 0.60 MIN 3 B 1.250.10 1 1.80 2 1 0.40 0.25 (0.20) 0.65 0.10 0.65 2 1.30 A B 0.50 MIN 1.30 LAND PATTERN RECOMMENDATION SEE DETAIL A 1.00 0.80 1.10 0.80 (0.425) 0.10 0.00 C 0.10 C 2.100.30 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED (R0.10) 0.26 0.10 SEATING PLANE 0.30 0.10 DETAIL A SCALE: 2X 30 0 A) THIS PACKAGE CONFORMS TO EIAJ SC-70. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) DRAWING FILE NAME: MKT-MAA03AREV2 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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