MT49H32M9CFM-25IT - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

288Mb: x9, x18, x36 2.5V V

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Features

PDF: 09005aef80a41b59/Source: 09005aef809f284b Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

CIO RLDRAM® II

MT49H32M9 – 32 Meg x 9 x 8 Banks

MT49H16M18 – 16 Me g x 18 x 8 Banks

MT49H8M36 – 8 Meg x 36 x 8 Banks

Features

• 400 MHz DDR operation (800 Mb/s/pi n da ta rate)

• 28.8 Gb/s peak bandwidth (x36 at 400 MHz

clock frequency)

• Organization

–32 Meg x 9, 16 Meg x 18, and 8 Meg x 36

• 8 internal banks for concurrent operation and

maximum bandwidth

• Reduced cycle time (20ns at 400 MHz)

• Nonmultiplexed addresses (address multiplexing

option available)

• SRAM-type interface

• Programmable READ latency (RL ), row cycle time,

and burst sequence length

• Balanced READ and WRITE latencies in order to

optimize data bus utilization

• Data mask for WRITE commands

• Differential input clocks (CK, CK#)

• Differential input data clocks (DKx, DKx#)

• On-die DLL generates CK edge-aligned data and

output data clock signals

• Data valid signal (QVLD)

• 32ms refresh (8K refresh for each bank; 64K r efresh

command must be issued in total each 32ms)

• 144-ball µBGA package

• HSTL I/O (1.5V or 1.8V nominal)

• 25–60Ω matched impedance outputs

• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O

• On-die termination (ODT) RTT

Figure 1: 144-Ball µBGA

Notes: 1. Contact Micron for availability of industrial

temperature products.

2. Contact Micron for availability of Pb-free

products.

3. The FBGA package is being phased out.

Options Marking

• Clock cycle ti ming

–2.5ns (400 MHz) -25

–3.3ns (300 MHz) -33

–5ns (200 MHz) -5

• Configuration

–32 Meg x 9 32M9

–16 Meg x 18 16M18

–8 M eg x 36 8M36

• Operating temperature

–Commercial (0° to +95°C) None

–In du strial (TC = –40°C to +95°C;

TA = –40°C to +85°C) IT1

•Package

–144-ball µBGA FM1

–144-ball µBGA (Pb-free) BM2

–144-ball FBGA HU3

–144-ball FBGA (Pb-free) HT2, 3

PDF: 09005aef80a41b59/Source: 09005aef809f284b Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

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Features

Figure 2: 288Mb RLDRAM II CIO Part Numbers

Notes: 1. The FBGA package is being phased out.

BGA Part Marking Decoder

Due to space limitations, BGA-packaged components have an abbreviated part marking

that is different from the part number. Micron’s BGA Part Marking Decoder is available

on Micron’s Web site at micron.com.

Package

144-ball µBGA

144-ball µBGA (Pb-free)

144-ball FBGA

144-ball FBGA (Pb-free)

HU1

HT1

Example Part Number: MT49H16M18FM-25

tCK = 2.5ns

tCK = 3.3ns

tCK = 5ns

Speed Grade

-25

-33

-5

Configuration

MT49H PackageSpeedTempI/O

Temperature

Commercial

Industrial

None

I/O

Common

Separate None

Configuration

32 Meg x 9

16 Meg x 18

8 Meg x 36

32M9

16M18

8M36

PDF: 09005aef80a41b59/Source: 09005aef809f284b Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

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Table of Contents

BGA Part Marking Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Electrical Specifications – IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Electrical Specifications – AC and DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

AC and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Input Slew Rate Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

MODE REGISTER SET (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

AUTO REFRESH (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Disabling the JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

TAP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

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List of Figur es

List of Figures

Figure 1: 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: 576Mb RLDRAM II CIO Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Figure 3: Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 7: 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Figure 8: Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 9: Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 10: Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 12: Read Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 13: On-Die Termination-Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 14: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 15: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 16: AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 17: Power-U p/Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 18: Power-U p/Initialization Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 19: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 20: Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 24: Basic READ Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 25: Consecutive READ Bursts (BL = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 26: Consecutive READ Bursts (BL = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 27: READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 28: Read Data Valid Window for x9 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 29: Read Data Valid Window for x18 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 30: Read Data Valid Window for x36 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 31: AUTO REFRESH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 32: READ Burst with ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 33: READ-NOP-READ with ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 35: Command Description in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 37: Mode Register D efi nit ion in Mul tip le xed Ad dre ss Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 38: BURST REFRESH Operation with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 39: Consecutive WRITE Bursts with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Figure 43: TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 44: TAP Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 45: JTAG Operation – Loading Instruction Code and Shifting Out Data . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 46: TAP Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

PDF: 09005aef80a41b59/Source: 09005aef809f284b Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

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Lisf of Tables

Table 1: 64 Meg x 9 Ball Assignments (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Table 2: 32 Meg x 18 Ball Assignments (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 3: 16 Meg x 36 Ball Assignments (Top View) 144-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 4: Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 5: IDD Operating Conditions and Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Table 6: Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 7: DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 8: Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 9: Differential Input Clock Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Table 10: Address and Command Setup and Hold Derating Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Table 11: Data Setup and Hold Derating Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Table 12: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 13: AC Electrical Characteristics: -18, -25E, -25, -33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 14: Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 15: Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 16: Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 17: Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 18: Cycle Time and READ/WRITE Latency Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 19: Address Widths at Different Burst Lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Table 20: On-Die Termination DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 21: 576Mb Address Mapping in Multiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Table 22: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode . . . . . . . . . . . . . .61

Table 23: TAP Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 24: TAP AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 25: TAP DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 26: Identification Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 27: Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 28: Instruction Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 29: Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

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General Description

The Micron® reduced latency DRAM (RLDRAM®) II is a high-speed memory device

designed for high bandwidth data storage—tele communications, networking, and

cache applicati o ns, etc. The chip’s 8-bank architecture is optimized for sustaina ble high

speed operation.

The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output

data is referenced to the free-running output data clock.

Commands, addresses, and control si gnals are registered at every positive edge of the

differ ential input clock, while input data is register ed at b oth positive and negative edges

of the input data clock(s).

Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is

programmable from 2, 4, or 8 by setting the mode register.

The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output

drivers.

Bank-scheduled refresh is supported with the row address generated internally.

The µBGA 144-ball package is used to enable ultra high-speed data transfer rates and a

simple upgrade path from early ge neration devices.

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State Diagram

Figure 3: Simplified State Diagram

Initialization

sequence

DSEL/NOP

READWRITE

MRSAREF

Automatic sequence

Command sequence

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State Diagram

Functional Block Diagrams

Figure 4: 32 Meg x 9 Functional Block Diagram

Notes: 1. Examples for BL = 2; column address will be reduced with an increase in burst length.

2. The “16” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).

WE#

CK#

CS#

REF#

A0–A201

BA0–BA2

I/O gating

DQM mask logic

Column

decoder

Bank 0

memory

array

(8,192 x 32 x 16 x 9)2

8,192

Bank

control

logic

Bank 1

Bank 0

Bank 2

Bank 3

Bank 4

Bank 6

Bank 5

Bank 7

Refresh

counter

Mode register

Control

logic

Command

decode

Row-

address

MUX

Address

Column-

address

counter/

latch

144

READ

logic

WRITE

FIFO

and

drivers

CLK

144

latch

QK/QK#

generator

Drivers

DLL

CK/CK#

RCVRS

Input

logic

(0 ....8)

ODT control

DQ0–DQ8

QK0/QK0#

QVLD

DK/DK#

Output drivers

ZQ CAL

SENSE AMPLIFIERS

Sense amplifiers

8,192

Bank 0

row-

address

latch

and

decoder

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State Diagram

Figure 5: 16 Meg x 18 Functional Block Diagram

Notes: 1. Examples for BL = 2; column address will be reduced with an increase in burst length.

2. The “8” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).

WE#

CK#

CS#

REF#

A0–A191

BA0–BA2

I/O gating

DQM mask logic

Column

decoder

Bank 0

memory

array

(8,192 x 32 x 8 x 18)2

8,192

Bank

control

logic

Bank 1

Bank 0

Bank 2

Bank 3

Bank 4

Bank 6

Bank 5

Bank 7

Refresh

counter

Mode register

Control

logic

Command

decode

Row-

address

MUX

Address

Column-

address

counter/

latch

144

READ

logic

WRITE

FIFO

and

drivers

144

latch

QK/QK#

generator

Drivers

DLL

CK/CK#

RCVRS

Input

logic

(0 ....17)

ODT control

DQ0–DQ17

QK0–QK1/

QK0#–QK1#

QVLD

DK/DK#

Output drivers

ZQ CAL

SENSE AMPLIFIERS

Sense amplifiers

8,192

CLK

Bank 0

row-

address

latch

and

decoder

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State Diagram

Figure 6: 8 Meg x 36 Functional Block Diagram

Notes: 1. Examples for BL = 2; column address will be reduced with an increase in burst length.

2. The “4” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).

WE#

CK#

CS#

REF#

A0–A181

BA0–BA2

I/O gating

DQM mask logic

Column

decoder

Bank 0

memory

array

(8,192 x 32 x 4 x 36)2

8,192

Bank

control

logic

Bank 1

Bank 0

Bank 2

Bank 3

Bank 4

Bank 6

Bank 5

Bank 7

Refresh

counter

Mode register

Control

logic

Command

decode

Row-

address

MUX

Address

Column-

address

counter/

latch

144

READ

logic

WRITE

FIFO

and

drivers

144

latch

QK/QK#

generator

Drivers

DLL

CK/CK#

RCVRS

Input

logic

(0 ....35)

ODT control

DQ0–DQ35

QK0–QK1/

QK0#–QK1#

QVLD

DK0–DK1/

DK0#–DK1#

Output drivers

ZQ CAL

SENSE AMPLIFIERS

Sense amplifiers

8,192

CLK

Bank 0

row-

address

latch

and

decoder

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Ball Assignments and Descriptions

Notes: 1. Reserved for future use. This signal is not connected.

2. Reserved for future use. This signal is internally connected and has parasitic characteristics

of an address input signal.

3. No function. This signal is internally co nn ected and has pa rasitic characteristics of a clock

input signal. This may optionally be connected to GND.

4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This

may optionally be connected to GND. Note that if ODT is enabled, these pins will be con-

nected to VTT.

Table 1: 32 Meg x 9 Ball Assignments (Top View) 144-Ball µBGA

12345678910 11 12

AVREF VSS VEXT VSS VSS VEXT TMS TCK

BVDD DNU4DNU4VSSQVSSQDQ0 DNU4VDD

CVTT DNU4DNU4VDDQVDDQDQ1 DNU4VTT

DA221DNU4DNU4VSSQVSSQ QK0# QK0 VSS

EA212DNU4DNU4VDDQVDDQDQ2 DNU4A20

FA5 DNU4DNU4VSSQVSSQDQ3 DNU4QVLD

GA8 A6A7 VDD VDD A2 A1 A0

HB2 A9 VSS VSS VSS VSS A4 A3

JNF3NF3VDD VDD VDD VDD B0 CK

KDK DK# VDD VDD VDD VDD B1 CK#

LREF# CS# VSS VSS VSS VSS A14 A13

MWE# A16A17 VDD VDD A12 A11 A10

NA18 DNU4DNU4VSSQVSSQDQ4 DNU4A19

PA15 DNU4DNU4VDDQVDDQDQ5 DNU4DM

RVSS DNU4DNU4VSSQVSSQDQ6DNU4VSS

TVTT DNU4DNU4VDDQVDDQDQ7 DNU4VTT

UVDD DNU4DNU4VSSQVSSQDQ8 DNU4VDD

VVREF ZQ VEXT VSS VSS VEXT TDO TDI

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Ball Assignments and Descriptions

Notes: 1. Reserved for future use. This may optionally be connected to GND.

2. Reserved for future use. This signal is internally connected and has parasitic characteristics

of an address input signal. This may optionally be con nected to GND.

3. No function. This signal is internally co nn ected and has pa rasitic characteristics of a clock

input signal. This may optionally be connected to GND.

4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This

may optionally be connected to GND. Note that if ODT is enabled, these pins will be con-

nected to VTT.

Table 2: 16 Meg x 18 Ball Assignments (Top View) 144-Ball µBGA

12345678910 11 12

AVREF VSS VEXT VSS VSS VEXT TMS TCK

BVDD DNU4DQ4 VSSQVSSQDQ0 DNU4VDD

CVTT DNU4DQ5 VDDQVDDQDQ1 DNU4VTT

DA221DNU4DQ6VSSQVSSQ QK0# QK0 VSS

EA212DNU4DQ7 VDDQVDDQDQ2 DNU4A202

FA5 DNU4DQ8 VSSQVSSQDQ3 DNU4QVLD

GA8 A6A7 VDD VDD A2 A1 A0

HB2 A9 VSS VSS VSS VSS A4 A3

JNF3NF3VDD VDD VDD VDD B0 CK

KDK DK# VDD VDD VDD VDD B1 CK#

LREF# CS# VSS VSS VSS VSS A14 A13

MWE# A16A17 VDD VDD A12 A11 A10

NA18 DNU4DQ14 VSSQVSSQDQ9 DNU4A19

PA15 DNU4DQ15 VDDQVDDQDQ10 DNU4DM

RVSS QK1 QK1# VSSQVSSQDQ11 DNU4VSS

TVTT DNU4DQ16VDDQVDDQDQ12 DNU4VTT

UVDD DNU4DQ17 VSSQVSSQDQ13 DNU4VDD

VVREF ZQ VEXT VSS VSS VEXT TDO TDI

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Ball Assignments and Descriptions

Notes: 1. Reserved for future use. This may optionally be connected to GND.

2. Reserved for future use. This signal is internally connected and has parasitic characteristics

of an address input signal. This may optionally be con nected to GND.

Table 3: 8 Meg x 36 Ball Assignments (Top View) 144-Ball µBGA

12345678910 11 12

AVREF VSS VEXT VSS VSS VEXT TMS TCK

BVDD DQ8 DQ9 VSSQVSSQDQ1 DQ0 VDD

CVTT DQ10 DQ11 VDDQVDDQDQ3 DQ2 VTT

DA22 DQ12 DQ13 VSSQVSSQ QK0# QK0 VSS

EA212DQ14 DQ15 VDDQVDDQDQ5 DQ4 A202

FA5 DQ16DQ17 VSSQVSSQDQ7 DQ6QVLD

GA8 A6A7 VDD VDD A2 A1 A0

HB2 A9 VSS VSS VSS VSS A4 A3

JDK0 DK0# VDD VDD VDD VDD B0 CK

KDK1 DK1# VDD VDD VDD VDD B1 CK#

LREF# CS# VSS VSS VSS VSS A14 A13

MWE# A16A17 VDD VDD A12 A11 A10

NA18 DQ24 DQ25 VSSQVSSQDQ35 DQ34 A192

PA15 DQ22 DQ23 VDDQVDDQDQ33 DQ32 DM

RVSS QK1 QK1# VSSQVSSQDQ31 DQ30 VSS

TVTT DQ20 DQ21 VDDQVDDQDQ29 DQ28 VTT

UVDD DQ18 DQ19 VSSQVSSQDQ27 DQ26VDD

VVREF ZQ VEXT VSS VSS VEXT TDO TDI

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Ball Assignments and Descriptions

Table 4: Ball Descriptions

Symbol Type Description

A0–A20 Input Addr ess inputs: A0–A20 define the row and column addresses for READ and WRITE operations.

During a MODE REGISTER SET, the address inputs define the register settings. They are sampled

at the rising edge of CK.

BA0–BA2 Input Bank address inputs: Select to which internal bank a command is being applied.

CK, CK# Input Input clock: CK and CK# are differential input clocks. Addresses and commands are la tched on

the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.

CS# Input Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When

the command decoder is disabled, new commands are ignored, but internal operations continue.

DQ0–DQ35 Input Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is

referenced to both edges of QKx. During WRITE commands, the data is sampled at both edges of

DK.

DK, DK# Input Input data clock: DK and DK# ar e the dif fer ential input data clocks. All input data is referenced

to both edges of DK. DK# is ideally 180 degrees out of phase with DK. For the x36 device, DQ0–

DQ17 are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the

x9 and x18 devices, all DQs are referenced to DK and DK#. All DKx and DKx# pins must always be

supplied to the device.

DM Input Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked

when DM is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration).

Ti e signal to ground if not used.

TCK Input IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.

TMS, TDI Input IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.

WE#, REF# Input Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with

CS#) the command to be executed.

VREF Input Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.

ZQ I/O External impedance (25–60Ω): This signal is used to tune the device outputs to the system data

bus impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to

ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ to VDD

invokes the maximum impedance mode. Refer to Figure 16 on page 44 to activate this function.

QKx, QKx# Output Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are free-

running, and during READs, are edge-aligned with data output from the RLDRAM. QKx# is

ideally 180 de grees out of phase wit h QKx. For the x36 device, QK0 and QK0# are aligned with

DQ0–DQ17, and QK1 and QK1# are aligned with DQ18–DQ35. For the x18 device, QK0 and QK0#

are aligned with DQ0–DQ8, while QK1 and QK1# are aligned with Q9–Q17. For the x9 device, all

DQs are aligned with QK0 and QK0#.

QVLD Output Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and Q Kx#.

TDO Output IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function

is not used.

VDD Supply Power supply: Nominally, 1.8V. See Table 12 on page 29 for range.

VDDQ Supply DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.

See Table 12 on page 29 for range.

VEXT Supply Power supply: Nominally, 2.5V. See Table 12 on page 29 for range.

VSS Supply Ground.

VSSQ Supply DQ ground: Isolated on the device for improved noise immunity.

VTT Supply Power supply: Isolated termination supply. Nominally, VDDQ/2. See Table 12 on page 29 for

range.

A21 – Reserved for future use: This signal is internally conn ected and can be treated as an address

input.

A22 – Reserved for future use: This signal is not connected and can be connected to ground.

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Ball Assignments and Descriptions

DNU – Do not use: These balls may be connected to ground. Note that if ODT is enabled, these pins will

be connected to VTT.

NF – No function: These balls can be connected to ground.

Table 4: Ball Descriptions (continued)

Symbol Type Description

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Package Dimensions

Figure 7: 144-Ball µBGA

Notes: 1. All dimensions are in millimeters.

BALL A1 ID

17.90 CTR

0.44 ±0.05

0.39 ±0.05

BALL A1

BALL A1 ID

0.08 A A

SEATING PLANE

10º TYP

0.08 MAX

10.70 CTR

11.00 ±0.10

4.40 5.50 ±0.05

8.80

2.41 CTR

0.80 TYP

1.00 TYP

9.25 ±0.05

8.50

15.40 17.00 18.50 ±0.10

144X Ø 0.45

DIMENSIONS APPLY

TO SOLDER BALLS

POST REFLOW. THE

PRE-REFLOW BALL

DIAMETER IS 0.50 ON A

0.40 SMD BALL PAD.

BALL A12 MOLD COMPOUND:

EPOXY NOVOLAC

SUBSTRATE MATERIAL:

PLASTIC LAMINATE

SOLDER BALL MATERIAL:

62% Sn, 36% Pb, 2%Ag OR

96.5% Sn, 3%Ag, 0.5% Cu

MOLD

COMPOUND

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288Mb: x9, x18, x36 2.5V V

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Package Dimensions

Figure 8: 144-Ball FBGA

Notes: 1. All dimensions are in millimeters.

2. The FBGA package is being phased out.

SEATING

PLANE

0.155 ±0.013

0.75 ±0.05

0.10 A A

BALL A1 ID

BALL A1

MOLD

COMPOUND

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE MATERIAL: PLASTIC LAMINATE

1.20 MAX

SOLDER BALL MATERIAL:

62% Sn, 36% Pb, 2%Ag OR

96.5% Sn, 3%Ag, 0.5%Cu

18.50 ±0.10

17.00

1.00 TYP

4.40

11.00 ±0.10

5.50 ±0.05

8.50

9.25 ±0.05

BALL A12

144X 0.55 Ø

DIMENSIONS APPLY TO

SOLDER BALLS POST

REFLOW. THE PRE-REFLOW

BALL IS Ø0.50 ON A Ø0.40

NSMD BALL PAD.

8.80

2.20 ±0.025

CTR

0.80 TYP

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288Mb: x9, x18, x36 2.5V V

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Electrical Specifications – I

Electrical Specifications – IDD

Table 5: IDD Operating Conditions and Maximum Limits

Description Condition Symbol -25 -33 -5 Units

Standby current tCK = idle; All banks idle; No inputs toggling ISB1 (VDD) x9/x18 48 48 48 mA

ISB1 (VDD) x3648 48 48

ISB1 (VEXT)262626

Active standby

current CS# = 1; No commands; Bank address

incremented and half address/data change

once every 4 clock cycles

ISB2 (VDD) x9/x18 288 233 189 mA

ISB2 (VDD) x36288 233 189

ISB2 (VEXT)262626

Operational

current BL = 2; Sequential bank access; Bank transitions

once every tRC; Half address transitions once

every tRC; Read followed by write sequence;

continuous data during WRITE commands

IDD1 (VDD) x9/x18 348 305 255 mA

IDD1 (VDD) x36374 343 292

IDD1 (VEXT)413636

Operational

current BL = 4; Sequential bank access; Bank transitions

once every tRC; Half address transitions once

every tRC; Read followed by write sequence;

Continuous data during WRITE commands

IDD2 (VDD) x9/x18 362319269mA

IDD2 (VDD) x36418 389 339

IDD2 (VEXT) 484242

Operational

current BL = 8; Sequential bank access; Bank transitions

once every tRC; half address transitions once

every tRC; Read followed by write sequence;

continuous data during WRITE commands

IDD3 (VDD) x9/x18 408 368286mA

IDD3 (VDD) x36n/a n/a n/a

IDD3 (VEXT) 554848

Burst refresh

current Eight-bank cyclic refresh ; Co ntin uo us address/

data; Command bus remains in refresh for all

eight banks

IREF1 (VDD) x9/x18 785 615 430 mA

IREF1 (VDD) x36785 615 430

IREF1 (VEXT) 133 111 105

Distributed

refresh current Single-bank refresh; Sequential bank acce ss;

Half address transitions once every tRC,

continuous data

IREF2 (VDD) x9/x18 325 267221mA

IREF2 (VDD) x36326281 227

IREF2 (VEXT) 484242

Operating burst

write current

example

BL = 2; Cyclic bank access; Half of address bits

change every clock cycle; Continuous data;

measurement is taken during continuous

WRITE

IDD2W (VDD)

x9/x18 970 819 597 mA

IDD2W (VDD) x36990 914 676

IDD2W (VEXT)1009069

Operating burst

write current

example

BL = 4; Cyclic bank access; Half of address bits

change every 2 clock cycles; Continuous data;

Measurement is taken during continuous

WRITE

IDD4W (VDD)

x9/x18 779 609 439 mA

IDD4W (VDD) X36882 790 567

IDD4W (VEXT)887763

Operating burst

write current

example

BL = 8; Cyclic bank access; Half of address bits

change every 4 clock cycles; continuous data;

Measurement is taken during continuous

WRITE

IDD8W (VDD)

x9/x18 668525364mA

IDD8W (VDD) x36n/a n/a n/a

IDD8W (VEXT)605140

Operating burst

read current

example

BL = 2; Cyclic bank access; Half of address bits

change every clock cycle; Measurement is taken

during continuous READ

IDD2R (VDD) x9/x18 860735525mA

IDD2R (VDD) x3 6880 795 565

IDD2R (VEXT)1009069

Operating burst

read current

example

BL = 4; Cyclic bank access; Half of address bits

change every 2 clock cycles; Measurement is

taken during continuous READ

IDD4R (VDD) x9/x18 680 525 380 mA

IDD4R (VDD) x3 6730 660455

IDD4R (VEXT)887763

Operating burst

read current

example

BL = 8; Cyclic bank access; Half of address bits

change every 4 clock cycles; Measurement is

taken during continuous READ

IDD8R (VDD) x9/x18 570 450 310 mA

IDD8R (VDD) x3 6n/a n/a n/a

IDD8R (VEXT)605140

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288Mb: x9, x18, x36 2.5V V

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Electrical Specifications – I

Notes: 1. IDD specifications are tested after the device is properly initialized. +0°C ≤ TC ≤ +95°C; +1.7V

≤ VDD ≤ +1.9V, +2.38V ≤ VEXT ≤ +2.63V, +1.4V ≤ VDDQ ≤ VDD, VREF = VDDQ/2.

2. tCK = tDK = MIN, tRC = MIN.

3. Input slew rate is specified in Table 8 on page 19.

4. Defi nitions for IDD conditions:

4a. LOW is defined as VIN ≤ VIL(AC) MAX.

4b. HIGH is defined as VIN ≥ VIH(AC) MIN.

4c. Stable is defined as inputs remaining at a HIGH or LOW level.

4d. Floating is defined as inputs at VREF = VDDQ/2.

4e. Continuous data is defined as half the DQ signals changing between HIGH and LOW

every half clock cycle (twice per clock).

4f. Continuous address is defined as half the address signals changing between HIGH and

LOW every clock cycle (once per clock).

4g. Sequential bank access is defined as the bank address incrementing by one every tRC.

4h. Cyclic bank access is defined as the bank address incrementing by one for each com-

mand access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for

BL = 8 this is every fourth clock.

5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transi-

tions more than once per clock cycle.

6.I

DD parameters are specifie d with ODT disabled.

7. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nomi-

nal reference/supply voltage levels, but the related specifications and device operations are

tested for the full voltage range specifie d.

8. IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing

is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications

are tested for the specified AC input levels under normal use conditions. The minimum slew

rate for the input signals used to test the device is 2 V/ns in the range between VIL(AC) and

VIH(AC).

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Electrical Specifications – AC and DC

Absolute Maximum Ratings

S tresses greater than those li sted in Table 6 may cause permanent damage to the device.

This is a stress rating only, and functional operation of the device at these or any other

conditions outside those indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for extended periods may

affect reli ability.

AC and DC Operating Conditions

Notes: 1. All volt ages refere nc ed to VSS (GND).

2. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL(AC) ≥ –0.5V for t ≤ tCK/2. Dur-

ing normal operation, V DDQ must not exceed VDD. Control input signals may not have pulse

widths less than tCK/2 or operate at freque ncies exceed ing tCK (MAX).

3. VDDQ can be set to a nominal 1.5V ± 0.1 V or 1.8V ± 0.1V supply.

4. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is

expected to track variations in VDDQ.

5. Peak-to-peak AC noise on VREF must not exceed ±2 percent VREF(DC).

6.V

REF is expected to equal VDDQ/2 of the transmitting device and to track variations in the

DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2

percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±2 percent V DDQ/2 for DC error

and an additional ±2 percent VDDQ/2 for AC noise. This measurement is to be taken at the

nearest VREF bypass capacitor.

Table 6: Absolute Maximum Ratings

Parameter Min Max Units

I/O voltage –0.3 VDDQ + 0.3 V

Voltage on VEXT supply relative to VSS –0.3 +2.8 V

Voltage on VDD supply relative to VSS –0.3 +2.1 V

Voltage on VDDQ supply relative to VSS –0.3 +2.1 V

Table 7: DC Electrical Characteristics and Operating Conditions

Note 1 applies to the entire table; Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V

Description Conditions Symbol Min Max Units Notes

Supply voltage –V

EXT 2.38 2.63V

Supply voltage –V

DD 1.7 1.9 V 2

Isolated output buffer supply –V

DDQ1.4 VDD V 2, 3

Reference voltage –V

REF 0.49 × VDDQ 0.51 × VDDQV 4, 5, 6

Termination voltage –V

TT 0.95 × VREF 1.05 × VREF V7, 8

Input high (logi c 1) vol tag e –V

IH VREF + 0.1 VDDQ + 0.3 V 2

Input low (logic 0) voltage –V

IL VSSQ - 0.3 VREF - 0.1 V 2

Output high current VOH = VDDQ/2 IOH (VDDQ/2)/

(1.15 × RQ/5) (VDDQ/2)/

(0.85 × RQ/5) A 9, 10, 11

Output low current VOL = VDDQ/2 IOL (VDDQ/2)/

(1.15 × RQ/5) (VDDQ/2)/

(0.85 × RQ/5) A 9, 10, 11

Clock input leakage current 0V ≤ VIN ≤ VDD ILC –5 5 µA

Input leakage current 0V ≤ VIN ≤ VDD ILI –5 5 µA

Output leakage current 0V ≤ VIN ≤ VDDQILO –5 5 µA

Reference voltage current –I

REF –5 5 µA

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Electrical Specifications – AC and DC

7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.

8. On-die termination may be selected using mode register bit 9 (see F igure 11 on page 32). A

resistance RTT from each data input signal to the nearest VTT can be enabled.

RTT = 125–185Ω at 95°C TC.

9. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the

device, IOL flows into the device.

10. If MRS bit A8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external imped-

ance matched resistor.

11. For VOL and VOH, refer to the RLDRAM II HSPICE or IBIS driver models.

Notes: 1. All volt ages refere nc ed to VSS (GND).

2. The AC and DC input level specifications are as defined in the HSTL standard (that is, the

receiver will effectively switch as a result of the signal crossing the AC input level, and will

remain in that state as long as the signal does not ring back above [below] the DC input

LOW [HIGH] level).

3. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range

between VIL(AC) and VIH(AC). See illustration below:

Table 8: Input AC Logic Levels

Notes 1–3 apply to entire table; Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V

Description Symbol Min Max Units

Input high (logic 1) voltage VIH VREF + 0.2 – V

Input low (logi c 0) voltage VIL –VREF - 0.2 V

VIH(AC) MIN

VIL(AC) MAX

Rise time:

2 V/ns Fall time:

2 V/ns

VDD

GND

VSWING

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Electrical Specifications – AC and DC

Notes: 1. DKx and DKx# have the same requirements as CK and CK#.

2. All voltages referenced to VSS (GND).

3. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK

and CK# cross. The inp ut reference level for signals other than CK/CK# i s VREF.

4. CK and CK# input slew rate must be ≥2 V/ns (≥4 V/ns if meas u re d di fferentially).

5. VID is the magnitude of the difference between the input level on CK and the input level on

CK#.

6. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track vari-

ations in the DC level of the same.

Figure 9: Clock Input

Notes: 1. CK and CK# must cross within this region.

2. CK and CK# must meet at least VID(DC) MIN when static and centered around VDDQ/2.

3. Minimum peak-to -peak swing.

4. It is a violation to tristate CK and CK# after the part is initialized.

Table 9: Differential Input Clock Operating Conditions

Notes 1–4 apply to the entire table; Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V

Parameter/Condition Symbol Min Max Units Notes

Clock input vol tage level: CK and CK# VIN(DC)–0.3VDDQ + 0.3 V

Clock input differential voltage: CK and CK# VID(DC)0.2VDDQ + 0.6V5

Clock input differential voltage: CK and CK# VID(AC)0.4VDDQ + 0.6V5

Clock input crossing point voltage: CK and CK# VIX(AC)VDDQ/2 - 0.15 VDDQ/2 + 0.15 V 6

CK#

VIN(DC) MAX

Maximum clock level

Minimum clock level

VIN(DC) MIN

Q/2

Q/2 + 0.15

Q/2 - 0.15 X X

X X

(

(AC) MAX

(AC) MIN

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Electrical Specifications – AC and DC

Input Slew Rate Derating

Table 10 on page 22 and Table 11 on page 23 define the address, command, and data

setup and hold derating va lues. These values are added to the default tAS/tCS/tDS and

tAH/tCH/tDH specifications when the slew rate of any of these input signals is less than

the 2 V/ns the nominal setup and hold specifications ar e based upon.

To determine the setup and hold time needed for a given slew rate, add the tAS/tCS

default specification to the “tAS/tCS VREF to CK/CK# Crossing” and the tAH/tCH default

specification to the "tAH/tCH CK/CK# Cr ossing to VREF" derated values on Table 10. The

derated data setup and hold values can be determined in a like manner using the “tDS

VREF to CK/CK# Crossing” and “tDH to CK/CK# Crossing to V REF” values on Table 11. The

derating values on Table 10 and Table 11 apply to all speed grades.

The setup times on Table 10 and Table 11 represent a rising signal. In this case, the time

from which the rising signal crosses VIH(AC) MIN to the CK/CK# cross point is static and

must be maintained across all slew rates. The derated setup timing represents the point

at which the rising signal crosses VREF(DC) to the CK/CK# cross point. This derate d value

is calculated by determining the time needed to maintain the given slew rate and the

delta between VIH(AC) MIN and the CK/CK# cross point. The setup values in Table 10

and Table 11 are also valid for falling signals (with respect to VIL[AC] MAX and the CK/

CK# cross point).

The hold times in Table 10 and Table 11 represent falling signals. In this case, the time

from the CK/CK# cross point to when the signal crosses VIH(DC) MIN is static and must

be maintained across all slew rates. The derated hold timi ng represents the delta

between the CK/CK# cross point to when the falling signal crosses VREF(DC). This

derated value is calculated by determining the time needed to maintain the given slew

rate and the delta between the CK/CK# cross point and VIH(DC). The hold values in

Table 10 and Table 11 are also valid for rising signals (with respect to VIL[DC] MAX and

the CK and CK# cross point).

Note: The abov e descriptions also pertain to data setup and hold derating when CK/CK# are

replaced with DK/DK#.

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Electrical Specifications – AC and DC

Table 10: Address and Command Set up and Hold Derating Values

Command/

Address Slew

Rate (V/ns) tAS/tCS VREF to

CK/CK# Crossing

tAS/tCS VIH(AC)

MIN to CK/CK#

Crossing tAH/tCH CK/CK#

Crossing to VREF

tAH/tCH CK/CK#

Crossing to

VIH(DC) MIN Units

CK, CK# Differential Slew Rate: 2.0 V/ns

2.0 0 –100 0 –50 ps

1.9 5 –100 3 –50 ps

1.8 11 –100 6–50 ps

1.7 18 –100 9 –50 ps

1.625 –100 13 –50 ps

1.533–10017 –50ps

1.443–10022 –50ps

1.354–10027 –50ps

1.2 67–10034 –50ps

1.182–10041 –50ps

1.0 100 –100 50 –50 ps

CK, CK# Differential Slew Rate: 1.5 V/ns

2.0 30 –70 30 –20 ps

1.9 35 –70 33 –20 ps

1.8 41 –70 36–20 ps

1.7 48 –70 39 –20 ps

1.655 –70 43 –20 ps

1.5 63 –70 47 –20 ps

1.4 73 –70 52 –20 ps

1.3 84 –70 57 –20 ps

1.2 97 –70 64–20ps

1.1 112 –70 71 –20 ps

1.0 130 –70 80 –20 ps

CK, CK# Differential Slew Rate: 1.0 V/ns

2.0 60–406010ps

1.9 65–406310ps

1.8 71 –40 66 10 ps

1.7 78 –40 6910ps

1.685 –40 73 10 ps

1.5 93 –40 77 10 ps

1.4 103 –40 82 10 ps

1.3 114 –40 87 10 ps

1.2 127 –40 94 10 ps

1.1 142 –40 101 10 ps

1.0 160 –40 110 10 ps

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Electrical Specifications – AC and DC

Table 11: Data Setup and Hold Derating Values

Data Slew Rate

(V/ns) tDS VREF to

CK/CK# Crossing tDS VIH(AC) MIN to

CK/CK# Crossing tDH CK/CK#

Crossing to VREF

tDH CK/CK#

Crossing to

VIH(DC) MIN Units

DK, DK# Differential Slew Rate: 2.0 V/ns

2.0 0 –100 0 –50 ps

1.9 5 –100 3 –50 ps

1.8 11 –100 6–50 ps

1.7 18 –100 9 –50 ps

1.625 –100 13 –50 ps

1.533–10017 –50ps

1.443–10022 –50ps

1.354–10027 –50ps

1.2 67–10034 –50ps

1.182–10041 –50ps

1.0 100 –100 50 –50 ps

DK, DK# Differential Slew Rate: 1.5 V/ns

2.0 30 –70 30 –20 ps

1.9 35 –70 33 –20 ps

1.8 41 –70 36–20 ps

1.7 48 –70 39 –20 ps

1.655 –70 43 –20 ps

1.5 63 –70 47 –20 ps

1.4 73 –70 52 –20 ps

1.3 84 –70 57 –20 ps

1.2 97 –70 64–20ps

1.1 112 –70 71 –20 ps

1.0 130 –70 80 –20 ps

DK, DK# Differential Slew Rate: 1.0 V/ns

2.0 60–406010ps

1.9 65–406310ps

1.8 71 –40 66 10 ps

1.7 78 –40 6910ps

1.685 –40 73 10 ps

1.5 93 –40 77 10 ps

1.4 103 –40 82 10 ps

1.3 114 –40 87 10 ps

1.2 127 –40 94 10 ps

1.1 142 –40 101 10 ps

1.0 160 –40 110 10 ps

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Electrical Specifications – AC and DC

Figure 10: Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate

Notes: 1. Capacitance is not tested on ZQ pin.

2. JTAG pins are tested at 50 MHz.

Table 12: Capacitance

Notes 1–2 apply to entire table

Description Symbol Conditions Min Max Units

Address/control input capacitance CITA = 25°C; f = 100 MHz

VDD = VDDQ = 1.8V 1.5 2.5 pF

Input/output capacitance (DQ, DM, and QK/QK#) CO3.5 5.0 pF

Clock capacitance (CK/CK#, and DK/DK#) CCK 2.0 3.0 pF

JTAG pins CJTAG 2.0 5.0 pF

VSWING (MAX)

VREF to AC

region

VREF to DC

region

VREF to DC

region

VREF to AC

region

VREF(DC)

VIL(DC) MAX

VIL(AC) MAX

VSSQ

VIH(DC) MIN

VIH(AC) MIN

VDDQ

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Electrical Specifications – AC and DC

Table 13: AC Electrical Characteristics: -25, -33, -5

Notes 1–4 (page 39) apply to the entire table

Description Symbol

-25 -33 -5

Units NotesMin Max Min Max Min Max

Clock

Input clock cyc le time tCK 2.5 5.7 3.3 5.7 5.0 5.7 ns

Input data clock cycle time tDK tCK tCK tCK ns

Clock jitter: period tJITPER –150 150 –200 200 –250 250 ps 5, 6

Clock jitter: cycle-to-cycle tJITCC 300 400 500 ps

Clock HIGH time tCKH,

tDKH 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock LOW time tCKL,

tDKL 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock to input data clock tCKDK –0.3 0.5 –0.3 1.0 –0.3 1.5 ns

Mode register set cycle time

to any command

tMRSC 6–6–6–tCK

Setup Times

Address/command and input

setup time

tAS/tCS0.4–0.5–0.8–ns

Data-in and data mask to DK

setup time

tDS 0.25 – 0.3 – 0.4 – ns

Hold Times

Address/command and input

hold time

tAH/tCH0.4–0.5–0.8–ns

Data-in and data mask to DK

hold time

tDH 0.25 – 0.3 – 0.4 – ns

Data and Data Strobe

Output data clock HIGH time tQKH 0.9 1.1 0.9 1.1 0.9 1.1 tCKH

Output data clo ck L OW ti me tQKL 0.9 1.1 0.9 1.1 0.9 1.1 tCKL

Half-clock period tQHP MIN (tQKH,

tQKL) –MIN (

tQKH,

tQKL) –MIN (

tQKH,

tQKL) –

QK edge to clock edge skew tCKQK –0.25 0.25 –0.3 0.3 –0.5 0.5 ns

QK edge to output data edge tQKQ0,

tQKQ1 –0.2 0.2 –0.25 0.25 –0.3 0.3 ns 7

QK edge to any output data

edge

tQKQ –0.3 0.3 –0.35 0.35 –0.4 0.4 ns 8

QK edge to QVLD tQKVLD –0.3 0.3 –0.35 0.35 –0.4 0.4 ns

Data valid window tDVW tQHP -

(tQKQx

[MAX] +

|tQKQx

[MIN]|)

–tQHP -

(tQKQx

[MAX] +

|tQKQx

[MIN]|)

–tQHP -

(tQKQx

[MAX] +

|tQKQx

[MIN]|)

–

Refresh

Average periodic refresh

interval

tREFI – 0.49 – 0.49 – 0.49 µs 9

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Electrical Specifications – AC and DC

Notes 1. All timing parameters are measured relative to the cros sing poin t of CK/CK #, DK/ DK#

and to the crossing point with VREF of the command, addres s, and data signals.

2. Outputs measured with equivalent load:

3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted

at nominal reference/supply volt age levels, but the related specifications and devic e

operations are tested for the full voltage r ange specified.

4. AC timing may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input

timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter

specifications are tested for the specified AC input level s under normal use condi-

tions. The minimum slew rate for the input signals used to test the device is 2 V/ns in

the range between VIL(AC) and VIH(AC).

5. Clock phase jitter is the variance from clock rising edge to the next expected clock ris-

ing edge.

6. Freq uenc y drift is not allowed.

7. tQK Q0 is r eferenc ed to DQ0–DQ17 for the x36 configuration and DQ0–DQ8 for the x18

configuration. tQKQ1 is referenced to DQ18–DQ35 for the x36 configuration and

DQ9–DQ17 for the x18 configuration.

8. tQKQ takes into account the skew between any QKx and any Q.

9. To impro ve efficiency, eight AREF commands (one for each bank) can be posted to the

RLDRAM on consecutive cycles at periodic intervals of 3.90µs.

10pF

50Ω

VTT

Test point

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Temperature and Thermal Impedance

It is imperative that the RLDRAM device’s temperature specifications, shown in Table 14,

be maintained in order to ensure the junction temperature is in the proper operating

range to meet data sheet specifications. An important step in maintaining the proper

junction temperature is using the device’s thermal impedances correctly. The thermal

impedances are listed for the packages available.

Incorr ectly using thermal impedances can produce significant errors. Read Micron tech-

nical note TN-00-08, “Thermal Applications” prior to using the thermal impedanc e s

listed in Table 14. For designs that are expected to last several years and r equire the flexi-

bility to use several DRAM die shrinks, consider using final target theta values (rather

than existing values) to account for increased thermal impedances from the die size

reduction.

The RLDRAM device’s safe junction temperature range can be maintained when the TC

specification is not exceeded. In applications where the device’s ambient temperatur e is

too high, use of forced air and/or heat sinks may be required in order to satisfy the case

temperature specifications.

Notes: 1. MAX storage case temperature; TSTG is measured in the center of the package, as shown in

Figure 10 on page 29. This c ase temperature limit is allowed to be exceeded briefly during

package reflow, as noted in Micron technical note TN-00-15.

2. Temperatures greater than 110°C may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at or above this is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability

of the part.

3. Junction temperature depends upon packag e type, cycle time, loading, ambient tempera-

ture, and airflow.

4. MAX operating case temperature; TC is measured in the center of the package, as shown in

Figure 10 on page 29.

5. Device functionality is not guaranteed if the device exceeds maximum TC during operation.

6. Both temperature specifications must be satisfied.

Table 14: Temperature Limits

Parameter Symbol Min Max Units Notes

Storage temperature TSTG –55 +150 °C1

Reliability junction temperature Commercial TJ–+110°C2

Industrial –+110°C2

Operating junction temperature Commercial TJ0+100°C3

Industrial –40 +100 °C3

Operating case temperature Commercial TC0+95°C4, 5

Industrial –40 +95 °C4, 5, 6

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Temperature and Thermal Impedance

Notes: Thermal impedance data is based on a number of samples from multiple lots and should be

viewed as a typical number.

Figure 11: Example Temperature Test Point Location

Table 15: Thermal Impedance

Package Substrate θ JA (°C/W)

Airflow = 0m/s θ JA (°C/W)

Airflow = 1m/s θ JA (°C/W)

Airflow = 2m/s θ JB (°C/W) θ JC (°C/W)

µBGA 2-layer 41.2 29.1 25.3 14.3 2.27

4-layer 28.2 21.9 19.9 13.6

FBGA 2-layer 42.2 29.3 25.3 16.4 2.6

4-layer 28.5 22.0 19.9 13.4

11.00

5.50

18.50

9.25

Test point

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Commands

Commands The following table provides descriptions of the va lid commands of the RLDRAM. All

input states or sequences not shown are illegal or reser ved. All command and address

inputs must meet setup and hold times around the rising edge of CK.

Notes: 1. When the chip is deselected, internal NOP commands are generated and no commands are

accepted.

2. n = 20.

Notes: 1. X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address.

2. n = 20.

3. Only A0–A17 are used for the MRS command.

4. Address width varies with burst length; see Table 19 on page 34 for details.

Table 16: Description of Commands

Command Description Notes

DSEL/NOP The NOP command is used to perform a no operation to the RLDRAM, which essentially

deselects the chip. Use the NOP command to prevent unwanted commands from being

registered during idle or wait states. Operations already in progress are not affected. Output

values depend on command history.

MRS The mode register is set via the address inputs A0–A17. See Figure 11 on page 32 for further

information. The MRS command can only be issued when all banks are idle and no bursts are

in progress.

READ The READ command is used to initiate a burst read access to a bank. The value on the BA0–

BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data

location within the bank.

WRITE The WRITE command is used to initiate a burst write acc ess to a bank. The valu e on th e BA0–

BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data

location within the bank. Input data appearing on the DQ is written to the memory array

subject to the DM input logic level appearing coincident with the data. If the DM signal is

registered LOW, the corresponding data will be written to memory. If the DM signal is

registered HIGH, the corresponding data inputs will be ignored (that is, this part of the data

word will not be written).

AREF The AREF command is used during normal operation of the RLDRAM to refresh the memory

content of a bank. The command is nonpersistent, so it must be issued each time a refresh is

required. The value on the BA0–BA2 inputs selects the bank . The refresh address is

generated by an internal refresh controller, effectively making each address bit a “Don’t

Care” during the AREF command. See “AUTO REFRESH (AREF)” on page 39 for more details.

Table 17: Command Table

Notes 1–2 apply to the entire table

Operation Code CS# WE# REF# A0–An2BA0–BA2 Notes

Device DESELECT/no operation DSEL/NOP H X X X X

MRS MRSLLLOPCODEX 3

READ READ L H H A BA 4

WRITE WRITE L L H A BA 4

AUTO REFRESH AREF L H L X BA

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MODE REGISTER SET (MRS)

The mode register set stor es the data for controlli ng the operating modes of the memory.

It programs the RLDRAM configuration, burst length, test mode, and I/O options.

During an MRS command, the address inputs A0–A17 are sampled and stored in the

mode register. After issuin g a valid MRS command, tMRSC must be me t be fore any

command can be issued to the RLDRAM. This statement does not apply to the consecu-

tive MRS commands needed for internal logic reset during the initialization routine. The

MRS command can only be issued when all bank s are idle and no bursts are in progress.

Note: The data written by the prior burst length is not guaranteed to be accurate when the

burst length of the device is changed.

DON’T CARE

CK#

CS#

WE#

REF#

OPCODEADDRESS

BANK

ADDRESS

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Figure 11: Mode Register Definition in Nonmultiplexed Address Mode

Notes: 1. A10–A17 must be set to zero; A18–An = “Don’t Care.”

2. A6 not used in MRS.

3. BL = 8 is not available.

4. DLL RESET turns the DLL off.

5. Available in 576Mb part only.

6. ±30 percent temperature variation.

ConfigBLAMReserved1

A9A10 A7 A6A5 A4 A3A8 A2 A1 A0

Mode Register (Mx)

Address Bus

9765438210

A17

17–10

Configuration

13 (default)

43,5

Reserved

Address MUX

Nonmultiplexed (default)

Multiplexed

Drive Impedance

Internal 50Ω6 (default)

External (ZQ)

On-Die Termination

Off (default)

DLL NA2

ODT

Burst Length

2 (default)

Reserved

. . .

DLL Reset

DLL reset4 (default)

DLL enabled

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Configuration Tables

Table 18 shows the different configurations that can be programmed into the mode

in ord er t o maximize data bus utilization. Bits M0, M1, and M2 are used to select the

configuration during the MRS command.

Notes: 1. BL = 8 is not available.

Burst Length (BL)

Burst length is defined by M3 and M4 of the mode register. Read and write accesses to

the RLDRAM are burst-oriented, with the burst length being programmable to 2, 4, or 8.

Figure 12 on page 34 illustrates the different burst lengths with respect to a READ

command. Changes in the burst length affect the width of the address bus (see Table 19

on page 34 for details).

Note: The data written by the prior burst length is not guaranteed to be accurate when the

burst length of the device is changed.

Table 18: Cycle Time and READ/WRITE Latency Configuration Table

Parameter

Configuration

Units112 3

tRC 4 68tCK

tRL 4 68tCK

tWL579

tCK

Valid frequency range 200–175 300–175 400–175 MHz

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Figure 12: Read Burst Lengths

Notes: 1. DO an = data-out from bank a and address an.

2. Subsequent elements of data-out appear after DO n.

3. Shown with nominal tCKQK.

Address Multiplexing

Although the RLDRAM has the ability to operate with an SRAM interface by accepting

the entire address in one clock, an option in the mode re gist er can be set so that it func-

tions with multiplexed addresses, similar to a traditional DRAM. In multiplexed address

mode, the address can be provided to the RLDR AM i n two part s th at are latched into the

memory with two consecutive rising clock edges. This provides the advantage of only

needing a maximum of 11 addr ess balls to contr ol the RLDRAM, r educi ng the number of

Table 19: Address Widths at Different Burst Lengths

Burst Length x9 x18 x36

2A0–A20 A0–A19 A0–A18

4A0–A19 A0–A18 A0–A17

8A0–A18 A0–A17 n/a

COMMAND

ADDRESS

QVLD

QK#

RL = 4

CK#

DON’T CARETRANSITIONING DATA

READ NOP NOP NOP NOP NOP NOP NOP

Bank a,

Col n

T0 T1 T2 T3 T4n T5nT4 T5 T6n T7nT6 T7

QVLD

BL = 2BL = 4BL = 8

NOP

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signals on the controller side. The data bus effi ci enc y in c onti nuous burs t mod e is only

affected when using the BL = 2 setting since the device requires two clocks to read and

write the data. The bank addresses are delivered to the RLDRAM at the same time as the

WRITE and READ command and the first address part, Ax. Table 21 on page 60 and

Table 22 on page 61 show the addre sses needed for both the first and second rising clock

edges (Ax and Ay, respectively). The AREF command does not re quire an address on the

second rising clock edge, as only the bank address is needed during this command.

Because of this, AREF commands may be issued on consecutive clocks.

The multiplexed address option is available by setting bit M5 to “1” in the mode register.

Once this bit is set, the READ, WRITE, and MRS commands follow the format described

in Figure 35 on page 57. Further information on operation with multiplexed addresses

can be seen in “ Multiplexed Ad dress Mode” on page 57.

DLL RESET

DLL R E SET is selected with bit M7 of the mode register as is shown in Figure 11 on

page 32. The default setting for this option is LOW, whereby the DLL is disabled. Once

M7 is set HIGH, 1,024 cycles (5µs at 200 MHz) are needed before a READ command can

be issued. This time allows the internal clock to be synchronized with the external clock.

Failing to wait for synchronization to occur may result in a violation of the tCKQK

parameter. A reset of the DLL is necessary if tCK or VDD is changed after the DLL has

already been enabled. To reset the DLL, an MRS command must be issu e d w here M7 is

set LOW. After waiting tMRSC, a subsequent MRS command should be issued whereby

M7 goes HIGH. 1,024 clock cycles are then needed before a READ command is issued.

Drive Impedance Matching

The RLDRAM II is equipped with programmable impedance output buffers. This option

is selected by setting bit M8 HIGH during the MRS command. The purpose of the

programmable impedance output buffers is to allo w the user to match the driver imped-

ance to the system. To adjust the impedance, an external precision resistor (RQ) is

connected betwee n the ZQ ball and VSS. The value of the r esistor must be five times the

desir ed impedance. For e x ample, a 300Ω resistor is required for an output impedance of

60Ω. The range of RQ is 125–300Ω, which guarantees output im pedance in the range of

25–60Ω (within 15 percent).

Output impedance updates may be required because over time variations may occur in

supply voltage and temperature . When the external drive impedance is enabled in the

MRS, the device will periodically sample the value of RQ. An impedance upda te is trans-

parent to the system and does not affect device operation. All data sheet timing and

current specifications are met during an update.

When bit M8 is set LOW during the MRS command, the RLDRAM provides an internal

impedance at the output buffer of 50Ω (±30 percent with temperature var ia tion). This

impedance is also periodically sampled and adjusted to compensate for variation in

supply voltage and temperature .

On-Die Termination (ODT)

ODT is enabled by setting M9 to “1” during an MRS command. With ODT on, the DQs

and DM are terminated to VTT with a resistance RTT. The command, address , QVLD, and

clock signals are not terminated. Figure 13 on page 36 shows the equivalent circuit of a

DQ recei v er with ODT. The ODT function is dynamically switched off when a DQ begins

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to drive after a READ command is issued. Similarly, ODT is designed to switch on at the

DQs after the RLDRAM has issued the last piece of data. The DM pin wil l always be

terminated. See section entitled “Operations” on page 40 for relevant timing diagrams.

Notes: 1. All voltages refe renced to VSS (GND).

2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.

3. The RTT value is measured at 95°C TC.

Figure 13: On-Die Termination-Equivalent Circuit

Table 20: On-Die Termination DC Parameters

Description Symbol Min Max Units Notes

Termination voltage VTT 0.95 × VREF 1.05 × VREF V1, 2

On-die termination RTT 125 185 Ω3

VTT

RTT

DQ Receiver

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WRITE

Write accesses are in itiated wi th a WRITE co mmand, as shown in Figur e14. The addr ess

needs to be provided during the WRITE command.

During WRITE commands, data will be r egistered at both edges of DK according to the

programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that

is one cycle longer than the programmed READ latency (RL + 1), with the first valid data

registered at the first rising DK edge WL cycles after the WRITE command.

Any WRITE burst may be followed by a subsequent READ command (assuming tRC is

met). To avoid external da ta bus contention, at least one NOP command is needed

between the WRITE and READ commands. Figure 21 on page 45 and Figure22 on

page 46 illustrate the timing requirements for a WRITE followed by a READ where one

and two intermediary NOPs are required, respectively.

Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and

tDH. The input data is mas ke d if th e corresponding D M sig nal is H IGH . The se tup and

hold times for the DM signal are also tDS and tDH.

Figure 14: WRITE Command

CK#

WE#

REF#

CS#

ADDRESS

BANK

ADDRESS BA

DON’T CARE

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READ

Re ad ac cesse s ar e in itia ted wi th a READ command, as shown in Figure 15. Addres ses are

provided with the READ command.

During READ bursts, the memory device drives the read data so it is edge-aligned with

the QKx signals. After a programmable READ latency, data is available at the outputs.

One half clock cy cle pri or to vali d data on the read bus, the data valid signal, QVLD, tran-

sitions from LOW to HIGH. QVLD is also edge-aligned with the QKx signals.

The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the

skew between QK0 and the last vali d data edge generate d at the DQ signals associated

with QK0 (tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8

for the x18 configuration). tQKQ1 is the skew between QK1 and the last valid data edge

generated at the DQ signals associated with QK1 (tQK Q1 is r efer enced to DQ18–DQ35 for

the x36 and DQ9–DQ17 for the x18 configuration). tQKQx is derived at each QKx clock

edge and is not cumulative over time. tQKQ is defined as the skew between either QK

differ ential pair and any output data edge.

After completion of a burst, assuming no other commands have been initiated, output

data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ

burst. Note that if CK/CK# violates the VID(DC) specification while a READ burst is occur-

ring, QVLD will remain HIGH until a dummy READ command is issued. The QK clocks

are free-running and will continue to cycle after the read burst is complete. Back-to-

back READ commands are possible, producing a continuous flow of output data.

The data valid window is derived from each QK transition and is defined as:

tQHP - (tQKQ [MAX] + |tQKQ [M IN]|). See Figures28–30 for illustration.

Any READ burst may be followed by a subsequent WRITE command. Figure 27 on

page 50 illustrate the timing requireme n ts for a READ followed by a WRITE. S ome

systems having long line lengths or severe skews may need additional idle cycles

inserted between READ and WRITE commands to prevent data bus contention.

Figure 15: READ Command

DON’T CARE

CK#

CS#

WE#

REF#

ADDRESS

BANK

ADDRESS

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AUTO REFRESH (AREF)

AREF is used to perform a REFRESH cycle on one ro w in a specific bank. Because the ro w

addresses are ge nerated by an internal refresh counter for each bank, the external

address balls are “Don’t Care.” The ba nk addresses must be provided during the AREF

command. The bank address is needed during the AREF command so refreshing of the

part can effectively be hidden behind comma nds to other banks. The delay between the

AREF command and a subsequent command to the same bank must be at least tRC.

Within a period of 32ms (tREF), the entire device must be r e freshed. For the 288Mb

device, the RLDRAM requir es 64K cycles at an average periodic interval of 0.49µs MAX

(actual periodic refresh interval is 32ms/8K rows/8 banks = 0.488µs). To impro ve effi-

ciency, eight AREF commands (one for each bank) can be posted to the RLDRAM at peri-

odic intervals of 3.9µs (32ms/8K rows = 3.90µs). Figure 31 on page 54 illustrates an

example of a refresh sequence.

Figure 16: AUTO REFRESH Command

CK#

WE#

REF#

CS#

ADDRESS

BANK

ADDRESS BA

DON’T CARE

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INITIALIZATION

The RLDRAM must be powered up and initialized in a predefined manner. Operational

procedur es other than those specifi ed may re sult in undefined oper ations or permanent

damage to the device.

The following sequence is used for power-up:

1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) and start clock as soon as the sup ply volt-

ages are stable. Apply VDD and VEXT before or at the same time as VDDQ.1 Apply VDDQ

before or at the same time as V

REF and VTT. Although there is no timing relation

between VEXT and VDD, the chip starts the power-up sequence only after both volt-

ages approach their nominal levels. CK/CK# must meet VID(DC) prior to being

applied.2 Apply NOP conditions to command pins. Ensuring CK/CK# meet VID(DC)

while applying NOP conditions to the command pins guarantees that the RLDRAM

will not receive unwanted commands during initiali zation.

2. Maintain stable conditions for 200µs (MIN).

3. Issue at least thr ee consecutive MRS commands: two or mor e dummi es plus one val id

MRS. The purpose of these consecutiv e MRS commands is to internally reset the logic

of the RLDRAM. N ote that tMRSC does not need to be met betwee n these consecutiv e

commands. It is recommended that all address pins are held LOW duri ng the dummy

MRS commands.

4. tMRSC after the valid MRS, an AUTO REFRESH command to all 8 banks (along with

1,024 NOP commands) must be issued prior to normal operation. The sequence of

the eight AUTO REFRESH commands (with r espect to the 1,024 NOP commands)

does not matter. As is required for any operation, tRC must be met betwe en an AUTO

REFRESH command and a subsequent VALID command to the same bank. Note that

older versions of the data sheet r equir ed each of these AUTO REFRESH commands be

separated by 2,048 NOP commands. This properly initializes the RLDRAM but is no

longer required.

Notes: 1. I t is possible to apply VDDQ before VDD. However, when doing this, the DQs , DM, and

all other pins with an output driver , will go HIGH instead of tri-s tating. These pins will

re main HIGH until VDD is at the sam e le ve l as VDDQ. Care should be taken to avoid

bus conflicts during this period.

2. If VID(DC) on CK/CK# can not be met pri or to b eing applie d to t he RLDRAM, placing a

large external resistor from CS# to VDD is a viable option for ensuring the command

bus does not receive unwanted commands during this unspecified state.

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Figure 17: Power-Up/Initialization Sequence

Notes: 1. Recommend all address pins held LOW during dummy MRS commands.

2. A10–A17 must be LOW.

3. DLL must be reset if tCK or VDD are changed.

4. CK and CK# must be separated at all times to prevent bogus commands from being issued.

5. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com-

mands) does not matter. As is requir ed for any operation, tRC must be met between an

AUTO REFRESH command and a subsequent VALID command to the same bank.

BANK ADDRESS

Power-up:

and stable

clock (CK, CK#)

T = 200µs (MIN)

()()

ADDRESS

REF

COMMAND NOPNOPNOP

()()

DON’T CARE

EXT

tMRSC Refresh

all banks51,024 NOP

commands

()()

MRSREF

CODE2

Bank 0 Bank 7

()()

MRSMRS

CODE1,2 CODE1,2

()()

VALID

CK#

tCKL

T0 T2T1

tCKH

tCKT3

()()

T8 T9

T6 T7

T4 T5

()()

DK#

tDKL

tDKH

tDK

()()

NOP

()()

REF

()()

High-Z

()()()()

()()

Indicates a break in

time scale

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Figure 18: Power-Up/Initialization Flow Chart

Notes: 1. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com-

mands) does not matter. As is requir ed for any operation, tRC must be met between an

AUTO REFRESH command and a subsequent VALID command to the same bank.

DD,

and V

EXT

ramp

Q ramp

Apply V

REF

and V

Apply stable CK/CK# and DK/DK#

Issue MRS command—A10–A17 must be LOW

Wait at least 200µs

Issue MRS command—A10–A17 must be LOW

Desired load mode register with A10–A17 LOW

Assert NOP for

MRSC

Issue AUTO REFRESH to bank 0

Issue AUTO REFRESH to bank 1

Issue AUTO REFRESH to bank 4

Issue AUTO REFRESH to bank 5

Issue AUTO REFRESH to bank 6

Issue AUTO REFRESH to bank 7

Valid command

Wait 1,024 NOP commands1

Step

Issue AUTO REFRESH to bank 3

Issue AUTO REFRESH to bank 2

MRS commands

must be on

consecutive clock

cycles

Voltage rails

can be applied

simultaneously

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WRITE

Figure 19: WRITE Burst

Notes: 1. DI an = data-in for bank a and address n; subsequent elements of burst are applied follow-

ing DI an.

2. BL = 4.

tCKDK (NOM)

COMMAND WRITE NOP NOP NOP NOPNOP

ADDRESS Bank a,

Add n

NOP

CK#

T0 T1 T2 T3 T4 T5 T5n T6 T6n T7

DK#

tCKDK (MIN)

tCKDK (MAX)

DON’T CARETRANSITIONING DATA

WL = 5

DK#

NOP

WL - tCKDK

WL + tCKDK

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Figure 20: Consecutive WRITE-to-WRITE

Notes: 1. DI an (or bn) = data-in fo r bank a (or b) and address n.

2. Three subsequent elements of the burst are applied follo wing DI for each bank.

3. BL = 4.

4. Each WRITE command may be to any bank; if the second WRITE is to the same bank,

tRC must be met.

5. Nominal conditions are assumed for specifications not defined.

CK#

COMMAND

WRITE NOP WRITE WRITE NOP NOP NOP NOP NOP

Bank a,

Add nBank b,

Add nBank a,

Add n

NOP

ADDRESS

T0 T1

T3 T4 T5 T6 T6nT5n T7 T8 T9T8nT7n

bn DI

DON’T CARETRANSITIONING DATA

WL = 5

tRC = 4

WL = 5

DK#

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Figure 21: WRITE-to-READ

Notes: 1. DI an = data-in for bank a an d ad dr ess n.

2. DO bn = data-out from bank b and address n.

3. Two su bsequent elements of each burst follow DI an and DO bn.

4. BL = 2.

5. Nominal conditions are assumed for specifications not defined.

COMMAND NOP READ NOP NOPNOP

ADDRESS Bank a,

Add n

NOP

CK#

T0 T1 T2 T3 T4 T5 T5n T6 T6n T7

an DO

DON’T CARE TRANSITIONING DATA

WL = 5

QVLD

DK#

QK#

NOP

Bank b,

Add n

WRITE

RL = 4

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Figure 22: WRITE-to-READ (Separated by Two NOPs)

Notes: 1. DI an = data-in for bank a and addr ess n.

2. DO bn = data-out from bank b and address n.

3. One subsequent element of each burst follow both DI an and DO bn.

4. BL = 2.

5. Only one NOP separating the WRITE and READ would have led to contention on the data

bus because of the input and output data timing conditions being used.

6. Nominal conditions are assumed for specifications not defined.

COMMAND NOP NOP READ NOP NOPNOP

ADDRESS Bank a,

Add n

CK#

T0 T1 T2 T3 T4 T5 T5n T6 T7nT7 T8

an DO

DON’T CARE

TRANSITIONING DATA

WL = 5

QVLD

DK#

QK#

NOP NOP

Bank b,

Add n

WRITE

RL = 4

tQKQ (MIN)

tCKQK (MIN)

tCKDK (MAX)

tDH

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Figure 23: WRITE – DM Operation

Notes: 1. DI an = data-in for bank a and address n.

2. Subsequent elements of burst are provided on following clock edges.

3. BL = 4.

4. Nominal conditions are assumed for specifications not defined.

CK#

DK#

tCKtCHtCL

T0 T1 T2 T3 T4 T5 T7nT6 T7 T8T6n

NOPNOP

COMMAND WRITE

Bank a,

Add n

NOPNOP NOP NOP NOP

tDKL tDKH

DON’T CARE

TRANSITIONING DATA

ADDRESS

WL = 5

NOP

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READ

Figure 24: Basic READ Burst Timing

Notes: 1. DO an = data-out from bank a and address an.

2. Three subsequent elements of the burst are applied following DO an.

3. BL = 4.

4. Nominal conditions are assumed for specifications not defined.

CK#

tCKtCHtCL

tQK tQKH tQKL

tRC = 4

RL = 4

T0 T1 T2 T3 T4 T5 T5n T6nT6 T7

QVLD

QK#

tCKQK

(

MIN)

CKQK

(

MIN)

NOPNOP

COMMAND READ

Bank a

Add nBank a

Add n

NOPNOP READ NOP NOP

tQK tQKH tQKL

DON’T CARETRANSITIONING DATA

ADDRESS

QVLD

QK#

tCKQK

(

MAX)

CKQK

(

MAX)

QKVLD

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Operations

Figure 25: Consecutive READ Bursts (BL = 2)

Notes: 1. DO an (or bn or cn) = data-out from bank a (or bank b or bank c) and address n.

2. One subsequent element of the burst from each bank appears after each DO x.

3. Nominal conditions are assumed for specifications not defined.

4. Example applies only when READ commands are issued to same device.

5. Bank address can be to any bank, but the subsequent READ can only be to the same bank if

tRC has been met.

6. Data from the READ commands to bank d through bank g will appear on subsequent clock

cycles that are not shown.

Figure 26: Consecutive READ Bursts (BL = 4)

Notes: 1. DO an (or bn) = data-out from bank a (or bank b) and address n.

2. Three subsequent elements of the burst from each bank appears after each DO x.

3. Nominal conditions are assumed for specifications not defined.

4. Example applies only when READ commands are issued to same device.

5. Bank address can be to any bank, but the subsequent READ can only be to the same bank if

tRC has been met.

6. Data from the READ commands to banks c and d will appear on subsequent clock cyc les

that are not shown.

COMMAND READ READ READ READ READ READ

ADDRESS

CK#

QK#

QVLD

RL = 4

an DO

bn DO

T0 T1 T2 T3

Bank a

Add n Bank b

Add n Bank c

Add n Bank d

Add nBank e

Add n Bank f

Add n Bank g

Add n

READ

T4nT4 T5 T6

T5n T6n

DON’T CARETRANSITIONING DATA

COMMAND READ NOP READ NOP READ NOP

ADDRESS Bank a

Add nBank b

Add nBank c

Add nBank d

Add n

CK#

QK#

QVLD

RL = 4

an DO

T0 T1 T2 T3

READ

T4nT4 T5 T6

T5n T6n

DON’T CARETRANSITIONING DATA

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Figure 27: READ-to-WRITE

Notes: 1. DO an = data-out from bank a and address n.

2. DI bn = data-in for bank b and address n.

3. Three subsequent elements of each burst follow DI bn and each DO an.

4. BL = 4.

5. Nominal conditions are assumed for specifications not defined.

CK#

COMMAND

ADDRESS

QVLD

READ

T0 T1 T2

DON’T CARETRANSITIONING DATA

WRITE NOP

T3 T4 T5

NOP NOP

NOP

WL = RL + 1 = 5

T7 T8

NOP NOP

DK#

QK#

an DI

RL = 4

Bank a,

Add nBank b,

Add n

NOP NOP

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Operations

Figure 28: Read Data Valid Window for x9 Device

Notes: 1. tQHP is defined as the lesser of tQK H or tQKL.

2. tQKQ0 is referenced to DQ0–DQ8.

3. Minimum data valid window (tDVW) can be expressed as

tQHP - (tQKQx [MAX] + |tQKQx [MIN]|).

QHP1

QKQ0 (MAX)2

QKQ0 (MIN)2

QKQ0 (MAX)2

QKQ0 (MIN)2

QKQ0 (MAX)2

DQ0

DQ8

DQ (last valid data)

DQ (first valid data)

All DQs and QKs collectively

QK0#

QK0

DVW3

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Operations

Figure 29: Read Data Valid Window for x18 Device

Notes: 1. tQHP is defined as the lesser of tQK H or tQKL.

2. tQKQ0 is referenced to DQ0–DQ8.

3. Minimum data valid window (tDVW) can be expressed as

tQHP - (tQKQx[MAX] + |tQKQx[MIN]|).

4. tQKQ1 is referenced to DQ9–DQ17.

5. tQKQ takes into account the skew between any QKx and any DQ.

QHP1

QKQ0 (MAX)2

QKQ0 (MIN)2

QKQ0 (MAX)2

DQ0

DQ8

DQ (last valid data)

DQ (first valid data)

All DQs and QKs collectively

QK0#

QK0

DVW3

QHP1

QKQ1 (MAX)4

QKQ1 (MIN)4

QKQ1 (MAX)4

DQ9

DQ17

DQ (last valid data)

DQ (first valid data)

All DQs and QKs collectively

QK1#

QK1

DVW3

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Operations

Figure 30: Read Data Valid Window for x36 Device

Notes: 1. tQHP is defined as the lesser of tQKH or tQKL.

2. tQKQ0 is referenced to DQ0–DQ17.

3. Minimum data valid window, tDVW, can be expressed as

tQHP - (tQKQx [MAX] + |tQKQx[MIN]|).

4. tQKQ1 is referenced to DQ18–DQ35.

5. tQKQ takes into account the skew between any QKx and any DQ.

QHP1

QKQ0 (MIN)2

QKQ0 (MAX)2

QKQ0 (MIN)2

QKQ0 (MAX)2

QKQ0 (MIN)2

QKQ0 (MAX)2

QKQ0 (MIN)2

DQ0

DQ17

DQ (last valid data)

DQ (first valid data)

All DQs and QKs collectively

QK0#

QK0

DVW3

Lower word

QHP1

QKQ1 (MIN)4

QKQ1 (MAX)4

QKQ1 (MIN)4

QKQ1 (MAX)4

QKQ1(MIN)

QKQ1(MAX)

QKQ1 (MIN)4

DQ18

DQ35

DQ (last valid data)

DQ (first valid data)

All DQs and QKs collectively

QK1#

QK1

DVW3

Upper word

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Operations

AUTO REFRESH

Figure 31: AUTO REFRESH Cycle

Notes: 1. AREFx = AUTO REFRESH command to bank x.

2. ACx = any command to bank x; ACy = any command to bank y.

3. BAx = bank address to bank x; BAy = bank address to bank y.

CK#

COMMAND AREFxACxAREFyACy

ADDRESS

BANK BAxBAy

tCKtCHtCL

DK, DK#

tRC

T0 T1 T2 T3

DON’T CARE

()()

Indicates a break in

time scale

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Operations

On-Die Termination

Figure 32: READ Burst with ODT

Notes: 1. DO an = data out from bank a and addres s n.

2. DO an is followed by the remaining bits of the burst.

3. Nominal conditions are assumed for specifications not defined.

COMMAND

ADDRESS

DQ ODT

QVLD

DQ ODT off

QK#

RL = 4

CK#

DQ ODT

DON’T CARETRANSITIONING DATA

READ NOP NOP NOP NOP NOP NOP NOP

Bank a,

Col n

T0 T1 T2 T3 T4n T5nT4 T5 T6n T7nT6 T7

QVLD

BL = 2BL = 4BL = 8

NOP

DQ ODT on DQ ODT on

DQ ODT off

DQ ODT on on

DQ ODT off

DQ ODT on DQ ODT on

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Figure 33: READ-NOP-READ with ODT

Notes: 1. DO an (or bn) = data-out from bank a (or bank b) and address n.

2. BL = 2.

3. One subsequent element of the burst appear after DO an and DO bn.

4. Nominal conditions are assumed for specifications not defined.

Figure 34: READ-to-WRITE with ODT

Notes: 1. DO an = data-out from bank a and address n; DI bn = data-in for bank b and address n.

2. BL = 2.

3. One subsequent element of each burst appears after ea ch DO an and DI bn.

4. Nominal conditions are assumed for specifications not defined.

COMMAND

ADDRESS

DQ ODT

QVLD

an DO

DQ ODT off DQ ODT off

QK#

RL = 4

CK#

DON’T CARETRANSITIONING DATA

READ NOP READ NOP NOP NOP NOP NOP

Bank a,

Col nBank b,

Col n

T0 T1 T2 T3 T4nT4 T5 T6nT6 T7

NOP

DQ ODT on DQ ODT on DQ ODT on

CK#

COMMAND

ADDRESS

RL = 4

QKx

QKx#

an DI

READ

Bank a

Add n

WRITE NOP NOP NOP NOP NOP NOP NOP

DON’T CARE

UNDEFINED

ODT ODT on

ODT on ODT off

WL = 5

DKx#

DKx

Bank b

Add n

T0 T1 T2 T3 T4 T5 T6T7 T8 T9T4n T6n

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Operations

Multiplexed Address Mode

Figure 35: Command Description in Multiplexed Address Mode

Notes: 1. The minimum setup and hold times of the two address parts are defined tAS and tAH.

BA BA BA

ADDRESS

BANK

ADDRESS

AxAyAxAy

AxAy

MRSREFWRITEREAD

DON’T CARE

CK#

CS#

WE#

REF#

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Figure 36: Power-Up/Initialization Sequence in Multiplexed Address Mode

Notes: 1. Recommended that all address pins held LOW during dummy MRS commands.

2. A10–A18 must be LOW.

3. Set address A5 HIGH. This enbles the part to enter multiplexed address mode when in non-

multiplexed mode operation. Multiplexed address mode can also be entered at some later

time by issuing an MRS command with A5 HIGH. Once address bit A5 is set HIGH, tMRSC

must be satisfied before the two-cycle multiplexed mode MRS command is issued.

4. Address A5 must be set HIGH. This and the following step set the desired mode register

once the RLDRAM is in multiplexed address mode.

5. Any command or address.

6.The above sequence must be followed in order to power up the RLDRAM in the multiplexed

address mode.

7. DLL must be reset if tCK or VDD are changed.

8. CK and CK# must separated at all times to prevent bogus commands from being issued.

9. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP com-

mands) does not matter. As is requir ed for any operation, tRC must be met between an

AUTO REFRESH command and a subsequent VALID command to the same bank.

BANK

ADDRESS

Power-up:

VDD and stable

clock (CK, CK#)

T = 200µs (MIN)

()()

ADDRESS

REF

COMMAND NOPNOPNOP

()()

DON’T CARE

EXT

tMRSC tMRSC Refresh

all banks91,024 NOP

commands

()()

MRSMRS

CODE2,3 Ax2,4

()()

MRSMRS

CODE1,2 CODE1,2

()()

VALID5

CK#

tCKL

T0 T1 T2

tCKH

tCKT3

()()

T8 T9 T10 T11

T6 T7

T4 T5

()()

DK#

tDKL

tDKH

tDK

()()

NOP

High-Z

()()()()()()()()

()()

Bank 7

()()

NOP REF REF

()()

Ay2

Bank 0

()()

Indicates a break in

time scale

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Figure 37: Mode Register Definition in Multiplexed Address Mode

Notes: 1. Bits A10–A18 must be set to zero.

2. BL = 8 is not available.

3. ±30 percent temperature variation.

4. DLL RESET turns the DLL off.

5. Ay8 not used in MRS.

6. Available only in 576Mb device.

7. BA0–BA2 are “Don’t Care.”

8. Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode

2103458918–1076ConfigBLAMReserved1Mode Register (Mx)

Configuration

12 (default)

42,6

Reserved

Address MUX

Nonmultiplexed (default)

Multiplexed

Drive Impedance

Internal 50Ω3 (default)

External (ZQ)

On-Die Termination

Off (default)

DLL NA5

DLL Reset

DLL reset4 (default)

DLL enabled

ODT

Burst Length

2 (default)

Reserved

A3A4A8A9Ay. . .A18 A0A3A4A5A8A9

AxA10

. . .A18 A10

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Address Mapping in Multiplexed Address Mode

Notes: 1. X = “Don’t Care.”

Table 21: 288Mb Address Mapping in Multiplexed Address Mode

Data

Width Burst

Length Ball

Address

A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18

x362AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18

AyXA1A2XA6A7 X A11 A12 A16A15

4AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 X

AyXA1A2XA6A7 X A11 A12 A16A15

x18 2 AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18

AyXA1A2XA6A7 A19 A11 A12 A16A15

4AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18

AyXA1A2XA6A7 X A11 A12 A16A15

8AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 X

AyXA1A2XA6A7 X A11 A12 A16A15

x9 2 AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18

AyA20 A1 A2 X A6A7 A19 A11 A12 A16A15

4AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18

AyXA1A2XA6A7 A19 A11 A12 A16A15

8AxA0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18

AyXA1A2XA6A7 X A11 A12 A16A15

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Operations

Configuration Tables in Multiplexed Address Mode

In multiplexed address mode, the read and write latencies are increased by one clock

cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed

address mode.

Notes: 1. BL = 8 is not available.

REFRESH Command in Multiplexed Address Mode

Simi lar to other commands when in multiple xed addr ess mode , AREF is exe cuted on the

rising clock edge following the one on which the command is issued. However, since

only the bank address is required for AREF, the next command can be applied on the

following clock. The operation of the AREF command and any other command is repre-

sented in Figure38 on page 61.

Figure 38: BURST REFRESH Operation with Multiplexed Addressing

Notes: 1. Any command.

2. Bank n is chosen so that tRC is met.

Table 22: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode

Parameter

Configuration

Units112 3

tRC 4 68tCK

tRL579

tCK

tWL 6810

tCK

Valid frequency range 200–175 300–175 400–175 MHz

CK#

COMMAND

AC1NOP

AREF AREF AREF AREFAREF AREF AREF AREF AC1

BANK

Bank 0Bank nBank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank n

ADDRESS

AxAy

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11

DON’T CARE

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Figure 39: Consecutive WRITE Bursts with Multiplexed Addressing

Notes: 1. Data from the second WRITE command to bank a will appear on subsequent clock cycles

that are not shown.

2. DI a = data-in for bank a; DI b = data-in for bank b.

3. Three subsequent elements of the burst are applied follo wing DI for each bank.

4. Each WRITE command may be to any bank; if the second WRITE is to the same bank, tRC

must be met.

CK#

COMMAND

WRITE NOP

WRITE WRITE NOP NOP NOP NOP NOP

BANK

Bank a

NOP

Bank bBank a1

ADDRESS

AxAxAxAy

T0 T1 T2 T3 T4 T5 T6 T6n T7 T8 T9T8nT7n

DON’T CARETRANSITIONING DATA

WL = 6

tRC = 4

DK#

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Figure 40: WRITE-to-READ with Multiplexed Addressing

Notes: 1. DI a = data-in for bank a.

2. DO b = data-out from bank b.

3. One subsequent element of each burst follows DI a and DO b.

4. BL = 2.

5. Nominal conditions are assumed for specifications not defined.

6. Bank address can be to any bank, but the subsequent READ can only be to the same bank if

tRC has been met.

COMMAND

NOP READ NOP NOPNOP

ADDRESS

AxAy

NOP

CK#

T0 T1 T2 T3 T4 T5 T6 T6n T7nT7

DON’T CARETRANSITIONING DATA

WL = 6

QVLD

DK#

QK#

NOP

BANK

Bank aBank b

WRITE

RL = 5

AxAy

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Figure 41: Consecutive READ Bursts with Multiplexed Addressing

Notes: 1. DO a = data-out from bank a.

2. Nominal conditions are assumed for specifications not defined.

3. BL = 4.

4. Three subsequent elements of the burst appear following DO a.

5. Example applies only when READ commands are issued to same device.

6. Bank address can be to any bank, but the subsequent READ can only be to the same bank if

tRC has been met.

7. Data from the READ commands to banks b through bank d will appear on subsequent clock

cycles that are not shown.

COMMAND READ NOP READ NOP READ NOP

ADDRESS AxAy

Bank a

CK#

QK#

BANK

QVLD

RL = 5

T0 T1 T2 T3

READ

T4 T5 T6T5n T6n

DON’T CARETRANSITIONING DATA

Bank bBank cBank d

AxAxAx

AyAy

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Figure 42: READ-to-WRITE with Multiplexed Addressing

Notes: 1. DO an = data-out from bank a.

2. DI bn = data-in for bank b.

3. Nominal conditions are assumed for specifications not defined.

4. BL = 4.

5. Three subsequent elements of the burst are applied following DO an.

6.Three subsequent elements of the burst which appear following DI bn are not all shown.

7. Bank address can be to any bank, but the WRITE command can only be to the same bank if

tRC has been met.

CK#

COMMAND

ADDRESS

BANK

QVLD

READ

T0 T1 T2

DON’T CARETRANSITIONING DATA

WRITE NOP

T3 T4 T5 T5n

NOP NOP

T6 T6n

NOP

WL = RL + 1 = 6

T7 T8 T8n

NOP NOP

DK#

QK#

an DI

RL = 5

AxAyAy

Bank a

Bank b

NOP NOP

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IEEE 1149.1 Serial Boundary Scan (JTAG)

RLDRAM incorporates a serial boundary-scan test access port (TAP) for the purpose of

testing the connectivity of the device once it has been mounted on a printed circuit

board (PCB). As the complexity of PCB high-de nsity surface mounting techniques

increases, the boundary-scan architecture is a valuable resource for interconnectivity

debug. This port operates in accordance with IEEE Standard 1149.1-2001 (JTAG) with

the excepti on of the ZQ pin. To ensure proper boundary-scan testing of the ZQ pin, MRS

bit M8 needs to be set to 0 until the JTAG testing of the pin is complete. Note that upon

power up, the default state of MRS bit M8 is low.

If the RLDRAM boundary scan register is to be used upon power up and prior to the

initialization of the RLDRAM device, it is imperative that the CK and CK# pins meet

VID(DC) or CS# be held HIGH from power up until testing. Not doing so could result in

inadvertent MRS commands to be loaded, an d subsequently cause unexpected results

from address pins that are dependent upon the state of the mode register. If these

measures cannot be taken, the part must be initialized prior to boundary scan testing. If

a full initialization is not practical or feasible prior to boundary scan testing, a single

MRS command with desired settings may be issued instead. After the single MRS

command is issued, the tMRSC parameter must be satisfied prior to boundary scan

testing.

The input signals of the test access port (TDI, TMS, and TCK) use VDD as a supply, while

the output signal of the TAP (TDO) uses VDDQ.

The JTAG test access port utilizes the TAP controller on the RLDRAM, from which the

instruction register, boundar y scan register, bypass register, and ID register can be

selected. Each of these functions of the TAP controller is described in detail below.

Disabling the JTAG Feature

It is possible to operate RLDRAM without using the JTAG feature. To disable the TAP

controller, TCK must be tied LOW (VSS) to preve n t clocking of the device. TDI and TMS

are in ternally pulled up and may be unconnected. They may alte rnately be conne cted to

VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the

device will come up in a reset state, which will not interfere with the operation of the

device.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only w it h the TAP controll er. Al l inp u ts are captured on the rising

edge of TCK. Al l outputs ar e driven from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the

rising edge of TCK.

All of the states in Figure 43: “TAP Controller State Diagram,” on page 68 are entered

through the serial input of the TMS pin. A “0” in the diagram represents a LOW on the

TMS pin during the rising edge of TCK while a “1” represents a HIGH on TMS.

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IEEE 1149.1 Serial Boundary Scan (JTAG)

Test Data-In (TDI)

The TDI ball is used to serially input test instructions and data into the registers and can

be connected to the input of any of the registers. The register between TDI and TDO is

chosen by the instruction that is loaded into the TAP instructio n register. For informa-

tion on loading the instruction r egister, see F igur e 43 on page 68. TDI is connected to the

most significant bit (MSB) of any register (see Figure 44 on page 68).

Test Data-Out (TDO)

The TDO output ball is used to serially clock test instructions and data out from the

registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP

controller states. I n all other states, the TDO pin is in a High-Z state. The output changes

on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any

TAP Controller

The TAP controller is a finite state machine that uses the state of the TMS pin at the

rising edge of TCK to navigate through its various modes of operation. The TAP

controller state diagram can be seen in Figure43 on page 68. Each state is described in

detail below.

Test-Logic-Reset

The test-logic-reset controller state is entered when TMS is held HIGH for at least five

consecutive rising edges of TCK. As long as TMS remains HIGH, the TAP controller will

remain in the test-logic-reset state. The test logic is inactive during this state.

Run-Test/Idle

The run-test/idle is a controller state in between scan operations. This state can be

maintained by holding TMS LOW. From here either the data registe r scan, or subse-

quently, the instruction register scan can be selected.

Select-DR-Scan

Select-DR-scan is a temporary controller state. All test data registers retain their previous

state while here.

Capture-DR

The capture-DR state is where the data is parallel-loaded into the test data registers. If

the boundary scan register is the currently selected register, then the data currently on

the pins is latched into the test data registers.

Shift-DR

Data is shifted serially through the data register while in this state. As new data is input

through the TDI pin, data is shifted out of the TDO pin.

Exit1-DR, Pause-DR, and Exit2-DR

The purpose of exit1-DR is used to provide a path to return back to the run-test/idle

state (through the update-DR state). The pause-DR state is entered when the shifting of

data through the test registers needs to be suspended. When shifting is to reconvene, the

controller enters the exit2-DR state and then can re-enter the shift-DR state.

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Update-DR

When the EXTEST instruction is selected, there are latched parallel outputs of the

boundar y-scan shift register that only change sta te d uring the update-DR controller

state.

Instruction Register States

The instruction r egister s tates of the TAP controller ar e similar to the data register states.

The desired instruction is serially shif ted into the instruction register during the shift-IR

state and is loaded during the update-IR state.

Figure 43: TAP Controller State Diagram

Figure 44: TAP Controller Block Diagram

Notes: 1. x = 112 for all configurations.

Capture-IR

Shift-IR

Exit1-IR

Pause-IR

Exit2-IR

Update-IR

1 1

0 0

1 1

0 0

1 0

Test-logic

reset

Run-test/

Idle Select

IR-scan

Select

DR-scan

Capture-DR

Shift-DR

Exit1-DR

Pause-DR

Exit2-DR

Update-DR

01234567

012293031 ...

012.. ...

TCK

TMS

Selection

circuitry Selection

circuitry

TDO

TDI

Boundry scan register

Identification register

Instruction register

TAP controller

Bypass register

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Performing a TAP RESET

A reset is performed by forcing TMS HIGH (VDDQ) for five rising edges of TCK. This

RESET does not affect the operation of the RLDRAM and may be performed while the

RLDRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO bal ls a nd all ow data to be scanned

into and out of the RLDRAM test circuitry. Only one register can be selected at a time

through the instr ucti o n register. Data is serially loaded into the TDI ball on the rising

edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Eight-bit instructions can be s erially loaded int o the ins truction register. This register is

loaded during the update-IR state of the TAP controller. Upon power - up, the instruction

instruction if the controller is placed in a reset state as describe d in the previou s section.

When the TAP controller is in the captur e-IR state , the two LSBs are loaded with a binary

“01” pattern to allow for fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is sometimes advantageo us

to skip cert ain chips. The by pas s register is a sing le -bit register that can be placed

between the TDI and TD O bal ls. This allows data to be shifted through the RLDRAM

with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is

executed.

Boundary Scan Register

The boundary scan register is connected to all the input and bidirectional balls on the

RLDRAM. Several balls are also included in the scan register to rese rved balls. The

RLDRAM has a 113-bit regis t er.

The boundary scan register is loaded with the contents of the RAM I/O ring when the

TAP controller is in the capture-DR state and is then placed between the TDI and TDO

balls when the controller is moved to the shift-DR st ate.

Table 29 on page 74 shows the order in which the bits are connected. Each bit corre-

sponds to one of the balls on the RLDRAM package. The MSB of the register is connected

to TDI, and the LSB is connected to TDO.

Identification (ID) Register

The ID regi ster is l oaded with a v endor-specific, 32-bit code during the capture-DR state

when the IDCODE command is loaded in the instruction register. The IDCODE is hard-

wire d into the RLDRAM and can be shifted out when the TAP controller is in the shift-DR

state. The ID register has a vendor code and other information described in Table 26 on

page 73.

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TAP Instruction Set

Overview

Many different instructions (28) are possible with the 8-bit instruction register. All

combinations used are listed in Table 28 on page 74. These six instructions ar e described

in detail below. The remaining ins truc tions are reserved and should not be used.

The TAP controller used in this RLDRAM is fully compliant to the 1149.1 co nvent ion .

Instructions are loaded into the TA P cont roller du ring the shift-IR state w hen the

instructio n register is placed be twe en TD I and TD O. Dur ing th is stat e, instructi ons are

shifted through the instruction register through the TDI and TDO balls. To execute the

instruction once it is shifted in, the TAP controller needs to be moved into the update-IR

state.

EXTEST

The EXTEST instruction allo ws cir cuitry external to the component package to be tested.

Boundary -scan r egister c ells at output balls are used to apply a test vector, while those at

input balls capture test results. Typically, the first test vector to be applied using the

EXTEST instruction will be shifted into the boundary scan register using the PRELOAD

instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on,

and the PRELOAD data is driven onto the output balls.

IDCODE

The IDCODE instr u c tion causes a vendor-specific, 32-bit cod e to be load e d into the

instruction register. I t also places the instruction register between the TDI and TDO balls

and allows the IDCODE to be shifted out of the device when the TAP controller enters

the shift-DR state. The IDCODE instruc ti on is lo ade d into the instruction register upon

power-up or whenever the TAP controller is given a test logic reset state.

High-Z

The High-Z instruction causes the boundary scan register to be connected between the

TDI and TDO. This places all RLDRAM outputs into a High-Z state.

CLAMP

When the CLAMP instruction is loaded into the instruction register, the data driven by

the output balls are determined from the values held in the boundary scan register.

SAMPLE/PRELOAD

When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the

TAP con troll er is in th e capture-DR state, a snapshot of data on the inputs and bidirec-

tional balls is captured in the boundary scan register.

The user must be aware that the TAP controller clock can only operate at a fre quency up

to 50 MHz, while the RLDRAM clock operates signi ficantly faste r. Because there is a large

differ ence between the clock fr equencie s, it is possible that during the captur e-DR state,

an input or output will undergo a transition. The TAP may then tr y to cap ture a signal

while in transi tion (me tastabl e stat e). This wil l not harm the devi ce, but there is no guar-

antee as to the value that will be captured. Repeatable results may not be possible.

To ensure that the boundary scan re gister will capture the correct value of a signal, the

RLDRAM signal mus t be stab il ized long enough to mee t the TAP con troll er’s capture

setup plus hold time (tCS plus tCH). The RLDRAM clock input might not be captured

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correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/

PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and

simply ignore the value of the CK and CK# captured in the boundary scan regis ter.

Once the data is captured, it is possible to shift out the data by putting the TAP into the

shift-DR state. This places the boundary scan register between the TDI and TDO balls.

BYPASS

When the BYPASS instruction is loaded in the instruction register and the TAP is placed

in a shift-DR state, the bypass register is placed between TDI and TDO. The advantage of

the BYPASS instruction is that it shortens the boundary scan path when multiple devices

are connected together on a board.

Reserved for Future Use

The remaining instructions are not implemented but are res erved for futur e use. Do not

use these instructions.

Figure 45: JTAG Operation – Loading In struction Code and Shifting Out Data

TMS

TDI

TCK

TDO

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

TAP

CONTROLLER

STATE

Test-Logic-

Reset Run-Test

Idle Capture-IR Shift-IR

Select-DR-

SCAN Select-IR-

SCAN

()()

Pause-IR Pause-IRShift-IR Exit 1-IR

()()

8-bit instruction code

DON’T CARETRANSITIONING DATA

TMS

TDI

TCK

TDO

TAP

CONTROLLER

STATE

T10 T11 T12 T13 T14 T15 T16 T17 T18

Exit 2-IR Select-DR-

Scan Capture-DR Shift-DR Shift-DR Exit1-DR Update-DR Run-Test

Idle

Update-IR

()()

n-bit register between TDI and TDO

T19

Run-Test

Idle

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Figure 46: TAP Timing

Notes: 1. tCS and tCH refer to the setup and hold time requirements of latc hing data from the bou nd-

ary scan register.

Table 23: TAP Input AC Logic Levels

+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted

Description Symbol Min Max Units

Input high (logi c 1) vol tag e VIH VREF + 0.3 – V

Input low (logic 0) voltage VIL –VREF - 0.3 V

Notes: 1. All voltages refe renced to VSS (GND).

Table 24: TAP AC Electrical Characteristics

+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V

Description Symbol Min Max Units

Clock

Clock cycle time tTHTH 20 ns

Clock frequency fTF 50 MHz

Clock HIGH time tTHTL 10 ns

Clock LOW time tTLTH 10 ns

TDI/TDO times

TCK LOW to TDO unknown tTLOX 0 ns

TCK LOW to TDO valid tTLOV 10 ns

TDI valid to TCK HIGH tDVTH 5 ns

TCK HIGH to TDI invalid tTHDX 5 ns

Setup times

TMS setup tMVTH 5 ns

Capture setup tCS 5 ns

Hold times

TMS hold tTHMX 5 ns

Capture hold tCH 5 ns

DON’T CARE

tTLTH

tTHTL tTHTH

tTHMX

tMVTH

tTHDX

tDVTH

tTLOX

tTLOV

UNDEFINED

Test clock

(TCK)

Test mode select

(TMS)

Test data-in

(TDI)

Test data-out

(TDO)

T1 T2 T3 T4 T5 T6

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Notes: 1. All voltages refe renced to VSS (GND).

2. Overshoot = VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2; undershoot = VIL(AC) ≥ –0.5V for t ≤ tCK/2;

during normal operation, VDDQ must not exceed VDD.

Table 25: TAP DC Electrical Characteristics and Operating Conditions

+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted

Description Condition Symbol Min Max Units Notes

Input high (logi c 1) vol tag e VIH VREF + 0.15 VDD + 0.3 V 1, 2

Input low (logic 0) voltage VIL VSSQ - 0.3 VREF - 0.15 V 1, 2

Input leakage current 0V ≤ VIN ≤ VDD ILI–5.0 5.0 µA

Output leakage current Output disabled,

0V ≤VIN ≤VDDQILO–5.0 5.0 µA

Output low voltage IOLC = 100µA VOL10.2V1

Output low voltage IOLT = 2mA VOL20.4V1

Output high voltage |IOHC| = 100µA VOH1VDDQ - 0.2 V 1

Output high voltage |IOHT| = 2mA VOH2VDDQ - 0.4 V 1

Table 26: Identification Register Definitions

Instruction Field All Devices Description

Revision number (31:28) abcd ab = die revision

cd = 00 for x9, 01 for x18, 10 for x36

Device ID (27:12) 00jkidef10100111 def = 000 for 288Mb, 001 for 576Mb

i = 0 for common I/O, 1 for separate I/O

jk = 01 for RLDRAM II, 00 for RLDRAM

Micron JEDEC ID code (11:1) 00000101100 Allows unique identification of RLDRAM vendor

ID register presence indicator (0) 1Indicates the presence of an ID register

Table 27: Scan Register Sizes

Instruction 8

Bypass 1

ID 32

Boundary scan 113

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Table 28: Instruction Codes

Instruction Code Description

Extest 0000 0000 Captures I/O ring contents; Places the boundary scan regist er between TDI and TDO;

This operation does not affect RLDRAM operations

ID code 0010 0001 Loads the ID register with the vendor ID code and places the register between TDI and

TDO; This operation does not affect RLDRAM operations

Sample/preload 0000 0101 Captures I/O ring contents; Plac es the boundary scan register between TDI and TDO

Clamp 0000 0111 Selects the bypass register to be connected between TDI and TDO; Data driven by

output balls ar e determined from values held in the boundar y scan register

High-Z 0000 0011 Selects the bypass register to be connected between TDI and TDO; All outputs are

forced into High-Z

Bypass 1111 1111 Places the bypass register between TDI and TDO; This operation does not affect

RLDRAM operations

Table 29: Boundary Scan (Exit) Order

Bit# Ball Bit# Ball Bit# Ball

1K139R1177C11

2K240R1178C11

3L241P1179C10

4L142P1180C10

5M143P1081B11

6M3 44 P10 82 B11

7 M2 45 N11 83 B10

8N146N11 84 B10

9 P1 47 N10 85 B3

10 N3 48 N10 86B3

11 N3 49 P12 87 B2

12 N2 50 N12 88 B2

13 N2 51 M11 89 C3

14 P3 52 M10 90 C3

15 P3 53 M12 91 C2

16P2 54 L12 92 C2

17 P2 55 L11 93 D3

18 R2 56K11 94 D3

19 R3 57 K12 95 D2

20 T2 58 J12 96D2

21 T2 59 J11 97 E2

22 T3 60 H11 98 E2

23 T3 61 H12 99 E3

24 U2 62G12100E3

25 U2 63G10101F2

26U3 64G11102F2

27 U3 65 E12 103 F3

28 V2 66 F12 104 F3

29 U10 67F10105E1

30 U10 68F10106F1

31 U11 69F11107G2

32 U11 70 F11 108 G3

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Qimonda AG in various

countries, and is used by Micron Technology, Inc. under license from Qimonda. All other trademarks are the property of their respective

owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.

Although considered final, these specifications are subject to change, as further product development and data characterization some-

times occur.

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33 T10 71 E10 109 G1

34 T10 72 E10 110 H1

35 T11 73 E11 111 H2

36T11 74 E11 112 J2

37 R10 75 D11 113 J1

38 R10 76D10 – –

Table 29: Boundary Scan (Exit) Order (continued)

Bit# Ball Bit# Ball Bit# Ball