Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16646T CY74FCT162646T 16-Bit Registered Transceivers SCCS060B - August 1994 - Revised September 2001 Features Functional Description * Ioff supports partial-power-down mode operation * Edge-rate control circuitry for significantly improved noise characteristics * Typical output skew < 250 ps * ESD > 2000V * TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages * Industrial temperature range of -40C to +85C * VCC = 5V 10% CY74FCT16646T Features: * 64 mA sink current, 32 mA source current * Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25C CY74FCT162646T Features: * Balanced 24 mA output drivers * Reduced system switching noise * Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA= 25C The CY74FCT16646T and CY74FCT162646T 16-bit transceivers are three-state, D-type registers, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a HIGH logic level. Output Enable (OE) and direction pins (DIR) are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register, or in both. The select controls can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when the Output Enable (OE) is Active LOW. In the isolation mode (Output Enable (OE) HIGH), A data may be stored in the B register and/or B data may be stored in the A register. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16646T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162646T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162646T is ideal for driving transmission lines. Logic Block Diagrams 2OE 1OE 2DIR 2CLKBA 2SBA 2CLKAB 1DIR 1CLKBA 1SBA 1CLKAB 2SAB 1SAB B REG B REG D D C C 2A1 1A1 A REG D 1B1 A REG D 2B1 C C TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS FCT16646-2 FCT16646-1 Copyright (c) 2001, Texas Instruments Incorporated CY74FCT16646T CY74FCT162646T Pin Configuration SSOP/TSSOP Top View 1DIR 1 56 1OE 1CLKAB 1SAB 2 55 3 54 1CLKBA 1SBA GND 4 53 GND 1A1 5 52 1B1 1A2 VCC 1A3 6 51 1B2 7 50 VCC 8 49 1B3 1A4 9 48 1B4 1A5 10 47 1B5 GND 11 46 GND 1A6 12 45 1B6 1A7 13 44 1B7 1A8 14 43 1B8 2A1 15 42 2B1 2A2 16 41 2B2 2A3 17 40 2B3 GND 18 39 GND 2A4 19 38 2B4 2A5 2A6 20 37 2B5 21 36 2B6 VCC 22 35 VCC 2A7 23 34 2B7 2A8 24 33 2B8 GND 25 32 GND 2SAB 26 31 2SBA 2CLKAB 27 30 2DIR 28 29 2CLKBA 2OE FCT16646-3 Pin Description Pin Names Description A Data Register A Inputs Data Register B Outputs B Data Register B Inputs Data Register A Outputs CLKAB, CLKBA Clock Pulse Inputs SAB, SBA Output Data Source Select Inputs DIR Direction OE Output Enable (Active LOW) 2 CY74FCT16646T CY74FCT162646T Function Table[1] Data I/O[2] Inputs Function OE DIR CLKAB CLKBA SAB SBA A B H H X X H or L H or L X X X X Input Input Isolation Store A and B Data L L L L X X X H or L X X L H Output Input Real Time B Data to A Bus Stored B Data to A Bus L L H H X H or L X X L H X X Input BUS A BUS B DIR L OE L CLKAB X CLKBA X SAB X Output Real Time A Data to Bus Stored A Data to B Bus BUS A SBA L DIR H BUS B OE L CLKAB X Real-Time Transfer Bus B to BusA OE L L H CLKAB CLKBA X X SAB L SBA X Real-Time Transfer BusA to Bus B BUS A DIR H L X CLKBA X SAB X X X BUS B BUS A SBA X X X DIR [3] L H Storage from A and/or B BUS A OE L L CLKAB X H or L CLKBA H or L X SAB X H SBA H X Transfer Stored Data to A and/or B Notes: 1. 2. 3. = LOW-to-HIGH Transition H = HIGH Voltage Level. L = LOW Voltage Level. X = Don't Care The data output functions may be enabled or disabled by various signals at the OE or DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Cannot transfer data to A-bus and B-bus simultaneously. . 3 CY74FCT16646T CY74FCT162646T Maximum Ratings[4] DC Output Current (Maximum Sink Current/Pin) ...........................-60 to +120 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Power Dissipation .......................................................... 1.0W Storage Temperature .....................Com'l -55C to +125C Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied .................................Com'l -55C to +125C Operating Range DC Input Voltage .................................................-0.5V to +7.0V Ambient Temperature VCC -40C to +85C 5V 10% Range DC Output Voltage ..............................................-0.5V to +7.0V Industrial Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VIH Input HIGH Voltage VIL Input LOW Voltage VH Input Hysteresis[6] VIK Input Clamp Diode Voltage VCC=Min., IIN=-18 mA IIH Input HIGH Current IIL IOZH Min. Typ.[5] Max. 2.0 Unit V 0.8 100 -1.2 V VCC=Max., VI=VCC 1 A Input LOW Current VCC=Max., VI=GND 1 A High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=2.7V 1 A IOZL High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=0.5V 1 A IOS Short Circuit Current[7] VCC=Max., VOUT=GND -80 -200 mA Current[7] VCC=Max., VOUT=2.5V -50 -180 mA 1 A Max. Unit IO Output Drive IOFF Power-Off Disable -0.7 V mV -140 VCC=0V, VOUT4.5V[9] Output Drive Characteristics for CY74FCT16646T Parameter VOH VOL Description Output HIGH Voltage Output LOW Voltage Min. Typ.[5] VCC=Min., IOH=-3 mA 2.5 3.5 V VCC=Min., IOH=-15 mA 2.4 3.5 V VCC=Min., IOH=-32 mA 2.0 3.0 V Test Conditions VCC=Min., IOL=64 mA 0.2 0.55 V Typ.[5] Max. Unit Output Drive Characteristics for CY74FCT162646T Parameter Description Test Conditions Min. IODL Output LOW Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA IODH Output HIGH Current[7] VCC=5V, VIN=VIH or VIL, VOUT=1.5V -60 -115 -150 mA VOH Output HIGH Voltage VCC=Min., IOH=-24 mA 2.4 3.3 VOL Output LOW Voltage VCC=Min., IOL=24 mA 0.3 V 0.55 V Notes: 4. Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 5. Typical values are at VCC= 5.0V, TA= +25C ambient. 6. This parameter is specified but not tested. 7. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametrics tests. In any sequence of parameter tests, IOS tests should be performed last. 8. This parameter is measured at characterization but not tested. 9. Tested at +25C. 4 CY74FCT16646T CY74FCT162646T Capacitance (TA = +25C, f = 1.0 MHz) Description[8] Symbol Typ. Max. Unit CIN Input Capacitance VIN = 0V Conditions 4.5 6.0 pF COUT Output Capacitance VOUT =0V 5.5 8.0 pF Power Supply Characteristics Parameter Description Test Conditions[10] VCC=Max. VIN<0.2V VIN>VCC-0.2V Min. Typ.[5] Max. Unit -- 5 500 A -- 0.5 1.5 mA ICC Quiescent Power Supply Current ICC Quiescent Power Supply Current VCC = Max. TTL Inputs HIGH VIN=3.4V[11] ICCD Dynamic Power Supply Current[12] VCC=Max. Outputs Open DIR=OE=GND One-Bit Toggling 50% Duty Cycle VIN=VCC or VIN=GND -- 75 120 A/MHz IC Total Power Supply Current[13] VCC=Max. Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle DIR=OE=GND One-Bit Toggling f1=5 MHz 50% Duty Cycle VIN=VCC or VIN=GND -- 0.8 1.7 mA VIN=3.4V or VIN=GND -- 1.3 3.2 VCC=Max. Outputs Open fo=10 MHz (CLKBA) 50% Duty Cycle DIR=OE=GND Sixteen-Bits Toggling f1=2.5 MHz 50% Duty Cycle VIN=VCC or VIN=GND -- 3.8 6.5[14] VIN=3.4V or VIN=GND -- 8.3 20.0[14] Notes: 10. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 11. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 12. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 13. IC IC = ICC+ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) = Duty Cycle for TTL inputs HIGH DH = Number of TTL inputs at DH NT ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 = Number of inputs changing at f1 N1 All currents are in milliamps and all frequencies are in megahertz. 14. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 5 CY74FCT16646T CY74FCT162646T Switching Characteristics Over the Operating Range[15] CY74FCT16646T Parameter Description CY74FCT16646AT CY74FCT162646AT Min. Max. Min. Max. Unit Fig. No.[16] tPLH tPHL Propagation Delay Bus to Bus 1.5 9.0 1.5 6.3 ns 1, 2 tPZH tPZL Output Enable Time DIR or OE to Bus 1.5 14.0 1.5 9.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time DIR or OE to Bus 1.5 9.0 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 9.0 1.5 6.3 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to Bus 1.5 11.0 1.5 7.7 ns 1,5 tSU Set-Up Time HIGH or LOW Bus to Clock 2.0 -- 2.0 -- ns 4 tH Hold Time HIGH or LOW Bus to Clock 1.5 -- 1.5 -- ns 4 tW Clock Pulse Width HIGH or LOW 5.0 -- 5.0 -- ns 6 tSK(O) Output Skew[17] -- 0.5 -- 0.5 ns -- CY74FCT16646CT CY74FCT162646CT Parameter Description Min. Max. Unit Fig. No.[16] tPLH tPHL Propagation Delay Bus to Bus 1.5 5.4 ns 1, 2 tPZH tPZL Output Enable Time DIR or OE to Bus 1.5 7.8 ns 1, 7, 8 tPHZ tPLZ Output Disable Time DIR or OE to Bus 1.5 6.3 ns 1, 7, 8 tPLH tPHL Propagation Delay Clock to Bus 1.5 5.7 ns 1, 5 tPLH tPHL Propagation Delay SBA or SAB to Bus 1.5 6.2 ns 1,5 tSU Set-Up Time HIGH or LOW Bus to Clock 2.0 -- ns 4 tH Hold Time HIGH or LOW Bus to Clock 1.5 -- ns 4 tW Clock Pulse Width HIGH or LOW 5.0 -- ns 6 tSK(O) Output Skew[17] -- 0.5 ns -- Notes: 15. Minimum limits are specified but not tested on Propagation Delays. 16. See "Parameter Measurement Information" in the General Information section. 17. Skew any two outputs of the same package switching in the same direction. This parameter is ensured by design. 6 CY74FCT16646T CY74FCT162646T Ordering Information CY74FCT16646 Speed (ns) Ordering Code Package Name Package Type Operating Range 5.4 CY74FCT16646CTPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial 6.3 CY74FCT16646ATPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial 9.0 CY74FCT16646TPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial Ordering Information CY74FCT162646 Speed (ns) 5.4 6.3 Ordering Code Package Name Package Type 74FCT162646CTPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT162646CTPVC O56 56-Lead (300-Mil) SSOP 74FCT162646CTPVCT O56 56-Lead (300-Mil) SSOP 74FCT162646ATPACT Z56 56-Lead (240-Mil) TSSOP CY74FCT162646ATPVC O56 56-Lead (300-Mil) SSOP 74FCT162646ATPVCT O56 56-Lead (300-Mil) SSOP 7 Operating Range Industrial Industrial CY74FCT16646T CY74FCT162646T Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 8 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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