CLC1003
ESURGENT
S E M I C O N D U C T O R
Low Distortion, Low Offset, RRIO Amplifier
© 2018 Resurgent Semiconductor, LLC 1 / 17 Rev 1D.R
FEATURES
1mV maximum input offset voltage
0.00005% THD at 1kHz
5.3nV/√Hz input voltage noise > 10kHz
-90dB/-85dB HD2/HD3 at 100kHz, RL = 100Ω
<-100dB HD2 and HD3 at 10kHz, RL = 1kΩ
Rail-to-rail input and output
55MHz unity gain bandwidth
12V/μs slew rate
+80mA, -55mA output current
-40°C to +125°C operating temperature
range
Fully specied at 3 and ±5V supplies
CLC1003: ROHS compliant TSOT-5,
SOIC-8 package options
APPLICATIONS
Active lters
Sensor interface
HIgh-speed transducer amp
Medical instrumentation
Probe equipment
Test equipment
Smoke detectors
Hand-held analytic instruments
Current sense applications
General Description
The CLC1003 is a single channel, high-performance, voltage feedback
amplier with near precision performance, low input voltage noise, and
ultra low distortion. The CLC1003 offers 1mV maximum input offset voltage,
3.5nV/√Hz broadband input voltage noise, and 0.00005% THD at 1kHz.
These ampliers also provide 55MHz gain bandwidth product and 12V/μs
slew rate making them well suited for applications requiring precision DC
performance and high AC performance. This high-performance amplier
also offers a rail-to-rail input and output, simplifying single supply designs
and offering larger dynamic range possibilities. The inputs extend beyond
the rails by 500mV.
The CLC1003 is designed to operate from 2.5V to 12V supplies and
operate over the extended temperature range of -40°C to +125°.
Typical Application
+
–
CLC1003 lph_1
lph_2
lph_3
VCC
SPM
(Smart
Power
Module) M
Current Sensing in 3-Phase Motor
THD vs. Frequency
-100
-95
-90
-85
-80
-75
-70
-65
100 200 300 400 500 600 700 800 900 1000
THD (dB)
Frequency (kHz)
V
OUT
= 1V
pp
RL= 1K
AV+1
Ordering Information - back page
CLC1003
© 2018 Resurgent Semiconductor, LLC 2 / 17 Rev 1D.R
Absolute Maximum Ratings
Stresses beyond the limits listed below may cause
permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect
device reliability and lifetime.
VS ................................................................................. 0V to +14V
VIN ............................................................ -VS - 0.5V to +VS +0.5V
Operating Conditions
Supply Voltage Range ................................................. 2.5V to 12V
Operating Temperature Range ...............................-40°C to 125°C
Junction Temperature ........................................................... 150°C
Storage Temperature Range ...................................-65°C to 150°C
Lead Temperature (Soldering, 10s) ......................................260°C
Package Thermal Resistance
θJA (TSOT-5) .....................................................................215°C/W
θJA (SOIC-8) .....................................................................150°C/W
Package thermal resistance (θJA), JEDEC standard, multi-layer
test boards, still air.
CLC1003
© 2018 Resurgent Semiconductor, LLC 3 / 17 Rev 1D.R
Electrical Characteristics at +3V
TA = 25°C, VS = +3V, Rf = 1kΩ, RL = 1kΩ to VS/2; G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Ty p Max Units
Frequency Domain Response
GBWP -3dB Gain Bandwidth Product G = 10, VOUT = 0.05Vpp 31 MHz
UGBW Unity Gain Bandwidth VOUT = 0.05Vpp, Rf = 0 50 MHz
BWSS -3dB Bandwidth VOUT = 0.05Vpp 24 MHz
BWLS Large Signal Bandwidth VOUT = 2Vpp 3.3 MHz
Time Domain
tR, tFRise and Fall Time VOUT = 2V step; (10% to 90%) 150 ns
tSSettling Time to 0.1% VOUT = 2V step 78 ns
OS Overshoot VOUT = 2V step 0.3 %
SR Slew Rate 2V step 11 V/μs
Distortion/Noise Response
HD2 2nd Harmonic Distortion 2Vpp, 10kHz, RL = 1kΩ -98 dBc
2Vpp, 100kHz, RL = 100Ω -85 dBc
HD3 3rd Harmonic Distortion 2Vpp, 10kHz, RL = 1kΩ -95 dBc
2Vpp, 100kHz, RL = 100Ω -81 dBc
THD Total Harmonic Distortion 1Vpp, 1kHz, G = 1, RL = 2kΩ 0.0005 %
enInput Voltage Noise >10kHz 5.5 nV/√Hz
>100kHz 3.9 nV/√Hz
DC Performance
VIO Input Offset Voltage 0.088 mV
dVIO Average Drift 1. 3 μV/°C
IBInput Bias Current -0.340 μA
dIB Average Drift 0.8 nA/°C
IOS Input Offset Current 0.2 μA
PSRR Power Supply Rejection Ratio DC 100 dB
AOL Open Loop Gain VOUT = VS / 2 104 dB
ISSupply Current per channel 1.85 mA
Input Characteristics
RIN Input Resistance Non-inverting, G = 1 30 MΩ
CIN Input Capacitance 1. 1 pF
CMIR Common Mode Input Range -0.5 to 3.5 V
CMRR Common Mode Rejection Ratio DC, VCM = 0.5V to 2.5V 94 dB
Output Characteristics
VOUT Output Swing
RL = 150Ω 0.085 to
2.80 V
RL = 1kΩ 0.04 to
2.91 V
IOUT Output Current +75, -40 mA
ISC Short Circuit Current VOUT = VS / 2 +95, -50 mA
CLC1003
© 2018 Resurgent Semiconductor, LLC 4 / 17 Rev 1D.R
Electrical Characteristics at ±5V
TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ to GND; G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Ty p Max Units
Frequency Domain Response
GBWP -3dB Gain Bandwidth Product G = 10, VOUT = 0.05Vpp 35 MHz
UGBW Unity Gain Bandwidth VOUT = 0.05Vpp, Rf = 0 55 MHz
BWSS -3dB Bandwidth VOUT = 0.05Vpp 25 MHz
BWLS Large Signal Bandwidth VOUT = 2Vpp 3.6 MHz
Time Domain
tR, tFRise and Fall Time VOUT = 2V step; (10% to 90%) 125 ns
tSSettling Time to 0.1% VOUT = 2V step 80 ns
OS Overshoot VOUT = 2V step 0.3 %
SR Slew Rate 4V step 12 V/μs
Distortion/Noise Response
HD2 2nd Harmonic Distortion 2Vpp, 10kHz, RL = 1kΩ -125 dBc
2Vpp, 100kHz, RL = 100Ω -90 dBc
HD3 3rd Harmonic Distortion 2Vpp, 10kHz, RL = 1kΩ -127 dBc
2Vpp, 100kHz, RL = 100Ω -85 dBc
THD Total Harmonic Distortion 1Vpp, 1kHz, G = 1, RL = 2kΩ 0.00005 %
enInput Voltage Noise >10kHz 5.3 nV/√Hz
>100kHz 3.5 nV/√Hz
DC Performance
VIO Input Offset Voltage -1 0.050 1 mV
dVIO Average Drift 1. 3 μV/°C
IBInput Bias Current -2.6 -0.30 2.6 μA
dIB Average Drift 0.85 nA/°C
IOS Input Offset Current 0.2 0.7 μA
PSRR Power Supply Rejection Ratio DC 82 100 dB
AOL Open Loop Gain VOUT = VS / 2 95 115 dB
ISSupply Current per channel 2.2 2.75 mA
Input Characteristics
RIN Input Resistance Non-inverting, G = 1 30 MΩ
CIN Input Capacitance 1 pF
CMIR Common Mode Input Range ±5.5 V
CMRR Common Mode Rejection Ratio DC, VCM = -3V to 3V 70 95 dB
Output Characteristics
VOUT Output Swing
RL = 150Ω -4.826 to
4.534 V
RL = 1kΩ -4.7 -4.93 to
4.85 4.7 V
IOUT Output Current +80, -55 mA
ISC Short Circuit Current VOUT = VS / 2 +115, -90 mA
CLC1003
© 2018 Resurgent Semiconductor, LLC 5 / 17 Rev 1D.R
SOIC-8
Pin No. Pin Name Description
1 NC No Connect
2 -IN Negative input
3 +IN Positive input
4 -VSNegative supply
5 NC No Connect
6 OUT Output
7 +VSPositive supply
8 NC No Connect
SOIC-8
-
+
1
2
3
4
NC
-IN
+IN
-Vs
NC
+Vs
OUT
NC
8
7
6
5
CLC1003 Pin Assignments
TSOT-5
Pin No. Pin Name Description
1 OUT Output
2 -VSNegative supply
3 +IN Positive input
4 -IN Negative input
5 +VSPositive supply
CLC1003 Pin Congurations
TSOT-5
-
+
2
3
5
4
+IN
+Vs
-IN
1
-Vs
OUT
CLC1003
© 2018 Resurgent Semiconductor, LLC 6 / 17 Rev 1D.R
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted.
Frequency Response vs. VOUT Frequency Response vs. RL
Frequency Response vs. CL Frequency Response vs. CL without RS
Non-Inverting Frequency Response Inverting Frequency Response
-9
-6
-3
0
3
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
G = -1
G = -2
G = -5
G = -10
V
OUT
= 0.05V
pp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
C
L
= 1000pF
R
s
= 7.5Ω
C
L
= 500pF
R
s
= 10Ω
C
L
= 3000pF
R
s
= 4Ω
V
OUT
= 0.05V
pp
-8
-6
-4
-2
0
2
4
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
C
L
= 500pF
C
L
= 300pF
C
L
= 100pF
C
L
= 50pF
C
L
= 10pF
V
OUT
= 0.05V
pp
Rs = 0Ω
-9
-6
-3
0
3
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
V
OUT
= 1V
pp
V
OUT
= 2V
pp
V
OUT
= 4V
pp
-6
-5
-4
-3
-2
-1
0
1
2
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
R
L
= 2.5KΩ
V
OUT
= 0.05V
pp
R
L
= 1KΩ
R
L
= 150Ω
R
L
= 50Ω
CLC1003
© 2018 Resurgent Semiconductor, LLC 7 / 17 Rev 1D.R
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted.
-3dB Bandwidth vs. Output Voltage at VS = 3V -3dB Bandwidth vs. Output Voltage
Frequency Response vs. VOUT at VS = 3V Frequency Response vs. RL at VS = 3V
Non-Inverting Frequency Response at VS = 3V Inverting Frequency Response at VS = 3V
-9
-6
-3
0
3
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
G = 1
R
f
= 0
G = 2
G = 5
G = 10
V
OUT
= 0.05V
pp
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
G = -1
G = -2
G = -5
G = -10
V
OUT
= 0.05V
pp
-9
-6
-3
0
3
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
V
OUT
= 1V
pp
V
OUT
= 2V
pp
V
OUT
= 2.5V
pp
-6
-5
-4
-3
-2
-1
0
1
2
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
R
L
= 2.5KΩ
V
OUT
= 0.05V
pp
R
L
= 1KΩ
R
L
= 150Ω
R
L
= 50Ω
0
3
6
9
12
15
18
21
24
0.0 0.5 1.0 1.5 2.0 2.5
-3dB Bandwidth (MHz)
V
OUT
(V
PP
)
0
3
6
9
12
15
18
21
24
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
-3dB Bandwidth (MHz)
V
OUT
(V
PP
)
CLC1003
© 2018 Resurgent Semiconductor, LLC 8 / 17 Rev 1D.R
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted.
CMRR vs. Frequency PSRR vs. Frequency
Input Voltage Noise CMIR at VS = 3V
Open Loop Gain and Phase vs. CMIR
-525
-450
-375
-300
-225
-150
-75
0
-60
-40
-20
0
20
40
60
80
10 100 1,000 10,000 100,000 1,000,000
PHASE (°)
GAIN (dB)
FREQ (KHz)
GAIN
PHASE
-0.1
0
0.1
0.2
0.3
0.4
0.5
-6 -4 -2 0246
Vout (V)
Vcm(V)
2
3
4
5
6
7
8
9
10
11
12
13
14
0.0001 0.001 0.01 0.1 1
Input Voltage Noise (nV/√Hz)
Frequency (MHz)
-0.1
0
0.1
0.2
0.3
0.4
0.5
-1 -0.5 00.5 11.5 22.5 33.5 4
Vout (V)
Vcm(V)
40
50
60
70
80
90
100
110
0.001 0.01 0.1 110 100 1000
CMRR (dB)
Frequency (MHz)
1000
50
60
70
80
90
100
110
0.001 0.01 0.1 110 100 1000
PSRR (dB)
Frequency (MHz)
1000
CLC1003
© 2018 Resurgent Semiconductor, LLC 9 / 17 Rev 1D.R
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted.
THD vs. Frequency
2nd Harmonic Distortion vs. VOUT 3rd Harmonic Distortion vs. VOUT
2nd Harmonic Distortion vs. RL 3rd Harmonic Distortion vs. RL
-110
-100
-90
-80
-70
-60
-50
100 200 300 400 500 600 700 800 900 1000
Distortion (dBc)
Frequency (KHz)
R
L
= 100Ω
V
OUT
= 2V
pp
R
L
= 10KΩ
R
L
= 1KΩ
R
L
= 500Ω
-110
-100
-90
-80
-70
-60
-50
100 200 300 400 500 600 700 800 900 1000
Distortion (dBc)
Frequency (KHz)
R
L
= 100Ω
V
OUT
= 2V
pp
R
L
= 10KΩ
R
L
= 1KΩ
R
L
= 500Ω
-100
-90
-80
-70
-60
-50
-40
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5
Distortion (dBc)
Output Amplitude (V
pp
)
RF=RL=10K
RF=RL=1K
FREQ = 500KHz
-100
-90
-80
-70
-60
-50
-40
-30
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5
Distortion (dBc)
Output Amplitude (V
pp
)
RF=RL=10K
RF=RL=1K
FREQ = 500KHz
-100
-95
-90
-85
-80
-75
-70
-65
100 200 300 400 500 600 700 800 900 1000
THD (dB)
Frequency (kHz)
V
OUT
= 1V
pp
RL= 1K
AV+1
CLC1003
© 2018 Resurgent Semiconductor, LLC 10 / 17 Rev 1D.R
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted.
THD vs. Frequency at VS = 3V
2nd Harmonic Distortion vs. VOUT at VS = 3V 3rd Harmonic Distortion vs. VOUT at VS = 3V
2nd Harmonic Distortion vs. RL at VS = 3V 3rd Harmonic Distortion vs. RL at VS = 3V
-100
-90
-80
-70
-60
-50
-40
100 200 300 400 500 600 700 800 900 1000
Distortion (dBc)
Frequency (KHz)
R
L
= 100Ω
V
OUT
= 2V
pp
R
L
= 10KΩ
R
L
= 1KΩ
R
L
= 500Ω
-100
-90
-80
-70
-60
-50
-40
100 200 300 400 500 600 700 800 900 1000
Distortion (dBc)
Frequency (KHz)
R
L
= 100Ω
V
OUT
= 2V
pp
R
L
= 10KΩ
R
L
= 1KΩ
R
L
= 500Ω
-100
-90
-80
-70
-60
-50
-40
0.5 0.75 11.25 1.5 1.75 22.25 2.5
Distortion (dBc)
Output Amplitude (V
pp
)
RF=RL=10K
RF=RL=1K
FREQ = 500KHz
-100
-90
-80
-70
-60
-50
-40
0.5 0.75 11.25 1.5 1.75 22.25 2.5
Distortion (dBc)
Output Amplitude (V
pp
)
RF=RL=10K
RF=RL=1K
FREQ = 500KHz
-100
-95
-90
-85
-80
-75
-70
-65
100 200 300 400 500 600 700 800 900 1000
THD (dB)
Frequency (kHz)
V
OUT
= 1V
pp
RL= 1K
AV+1
CLC1003
© 2018 Resurgent Semiconductor, LLC 11 / 17 Rev 1D.R
Typical Performance Characteristics
TA = 25°C, VS = ±5V, Rf = 1kΩ, RL = 1kΩ, G = 2; unless otherwise noted.
Input Offset Voltage vs. Temperature Input Offset Voltage Distribution
Large Signal Pulse Response Large Signal Pulse Response at VS = 3V
Small Signal Pulse Response Small Signal Pulse Response at VS = 3V
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
00.5 11.5 2
Voltage (V)
Time (ns)
1.35
1.4
1.45
1.5
1.55
1.6
1.65
00.5 11.5 2
Voltage (V)
Time (ns)
-6
-4
-2
0
2
4
6
012345678910
Voltage (V)
Time (ns)
0
0.5
1
1.5
2
2.5
3
00.5 11.5 2
Voltage (V)
Time (ns)
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
-40 -20 020 40 60 80 100 120
Vio (V)
Temperature (°C)
0
1000
2000
3000
4000
5000
Units
Input Offset Voltage (mV)
CLC1003
© 2018 Resurgent Semiconductor, LLC 12 / 17 Rev 1D.R
Application Information
Basic Information
Figures 1 and 2 illustrate typical circuit congurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+
-
Rf
0.1μF
6.8μF
Output
G = 1 + (Rf/Rg)
Input
+Vs
-Vs
Rg
0.1μF
6.8μF
RL
Figure 1: Typical Non-Inverting Gain Circuit
+
-
Rf
0.1μF
6.8μF
Output
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Input
+Vs
-Vs
0.1μF
6.8μF
RL
Rg
R1
Figure 2: Typical Inverting Gain Circuit
Power Dissipation
Power dissipation should not be a factor when operating
under the stated 500Ω load condition. However, applications
with low impedance, DC coupled loads should be analyzed
to ensure that maximum allowed junction temperature is
not exceeded. Guidelines listed below can be used to verify
that the particular application will not cause the device to
operate beyond it’s intended operating range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction
temperature, the package thermal resistance value ThetaJA
(θJA) is used along with the total die power dissipation.
TJunction = TAmbient + (θJA × PD)
Where TAmbient is the temperature of the working
environment.
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by the
supplies.
PD = Psupply - Pload
Supply power is calculated by the standard power equation.
Psupply = Vsupply × IRMSsupply
Vsupply = VS+ - VS-
Power delivered to a purely resistive load is:
Pload = ((Vload)RMS2)/Rloadeff
The effective load resistor (Rloadeff) will need to include the
effect of the feedback network. For instance,
Rloadeff in Figure 2 would be calculated as:
RL || (Rf + Rg)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
PD = PQuiescent + PDynamic - Pload
Quiescent power can be derived from the specied IS values
along with known supply voltage, Vsupply. Load power can
be calculated as above with the desired signal amplitudes
using:
(Vload)RMS = Vpeak / √2
( Iload)RMS = ( Vload)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDynamic = (VS+ - Vload)RMS × ( Iload)RMS
Assuming the load is referenced in the middle of the power
rails or Vsupply/2.
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the packages
available.
CLC1003
© 2018 Resurgent Semiconductor, LLC 13 / 17 Rev 1D.R
0
0.5
1
1.5
2
-40 -20 020 40 60 80 100 120
Maximum Power Dissipation (W)
Ambient Temperature (°C)
TSOT-6
SOIC-8
Figure 3. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive loading
can cause ringing, peaking in the frequency response, and
possible unstable behavior. Use a series resistance, RS,
between the amplier and the load to help improve stability
and settling performance. Refer to Figure 4.
+
-
Rf
Input
Output
Rg
Rs
CLRL
Figure 4. Addition of RS for Driving Capacitive Loads
The CLC1003 is capable of driving up to 300pF directly, with
no series resistance. Directly driving 500pF causes over
4dB of frequency peaking, as shown in the plot on page 6.
Table 1 provides the recommended RS for various capacitive
loads. The recommended RS values result in ≤ 1dB peaking
in the frequency response. The Frequency Response vs.
CL plots, on page 6, illustrate the response of the CLC1003.
CL (pF) RS (Ω) -3dB BW (MHz)
500 10 27
1000 7. 5 20
3000 4 15
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of
additional overshoot and ringing.
Overdrive Recovery
An overdrive condition is dened as the point when either
one of the inputs or the output exceed their specied
voltage range. Overdrive recovery is the time needed for the
amplier to return to its normal or linear operating point. The
recovery time varies based on whether the input or output
is overdriven and by how much the ranges are exceeded.
The CLC1003 will typically recover in less than 20ns from
an overdrive condition. Figure 5 shows the CLC1003 in an
overdriven condition.
-2
-2
-1
-1
0
1
1
2
2
-3
-2
-1
0
1
2
3
00.25 0.5 0.75 11.25 1.5 1.75 2
Output Voltage (V)
Input Voltage (V)
Time (us)
Output
Input
V
IN
= .8V
pp
G = 5
Figure 5: Overdrive Recovery
Considerations for Offset and Noise Performance
Offset Analysis
There are three sources of offset contribution to consider;
input bias current, input bias current mismatch, and input
offset voltage. The input bias currents are assumed to be
equal with and additional offset current in one of the inputs
to account for mismatch. The bias currents will not affect
the offset as long as the parallel combination of Rf and Rg
matches Rt. Refer to Figure 6.
IN
RgRf
Rt
RL
+Vs
-Vs
–
+
CLC1003
Figure 6: Circuit for Evaluating Offset
The rst place to start is to determine the source resistance.
If it is very small an additional resistance may need to be
added to keep the values of Rf and Rg to practical levels.
For this analysis we assume that Rt is the total resistance
present on the non-inverting input. This gives us one
equation that we must solve:
CLC1003
© 2018 Resurgent Semiconductor, LLC 14 / 17 Rev 1D.R
Rt = Rg||Rf
This equation can be rearranged to solve for Rg:
Rg = (Rt * Rf) / (Rf - Rt)
The other consideration is desired gain (G) which is:
G = (1 + Rf/Rg)
By plugging in the value for Rg we get
Rf = G * Rt
And Rg can be written in terms of Rt and G as follows:
Rg = (G * Rt) / (G - 1)
The complete input offset equation is now only dependent
on the voltage offset and input offset terms given by:
VIOS =VIO
( )
2+IOS ∗RT
( )
2
And the output offset is:
VOOS =G∗VIO
( )
2+IOS ∗RT
( )
2
Noise analysis
The complete equivalent noise circuit is shown in Figure 7.
RgRf
RL
–
+
CLC1003
+ – + –
Rg
+ –
+
–
+ –
w
Figure 7: Complete Equivalent Noise Circuit
The complete noise equation is given by:
v2
o=v2
orext +en1+RF
RG
2+ibp ∗RT 1 +RF
RG
2+ibn∗RF
( )
2
Where Vorext is the noise due to the external resistors and
is given by:
=en1+RF
RG
2+eG∗RF
RG
2+e2
F
v2
o
The complete equation can be simplied to:
=3∗4kT ∗G∗RT
( )
+enG
( )
2+2∗in∗RT
( )
2
v2
o
It’s easy to see that the effect of amplier voltage noise
is proportionate to gain and will tend to dominate at large
gains. The other terms will have their greatest impact at
large Rt values at lower gains.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. Exar has evaluation boards to
use as a guide for high frequency layout and as an aid in
device testing and characterization. Follow the steps below
as a basis for high frequency layout:
Include 6.8µF and 0.1µF ceramic capacitors for power supply
decoupling
Place the 6.8µF capacitor within 0.75 inches of the power pin
Place the 0.1µF capacitor within 0.1 inches of the power pin
Remove the ground plane under and around the part,
especially near the input and output pins to reduce parasitic
capacitance
Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more
information.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board # Products
CEB002 CLC1003 in TSOT
CEB003 CLC1003 in SOIC
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in
Figures 8-12 These evaluation boards are built for dual-
supply operation. Follow these steps to use the board in a
single-supply application:
1. Short -VS to ground.
2. Use C3 and C4, if the -VS pin of the amplier is not
directly connected to the ground plane.
CLC1003
© 2018 Resurgent Semiconductor, LLC 15 / 17 Rev 1D.R
Figure 8. CEB002 & CEB003 Schematic
Figure 9. CEB002 Top View
Figure 10. CEB002 Bottom View
Figure 11. CEB003 Top View
Figure 12. CEB003 Bottom View
CLC1003
© 2018 Resurgent Semiconductor, LLC 16 / 17 Rev 1D.R
Mechanical Dimensions
TSOT-5 Package
SOIC-8 Package
CLC1003
For Further Assistance:
www.resurgentsemi.net
NOTICE
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Semiconductor assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the
circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specic application.
While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.
Resurgent Semiconductor does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to signicantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Resurgent
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liability of Resurgent Semiconductor is adequately protected under the circumstances.
Reproduction, in part or whole, without the prior written consent of Resurgent Semiconductor is prohibited.
ESURGENT
S E M I C O N D U C T O R
© 2018 Resurgent Semiconductor, LLC 17 / 17 Rev 1D.R
Ordering Information
Part Number Package Green Operating Temperature Range Packaging Quantity
CLC1003 Ordering Information
CLC1003IST5X* TSOT-5 Ye s -40°C to +125°C 2.5k Tape & Reel
CLC1003IST5MTR* TSOT-5 Ye s -40°C to +125°C 250 Tape & Reel
CLC1003IST5EVB* Evaluation Board N/A N/A N/A
CLC1003ISO8X SOIC-8 Ye s -40°C to +125°C 2.5k Tape & Reel
CLC1003ISO8MTR SOIC-8 Ye s -40°C to +125°C 250 Tape & Reel
CLC1003ISO8EVB Evaluation Board N/A N/A N/A
Moisture sensitivity level for all parts is MSL-1.
*Contact Resurgent Semiconductor for availability.
Revision History
Revision Date Description
1D (ECN 1441-07) September
2014
Reformat into Exar data sheet template. Updated ordering information table to include MTR and EVB
part numbers. Increased “I” temperature range from +85 to +125°C. Removed “A” temp grade parts,
since “I” is now equivalent. Updated thermal resistance numbers and package outline drawings.
1D.R July 2018 Updated to Resurgent Semiconductor.