Rev.3.00, Jul.22.2005, page 1 of 4
HD74LS77
4-bit Bistable Latches REJ03D0418–0300
Rev.3.00
Jul.22.2005
The HD74LS77 is ideally suited for use as temporary storage for binary information between processing units and
input / output or indicator units. Information presen t at a data (D) input is transferred to the Q output when the enable
(G) is high and the Q output will follo w the data input a s long as the enable remains high. When the enable goes low,
the information (that was present at t he data input at t he ti me the transition occurred) is retained at the Q output until the
enable is permitted to go high.
Features
• Ordering Information
Part Name Package Type Package Code
(Previous Code) Package
Abbreviation Taping Abbreviation
(Quantity)
HD74LS77FPEL SOP-14 pin (JEITA) PRSP0014DF-B
(FP-14DAV) FP EL (2,000 pcs/reel)
Pin Arrangement
(Top view)
1Q
2Q
Enable 1-2
GND
3Q
NC
1D
NC
2D
Enable 3-4
V
CC
3D
4D
4Q
1
2
3
4
5
6
7
14
8
9
10
11
12
13
Q
Q
GD
GD
Q
GD
Q
G
D
Function Table
Inputs Outputs
D G Q
L H L
H H H
X L Q0
H; high level, L; low level, X; irrelevant
HD74LS77
Rev.3.00, Jul.22.2005, page 2 of 4
Block Diagram (1/4)
Enable
To Other
Latch
Data
Q
Absolute Maximum Ratings
Item Symbol Ratings Unit
Supply voltage VCC 7 V
Input voltage VIN 7 V
Power dissipation PT 400 mW
Storage temperature Tstg –65 to +150 °C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage VCC 4.75 5.00 5.25 V
IOH — — –400 µA
Output current IOL — — 8 mA
Operating temperature Topr –20 25 75 °C
Pulse width tw 20 — — ns
Setup time tsu 20 — — ns
Hold time th 5 — — ns
Electrical Characteristics
(Ta = –20 to +75 °C)
Item Symbol min. typ.* max. Unit Condition
VIH 2.0 — — V
Input voltage VIL — — 0.8 V
VOH 2.7 — — V
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
— — 0.4 IOL = 4 mA
Output voltage VOL — — 0.5 V IOL = 8 mA VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
D — — 20
G IIH — — 80 µA VCC = 5.25 V, VI = 2.7 V
D — — –0.4
G IIL — — –1.6
mA VCC = 5.25 V, VI = 0.4 V
D — — 0.1
Input current
G II — — 0.4
mA VCC = 5.25 V, VI = 7 V
Short-circuit output
current IOS –20 — –100 mA VCC = 5.25 V
Supply current** ICC — 6.9 13 mA VCC = 5.25 V
Input clamp voltag e VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** ICC is measured with all outputs open and all inputs grounded.
HD74LS77
Rev.3.00, Jul.22.2005, page 3 of 4
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item Symbol Inputs Outputs min. typ. max. Unit Condition
tPLH — 11 19
tPHL D Q
— 9 17
tPLH — 10 18
Propagation delay
time tPHL G Q
— 10 18
ns CL = 15 pF,
RL = 2 kΩ
Testing Method
Test Circuit
VCC Output
Input
D
G
Q
P.G.
Zout = 50Ω
RL
CL
Input
P.G.
Zout = 50Ω
Notes: 1. Test is put into the each latch.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
Waveform
VOH
VOL
0V
3V
0V
3V
D
G
Q
tTLH tTHL
10%
90%
1.3 V 1.3 V 1.3 V
1.3 V
10%
90%
tTHL
tPLH tPHL
tPHL
1.3 V
10%
90%
tTLH
tsu thtsu
1µs1µs
th
tPLH
10%
twtw
90%
1.3 V 1.3 V
1.3 V
1.3 V
Notes: 1. Input pulse; tTLH ≤ 10 ns, tTHL ≤ 10 ns.
2. When measuring propagation delay times from the D input, the corresponding G input must be
held high.
HD74LS77
Rev.3.00, Jul.22.2005, page 4 of 4
Package Dimensions
1.42
0.15
1.27
7.50 8.00
0.400.34
p
A
1
10.5
FP-14DAV
RENESAS CodeJEITA Package Code Previous Code
MaxNomMin
Dimension in Millimeters
Symbol
Reference
2.20
0.900.700.50
5.50
0.200.100.00
0.46
0.250.200.15
7.80
8
°
0
°
0.12
1.15
10.06
0.23g
MASS[Typ.]
1
E
1
1
2
L
Z
H
y
x
θ
c
b
A
E
D
b
c
e
L
A
P-SOP14-5.5x10.06-1.27 PRSP0014DF-B
Index mark
E
1
*2
*1
7
14 8
F
*3
p
Mx
y
D
E
H
Zb
A
p
Terminal cross section
( Ni/Pd/Au plating )
b
c
Detail F
1
1
L
L
A
θ
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
e
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