SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com FlatLinkTM RECEIVER Check for Samples: SN65LVDS86A-Q1 FEATURES 1 * 2 * * * * * * * * * * * * 3:21 Data Channel Expansion at up to 178.5 Mbytes/s Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI Three Data Channels and Clock Low-Voltage Differential Channels In and 21 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.3-V Supply Tolerates 4-kV Human-Body Model (HBM) ESD Packaged in Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch Consumes Less Than 1 mW When Disabled Wide Phase-Lock Input Frequency Range 31 MHz to 68 MHz No External Components Required for PLL Inputs Meet or Exceed the Standard Requirements of ANSI EIA/TIA-644 Standard Improved Replacement for the SN75LVDS86 and NSC DS90C364 Improved Jitter Tolerance Qualified for Automotive Applications DGG PACKAGE (TOP VIEW) D17 D18 GND D19 D20 NC LVDSGND A0M A0P A1M A1P LVDSVCC LVDSGND A2M A2P CLKINM CLKINP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKOUT D0 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 VCC D16 D15 D14 GND D13 VCC D12 D11 D10 GND D9 VCC D8 D7 D6 GND D5 D4 D3 VCC D2 D1 GND NC - Not connected DESCRIPTION The SN65LVDS86A FlatLinkTM receiver contains three serial-in 7-bit parallel-out shift registers and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a lower transfer rate. When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT). The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The SN65LVDS86A is characterized for operation over the full automotive temperature range of -40C to 125C. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FlatLink is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2006-2012, Texas Instruments Incorporated SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com ORDERING INFORMATION PACKAGE (1) TA -40C to 125C (1) TSSOP - DGG ORDERABLE PART NUMBER Reel of 2000 SN65LVDS86ADGGRQ1 TOP-SIDE MARKING 65LVDS86AQ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTIONAL BLOCK DIAGRAM Serial-In/ParallelOut Shift Register A0P A0M Serial In CLK D0 D1 D2 D3 D4 D5 D6 A, B, ...G Serial-In/ParallelOut Shift Register A1P A1M Serial In A, B, ...G D7 D8 D9 D10 D11 D12 D13 CLK Serial-In/ParallelOut Shift Register A2P A2M Serial In A, B, ...G CLK D14 D15 D16 D17 D18 D19 D20 Control Logic SHTDN Clock Generator CLK Clock In CLKINP CLKINM CLKOUT Clock Out Input Bus 2 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 www.ti.com CLKIN CC CC CC CC EE EE EE EE Previous Cycle D0-1 D6 A1 D7-1 D13 D14- 1 D20 CLKOUT CCC CCC CCC CCC EE EE EE EE Next Cycle D5 D4 D3 D2 D1 D0 D6+1 D12 D11 D10 D9 D8 D7 D13+1 D18 D17 D16 D14 D20+1 EE EE EE EE D19 CC CC CC CC D15 Dn - 1 D0 CC CC CC CC SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 Current Cycle A0 A2 CCC CCC CCC CCC SN65LVDS86A-Q1 EE EE EE EE CC CC CC CC Dn Dn + 1 Figure 1. SN65LVDS86A Load and Shift Timing Sequences EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS VCC 300 k VCC 300 k 5 100 D Output 100 AnM AnP 7V 7V 7V VCC OUTPUT INPUT 50 SHTDN 7V INPUT Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 Submit Documentation Feedback 3 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN VCC Supply voltage range (2) UNIT -0.5 4 -0.5 VCC + 0.5 V All pins (Class 3A) 4 kV All pins (Class 2B) 200 V Voltage range at any terminal Electrostatic discharge (3) MAX Continuous total power dissipation V See Dissipation Rating Table TJ Operating virtual junction temperature range -40 150 C Tstg Storage temperature range -65 150 C 260 C Lead temperature 1,6 mm (1/16 in) from case for 10 s Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the GND terminals unless otherwise noted. This rating is measured using MIL-STD-883C Method, 3015.7. (1) (2) (3) Dissipation Rating Table (1) PACKAGE TA 25C POWER RATING DERATING FACTOR (1) ABOVE TA = 25C TA = 70C POWER RATING TA = 125C POWER RATING DGG 1637 mW 13.1 mW/C 1048 mW 327 mW This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow. Recommended Operating Conditions See Figure 2 MIN NOM MAX 3.3 3.6 VCC Supply voltage 3 VIH High-level input voltage (SHTDN) 2 VIL Low-level input voltage (SHTDN) |VID| Magnitude differential input voltage VIC Common-mode input voltage TA Operating free-air temperature UNIT V V 0.8 V 0.6 V | ID 2 V 125 C 0.1 |V | ID 2 |V 2.4 * -40 Timing Requirements tc (1) 4 (1) Cycle time, input clock MIN NOM MAX UNIT 14.7 tc 32.4 ns Parameter tc is defined as the mean duration of a minimum of 32000 clock cycles. Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com Electrical Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input threshold voltage VIT- Negative-going differential input threshold voltage (2) VOH High-level output voltage IOH = -4 mA VOL Low-level output voltage IOL = 4 mA ICC MIN TYP (1) MAX UNIT 100 mV -100 Quiescent current (average) mV 2.4 V Disabled, All inputs to GND Enabled, AnM = 1.4 V, AnP = 1 V, tc = 15.38 ns 33 Enabled, Grayscale pattern (see Figure 3), CL = 8 pF, tc = 15.38 ns 43 Enabled, Worst-case pattern (see Figure 4), CL = 8 pF, tc = 15.38 ns 68 0.4 V 280 A 40 mA IIH High-level input current (SHTDN) VIH = VCC 20 A IIL Low-level input current (SHTDN) VIL = 0 25 A II Input current A inputs 0 VI 2.4 V 20 A IOZ High-impedance output current VO = 0 or VCC 10 A (1) (2) All typical values are at VCC = 3.3 V, TA = 25C. The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going input voltage threshold only. Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tsu Setup time, D0-D20 to CLKOUT th Data hold time, CLKOUT to D0-D20 t(RSKM) Receiver input skew margin (2) (see Figure 7) tc = 15.38 ns (0.2%), |Input clock jitter| < 50 ps, (3) td Delay time, CLKIN to CLKOUT (see Figure 7) VCC = 3.3 V, tc = 15.38 ns (0.2%), TA = 25C ten Enable time, SHTDN to phase lock See Figure 7 1 ms tdis Disable time, SHTDN to off state See Figure 8 400 ns tt Transition time, output (10% to 90% tr or tf) (data only) CL = 8 pF 3 ns tt Transition time, output (10% to 90% tr or tf) (clock only) CL = 8 pF 1.5 ns tw Pulse duration, output clock 0.50 tc ns (1) (2) (3) CL = 8 pF, See Figure 5 5 ns 5 ns 550 700 3 5 ps 7 ns All typical values are at VCC = 3.3 V, TA = 25C. The parameter t(RSKM) is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this parameter at clock periods other than 15.38 ns can be calculated from tRSKM = tc/14 - 550 ps. |Input clock jitter| is the magnitude of the change in input clock period. Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 Submit Documentation Feedback 5 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION AP VID VIAP (VIAP + VIAM)/2 AM VIC VIAM Figure 2. Voltage Definitions CLKIN/CLKOUT D0, D6, D12 D1, D7, D13 D2, D8, D14 D3, D9, D15 D18, D19, D20 ALL OTHERS A. The 16-grayscale test-pattern test device power consumption for a typical display pattern. Figure 3. 16-Grayscale Test-Pattern Waveforms tc CLKIN/CLKOUT Even Dn Odd Dn A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVTTL outputs. Figure 4. Worst-Case Test-Pattern Waveforms 6 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) tsu 70% VOH D0 -D20 30% VOH th 70% VOH CLKOUT 30% VOH Figure 5. Setup and Hold Time Waveforms Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 Submit Documentation Feedback 7 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Tektronix HFS9003/HFS9DG1 Stimulus System (repeating patterns of 1110111 and 0001000) An Device Under Test (DUT) CLKIN D0 - D20 Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector CLKOUT tc Internal Strobing Position 4 t t 7 c (RSKM) (see Note A) EE EE CC EE EE CC CC CC tsu1 3 t t 7 c (RSKM) (see Note A) An and An CC CC EE CC CC EE EE EE EE EE CC EE EE CC CC CC th1 CC CC EE CC CC EE EE EE CLKIN td tW CLKOUT tr < 1 ns 90% CLKIN or An 300 mV 0V 10% -300 mV td tW VOH 1.4 V CLKOUT A. VOL CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or delay is then reduced until there are no data errors observed. The magnitude of the advance or delay is t(RSKM). Figure 6. Receiver Input Skew Margin, Setup/Hold Time, and Delay Time Definitions 8 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) CLKIN An ten SHTDN Dn EEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEEEEEEEEE Invalid Valid Figure 7. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT Figure 8. Disable Time Waveforms Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 Submit Documentation Feedback 9 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 60 I CC - Supply Current - mA 55 VCC = 3.6 V 50 45 40 VCC = 3.3 V 35 30 VCC = 3 V 25 30 40 50 Grayscale Data Pattern CL = 8 pF TA = 25C 60 70 80 90 fclk - Clock Frequency - MHz Figure 9. RMS Grayscale ICC vs Clock Frequency 10 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com APPLICATION INFORMATION Host Cable Flat Panel Display SN75LVDS84/5 Y0M 41 8 100 Y0P Y1M 40 9 39 10 100 Y1P Y2M 38 11 35 14 100 Y2P CLKOUTM 34 15 33 16 100 CLKOUTP 32 17 SN75LVDS86A/ SN65LVDS86AQ D0 A0M D1 D2 D3 A0P D4 D5 D6 A1M D7 D8 D9 A1P D10 D11 D12 A2M D13 D14 D15 A2P D16 D17 D18 CLKINM D19 D20 CLKOUT CLKINP A. The four 100- terminating resistors are recommended to be 0603 types. B. NA - not applicable, these unused inputs should be left open. Graphics Controller 24 26 27 29 30 31 33 34 35 37 39 40 41 43 45 46 47 1 2 4 5 23 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK Figure 10. 18-Bit Color Host to Flat Panel Display Application Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 Submit Documentation Feedback 11 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 Host www.ti.com Cable Flat Panel Display SN75LVDS81/83 Y0M 48 8 SN75LVDS86A/ SN65LVDS86AQ A0M 100 Y0P Y1M 47 9 46 10 A0P A1M 100 Y1P Y2M 45 11 42 14 A1P A2M 100 Y2P 41 15 40 16 CLKOUTM A2P CLKINM 100 CLKOUTP Y3M Y3P 39 17 CLKINP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKOUT Graphics Controller 24 26 27 29 30 31 33 34 35 37 39 40 41 43 45 46 47 1 2 4 5 23 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK 38 37 A. The four 100- terminating resistors are recommended to be 0603 types. B. NA - not applicable, these unused inputs should be left open. Figure 11. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application See the FLatLink Designer's Guide (literature number SLLA012) for more application information. 12 Submit Documentation Feedback Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 SN65LVDS86A-Q1 SLLS768A - AUGUST 2006 - REVISED JANUARY 2012 www.ti.com Changes from Original (August 2006) to Revision A * Page Changed Wide Phase-Lock Input Frequency Range lower limit from 10 MHz to 31 MHz ................................................... 1 Copyright (c) 2006-2012, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS86A-Q1 Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 18-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) SN65LVDS86AQDGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 65LVDS86AQ SN65LVDS86AQDGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 65LVDS86AQ SN65LVDS86AQDGGRQ1 ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 65LVDS86AQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Jun-2014 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN65LVDS86A-Q1 : * Catalog: SN65LVDS86A NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product Addendum-Page 2 MECHANICAL DATA MTSS003D - JANUARY 1995 - REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0- 8 A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. 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