1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D17
D18
GND
D19
D20
NC
LVDSGND
A0M
A0P
A1M
A1P
LVDSVCC
LVDSGND
A2M
A2P
CLKINM
CLKINP
LVDSGND
PLLGND
PLLVCC
PLLGND
SHTDN
CLKOUT
D0
VCC
D16
D15
D14
GND
D13
VCC
D12
D11
D10
GND
D9
VCC
D8
D7
D6
GND
D5
D4
D3
VCC
D2
D1
GND
DGG PACKAGE
(TOP VIEW)
NC − Not connected
SN65LVDS86A-Q1
www.ti.com
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
FlatLink™RECEIVER
Check for Samples: SN65LVDS86A-Q1
1FEATURES
2•3:21 Data Channel Expansion at up to
178.5 Mbytes/s Throughput
•Suited for SVGA, XGA, or SXGA Display Data
Transmission From Controller to Display With
Very Low EMI
•Three Data Channels and Clock Low-Voltage
Differential Channels In and 21 Data and Clock
Low-Voltage TTL Channels Out
•Operates From a Single 3.3-V Supply
•Tolerates 4-kV Human-Body Model (HBM) ESD
•Packaged in Thin Shrink Small-Outline
Package (TSSOP) With 20-Mil Terminal Pitch
•Consumes Less Than 1 mW When Disabled
•Wide Phase-Lock Input Frequency Range
31 MHz to 68 MHz
•No External Components Required for PLL
•Inputs Meet or Exceed the Standard
Requirements of ANSI EIA/TIA-644 Standard
•Improved Replacement for the SN75LVDS86
and NSC DS90C364
•Improved Jitter Tolerance
•Qualified for Automotive Applications
DESCRIPTION
The SN65LVDS86A FlatLink™receiver contains three serial-in 7-bit parallel-out shift registers and four
low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt
of synchronous data from a compatible transmitter, such as the SN75LVDS81, '83, '84, or '85, over four
balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data at a
lower transfer rate.
When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input
clock (CLKIN) rate. The data is then unloaded to a 21-bit wide LVTTL parallel bus at the CLKIN rate. The
SN65LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).
The SN65LVDS86A requires only four line-termination resistors for the differential inputs and little or no control.
The data bus appears the same at the input to the transmitter and output of the receiver with the data
transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear
(SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low
level on this signal clears all internal registers to a low level.
The SN65LVDS86A is characterized for operation over the full automotive temperature range of –40°C to 125°C.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2FlatLink is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright ©2006–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Serial In
CLK
Serial-In/Parallel-
Out Shift Register
Serial In
CLK
Serial In
CLK
Control Logic
CLK
Clock In
Clock Generator
SHTDN
CLKINP
A2P
A2M
A1P
A1M
A0P
A0M
CLKOUT
CLKINM
D14
D15
D16
D17
D18
D19
D20
D7
D8
D9
D10
D11
D12
D13
D0
D1
D2
D3
D4
D5
D6
A, B, ...G
Clock Out
A, B, ...G
A, B, ...G
Serial-In/Parallel-
Out Shift Register
Serial-In/Parallel-
Out Shift Register
Input Bus
SN65LVDS86A-Q1
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
www.ti.com
ORDERING INFORMATION
TAPACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING
–40°C to 125°C TSSOP –DGG Reel of 2000 SN65LVDS86ADGGRQ1 65LVDS86AQ
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTIONAL BLOCK DIAGRAM
2Submit Documentation Feedback Copyright ©2006–2012, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS86A-Q1
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
CLKOUT
CLKIN
D0
A0
A1
A2
D0−1 D6 D4 D3 D2 D1 D0 D6+1
D7−1 D13 D12 D11 D10 D9 D8 D7 D13+1
D14−
1D20 D19 D18 D17 D16 D15 D14 D20+1
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Current CyclePrevious Cycle Next Cycle
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
Dn − 1 Dn Dn + 1
D5
VCC
50 Ω
7 V
SHTDN
VCC
7 V
5 Ω
D Output
INPUT
OUTPUT
VCC
300 kΩ
AnM
7 V 7 V
300 kΩ
AnP
INPUT
100 Ω
100 Ω
SN65LVDS86A-Q1
www.ti.com
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
Figure 1. SN65LVDS86A Load and Shift Timing Sequences
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Copyright ©2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): SN65LVDS86A-Q1
|VID|
2
2.4*
|VID|
2
SN65LVDS86A-Q1
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC Supply voltage range(2) –0.5 4 V
Voltage range at any terminal –0.5 VCC + 0.5 V
All pins (Class 3A) 4 kV
Electrostatic discharge(3) All pins (Class 2B) 200 V
Continuous total power dissipation See Dissipation Rating Table
TJOperating virtual junction temperature range –40 150 °C
Tstg Storage temperature range –65 150 °C
Lead temperature 1,6 mm (1/16 in) from case for 10 s 260 °C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the GND terminals unless otherwise noted.
(3) This rating is measured using MIL-STD-883C Method, 3015.7.
Dissipation Rating Table
TA≤25°C DERATING FACTOR(1) TA= 70°C TA= 125°C
PACKAGE POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
DGG 1637 mW 13.1 mW/°C 1048 mW 327 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board mounted and with no air flow.
Recommended Operating Conditions
See Figure 2 MIN NOM MAX UNIT
VCC Supply voltage 3 3.3 3.6 V
VIH High-level input voltage (SHTDN) 2 V
VIL Low-level input voltage (SHTDN) 0.8 V
|VID| Magnitude differential input voltage 0.1 0.6 V
VIC Common-mode input voltage V
TAOperating free-air temperature –40 125 °C
Timing Requirements MIN NOM MAX UNIT
tc(1) Cycle time, input clock 14.7 tc32.4 ns
(1) Parameter tcis defined as the mean duration of a minimum of 32000 clock cycles.
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Product Folder Link(s): SN65LVDS86A-Q1
SN65LVDS86A-Q1
www.ti.com
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
Positive-going differential input
VIT+ 100 mV
threshold voltage
Negative-going differential input
VIT––100 mV
threshold voltage(2)
VOH High-level output voltage IOH =–4 mA 2.4 V
VOL Low-level output voltage IOL = 4 mA 0.4 V
All inputs to
Disabled, 280 μA
GND
Enabled, AnP = 1 V, 33 40
AnM = 1.4 V, tc= 15.38 ns
ICC Quiescent current (average) Enabled, CL= 8 pF, 43 mA
Grayscale pattern (see Figure 3), tc= 15.38 ns
Enabled, CL= 8 pF, 68
Worst-case pattern (see Figure 4), tc= 15.38 ns
IIH High-level input current (SHTDN) VIH = VCC ±20 μA
IIL Low-level input current (SHTDN) VIL = 0 ±25 μA
IIInput current A inputs 0 ≤VI≤2.4 V ±20 μA
IOZ High-impedance output current VO= 0 or VCC ±10 μA
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
(2) The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the
negative-going input voltage threshold only.
Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
tsu Setup time, D0–D20 to CLKOUT↓5 ns
CL= 8 pF, See Figure 5
thData hold time, CLKOUT↓to D0–D20 5 ns
tc= 15.38 ns (±0.2%),
t(RSKM) Receiver input skew margin(2) (see Figure 7) 550 700 ps
|Input clock jitter| <50 ps,(3)
VCC = 3.3 V,
tdDelay time, CLKIN↑to CLKOUT↓(see Figure 7) 3 5 7 ns
tc= 15.38 ns (±0.2%), TA= 25°C
ten Enable time, SHTDN to phase lock See Figure 7 1 ms
tdis Disable time, SHTDN to off state See Figure 8 400 ns
ttTransition time, output (10% to 90% tror tf) (data only) CL= 8 pF 3 ns
ttTransition time, output (10% to 90% tror tf) (clock only) CL= 8 pF 1.5 ns
twPulse duration, output clock 0.50 tcns
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
(2) The parameter t(RSKM) is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value
of this parameter at clock periods other than 15.38 ns can be calculated from tRSKM = tc/14 –550 ps.
(3) |Input clock jitter| is the magnitude of the change in input clock period.
Copyright ©2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): SN65LVDS86A-Q1
VID
AP
AM
VIAM
VIAP
VIC
(VIAP + VIAM)/2
CLKIN/CLKOUT
D0, D6, D12
D1, D7, D13
D2, D8, D14
D3, D9, D15
D18, D19, D20
ALL OTHERS
tc
CLKIN/CLKOUT
Even Dn
Odd Dn
SN65LVDS86A-Q1
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION
Figure 2. Voltage Definitions
A. The 16-grayscale test-pattern test device power consumption for a typical display pattern.
Figure 3. 16-Grayscale Test-Pattern Waveforms
A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVTTL outputs.
Figure 4. Worst-Case Test-Pattern Waveforms
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Product Folder Link(s): SN65LVDS86A-Q1
D0−D20
tsu
CLKOUT
th
70% VOH
70% VOH
30% VOH
30% VOH
SN65LVDS86A-Q1
www.ti.com
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 5. Setup and Hold Time Waveforms
Copyright ©2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): SN65LVDS86A-Q1
An
CLKIN
tc
CLKOUT
td
0 V
≈300 mV
≈−300 mV
90%
10%
tr < 1 ns
VOL
VOH
1.4 V
td
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
3
7tct(RSKM)
th1
tsu1
4
7tct(RSKM)
and An
CLKIN
or An
CLKOUT
tW
tW
±
±
(see Note A)
(see Note A)
Internal Strobing Position
Device
Under
Test
(DUT)
CLKIN
Tektronix
HFS9003/HFS9DG1
Stimulus System
(repeating patterns of
1110111 and 0001000)
Tektronix
Microwave Logic
Multi-BERT-100RX
Word Error Detector
An D0 − D20
CLKOUT
SN65LVDS86A-Q1
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A. CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The advance or
delay is then reduced until there are no data errors observed. The magnitude of the advance or delay is t(RSKM).
Figure 6. Receiver Input Skew Margin, Setup/Hold Time, and Delay Time Definitions
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Product Folder Link(s): SN65LVDS86A-Q1
CLKIN
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ten
SHTDN
An
Dn ValidInvalid
CLKIN
CLKOUT
tdis
SHTDN
SN65LVDS86A-Q1
www.ti.com
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 7. Enable Time Waveforms
Figure 8. Disable Time Waveforms
Copyright ©2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): SN65LVDS86A-Q1
SUPPLY CURRENT
vs
CLOCK FREQUENCY
55
45
40
30
30 40 50 60 70
fclk − Clock Frequency − MHz
VCC = 3 V
VCC = 3.6 V
− Supply Current − mA
ICC
25
35
50
60
80 90
Grayscale Data Pattern
CL = 8 pF
TA = 25°C
VCC = 3.3 V
SN65LVDS86A-Q1
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS
Figure 9. RMS Grayscale ICC vs Clock Frequency
10 Submit Documentation Feedback Copyright ©2006–2012, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS86A-Q1
RED0 RED0
RED1 RED1
RED2 RED2
RED3 RED3
NA RED4
NA RED5
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
NA GREEN4
NA GREEN5
BLUE0 BLUE0
BLUE1 BLUE1
BLUE2 BLUE2
BLUE3 BLUE3
NA BLUE4
NA BLUE5
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLOCK CLOCK
12-BIT 18-BIT
Graphics Controller
SN75LVDS86A/
SN65LVDS86AQ
SN75LVDS84/5
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKOUT
24
26
27
29
30
31
33
34
35
37
39
40
41
43
45
46
47
1
2
4
5
23
100 Ω
8
9
41
40
100 Ω
10
11
39
38
100 Ω
14
15
35
34
100 Ω
16
17
33
32
Cable Flat Panel DisplayHost
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
A0M
A0P
A1M
A1P
A2M
A2P
CLKINM
CLKINP
SN65LVDS86A-Q1
www.ti.com
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
APPLICATION INFORMATION
A. The four 100-Ωterminating resistors are recommended to be 0603 types.
B. NA –not applicable, these unused inputs should be left open.
Figure 10. 18-Bit Color Host to Flat Panel Display Application
Copyright ©2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): SN65LVDS86A-Q1
SN75LVDS86A/
SN65LVDS86AQ
SN75LVDS81/83
100 Ω
8
9
48
47
100 Ω
10
11
46
45
100 Ω
14
15
42
41
16
17
100 Ω
40
39
Cable Flat Panel DisplayHost
Y0M
Y0P
Y1M
Y1P
Y2M
Y2P
CLKOUTM
CLKOUTP
A0M
A0P
A1M
A1P
A2M
A2P
CLKINM
CLKINP
RED0 RED0
RED1 RED1
RED2 RED2
RED3 RED3
NA RED4
NA RED5
GREEN0 GREEN0
GREEN1 GREEN1
GREEN2 GREEN2
GREEN3 GREEN3
NA GREEN4
NA GREEN5
BLUE0 BLUE0
BLUE1 BLUE1
BLUE2 BLUE2
BLUE3 BLUE3
NA BLUE4
NA BLUE5
H_SYNC H_SYNC
V_SYNC V_SYNC
ENABLE ENABLE
CLOCK CLOCK
12-BIT 18-BIT
Graphics Controller
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
CLKOUT
24
26
27
29
30
31
33
34
35
37
39
40
41
43
45
46
47
1
2
4
5
23
38
37
Y3M
Y3P
SN65LVDS86A-Q1
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
www.ti.com
A. The four 100-Ωterminating resistors are recommended to be 0603 types.
B. NA –not applicable, these unused inputs should be left open.
Figure 11. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application
See the FLatLink Designer's Guide (literature number SLLA012) for more application information.
12 Submit Documentation Feedback Copyright ©2006–2012, Texas Instruments Incorporated
Product Folder Link(s): SN65LVDS86A-Q1
SN65LVDS86A-Q1
www.ti.com
SLLS768A –AUGUST 2006–REVISED JANUARY 2012
Changes from Original (August 2006) to Revision A Page
•Changed Wide Phase-Lock Input Frequency Range lower limit from 10 MHz to 31 MHz ................................................... 1
Copyright ©2006–2012, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN65LVDS86A-Q1
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
SN65LVDS86AQDGGG4 ACTIVE TSSOP DGG 48 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 65LVDS86AQ
SN65LVDS86AQDGGRG4 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 65LVDS86AQ
SN65LVDS86AQDGGRQ1 ACTIVE TSSOP DGG 48 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 65LVDS86AQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 18-Jun-2014
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65LVDS86A-Q1 :
•Catalog: SN65LVDS86A
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
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