DS1338 2-Wire RTC with 56-Byte NV RAM www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS1338 serial real-time clock (RTC) is a lowpower, full binary-coded decimal (BCD) clock/calendar plus 56 Bytes of NV SRAM. Address and data are transferred serially through a 2-wire bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1338 has a built-in powersense circuit that detects power failures and automatically switches to the battery supply. RTC Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 56-Byte Battery-Backed NV RAM for Data Storage 2-Wire Serial Interface Programmable Square-Wave Output Signal Automatic Power-Fail Detect and Switch Circuitry Consumes Less than 500nA in Battery-Backup Mode with Oscillator Running Recognized by Underwriters Laboratory (UL) ORDERING INFORMATION APPLICATIONS Handhelds (GPS, POS Terminal) Consumer Electronics (Set-Top Box, Digital Recording, Network Appliance) Office Equipment (Fax/Printer, Copier) Medical (Glucometer, Medicine Dispenser) Telecommunications (Router, Switcher, Server) Other (Utility Meter, Vending Machine, Thermostat, Modem) TYPICAL OPERATING CIRCUIT PART TEMP RANGE PIN-PACKAGE TOP MARK DS1338Z-18 -40C to +85C 8 SO (150mil) DS1338-18 DS1338Z-3 -40C to +85C 8 SO (150mil) DS1338-3 DS1338Z-33 -40C to +85C 8 SO (150mil) DS1338-33 DS1338U-18 -40C to +85C 8 mSOP DS1338U-3 -40C to +85C 8 mSOP DS1338U-33 -40C to +85C 8 mSOP 1338 rr-18 1338 rr-3 1338 rr-33 rr = revision level PIN CONFIGURATION TOP VIEW X1 X2 VBAT GND VCC 1 8 2 7 3 6 SCL 4 5 SDA SQW/OUT SO, SOP Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 16 010803 DS1338 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.3V to +6.0V -40C to +85C -55C to +125C See IPC/JEDEC J-STD-020A Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device. RECOMMENDED DC OPERATING CONDITIONS (VCC = VCC MIN to VCC MAX, TA = -40C to +85C.) (Note 1) PARAMETER SYMBOL Supply Voltage VCC Logic 1 VIH Logic 0 VIL Power-Fail Voltage VPF VBAT Battery Voltage VBAT CONDITIONS MIN TYP MAX DS1338-18 DS1338-3 DS1338-33 (Note 2) 1.71 2.7 3.0 0.7 VCC 1.8 3.0 3.3 1.89 3.3 3.63 VCC + 0.3 (Note 2) DS1338-18 DS1338-3 DS1338-33 (Note 2) -0.3 1.51 2.45 2.70 1.3 0.3 VCC 1.71 2.70 2.97 3.7 1.62 2.59 2.82 3.0 UNITS V V V DC ELECTRICAL CHARACTERISTICS (VCC = VCC MIN to VCC MAX, TA = -40C to +85C.) (Note 1) PARAMETER VBAT Battery Voltage SYMBOL CONDITIONS VBAT (Note 2) Input Leakage ILI (Note 3) I/O Leakage ILO (Note 4) VCC > 2V; VOL = 0.4V VCC < 2V; VOL = 0.2 VCC VCC > 2V; VOL = 0.4V 1.71V < VCC < 2V; VOL = 0.2 VCC 1.3V < VCC < 1.71V; VOL = 0.2 VCC DS1338-18 DS1338-3 DS1338-33 DS1338-18 DS1338-3 DS1338-33 SDA Logic 0 Output IOLSDA SQW/OUT Logic 0 Output IOLSQW Active Supply Current (Note 5) ICCA Standby Current (Note 6) ICCS VBAT Leakage Current (VCC Active) IBATLKG 2 of 16 MIN TYP 1.3 MAX UNITS 3.7 V 1 mA 1 3.0 3.0 3.0 mA 3.0 250 75 110 120 60 80 85 150 200 200 100 125 125 25 100 mA mA mA mA mA nA DS1338 DC ELECTRICAL CHARACTERISTICS (VCC = 0V, TA = -40C to +85C.) (Note 1) PARAMETER Oscillator Current (OSC ON); VBAT = 3.7V, SQW/OUT OFF (Note 7) TYP MAX UNITS IBATOSC1 400 1200 nA SQW/OUT ON (32kHz) (Note 7) IBATOSC2 570 1400 nA VBAT Data-Retention Current; VBAT = 3.7V (Oscillator Off, VCC = 0.0V) IBATDAT 10 100 nA TYP MAX UNITS Oscillator Current (OSC ON); VBAT = 3.7V, SYMBOL MIN CRYSTAL SPECIFICATIONS* PARAMETER Nominal Frequency SYMBOL fO MIN 32.768 Series Resistance ESR Load Capacitance CL kHz 45 12.5 k pF *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. 3 of 16 DS1338 AC ELECTRICAL CHARACTERISTICS (TA = -40C to +85C) (Note 1) PARAMETER SYMBOL SCL Clock Frequency fSCL Bus Free Time Between STOP and START Condition tBUF Hold Time (Repeated) START Condition (Note 8) tHD:STA LOW Period of SCL Clock tLOW HIGH Period of SCL Clock tHIGH Setup Time for Repeated START Condition tSU:STA Data Hold Time (Notes 9, 10) tHD:DAT Data Setup Time (Note 11) tSU:DAT Rise Time of Both SDA and SCL Signals (Note 12) tR CONDITION Fast mode MIN TYP 100 400 Standard mode 100 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 1.3 Standard mode 4.7 Fast mode 0.6 Standard mode 4.0 Fast mode 0.6 Standard mode 4.7 Fast mode 0 Standard mode 0 Fast mode 100 Standard mode 250 Fast mode tF Setup Time for STOP Condition tSU:STO Fast mode UNITS kHz ms ms ms ms ms 0.9 ms ns 20 + 0.1CB 300 Standard mode Fall Time of Both SDA and SCL Signals (Note 12) MAX ns 1000 20 + 0.1CB 300 Standard mode ns 300 Fast mode 0.6 Standard mode 4.0 ms Capacitive Load for Each Bus Line (Note 12) CB I/O Capacitance CI/O 10 pF Oscillator Stop Flag (OSF) Delay (Note 13) tOSF 100 ms 400 4 of 16 pF DS1338 POWER-UP/POWER-DOWN CHARACTERISTICS (TA = -40C to +85C) (Note 1) PARAMETER SYMBOL MIN TYP MAX UNITS 2 ms Recovery at Power-Up (Note 14) tREC VCC Fall Time; VPF(MAX) to VPF(MIN) tVCCF 300 ms VCC Rise Time; VPF(MIN) to VPF(MAX) tVCCR 0 ms Note 1: Limits at -40C are guaranteed by design and not production tested. Note 2: All voltages are referenced to ground. Note 3: SCL only. Note 4: SDA and SQW/OUT. Note 5: ICCA--SCL clocking at max frequency = 400kHz. Note 6: Specified with 2-wire bus inactive. Note 7: Measured with a 32.768kHz crystal attached to X1 and X2. Note 8: After this period, the first clock pulse is generated. Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL. Note 10: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. Note 11: A fast mode device can be used in a standard mode system, but the requirement tSU:DAT to 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released. Note 12: CB--total capacitance of one bus line in pF. Note 13: The parameter tOSF is the time period the oscillator must be stopped for the OSF flag to be set over the voltage range of 0.0V VCC VCC MAX and 1.3V VBAT 3.7V. Note 14: This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay occurs. 5 of 16 DS1338 TYPICAL OPERATING CHARACTERISTICS (VCC = 3.3V, TA = +25 C, unless otherwise noted.) SUPPLY CURRENT (nA) SUPPLY CURRENT (nA) 900 850 800 750 700 650 600 1.8 2.3 2.8 3.3 3.8 4.3 4.8 1.3 5.3 1.8 2.3 2.8 3.3 3.8 4.3 VBAT (V) IBAT0SC1 vs. TEMPERATURE VBAT = 3.0V ICCA vs. VCC SQUARE-WAVE ON VCC = 0V 4.8 5.3 275 250 SUPPLY CURRENT (mA) 850 800 750 225 200 175 150 125 100 75 700 -20 0 20 40 60 50 80 1.8 2.3 TEMPERATURE ( C) 2.8 3.3 3.8 VCC (V) OSCILLATOR FREQUENCY vs. VBAT 32767.75 DS1338 toc05 -40 VCC = 0V 32767.74 32767.73 FREQUENCY (Hz) SUPPLY CURRENT (nA) VCC = 0V VBAT (V) DS1338 toc03 1.3 1400 1350 1300 1250 1200 1150 1100 1050 1000 950 900 850 800 750 700 DS1338 toc02 VCC = 0V 950 DS1338 toc04 1000 IBAT0SC2 vs. VCC SQUARE-WAVE ON DS1338 toc01 IBAT0SC1 vs. VCC SQUARE-WAVE OFF 32767.72 32767.71 32767.70 32767.69 32767.68 32767.67 32767.66 32767.65 1.3 1.8 2.3 2.8 3.3 VBAT (V) 6 of 16 3.8 4.3 4.8 5.3 4.3 4.8 5.3 DS1338 Figure 1. Timing Diagram Figure 2. Power-Up/Power-Down Timing VCC V PF(max) VPF(min) t VCCR t VCCF tREC INPUTS DON'T CARE RECOGNIZED RECOGNIZED HIGH-Z OUTPUTS VALID VALID 7 of 16 DS1338 Figure 3. Block Diagram X1 X2 TIMEKEEPING AND CONTROL REGISTERS OSCILLATOR AND DIVIDER SQW/OUT VCC VBAT POWER CONTROL CONTROL LOGIC RAM (56 x 8) SCL SERIAL BUS INTERFACE ADDRESS REGISTER SDA DS1338 8 of 16 DS1338 PIN DESCRIPTION PIN NAME 1 X1 2 X2 FUNCTION 32.768kHz Crystal Connections. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 12.5pF. Pin X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1. An external 32.768kHz oscillator can also drive the DS1338. In this configuration, the X1 pin is connected to the external oscillator signal and the X2 pin is floated. Note: For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks. 3 VBAT 4 GND 5 SDA 6 SCL 7 8 +3V Battery Input. Backup supply input for any standard 3V lithium cell or other energy source. Battery voltage must be held between the minimum and maximum limits for proper operation. If a backup supply is not required, VBAT must be grounded. Ground. DC power is provided to the device on these pins. VCC is the primary power input. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is connected to the device and VCC is below VPF, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. Serial Data. Input/output pin for the 2-wire serial interface. It is open drain and requires an external pullup resistor. Serial Clock. Used to synchronize data movement on the serial interface Square-Wave/Output Driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, SQW/OUT 32kHz). It is open drain and requires an external pullup resistor. Operates with either VCC or VBAT applied. Primary Power Supply. When voltage is applied within normal limits, the device is fully accessible and data can be written and read. When a backup supply is VCC connected to the device and VCC is below VPF, reads and writes are inhibited. However, the timekeeping function continues unaffected by the lower input voltage. 9 of 16 DS1338 Detailed Description The DS1338 serial RTC is a low-power, full BCD clock/calendar plus 56 Bytes of NV SRAM. Address and data are transferred serially through a 2-wire bidirectional bus. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with AM/PM indicator. The DS1338 has a built-in power-sense circuit that detects power failures and automatically switches to the battery supply. Operation The DS1338 operates as a slave device on the serial bus. Access is obtained by implementing a START condition and providing a device identification code, followed by data. Subsequent registers can be accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock registers are blocked from any access. If VPF is less than VBAT, the device power is switched from VCC to VBAT when VCC drops below VPF. If VPF is greater than VBAT, the device power is switched from VCC to VBAT when VCC drops below VBAT. The registers are maintained from the VBAT source until VCC is returned to nominal levels. The block diagram (Figure 3) shows the main elements of the DS1338. An enable bit in the seconds register controls the oscillator. Oscillator start-up times are highly dependent upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are the major contributors to long start-up times. A circuit using a crystal with the recommended characteristics and proper layout usually starts within 1 second. RTC and RAM Address Map Figure 5 shows the address map for the RTC and RAM registers. The RTC registers and control register are located in address locations 00h to 07h. The RAM registers are located in address locations 08h to 3Fh. During a multibyte access, when the register pointer reaches 3Fh (the end of RAM space) it wraps around to location 00h (the beginning of the clock space). On a 2-wire START, STOP, or register pointer incrementing to location 00h, the current time and date is transferred to a second set of registers. The time and date in the secondary registers are read in a multibyte data transfer, while the clock continues to run. This eliminates the need to reread the registers in case of an update of the main registers during a read. Clock and Calendar The time and calendar information is obtained by reading the appropriate register bytes. See Figure 4 for the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the BCD format. Bit 7 of Register 0 is the clock halt (CH) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled. The clock can be halted whenever the timekeeping functions are not required, which decreases VBAT current. The day-of-week register increments at midnight. Values that correspond to the day of week are userdefined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time and date entries result in undefined operation. When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero. The countdown chain is reset whenever the seconds register is written. Write transfers occur on the 10 of 16 DS1338 acknowledge from the DS1338. Once the countdown chain is reset, to avoid rollover issues the remaining time and date registers must be written within 1 second. The 1Hz square-wave output, if enabled, transitions high 500ms after the seconds data transfer, provided the oscillator is already running. Please note that the initial power-on state of all registers, unless otherwise specified, is not defined. Therefore, it is important to enable the oscillator (CH = 0) during initial configuration. The DS1338 runs in either 12-hour or 24-hour mode. Bit 6 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit, with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20-23 hours). On a 2-wire START, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock continues to run. This eliminates the need to reread the registers in case of an update of the main registers during a read. Figure 4. RTC and RAM Address Map ADDRESS BIT 7 00H 01H CH 0 02H 0 12/24 03H 04H 05H 06H 07H 08H-3FH 0 0 0 0 0 0 OUT BIT 6 BIT 5 10 seconds 10 minutes AM/PM 10 hour 0 BIT 4 BIT 3 BIT 2 10 hour 0 10 date 0 10 mo 10 year 0 OSF SQWE 0 0 11 of 16 BIT 1 FUNCTION RANGE seconds minutes seconds minutes hour hours 00-59 00-59 1-12 +am/pm 00-23 1-7 00-31 01-12 00-99 day date month year 0 RS1 BIT 0 RS0 day date month year control RAM 56 x 8 00H-FFH DS1338 Control Register (07h) BIT 7 OUT BIT 6 0 BIT 5 OSF BIT 4 SQWE BIT 3 0 BIT 2 0 BIT 1 RS1 BIT 0 RS0 The control register controls the operation of the SQW/OUT pin and provides oscillator status. BIT 7 5 4 1, 0 NAME FUNCTION Output Control. Controls the output level of the SQW/OUT pin when the squareOUT wave output is disabled. If SQWE = 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0. Oscillator Stop Flag. A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The following are examples of conditions that may cause the OSF bit to be set: OSF 1) The first time power is applied. 2) The voltage present on VCC and VBAT are insufficient to support oscillation. 3) The CH bit is set to 1, disabling the oscillator. 4) External influences on the crystal (i.e., noise, leakage, etc.). This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1 leaves the value unchanged. Square-Wave Enable. When set to logic 1, this bit enables the oscillator output to SQWE operate with either VCC or VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits. Rate Select. These bits control the frequency of the square-wave output when the RS square-wave output has been enabled. Table 1 lists the square-wave frequencies that can be selected with the RS bits. Table 1. Square-Wave Output Frequency RS1 0 0 1 1 RS0 0 1 0 1 SQW OUTPUT FREQUENCY 1Hz 4.096kHz 8.192kHz 32.768kHz 12 of 16 DS1338 2-Wire Serial Data Bus The DS1338 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data is a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. The bus must be controlled by a master device, which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1338 operates as a slave on the 2-wire bus. Within the bus specifications, a standard mode (100kHz cycle rate) and a fast mode (400kHz cycle rate) are defined. The DS1338 works in both modes. Figures 5, 6, and 7 detail how data is transferred on the 2-wire bus. Data transfer can be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Within the 2-wire bus specifications a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate) are defined. Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. 13 of 16 DS1338 Depending upon the state of the R/W bit, two types of data transfer are possible: 1) Data transfer from a master transmitter to a slave receiver. The master transmits the first byte (the slave address). Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data is transferred with the most significant bit (MSB) first. 2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte (the slave address). The slave then returns an acknowledge bit, which is followed by the slave transmitting a number of data bytes. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a "not acknowledge" is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the bus is not released. Data is transferred with the most significant bit (MSB) first. The DS1338 can operate in the following two modes: 1) Slave receiver mode (write mode): Serial data and clock are received through SDA and SCL. An acknowledge bit is transmitted after each byte is received. START and STOP conditions are recognized as the beginning and end of a serial transfer. Hardware performs address recognition after reception of the slave address and direction bit (Figure 6). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1338 address--1101000--followed by the direction bit (R/W), which, for a write, is 0. After receiving and decoding the slave address byte, the slave outputs an acknowledge on the SDA line. After the DS1338 acknowledges the slave address and write bit, the master transmits a word address to the DS1338. This sets the register pointer on the DS1338, with DS1338 acknowledging the transfer. The master may then transmit zero or more bytes of data, with the DS1338 acknowledging each byte received. The register pointer increments after each byte is transferred. The master generates a STOP condition to terminate the data write. 2) Slave transmitter mode (read mode): The first byte is received and handled as in the slave receiver mode. However, in this mode, the direction bit indicates that the transfer direction is reversed. The DS1338 transmits serial data on SDA while the serial clock is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer (Figure 7). The slave address byte is the first byte received after the master generates the START condition. The slave address byte contains the 7-bit DS1338 address--1101000--followed by the direction bit (R/W), which, for a read, is 1. After receiving and decoding the slave address byte, the slave outputs an acknowledge on the SDA line. The DS1338 then starts transmitting data using the register address pointed to by the register pointer. If the register pointer is not set before the initiation of a read mode, the first address that is read is the last one stored in the register pointer. The register pointer is incremented after each byte is transferred. The DS1338 must receive a "not acknowledge" to end a read. 14 of 16 DS1338 Figure 5. Data Transfer On 2-Wire Serial Bus Figure 6. Data Write: Slave Receiver Mode Figure 7. Data Read: Slave Transmitter Mode 15 of 16 DS1338 Package Information (For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) 16 of 16