DS1338
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Detailed Description
The DS1338 serial RTC is a low-power, full BCD clock/calendar plus 56 Bytes of NV SRAM. Address
and data are transferred serially through a 2-wire bidirectional bus. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information. The end of the month date is automatically
adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in
either the 24-hour or 12-hour format with AM/PM indicator. The DS1338 has a built-in power-sense
circuit that detects power failures and automatically switches to the battery supply.
Operation
The DS1338 operates as a slave device on the serial bus. Access is obtained by implementing a START
condition and providing a device identification code, followed by data. Subsequent registers can be
accessed sequentially until a STOP condition is executed. The device is fully accessible and data can be
written and read when VCC is greater than VPF. However, when VCC falls below VPF, the internal clock
registers are blocked from any access. If VPF is less than VBAT, the device power is switched from VCC to
VBAT when VCC drops below VPF. If VPF is greater than VBAT, the device power is switched from VCC to
VBAT when VCC drops below VBAT. The registers are maintained from the VBAT source until VCC is
returned to nominal levels. The block diagram (Figure 3) shows the main elements of the DS1338.
An enable bit in the seconds register controls the oscillator. Oscillator start-up times are highly dependent
upon crystal characteristics, PC board leakage, and layout. High ESR and excessive capacitive loads are
the major contributors to long start-up times. A circuit using a crystal with the recommended
characteristics and proper layout usually starts within 1 second.
RTC and RAM Address Map
Figure 5 shows the address map for the RTC and RAM registers. The RTC registers and control register
are located in address locations 00h to 07h. The RAM registers are located in address locations 08h to
3Fh. During a multibyte access, when the register pointer reaches 3Fh (the end of RAM space) it wraps
around to location 00h (the beginning of the clock space). On a 2-wire START, STOP, or register pointer
incrementing to location 00h, the current time and date is transferred to a second set of registers. The time
and date in the secondary registers are read in a multibyte data transfer, while the clock continues to run.
This eliminates the need to reread the registers in case of an update of the main registers during a read.
Clock and Calendar
The time and calendar information is obtained by reading the appropriate register bytes. See Figure 4 for
the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes.
The contents of the time and calendar registers are in the BCD format. Bit 7 of Register 0 is the clock halt
(CH) bit. When this bit is set to 1, the oscillator is disabled. When cleared to 0, the oscillator is enabled.
The clock can be halted whenever the timekeeping functions are not required, which decreases VBAT
current.
The day-of-week register increments at midnight. Values that correspond to the day of week are user-
defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on). Illogical time
and date entries result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors
when the internal registers update. When reading the time and date registers, the user buffers are
synchronized to the internal registers on any start or stop and when the register pointer rolls over to zero.
The countdown chain is reset whenever the seconds register is written. Write transfers occur on the