CX81801-83 - Conexant Systems, Inc.

Doc. No. 102247B

October 30, 2003

CX81801-7x/8x

SmartV.XX

V.92/V.34/V.32bis Modem in 128-Pin LQFP

with CX20493 SmartDAA in 32-Pin LQFP

and Optional CX20442 Voice Codec

Data Sheet

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

ii Conexant 102247B

Revision Record

Revision Date Comments

A 8/27/2003 Initial release.

B 10/30/2003 Rev. B release.

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CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant iii

Contents

1. Introduction..........................................................................................................................................1-1

1.1 Overview ......................................................................................................................................................................... 1-1

1.2 Applications .................................................................................................................................................................... 1-2

1.3 Features .......................................................................................................................................................................... 1-4

1.3.1 General Modem Features................................................................................................................................ 1-4

1.3.2 SmartDAA Features ........................................................................................................................................ 1-5

1.3.3 Applications.................................................................................................................................................... 1-5

1.4 Technical Overview......................................................................................................................................................... 1-6

1.4.1 General Description ........................................................................................................................................ 1-6

1.4.2 MCU Firmware................................................................................................................................................ 1-6

1.4.3 Operating Modes ............................................................................................................................................ 1-6

1.4.3.1 Data/Fax Modes.......................................................................................................................... 1-6

1.4.3.2 V.44 Data Compression.............................................................................................................. 1-7

1.4.3.3 Worldwide Operation.................................................................................................................. 1-7

1.4.3.4 TAM Mode.................................................................................................................................. 1-8

1.4.3.5 Speakerphone Mode (S Models)................................................................................................ 1-9

1.4.4 Reference Designs.......................................................................................................................................... 1-9

1.5 Hardware Description ..................................................................................................................................................... 1-9

1.5.1 CX81801 Modem Device ................................................................................................................................ 1-9

1.5.2 Digital Isolation Barrier................................................................................................................................. 1-10

1.5.3 CX20493 SmartDAA Line Side Device.......................................................................................................... 1-10

1.5.4 CX20442 Voice Codec .................................................................................................................................. 1-10

1.6 AT Commands .............................................................................................................................................................. 1-10

2. Technical Specifications .......................................................................................................................2-1

2.1 Serial DTE Interface Operation........................................................................................................................................ 2-1

2.1.1 Automatic Speed/Format Sensing .................................................................................................................. 2-1

2.2 Parallel Host Bus Interface Operation............................................................................................................................. 2-2

2.3 Establishing Data Modem Connections .......................................................................................................................... 2-2

2.3.1 Dialing ............................................................................................................................................................ 2-2

2.3.2 Telephone Number Directory.......................................................................................................................... 2-2

2.3.3 Modem Handshaking Protocol ....................................................................................................................... 2-2

2.3.4 Call Progress Tone Detection ......................................................................................................................... 2-2

2.3.5 Answer Tone Detection................................................................................................................................... 2-2

2.3.6 Ring Detection................................................................................................................................................ 2-2

2.3.7 Billing Protection ............................................................................................................................................ 2-3

2.3.8 Connection Speeds......................................................................................................................................... 2-3

2.3.9 Automode ....................................................................................................................................................... 2-3

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

iv Conexant 102247B

2.4 Data Mode ...................................................................................................................................................................... 2-4

2.4.1 Speed Buffering (Normal Mode) .................................................................................................................... 2-4

2.4.2 Flow Control ................................................................................................................................................... 2-4

2.4.3 Escape Sequence Detection............................................................................................................................ 2-4

2.4.4 BREAK Detection ............................................................................................................................................ 2-4

2.4.5 Telephone Line Monitoring............................................................................................................................. 2-4

2.4.6 Fall Forward/Fallback (V.92/V.90/V.34/V.32 bis/V.32) ................................................................................... 2-4

2.4.7 Retrain............................................................................................................................................................ 2-5

2.4.8 Programmable Inactivity Timer ...................................................................................................................... 2-5

2.4.9 DTE Signal Monitoring (Serial DTE Interface Only)........................................................................................ 2-5

2.5 V.92 Features.................................................................................................................................................................. 2-5

2.5.1 Modem-on-Hold ............................................................................................................................................. 2-5

2.5.2 Quick Connect ................................................................................................................................................ 2-6

2.5.3 PCM Upstream ............................................................................................................................................... 2-6

2.6 Error Correction and Data Compression......................................................................................................................... 2-6

2.6.1 V.42 Error Correction ..................................................................................................................................... 2-6

2.6.2 MNP 2-4 Error Correction .............................................................................................................................. 2-6

2.6.3 V.44 Data Compression.................................................................................................................................. 2-6

2.6.4 V.42 bis Data Compression ............................................................................................................................ 2-6

2.6.5 MNP 5 Data Compression .............................................................................................................................. 2-7

2.7 Telephony Extensions..................................................................................................................................................... 2-7

2.7.1 Line In Use Detection ..................................................................................................................................... 2-7

2.7.2 Extension Pickup Detection............................................................................................................................ 2-7

2.7.3 Remote Hangup Detection.............................................................................................................................. 2-8

2.8 Fax Class 1 and Fax Class 1.0 Operation ........................................................................................................................ 2-8

2.9 Point-of-Sales Support ................................................................................................................................................... 2-8

2.10 Voice/Audio Mode .......................................................................................................................................................... 2-8

2.10.1 Online Voice Command Mode ........................................................................................................................ 2-8

2.10.2 Voice Receive Mode ....................................................................................................................................... 2-8

2.10.3 Voice Transmit Mode ..................................................................................................................................... 2-9

2.10.4 Full-Duplex Receive and Transmit Mode........................................................................................................ 2-9

2.10.5 Audio Mode .................................................................................................................................................... 2-9

2.10.6 Tone Detectors ............................................................................................................................................... 2-9

2.10.7 Speakerphone Mode....................................................................................................................................... 2-9

2.11 V.80 Synchronous Access Mode (SAM) - Video Conferencing...................................................................................... 2-9

2.12 Full-Duplex Speakerphone (FDSP) Mode (S Models)................................................................................................... 2-10

2.13 Caller ID ........................................................................................................................................................................ 2-10

2.14 Worldwide Country Support ......................................................................................................................................... 2-10

2.15 Diagnostics................................................................................................................................................................... 2-11

2.15.1 Commanded Tests........................................................................................................................................ 2-11

2.15.2 Power On Reset Tests .................................................................................................................................. 2-11

2.16 Low Power Sleep Mode ................................................................................................................................................ 2-12

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102247B Conexant v

3. Hardware Interface ...............................................................................................................................3-1

3.1 CX81801 Modem Hardware Pins and Signals ................................................................................................................ 3-1

3.1.1 Common to Parallel and Serial Interface Configurations................................................................................ 3-1

3.1.1.1 LSD Interface (Through DIB)...................................................................................................... 3-1

3.1.1.2 Call Progress Speaker Interface .................................................................................................3-1

3.1.1.3 Voice Relay Interface (S Models) ............................................................................................... 3-1

3.1.1.4 Serial EEPROM Interface............................................................................................................ 3-1

3.1.1.5 External Bus Interface ................................................................................................................ 3-2

3.1.2 Serial Interface Configuration Only................................................................................................................. 3-2

3.1.2.1 Serial DTE Interface and Indicator Outputs (PARIF = Low)........................................................ 3-2

3.1.3 Parallel Interface Configuration Only (PARIF = High)..................................................................................... 3-3

3.1.3.1 Parallel Host Bus Interface ......................................................................................................... 3-3

3.1.4 CX81801 Modem Interface Signals................................................................................................................ 3-3

3.2 CX20493 LSD Hardware Pins and Signals ................................................................................................................... 3-22

3.2.1 CX20493 LSD Signal Summary.................................................................................................................... 3-22

3.2.1.1 CX81801 Interface (Through DIB)............................................................................................ 3-22

3.2.1.2 Telephone Line Interface .......................................................................................................... 3-22

3.2.1.3 Voltage References................................................................................................................... 3-22

3.2.1.4 General Purpose Input/Output.................................................................................................. 3-23

3.2.1.5 No Connects............................................................................................................................. 3-23

3.2.2 CX20493 LSD Pin Assignments and Signal Definitions ............................................................................... 3-23

3.3 CX20442 VC Hardware Pins and Signals (S Models)................................................................................................... 3-28

3.3.1 CX20442 VC Signal Summary...................................................................................................................... 3-28

3.3.1.1 Speakerphone Interface............................................................................................................ 3-28

3.3.1.2 Telephone Handset/Headset Interface...................................................................................... 3-28

3.3.1.3 CX81801 Modem Interface....................................................................................................... 3-28

3.3.1.4 Host Interface........................................................................................................................... 3-28

3.3.2 CX20442 VC Pin Assignments and Signal Definitions ................................................................................. 3-29

3.4 Electrical and Environmental Specifications ................................................................................................................. 3-35

3.4.1 Operating Conditions, Absolute Maximum Ratings, and Power Requirements ........................................... 3-35

3.4.2 Interface and Timing Waveforms ................................................................................................................. 3-37

3.4.2.1 External Memory Bus Timing ................................................................................................... 3-37

3.4.2.2 Parallel Host Bus Timing .......................................................................................................... 3-39

3.4.2.3 Serial DTE Interface.................................................................................................................. 3-41

3.5 Crystal Specifications ................................................................................................................................................... 3-42

4. Package Dimensions ............................................................................................................................4-1

5. Parallel Host Interface ..........................................................................................................................5-1

5.1 Overview ......................................................................................................................................................................... 5-1

5.2 Register Signal Definitions ............................................................................................................................................. 5-3

5.2.1 IER - Interrupt Enable Register (Addr = 1, DLAB = 0) .................................................................................... 5-3

5.2.2 FCR - FIFO Control Register (Addr = 2, Write Only) ....................................................................................... 5-4

5.2.3 IIR - Interrupt Identifier Register (Addr = 2) .................................................................................................. 5-5

5.2.4 LCR - Line Control Register (Addr = 3) .......................................................................................................... 5-6

5.2.5 MCR - Modem Control Register (Addr = 4).................................................................................................... 5-7

5.2.6 LSR - Line Status Register (Addr = 5)............................................................................................................ 5-7

5.2.7 MSR - Modem Status Register (Addr = 6) ..................................................................................................... 5-9

5.2.8 RBR - RX Buffer (Receiver Buffer Register) (Addr = 0, DLAB = 0) ................................................................ 5-9

5.2.9 THR - TX Buffer (Transmitter Holding Register) (Addr = 0, DLAB = 0).......................................................... 5-9

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

vi Conexant 102247B

5.2.10 Divisor Registers (Addr = 0 and 1, DLAB = 1).............................................................................................. 5-10

5.3 Receiver FIFO Interrupt Operation ................................................................................................................................ 5-10

5.3.1 Receiver Data Available Interrupt ................................................................................................................. 5-10

5.3.2 Receiver Character Timeout Interrupts......................................................................................................... 5-11

5.4 Transmitter FIFO Interrupt Operation ........................................................................................................................... 5-11

5.4.1 Transmitter Empty Interrupt......................................................................................................................... 5-11

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant vii

Figures

Figure 1-1. SmartV.XX Modem Simplified Interface Diagram ............................................................................................ 1-3

Figure 1-2. SmartV.XX Modem Major Interfaces................................................................................................................ 1-3

Figure 2-1. TMIND# Test Results Pulse Cycles ................................................................................................................ 2-12

Figure 3-1. CX81801 Modem Hardware Signals for Parallel Interface (PARIF = High) ...................................................... 3-4

Figure 3-2. CX81801 Modem 128-Pin LQFP Pin Signals for Parallel Interface (PARIF = High) ......................................... 3-5

Figure 3-3. CX81801 Modem Hardware Signals for Serial Interface (PARIF = Low)........................................................ 3-12

Figure 3-4. CX81801 Modem 128-Pin LQFP Pin Signals for Serial Interface (PARIF = Low)...........................................3-13

Figure 3-5. CX20493 LSD Hardware Interface Signals ..................................................................................................... 3-23

Figure 3-6. CX20493 LSD 32-Pin LQFP Pin Signals ......................................................................................................... 3-24

Figure 3-7. CX20442 VC Hardware Interface Signals ....................................................................................................... 3-30

Figure 3-8. CX20442 VC 32-Pin LQFP Pin Signals ........................................................................................................... 3-30

Figure 3-9. Waveforms - External Memory Bus................................................................................................................ 3-38

Figure 3-10. Waveforms - Parallel Host Bus..................................................................................................................... 3-40

Figure 3-11. Waveforms - Serial DTE Interface ................................................................................................................ 3-41

Figure 4-1. Package Dimensions - 128-Pin LQFP............................................................................................................... 4-2

Figure 4-2. Package Dimensions - 32-Pin LQFP................................................................................................................. 4-3

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

viii Conexant 102247B

Tables

Table 1-1. SmartV.XX Modem Models and Functions ........................................................................................................ 1-2

Table 1-2. Default Countries Supported.............................................................................................................................. 1-8

Table 2-1. +MS Command Automode Connectivity............................................................................................................ 2-3

Table 3-1. CX81801 Modem 128-Pin LQFP Pin Signals for Parallel Interface (PARIF = High)........................................... 3-6

Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) ................................................. 3-8

Table 3-3. CX81801 Modem 128-Pin LQFP Pin Signals for Serial Interface (PARIF = Low)............................................3-14

Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low)................................................... 3-16

Table 3-5. CX81801 Modem I/O Type Definitions ............................................................................................................ 3-21

Table 3-6. CX81801 Modem DC Electrical Characteristics ............................................................................................... 3-21

Table 3-7. CX20493 LSD 32-Pin LQFP Pin Signals .......................................................................................................... 3-24

Table 3-8. CX20493 LSD Pin Signal Definitions ............................................................................................................... 3-25

Table 3-9. CX20493 LSD GPIO DC Electrical Characteristics ........................................................................................... 3-27

Table 3-10. CX20493 AVdd DC Electrical Characteristics................................................................................................. 3-27

Table 3-11. CX20442 VC 32-Pin LQFP Pin Signals........................................................................................................... 3-31

Table 3-12. CX20442 VC Pin Signal Definitions ............................................................................................................... 3-32

Table 3-13. CX20442 VC DC Electrical Characteristics..................................................................................................... 3-33

Table 3-14. CX20442 VC Analog Electrical Characteristics............................................................................................... 3-34

Table 3-15. Operating Conditions ..................................................................................................................................... 3-35

Table 3-16. Absolute Maximum Ratings........................................................................................................................... 3-35

Table 3-17. Current and Power Requirements.................................................................................................................. 3-36

Table 3-18. Timing - External Memory Bus ...................................................................................................................... 3-37

Table 3-19. Timing - Parallel Host Bus ............................................................................................................................. 3-39

Table 3-20. Crystal Specifications..................................................................................................................................... 3-42

Table 5-1. Parallel Interface Registers ................................................................................................................................ 5-2

Table 5-2. Interrupt Sources and Reset Control ................................................................................................................. 5-5

Table 5-3. Programmable Baud Rates .............................................................................................................................. 5-10

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 1-1

1. Introduction

1.1 Overview

The Conexant SmartV.XX Modem is a full-featured, worldwide, controller-based

modem that integrates modem controller (MCU), modem data pump (MDP), 256 KB

ROM, 32 KB RAM, and SmartDAA system side device (SSD) functions onto a single

die.

The modem operates by executing firmware from internal ROM and RAM. Optional

customized firmware is supported with optional external flash ROM memory.

Additionally, added/modified country profiles are supported by internal SRAM patch

(maximum of one profile) or serial EEPROM. Downloadable architecture supports

downloading of customized MCU firmware from the host/DTE to the SmartV.XX

modem.

The SmartV.XX Modem device set consists of a CX81801 modem device in a 128-pin

LQFP and a CX20493 SmartDAA Line Side Device (LSD) in a 32-pin LQFP

Conexant’s SmartDAA technology eliminates the need for a costly analog transformer,

relays and opto-isolations typically used in discrete DAA (Data Access Arrangement)

implementations. The SmartDAA architecture also simplifies product implementation by

eliminating the need for country-specific board configurations enabling worldwide

homologation of a single modem board design and a single bill of materials (BOM).

Low profile, small LQFP and LQFP packages with reduced voltage operation and low

power consumption makes this device set an ideal solution for embedded and palmtop

application using parallel host or serial DTE interface.

The SmartV.XX Modem supports data rates up to V.92, data compression, error

correction, fax rates up to 14.4 kbps and speakerphone mode.

In V.92 and V.90 (V.92 models) data modes, the modem can receive data at speeds up to

56 kbps. In V.34 data mode (V.92 and V.34 models), the modem can receive data at

speeds up to 33.6 kbps. In V.32 bis data mode, the modem can receive data at speeds up

to 14.4 kbps.

Data compress (V.44/V.42bis/MNP5) and error correction (V.42/MNP 2-4) modes are

supported to maximize data throughput and data transfer integrity. Non-error-correction

mode is also supported.

Fax Group 3 send and receive rates are supported up to 14.4 kbps with T.30 protocol.

The SmartV.XX modem operates with PSTN telephone lines worldwide.

S models, using the optional CX20442 Voice Codec (VC) in a 32-pin LQFP, support

position independent, full-duplex speakerphone (FDSP) operation using microphone and

speaker, as well as other voice/TAM applications using handset or headset.

Table 1-1 lists the available models. A simplified device interface drawing is shown in

Figure 1-1. A functional interface drawing showing optional memory is shown in

Figure 1-2.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

1-2 Conexant 102247B

1.2 Applications

• Set top boxes

• Gaming devices

• Point of sale terminals

• Remote monitoring and data collections systems

• Handheld computers

• Other embedded systems

Table 1-1. SmartV.XX Modem Models and Functions

Model/Order/Part Numbers Supported Functions

Marketing Name Device Set Order

No.

Modem Device

[128-Pin LQFP]

Part No.

Line Side Device

(LSD)

[32-Pin LQFP]

Part No.

Voice Codec

(VC)

[32-Pin LQFP]

Part No.

V.90 Data,

QC, MOH

V.34 Data V.32 bis Data,

V.44 Data

Compression,

V.17 Fax, TAM,

Worldwide

Voice/

FDSP

SmartV.92 TBD CX81801-74 CX20493-25/APP — Y Y Y —

SmartV.92/S TBD CX81801-74 CX20493-25/APP CX20442-11 Y Y Y Y

SmartV.34 TBD CX81801-72 CX20493-25/APP — — Y Y —

SmartV.34/S TBD CX81801-72 CX20493-25/APP CX20442-11 — Y Y Y

SmartV.32bis TBD CX81801-73 CX20493-25/APP — — — Y —

SmartV.32bis/S TBD CX81801-73 CX20493-25/APP CX20442-11 — — Y Y

Lead-Free Device Sets (See Note 2)

SmartV.92/LF TBD CX81801-84 CX20493-35/APP — Y Y Y —

SmartV.34/LF TBD CX81801-82 CX20493-35/APP — — Y Y —

SmartV.32bis/LF TBD CX81801-83 CX20493-35/APP — — — Y —

Notes:

1. Supported functions (Y = Supported; — = Not supported).

QC, MOH, PCM Quick connect, Modem-on-Hold, PCM upstream

TAM Telephone answering machine (Voice playback and record through telephone line)

FDSP Full-duplex speakerphone and voice playback and record through telephone line, handset, and mic/speaker

2. LF = Lead (Pb)-free devices.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 1-3

Figure 1-1. SmartV.XX Modem Simplified Interface Diagram

CX81801

Modem

128-Pin LQFP

CX20493

SmartDAA

Line Side

Device (LSD)

32-Pin LQFP

CX20442

Voice Codec

(VC)

32-Pin LQFP

(Optional)

MIC

SPEAKER

TIP

RING

Telephone

Line

Interface

Discrete

Components

102247_001

Digital

Isolation

Barrier

(DIB)

TIP

RING HANDSET (OPTIONAL)

TELEPHONE LINE

(OPTIONAL)

PARALLEL

HOST BUS OR

SERIAL DTE

INTERFACE

Figure 1-2. SmartV.XX Modem Major Interfaces

CX81801 Modem

128-Pin LQFP

CX20442

Voice Codec (VC)

32-Pin LQFP

(Optional)

SmartDAA

Interface

Modem Data

Pump (MDP)

Digital Speaker

Circuit (Optional)

Paralle Host

or Serial DTE

Interface

MIC

SPEAKER

102247_002

SOUNDUCER

HS Hybrid

Components

(Optional)

RAM

(32K x 8)

ROM

(256k x 8)

Optional RAM

Up to 1M (128K x 8)

Optional Flash ROM

Up to 4M (512K x 8)

Microcontroller

Unit (MCU)

Serial EEPROM

2K (256 x 8) to

256K (32K x 8)

(Optional)

TIP

RING

Telephone

Line Interface

Discrete

Components

TIP

RING

Voice Relay,

HS Pickup

Detector

(Optional)

TELEPHONE

LINE

TELEPHONE

HANDSET

Digital

Isolation

Barrier (DIB)

Components

CX20493 SmartDAA

Line Side Device (LSD)

32-Pin LQFP

Line

Side

DIB

Interface

(LSDI)

Codec

Telephone

Line

Interface

DAA Hardware

Rectifier

and Filter

Components

(Mic/Speaker)

Interface

(Optional)

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

1-4 Conexant 102247B

1.3 Features

1.3.1 General Modem Features

• Data modem

− Quick connect, Modem-on-Hold, and PCM upstream functions (V.92 models)

− ITU-T V.92/V.90 (V.92 models), V.34 (V.92 and V.34 models), V.32bis, V.32,

V.29, FastPOS (V.29), V.22 bis, V.22, V.22 Fast Connect, V.23, V.21,

Bell 212A, and Bell 103

− V.250 and V.251 commands

• Data compression and error correction

− V.44 data compression

− V.42 bis and MNP 5 data compression

− V.42 LAPM and MNP 2-4 error correction

• Fax modem send and receive rates up to 14.4 kbps

− V.17, V.29, V.27 ter, and V.21 channel 2

− EIA/TIA 578 Class 1 and T.31 Class 1.0

• V.80 synchronous access mode supports host-controlled communication protocols

with H.324 interface support

• Interfaces to optional external ROM/flash ROM, RAM, and/or optional serial

EEPROM

• Data/Fax/Voice call discrimination

• Hardware-based modem controller

• Hardware-based digital signal processor (DSP)

• Worldwide operation

− Complies to TBR21 and other country requirements

− On-hook and/or off-hook Caller ID detection for selected countries

− Call progress, blacklisting

− Internal ROM includes default values for 29 countries

− Additional and modified country profile can be stored in internal SRAM

• Caller waiting detection

• Caller ID detect

− On-hook Caller ID detection

− Off-hook Call Waiting Caller ID detection during data mode in V.92, V.90,

V.34, V.32bis, and V.32

• Distinctive ring detect

• Modem customization available through patch code that can be stored in optional

serial EEPROM or internal SRAM

• Telephony/TAM

− V.253 commands

− 2-bit and 4-bit Conexant ADPCM, 8-bit linear PCM, and 4-bit IMA coding

− 8 kHz sample rate

− Concurrent DTMF, ring, and Caller ID detection

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 1-5

• Full-duplex speakerphone (FDSP) mode using optional CX20442 Voice Codec

(S models)

− Microphone and speaker interface

− Telephone handset or headset interface

− Acoustic and line echo cancellation

− Microphone gain and muting

− Speaker volume control and muting

• Built-in host/DTE interface

− Parallel 16550A UART-compatible interface up to 230.4 kbps

− Serial ITU-T V.24 (EIA/TIA-232-E) logical interface up to 115.2 kbps

• Downloadable architecture

• Direct mode (serial DTE interface)

• Flow control and speed buffering

• Automatic format/speed sensing

• Serial async/sync data; parallel async data

• Low profile packages (1.6 mm max. height)

− CX81801 Modem device in 128-pin LQFP

− CX20493 LSD in 32-pin LQFP

− CX20442 VC in 32-pin LQFP

• +3.3V operation with +5V tolerant digital inputs

• Typical power use

− CX81801 and CX20493: 215 mW (Normal Mode); 59 mW (Sleep Mode)

− CX20442: 5 mW (Normal Mode)

1.3.2 SmartDAA Features

• System side powered DAA operates under poor line current supply conditions

• Modem Wake-on-Ring

• Ring detection

• Line current loss detection

• Pulse dialing

• Line-in-use detection during on-hook operation

• Remote hang-up detection for efficient call termination

• Extension pickup detection

• Digital PBX line protection

• Meets worldwide DC Voltage/Current (VI) masks requirements

1.3.3 Applications

• Set top boxes

• Gaming devices

• Point of sale terminals

• Remote monitoring and data collections systems

• Handheld computers

• Other embedded systems

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1.4 Technical Overview

1.4.1 General Description

Modem operation, including dialing, call progress, telephone line interface, telephone

handset interface, optional voice/speakerphone interface, and host interface functions are

supported and controlled through the V.250, V.251, and V.253-compatible command set.

The modem hardware connects to the host via a parallel or serial interface as selected by

the PARIF input. The OEM adds a crystal circuit, DIB components, telephone line

interface, telephone handset/telephony extension interface, voice/speakerphone interface,

optional external serial EEPROM, optional external ROM/flash ROM, optional external

RAM, and other supporting discrete components as supported by the modem model

(Table 1-1) and required by the application to complete the system.

Customized modem firmware can be supported by the use of external memory in various

combinations, e.g., either external ROM/flash ROM (up to 256 KB), or external serial

EEPROM (256 to 32 KB) and external RAM (up to 128 KB). To support country profile

addition or modification, external serial EEPROM (256 to 32 KB) can be installed.

Customized code can include OEM-defined commands, i.e., identification codes (I3),

identifier string (I4), manufacturer identification (+GMI), model identification (+GMM),

and revision identification (+GMR), as well as code modification.

Parallel interface operation is selected by PARIF input high.

Serial interface operation is selected by PARIF input low.

1.4.2 MCU Firmware

MCU firmware performs processing of general modem control, command sets, data

modem, error correction and data compression (ECC), fax class 1, fax class 1.0,

voice/audio/TAM/speakerphone, worldwide, V.80, and serial DTE/parallel host interface

functions according to modem models (Table 1-1).

MCU firmware can be customized to include OEM-defined commands, i.e., identification

codes (I3), identifier string (I4), manufacturer identification (+GMI), model identification

(+GMM), and revision identification (+GMR), as well as code modification.

The modem firmware is provided in object code form for the OEM to program into

external ROM/flash ROM. The modem firmware may also be provided in source code

form under a source code addendum license agreement. External ROM/Flash ROM and

RAM must be installed in order to operate the modem with customized firmware.

1.4.3 Operating Modes

1.4.3.1 Data/Fax Modes

Data modem modes perform complete handshake and data rate negotiations. Using

modem modulations to optimize modem configuration for line conditions, the modem

can connect at the highest data rate that the channel can support from 56 kbps down to

2400 bps with automatic fallback.

In V.92/V.90 data modem modes (V.92 models), the modem can receive data from a

digital source using a V.92-compatible central site modem at line speeds up to 56 kbps.

With PCM upstream enabled (V.92 only), data transmission supports sending data at line

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speeds up to 48 kbps. When PCM upstream is disabled, data transmission supports

sending data at line speeds up to V.34 rates. This mode can fallback to V.34 mode and to

lower rates as dictated by line conditions.

The following modes are supported in V.92 models when connected to a V.92-

compatible server supporting the feature listed.

• Quick connect: Allows quicker subsequent connections to a server by using stored

line parameters obtained during the initial connection.

• Modem-on-Hold: Allows detection and reporting of incoming phone calls on the

PSTN with enabled Call Waiting. If the incoming call is accepted by the user, the

user has a pre-defined amount of time of holding the data connection for a brief

conversation. The data connection resumes upon incoming call termination.

• PCM upstream: Boosts the upstream data rates. A maximum of 48 kbps is supported

when connected to a V.92 server that supports PCM upstream.

In V.34 data modem mode (V.92 and V.34 models), the modem can operate in full-

duplex, asynchronous modes at line rates up to 33.6 kbps. Automode operation in V.34 is

provided in accordance with PN3320 and in V.32 bis in accordance with PN2330. All

tone and pattern detection functions required by the applicable ITU or Bell standards are

supported.

In V.32 bis data modem mode, the modem can operate at line speeds up to 14.4 kbps.

In fax modem mode, the modem can operate in half-duplex, synchronous modes and can

support Group 3 facsimile send and receive speeds of 14400, 12000, 9600, 7200, 4800,

and 2400 bps. Fax data transmission and reception performed by the modem are

controlled and monitored through the EIA/TIA-578 Fax Class 1, or T.31 Fax Class 1.0

command interface. Full HDLC formatting, zero insertion/deletion, and CRC

generation/checking are provided.

1.4.3.2 V.44 Data Compression

V.44 provides efficient data compression that minimizes the download time for the types

of files associated with Internet use. This improvement is most noticeable when browsing

and searching the web since HTML text files are highly compressible. (The improved

performance amount varies both with the actual format and with the content of individual

pages and files.)

1.4.3.3 Worldwide Operation

SmartDAA technology allows a single PCB design and single BOM to be homologated

worldwide. Advanced features such as extension pickup detection, remote hang-up

detection, line-in-use detection, and digital PBX detection are supported.

Country-dependent modem parameters for functions such as dialing, carrier transmit

level, calling tone, call progress tone detection, answer tone detection, blacklisting, caller

ID, and relay control are programmable.

Country code IDs are defined by ITU-T T.35.

Embedded ROM code includes default profiles for 29 countries. Additional country

profiles can be stored in internal SRAM or external serial EEPROM (request additional

country profiles from a Conexant Sales Office). Duplicate country profiles stored in

internal SRAM or external serial EEPROM will override the profiles in embedded ROM

code. The default countries supported are listed in Table 1-2. Country profiles for

CTR-21 countries are TBR-21 compliant.

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Table 1-2. Default Countries Supported

Country Country

Code

Call Waiting Tone

Detection (CW)

Supported

On-Hook Type 1

Caller ID (CID)

Supported

Off-Hook Type 2

Called ID (CID2)

Supported

Australia 09 X X

Austria 0A X X

Belgium 0F X

Brazil 16 X

China 26 X X

Denmark 31 X X

Finland 3C X X

France 3D X X X

Germany 42 X X

Hong Kong 50 X X X

India 53 X

Ireland 57 X

Italy 59 X X

Japan 00 X X X

Korea 61 X

Malaysia 6C X

Mexico 73

Netherlands 7B X

Norway 82 X X

Poland 8A X

Portugal 8B X

Singapore 9C X X X

South Africa 9F X

Spain A0 X X

Sweden A5 X X

Switzerland A6 X

Taiwan FE X X

United Kingdom B4 X X X

United States B5 X X X

Reserved FD X X X

1.4.3.4 TAM Mode

TAM Mode features include 8-bit linear coding at 8 kHz sample rate. Tone detection/

generation, call discrimination, and concurrent DTMF detection are also supported.

TAM Mode is supported by four submodes:

• Online Voice Command Mode supports connection to the telephone line or, for S

models, a microphone/speaker/handset/headset.

• Voice Receive Mode supports recording voice or audio data input from the telephone

line or, for S models, a microphone/handset/headset.

• Voice Transmit Mode supports playback of voice or audio data to the telephone line

or, for S models, a speaker/handset/headset.

• Full-duplex Receive and Transmit Mode.

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1.4.3.5 Speakerphone Mode (S Models)

S models include additional telephone handset, external microphone, and external

speaker interfaces which support voice and full-duplex speakerphone (FDSP) operation.

Hands-free full-duplex telephone operation is supported in Speakerphone Mode under

host control. Speakerphone Mode features an advanced proprietary speakerphone

algorithm which supports full-duplex voice conversation with acoustic, line, and handset

echo cancellation. Parameters are constantly adjusted to maintain stability with automatic

fallback from full-duplex to pseudo-duplex operation. The speakerphone algorithm

allows position independent placement of microphone and speaker. The host can

separately control volume, muting, and AGC in microphone and speaker channels.

1.4.4 Reference Designs

A data/fax/TAM/speakerphone reference design for an external modem is available to

minimize application design time, reduce development cost, and accelerate market entry.

A design package is available in electronic form. This package includes schematics, bill

of materials (BOM), vendor part list (VPL), and complete documentation.

1.5 Hardware Description

SmartDAA technology eliminates the need for a costly analog transformer, relays, and

opto-isolators that are typically used in discrete DAA implementations. The

programmable SmartDAA architecture simplifies product implementation in worldwide

markets by eliminating the need for country-specific components.

1.5.1 CX81801 Modem Device

The CX81801 Modem, packaged in a 128-pin LQFP, includes a Microcontroller (MCU),

a Modem Data Pump (MDP), 256 KB internal ROM, 32 KB internal RAM, and

SmartDAA interface functions.

The CX81801 Modem connects to host via a parallel host (PARIF = high) or a logical

V.24 (EIA/TIA-232-E) serial DTE interface (PARIF = low).

The CX81801 Modem performs the command processing and host interface functions.

The crystal frequency is 28.224 MHz ± 50 ppm.

The CX81801 Modem optionally connects to an external OEM-supplied serial EEPROM

over a dedicated 2-line serial interface. The capacity of the EEPROM can be 256 bytes up

to 32 KB. The EEPROM can hold information such as firmware configuration

customization, and country code parameters.

The CX81801 Modem performs telephone line signal modulation/demodulation in a

hardware digital signal processor (DSP) which reduces computational load on the host

processor.

The SmartDAA interface communicates with, and supplies power and clock to, the LSD

through the DIB.

The CX81801 optionally connects to external OEM-supplied ROM/flash ROM and RAM

over a non-multiplexed 19-bit address bus and 8-bit data bus.

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1.5.2 Digital Isolation Barrier

The OEM-supplied Digital Isolation Barrier (DIB) electrically DC isolates the CX81801

from the LSD and telephone line. The modem is connected to a fixed digital ground and

operates with standard CMOS logic levels. The LSD is connected to a floating ground

and can tolerate high voltage input (compatible with telephone line and typical surge

requirements).

The DIB transformer couples power and clock from the CX81801 to the LSD.

The DIB data channel supports bidirectional half-duplex serial transfer of data, control,

and status information between the CX81801 and the LSD over two lines.

1.5.3 CX20493 SmartDAA Line Side Device

The CX20493 SmartDAA Line Side Device (LSD) includes a Line Side DIB Interface

(LSDI), a coder/decoder (codec), and a Telephone Line Interface (TLI).

The LSDI communicates with, and receives power and clock from, the SmartDAA

interface in the CX81801 through the DIB.

LSD power is received from the MDP PWRCLKP and PWRCLKN pins via the DIB

through a full-wave rectified bridge and capacitive power filter circuit connected to the

DIB transformer secondary winding.

The CLK input is also accepted from the DIB transformer secondary winding through a

capacitor and a resistor in series.

Information is transferred between the LSD and the CX81801 through the DIB_P and

DIB_N pins. These pins connect to the CX81801 DIB_DATAP and DIB_DATAN pins,

respectively, through the DIB.

The TLI integrates DAA and direct telephone line interface functions and connects

directly to the line TIP and RING pins, as well as to external line protection components.

Direct LSD connection to TIP and RING allows real-time measurement of telephone line

parameters, such as the telephone central office (CO) battery voltage, individual

telephone line (copper wire) resistance, and allows dynamic regulation of the off-hook

TIP and RING voltage and total current drawn from the central office (CO). This allows

the modem to maintain compliance with U.S. and worldwide regulations and to actively

control the DAA power dissipation.

1.5.4 CX20442 Voice Codec

The optional CX20442 Voice Codec (VC), packaged in a 32-pin LQFP, supports

voice/full-duplex speakerphone (FDSP) operation with interfaces to a microphone and

speaker and to a telephone handset/headset.

1.6 AT Commands

The SmartV.XX Modem supports AT commands for data mode, fax class 1 or 1.0,

voice/audio, full-duplex speakerphone (FDSP), V.80 commands, and S Register. See

Doc. No. 102184 for a description of the commands.

Data Mode Operation. Data functions operate in response to the AT commands when

+FCLASS=0. Default parameters support U.S./Canada operation.

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Fax Mode Operation. Facsimile functions operate in response to fax class 1 commands

when +FCLASS=1 or to fax class 1.0 commands when +FCLASS=1.0.

Voice/Audio Operation. Voice/audio functions operate in response to voice/audio

commands when +FCLASS=8.

Speakerphone Operation. FDSP functions operate in response to speakerphone

commands when +FCLASS=8 and +VSP=1 is selected.

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2. Technical Specifications

2.1 Serial DTE Interface Operation

2.1.1 Automatic Speed/Format Sensing

Command Mode and Data Mode. The modem can automatically determine the speed

and format of the data sent from the DTE. The modem can sense speeds of 300, 600,

1200, 2400, 4800, 7200, 9600, 12000, 14400, 16800, 19200, 21600, 24000, 26400,

28800, 38400, 57600, and 115200 bps and the following data formats:

Parity

Data Length

(No. of Bits)

No. of

Stop Bits

Character Length

(No. of Bits)

None 7 2 10

Odd 7 1 10

Even 7 1 10

None 8 1 10

Odd 8 1 11*

Even 8 1 11*

*11-bit characters are sensed, but the parity bit is stripped off during

data transmission in Normal and Error Correction modes.

The modem can speed sense data with mark or space parity and configures itself as

follows:

DTE Configuration Modem Configuration

7 mark 7 none

7 space 8 none

8 mark 8 none

8 space 8 even

Fax Mode. In V.17 fax mode, the modem can sense speeds up to 115.2 kbps.

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2.2 Parallel Host Bus Interface Operation

Command Mode and Data Mode. The modem can operate at rates up to 230.4 kbps by

programming the Divisor Latch in the parallel interface registers if supported by

communications software and/or driver.

Fax Mode. In V.17 mode, the modem can operate at rates up to 230.4 kbps by

programming the Divisor Latch in the parallel interface registers if supported by

communications software and/or driver.

2.3 Establishing Data Modem Connections

2.3.1 Dialing

DTMF Dialing. DTMF dialing using DTMF tone pairs is supported in accordance with

ITU-T Q.23. The transmit tone level complies with Bell Publication 47001.

Pulse Dialing. Pulse dialing is supported in accordance with EIA/TIA-496-A.

Blind Dialing. The modem can blind dial in the absence of a dial tone if enabled by the

X0, X1, or X3 command.

2.3.2 Telephone Number Directory

The modem supports four telephone number entries in a directory that can be saved in a

serial EEPROM. Each telephone number can be up to 32 characters (including the

command line terminating carriage return) in length. A telephone number can be saved

using the &Zn=x command, and a saved telephone number can be dialed using the DS=n

command.

2.3.3 Modem Handshaking Protocol

If a tone is not detected within the time specified in the S7 register after the last digit is

dialed, the modem aborts the call attempt.

2.3.4 Call Progress Tone Detection

Ringback, equipment busy, congested tone, warble tone, and progress tones can be

detected in accordance with the applicable standard.

2.3.5 Answer Tone Detection

Answer tone can be detected over the frequency range of 2100 ± 40 Hz in ITU-T modes

and 2225 ± 40 Hz in Bell modes.

2.3.6 Ring Detection

A ring signal can be detected from a TTL-compatible 15.3 Hz to 68 Hz square wave

input.

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2.3.7 Billing Protection

When the modem goes off-hook to answer an incoming call, both transmission and

reception of data are prevented for 2 seconds (data modem) or 4 seconds (fax adaptive

answer) to allow transmission of the billing tone signal.

2.3.8 Connection Speeds

The modem functions as a data modem when the +FCLASS=0 command is active.

Line connection can be selected using the +MS command. The +MS command selects

modulation, enables/disables automode, and selects minimum and maximum line speeds

(Table 2-1).

2.3.9 Automode

Automode detection can be enabled by the +MS command to allow the modem to

connect to a remote modem in accordance with draft PN-3320 for V.34 (Table 2-1).

Table 2-1. +MS Command Automode Connectivity

Modulation <carrier> Possible (<min_rx_rate>, <min_rx_rate>, (<min_tx_rate>),

and <max_tx_rate>) Rates (bps)

Bell 103 B103 300

Bell 212 B212 1200 Rx/75 Tx or 75 Rx/1200 Tx

V.21 V21 300

V.22 V22 1200

V.22 bis V22B 2400 or 1200

V.23 V23C 1200

V.32 V32 9600 or 4800

V.32 bis V32B 14400, 12000, 9600, 7200, or 4800

V.34 V34 33600, 31200, 28800, 26400, 24000, 21600, 19200, 16800,

14400, 12000, 9600, 7200, 4800, or 2400

V.90 V90 56000, 54667, 53333, 52000, 50667, 49333, 48000, 46667,

45333, 44000, 42667, 41333, 40000, 38667, 37333, 36000,

34667, 33333, 32000, 30667, 29333, 28000

V.92 downstream V92 56000, 54667, 53333, 52000, 50667, 49333, 48000, 46667,

45333, 44000, 42667, 41333, 40000, 38667, 37333, 36000,

34667, 33333, 32000, 30667, 29333, 28000

V.92 upstream V92 48000, 46667, 45333, 44000, 42667, 41333, 40000, 38667,

37333, 36000, 34667, 33333, 32000, 30667, 29333, 28000,

26667, 25333, 24000

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2.4 Data Mode

The modem enters data mode when a telephone line connection has been established

between modems and all handshaking has been completed.

2.4.1 Speed Buffering (Normal Mode)

Speed buffering allows a DTE to send data to, and receive data from, a modem at a speed

different than the line speed. The modem supports speed buffering at all line speeds.

2.4.2 Flow Control

DTE-to-Modem Flow Control. If the modem-to-line speed is less than the DTE-to-

modem speed, the modem supports XOFF/XON or RTS/CTS flow control with the DTE

to ensure data integrity.

2.4.3 Escape Sequence Detection

The +++ escape sequence can be used to return control to the command mode from the

data mode. Escape sequence detection is disabled by an S2 Register value greater than

127.

2.4.4 BREAK Detection

The modem can detect a BREAK signal from either the DTE or the remote modem. The

\Kn command determines the modem response to a received BREAK signal.

2.4.5 Telephone Line Monitoring

GSTN Cleardown (V.90, V.34, V.32 bis, V.32). Upon receiving GSTN Cleardown from

the remote modem in a non-error correcting mode, the modem cleanly terminates the call.

Loss of Carrier (V.22 bis and Below). If carrier is lost for a time greater than specified

by the S10 register, the modem disconnects.

2.4.6 Fall Forward/Fallback (V.92/V.90/V.34/V.32 bis/V.32)

During initial handshake, the modem will fallback to the optimal line connection within

V.92/V.90/V.34/V.32 bis/V.32 mode depending upon signal quality if automode is

enabled by the +MS or N1 command.

When connected in V.92/V.90/V.34/V.32 bis/V.32 mode, the modem will fall forward or

fallback to the optimal line speed within the current modulation depending upon signal

quality if fall forward/fallback is enabled by the %E2 command.

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2.4.7 Retrain

The modem may lose synchronization with the received line signal under poor or

changing line conditions. If this occurs, retraining may be initiated to attempt recovery

depending on the type of connection.

The modem initiates a retrain if line quality becomes unacceptable if enabled by the %E

command. The modem continues to retrain until an acceptable connection is achieved, or

until 30 seconds elapse resulting in line disconnect.

2.4.8 Programmable Inactivity Timer

The modem disconnects from the line if data is not sent or received for a specified length

of time. In normal or error-correction mode, this inactivity timer is reset when data is

received from either the DTE or from the line. This timer can be set to a value between 0

and 255 seconds by using register S30. A value of 0 disables the inactivity timer.

2.4.9 DTE Signal Monitoring (Serial DTE Interface Only)

DTR#. When DTR# is asserted, the modem responds in accordance with the &Dn and

&Qn commands.

RTS#. RTS# is used for flow control if enabled by the &K command in normal or error-

correction mode.

2.5 V.92 Features

Modem-on-Hold, quick connect, and PCM upstream are only available in V.92 models

when connecting in V.92 data mode. V.92 features are only available when the server

called is a V.92 server that supports that particular feature.

2.5.1 Modem-on-Hold

The Modem-on-Hold (MOH) function enables the modem to place a data call to the

Internet on hold while using the same line to accept an incoming or place an outgoing

voice call. This feature is available only with a connection to a server supporting MOH.

MOH can be executed through either of two methods:

• One method is to enable MOH through the +PMH command. With Call Waiting

Detection (+PCW command) enabled, an incoming call can be detected while on-

line. Using a string of commands, the modem negotiates with the server to place the

data connection on hold while the line is released so that it can be used to conduct a

voice call. Once the voice call is completed, the modem can quickly renegotiate with

the server back to the original data call.

• An alternative method is to use communications software that utilizes the Conexant

Modem-on-Hold drivers under Windows PC operating systems. Using this method,

the software can detect an incoming call, place the data connection on hold, and

switch back to a data connection.

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2.5.2 Quick Connect

The quick connect function enables the modem to shorten the connect time of subsequent

calls to a server supporting quick connect. The quick connect feature is supported by the

+PQC command.

2.5.3 PCM Upstream

PCM upstream boosts the upstream data rates between the user and ISP to reduce upload

times for large files and email attachments. A maximum of 48 kbps upstream rate is

supported with PCM upstream enabled, in contrast to a maximum of 32.2 kbps upstream

rate with PCM upstream not enabled. PCM upstream is supported by the +PCM

command. PCM upstream is disabled by default.

2.6 Error Correction and Data Compression

2.6.1 V.42 Error Correction

V.42 supports two methods of error correction: LAPM and, as a fallback, MNP 4. The

modem provides a detection and negotiation technique for determining and establishing

the best method of error correction between two modems.

2.6.2 MNP 2-4 Error Correction

MNP 2-4 is a data link protocol that uses error correction algorithms to ensure data

integrity. Supporting stream mode, the modem sends data frames in varying lengths

depending on the amount of time between characters coming from the DTE.

2.6.3 V.44 Data Compression

V.44 data compression mode, enabled by the +DS44 command, encodes pages and files

associated with Web pages. These files include WEB pages, graphics and image files,

and document files. V.44 can provide an effective data throughput rate up to DTE rate for

a 56-kbps connection. The improved performance amount varies both with the actual

format and with the content of individual pages and files.

2.6.4 V.42 bis Data Compression

V.42 bis data compression mode, enabled by the %Cn command or S46 register, operates

when a LAPM connection is established.

The V.42 bis data compression employs a “string learning” algorithm in which a string of

characters from the DTE is encoded as a fixed length codeword. Two 2-KB dictionaries

are used to store the strings. These dictionaries are dynamically updated during normal

operation.

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2.6.5 MNP 5 Data Compression

MNP 5 data compression mode, enabled by the %Cn command, operates during an MNP

connection.

In MNP 5, the modem increases its throughput by compressing data into tokens before

transmitting it to the remote modem, and by decompressing encoded received data before

sending it to the DTE.

2.7 Telephony Extensions

The following telephony extension features are supported and are typically implemented

in designs for set-top box applications and TAM software applications to enhance end-

user experience:

• Line In Use detection

• Extension Pickup detection

• Remote Hang-up detection

The telephony extension features are enabled through the -STE command. The -TTE

command can be used to adjust the voltage thresholds for the telephony extension

features.

2.7.1 Line In Use Detection

The Line In Use Detection feature can stop the modem from disturbing the phone line

when the line is already being used. When an automated system tries to dial using ATDT

and the phone line is in use, the modem will not go off hook and will respond with the

message “LINE IN USE”. In the case where no phone line is connected to the modem,

the modem will respond with the message “NO LINE”.

2.7.2 Extension Pickup Detection

The Extension Pickup Detection feature (also commonly referred as PPD or Parallel

phone detection) allows the modem to detect when another telephony device (i.e., fax

machine, phone, satellite/cable box) is attempting to use the phone line. When an

extension pickup has been detected, the modem will go on-hook and respond with the

message “OFF-HOOK INTRUSION”.

The Remote Hangup Detection feature will cause the modem to go back on-hook and

respond with the message “LINE REVERSAL DETECTED” during a data connection

when the remote modem is disconnected for abnormal termination reasons (remote phone

line unplugged, remote server/modem shutdown). For Voice applications, this method

can be used in addition to silence detection to determine when a remote caller has hung

up to terminate a voice recording.

This feature can be used to quickly drop a modem connection in the event when a user

picks up a extension phone line. For example, this feature allows set top boxes with an

integrated SmartV.XX modem to give normal voice users the highest priority over the

telephone line.

This feature can also be used in Telephone Answering Machine applications (TAM). Its

main use would be to stop the TAM operation when a phone is picked up.

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2.7.3 Remote Hangup Detection

The Remote Hangup Detection feature will cause the modem to go back on-hook and

respond with the message “LINE REVERSAL DETECTED” during a data connection

when the remote modem is disconnected for abnormal termination reasons (remote phone

line unplugged, remote server/modem shutdown). For Voice applications, this method

can be used in addition to silence detection to determine when a remote caller has hung

up to terminate a voice recording.

2.8 Fax Class 1 and Fax Class 1.0 Operation

Facsimile functions operate in response to fax class 1 commands when +FCLASS=1 or to

fax class 1.0 commands when +FCLASS=1.0.

In the fax mode, the on-line behavior of the modem is different from the data (non-fax)

mode. After dialing, modem operation is controlled by fax commands. Some AT

commands are still valid but may operate differently than in data modem mode.

Calling tone is generated in accordance with T.30.

2.9 Point-of-Sales Support

Point-of-Sales (POS) terminals usually need to exchange a small amount of data in the

shortest amount of time. Low speed modulations such as Bell212A or V.22 are still

mainly used in POS applications. Additionally, new non-standard sequences have been

developed to better support POS applications.

Industry standard and shortened answer tone B103 and V.21 are supported, as well as

FastPOS (V.29) and V.22 Fast Connect. POS terminal modulations are supported by the

$F command.

2.10 Voice/Audio Mode

Voice and audio functions are supported by the Voice Mode. Voice Mode includes four

submodes: Online Voice Command Mode, Voice Receive Mode, Voice Transmit Mode

and Full-Duplex Receive and Transmit Mode.

2.10.1 Online Voice Command Mode

This mode results from the connection to the telephone line or a voice/audio I/O device

(e.g., microphone, speaker, or handset) through the use of the +FCLASS=8 and +VLS

commands. After mode entry, AT commands can be entered without aborting the

connection.

2.10.2 Voice Receive Mode

This mode is entered when the +VRX command is active in order to record voice or

audio data input at the RIN pin, typically from a microphone/handset or the telephone

line.

Received analog voice samples are converted to digital form and compressed for reading

by the host. AT commands control the codec bits-per-sample rate.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 2-9

Received analog mono audio samples are converted to digital form and formatted into 8-

bit unsigned linear PCM format for reading by the host. AT commands control the bit

length and sampling rate. Concurrent DTMF/tone detection is available at the 8 kHz

sample rate.

2.10.3 Voice Transmit Mode

This mode is entered when the +VTX command is active in order to playback voice or

audio data to the TXA output, typically to a speaker/handset or to the telephone line.

Digitized voice data is decompressed and converted to analog form at the original

compression quantization sample-per-bits rate then output to the TXA output.

Digitized audio data is converted to analog form then output to the TXA output.

2.10.4 Full-Duplex Receive and Transmit Mode

This mode is entered when the +VTR command is active in order to concurrently receive

and transmit voice.

2.10.5 Audio Mode

The audio mode enables the host to transmit and receive 8-bit audio signals. In this mode,

the modem directly accesses the internal analog-to-digital (A/D) converter (ADC) and the

digital-to-analog (D/A) converter (DAC). Incoming analog audio signals can then be

converted to digital format and digital signals can be converted to analog audio output.

2.10.6 Tone Detectors

The tone detector signal path is separate from the main received signal path thus enabling

tone detection to be independent of the configuration status. In Tone Mode, all three tone

detectors are operational.

2.10.7 Speakerphone Mode

Speakerphone mode is controlled in voice mode with the following commands:

Use Speakerphone After Dialing or Answering (+VSP=1). +VSP=1 selects

speakerphone mode while in +FCLASS=8 mode. Speakerphone operation is entered

during Voice Online Command mode after completing dialing or answering.

Speakerphone Settings. The +VGM and +VGS commands can be used to control the

microphone gain and speaker volume, respectively. VGM and +VGS commands are valid

only after the modem has entered the Voice Online mode while in the +VSP=1 setting.

2.11 V.80 Synchronous Access Mode (SAM) - Video Conferencing

V.80 Synchronous Access Mode between the modem and the host/DTE is provided for

host-controlled communication protocols, e.g., H.324 video conferencing applications.

Voice-call-first (VCF) before switching to a videophone call is also supported.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

2-10 Conexant 102247B

2.12 Full-Duplex Speakerphone (FDSP) Mode (S Models)

The modem operates in FDSP mode when +FCLASS=8 and +VSP=1 (Section 2.10.7).

In FDSP Mode, speech from a microphone or handset is converted to digital form,

shaped, and output to the telephone line through the line interface circuit. Speech

received from the telephone line is shaped, converted to analog form, and output to the

speaker or handset. Shaping includes both acoustic and line echo cancellation.

2.13 Caller ID

Both Type I Caller ID (On-Hook Caller ID) and Type II Caller ID (Call Waiting Caller

ID) are supported for U.S. and many other countries (see Section 2.14). Both types of

Caller ID are enabled/disabled using the +VCID command. Call Waiting Tone detection

must be enabled using the +PCW command to detect and decode Call Waiting Caller ID.

When enabled, caller ID information (date, time, caller code, and name) can be passed to

the DTE in formatted or unformatted form. Inquiry support allows the current caller ID

mode and mode capabilities of the modem to be retrieved from the modem.

Type II Caller ID (Call Waiting Caller ID) detection operates only during data mode in

V.92, V.90, V.34, V.32bis, or V.32.

2.14 Worldwide Country Support

Internal modem firmware supports 29 country profiles (see Section 1.3.2). These country

profiles include the following country-dependent parameters:

• Dial tone detection levels and frequency ranges.

• DTMF dialing parameters: Transmit output level, DTMF signal duration, and DTMF

interdigit interval.

• Pulse dialing parameters: Make/break times, set/clear times, and dial codes are

programmable

• Ring detection frequency range.

• Type I and Type II Caller ID detection are supported for many countries. Contact

your local Conexant sales office for additional country support.

• Blind dialing enabled/disable.

• Carrier transmit level (through S91 for data and S92 for fax). The maximum,

minimum, and default values can be defined to match specific country and DAA

requirements.

• Calling tone is generated in accordance with V.25. Calling tone may be toggled

(enabled/disabled) by inclusion of a “^” character in a dial string. It may also be

disabled.

• Frequency and cadence of tones for busy, ringback, congested, warble, dial tone 1,

and dial tone 2.

• Answer tone detection period.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 2-11

• Blacklist parameters. The modem can operate in accordance with requirements of

individual countries to prevent misuse of the network by limiting repeated calls to

the same number when previous call attempts have failed. Call failure can be

detected for reasons such as no dial tone, number busy, no answer, no ringback

detected, voice (rather than modem) detected, and key abort (dial attempt aborted by

user). Actions resulting from such failures can include specification of minimum

inter-call delay, extended delay between calls, and maximum numbers of retries

before the number is permanently forbidden ("blacklisted").

These country profiles may be altered or customized by modifying the country-dependent

parameters. Additional profiles may also be included. There are two ways to add or

modify profiles:

• Incorporating additional or modified profiles into external flash ROM containing the

entire modem firmware code.

• Linking additional or modified profiles from an external serial EEPROM (needed

only if the external flash ROM capacity is exceeded.

Please contact an FAE at the local Conexant sales office if a country code customization

is required.

2.15 Diagnostics

2.15.1 Commanded Tests

Diagnostics are performed in response to test commands.

Analog Loopback (&T1 Command). Data from the local DTE is sent to the modem,

which loops the data back to the local DTE.

DMTF Generation (%TT0 Command). Continuous DTMF tones are generated by the

DSP and output through the DAA.

Tone Generation (%TT3 Command). Continuous tones are generated by the DSP and

output through the DAA.

2.15.2 Power On Reset Tests

Upon power on, the modem performs tests of the modem and internal RAM. If the

modem or internal RAM test fails, the TMIND# output is pulsed as follows (Figure 2-1):

• Internal RAM test fails: One pulse cycle (pulse cycle = 0.5 sec. on, 0.5 sec. off)

every 1.5 seconds.

• Modem device test fails: Three pulse cycles every 1.5 seconds.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

2-12 Conexant 102247B

Figure 2-1. TMIND# Test Results Pulse Cycles

102179_004

0 .5 11.522.533.544.55

Internal RAM Fails

0 .5 11.522.533.544.55

Modem Device Fails

5.5

5.566.57

Pulse Cycle

Pulse Cycle 1.5 Sec

1.5 Sec

2.16 Low Power Sleep Mode

Sleep Mode Entry. The modem enters the low power sleep mode when no line

connection exists and no host activity occurs for the period of time specified in the S24

consume reduced power while being able to immediately wake up and resume normal

operation.

Wake-up. Wake-up occurs when a ring is detected on the telephone line, the host writes

to the modem (parallel interface), or the DTE sends a character to the modem (serial

interface).

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-1

3. Hardware Interface

3.1 CX81801 Modem Hardware Pins and Signals

3.1.1 Common to Parallel and Serial Interface Configurations

3.1.1.1 LSD Interface (Through DIB)

The DIB interface signals are:

• Clock and Power Positive (PWRCLKP); output

• Clock and Power Negative (PWRCLKN); output

• Data Positive (DIB_DATAP); input/output

• Data Negative (DIB_DATAN); input/output

3.1.1.2 Call Progress Speaker Interface

The call progress speaker interface signal is:

• Digital speaker output (DSPKOUT); output

DSPKOUT is a square wave output in Data/Fax mode used for call progress or carrier

monitoring. This output can be optionally connected to a low-cost on-board speaker, e.g.,

a sounducer, or to an analog speaker circuit.

3.1.1.3 Voice Relay Interface (S Models)

The voice relay interface signal is:

• Voice Relay Control (VOICE#); output

3.1.1.4 Serial EEPROM Interface

A 2-line serial interface to an optional serial EEPROM is supported. The interface signals

are:

• Bidirectional Data input/output (NVMDATA)

• Clock output (NVMCLK)

The EEPROM can hold information such as firmware customization, and country code

parameters. Data stored in EEPROM takes precedence over the factory default settings.

Note: This information is usually stored in flash ROM; serial EEPROM is required only

if storage is required for more than 31 country profiles.

The EEPROM size can range from 2 Kb (256 x 8) to 256 Kb (32K x 8). A 2 Kb

EEPROM must be 100 kHz or 400 kHz; higher capacity EEPROMs must be 400 kHz.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-2 Conexant 102247B

3.1.1.5 External Bus Interface

The external bus optionally connects to OEM-supplied external memory:

• Up to 4 Mb (512K x 8) ROM/flash ROM

• Up to 1 Mb (128K x 8) RAM

The non-multiplexed external bus interface signals are:

• Eight bidirectional Data lines (D0-D7)

• 19 Address output lines (A0-A18)

• Read Enable output (READ#)

• Write Enable output (WRITE#)

• ROM Chip Select output (ROMSEL#)

• RAM Chip Select output (RAMSEL#)

3.1.2 Serial Interface Configuration Only

3.1.2.1 Serial DTE Interface and Indicator Outputs (PARIF = Low)

A V.24/EIA/TIA-232-E logic-compatible serial DTE interface is selected when the

PARIF input is low.

The supported DTE interface signals are:

• Serial Transmit Data input (TXD#)

• Serial Receive Data output line (RXD#)

• Clear to Send output (CTS#)

• Data Set Ready output (DSR#)

• Received Line Signal Detector (RLSD#)

• Test Mode output (TM#)

• Ring Indicator (RI#)

• Data Terminal Ready control input (DTR#)

• Request to Send control input (RTS#)

Additional clock signals provided for synchronous mode are:

• Receive Data Clock (RXCLK#)

• Transmit Data Clock (TXCLK#)

• External Clock (XTCLK#)

The following indicator output lines are also supported:

• Auto Answer indicator output (AAIND#)

• Data Terminal Ready indicator output (DTRIND#)

• Test Mode indicator output (TMIND#)

• Off-hook indicator output (OHIND#)

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-3

3.1.3 Parallel Interface Configuration Only (PARIF = High)

A 16550A UART-compatible parallel host bus interface is selected when the PARIF

input is high.

3.1.3.1 Parallel Host Bus Interface

The parallel host interface signals are:

• Host Reset control input line (RESET#)

• Host Chip Select control input (HCS#)

• Host Read control input (HRD#) and Host Write control input (HWT#)

• Host Interrupt output line (HINT)

• Three Host Address input lines (HA0-HA2)

• Eight Host Data lines (HD0-HD7)

3.1.4 CX81801 Modem Interface Signals

CX81801 Modem 128-pin LQFP hardware interface signals for parallel interface are

shown by major interface in Figure 3-1, are shown by pin number in Figure 3-2, and are

listed by pin number in Table 3-1. The Smart Modem hardware interface signals for

parallel interface are defined in Table 3-2.

CX81801 Modem 128-pin LQFP hardware interface signals for serial interface are shown

by major interface in Figure 3-3, are shown by pin number in Figure 3-4, and are listed

by pin number in Table 3-3. CX81801 Modem hardware interface signals for serial

interface are defined in Table 3-4.

I/O types are defined in Table 3-5.

DC electrical characteristics are listed in Table 3-6.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-4 Conexant 102247B

Figure 3-1. CX81801 Modem Hardware Signals for Parallel Interface (PARIF = High)

XTLI

XTLO

CLKIN

CLKOUT

XCLK

DV1TP

LPO

NOXYCK

PARIF

STPMODE# (PD3)

NMI#

RESET#

HCS# (PD4)

HRD# (PD6)

HWT# (PD5)

HINT (PB7)

HA0 (PD0)

HA1 (PD1)

HA2 (PD2)

HD0 (PC0)

HD1 (PC1)

HD2 (PC2)

HD3 (PC3)

HD4 (PC4)

HD5 (PC5)

HD6 (PC6)

HD7 (PC7)

RESERVED (PA0)

RESERVED (PE6)

RESERVED (PA1)

TESTP

PHS2

SR4IN

PD7

RESERVED (PA2)

RESERVED (PA6)

RESERVED (PB1)

RESERVED (P_PA00)

RESERVED (P_PA04)

RESERVED (P_PA05)

RESERVED (P_PB01)

RESERVED (BD2CLK)

RESERVED (P_GP00)

P_PX00

P_PX02

P_PX03

VGG

VDD

VDD_CORE

GND

114

115

113

111

117

109

122

123

125

126

127

110

121

101

100

108

116

124

103

112

120

128

HOST

PARALLEL

BUS

LINE_SEL (PE7)

RESERVED (PA5)

RESERVED (PA4)

RESERVED (PE5)

RESERVED (PE2)

RESERVED (PA3)

RESERVED (PE0)

VOICE# (PE1)

HS_LCS (PE4)

DSPKOUT

PWRCLKP

PWRCLKN

DIB_DATAP

DIB_DATAN

IASLEEP (P_PF05)

M_CLK (P_PB00)

SR2CLK (P_PGP05)

SA2CLK (P_PX05)

SR3OUT

SR3IN (P_PX01)

SR2IO (P_PX06)

NVMCLK (PA7)

NVMDATA (PE3)

A10

A11

A12

A13

A14

A15

A16 (PB0)

A17 (PB4)

A18 (PB5)

WRITE#

READ#

ROMSEL# (PB2)

RAMSEL# (PB3)

EXT_RES# (PB6)

PLLVDD

PLLGND

105

106

118

119

102

104

107

EEPROM

(OPTIONAL)

1022xx_003

+3.3V

CX81801

Smart Modem

128-Pin LQFP

Parallel Interface

(PARIF = High)

+3.3V

DIGITAL ISOLATION

BARRIER (DIB)

0.1 uF

+3.3V

CRYSTAL

CIRCUIT

EXTERNAL MEMORY

+3.3V

SPEAKER CIRCUIT

+3.3V

CX20442

VOICE CODEC (VC)

(OPTIONAL)

SLEEP

M_CLKIN

M_SCK

M_STROBE

M_TXSIN

M_RXOUT

M_CNTRLSIN

VOICE#

HS_LCS

240K

DAA

47K

+3.3V

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-5

Figure 3-2. CX81801 Modem 128-Pin LQFP Pin Signals for Parallel Interface (PARIF = High)

102199_004

102

101

100

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

GND

HD4 (PC4)

HD3 (PC3)

HD2 (PC2)

VDD

HD1 (PC1)

HD0 (PC0)

PHS2

GND

READ#

WRITE#

NMI#

VDD

XTLO

XTLI

CLKIN

GND

DV1TP

TESTP

HINT (PB7)

VDD

EXT_RES# (PB6)

A18 (PB5)

A17 (PB4)

RAMSEL# (PB3)

GND

SR2IO (P_PX06)

VDD

P_PX00

P_PX02

P_PX03

GND

SR4IN

PD7

NOXYCK

GND

XCLK

IASLEEP (P_PF05)

RXCLK (P_PB01)

XTCLK (GP00)

VDD_CORE

TXCLK (P_PA04)

RESERVED (P_PA00)

RESERVED (P_PA05)

LPO

VDD

RESERVED (BD2CLK)

VGG

CLKOUT

ROMSEL# (PB2)

RESERVED (PB1)

VDD

A16 (PB0)

DSPKOUT

PWRCLKN

PWRCLKP

GND

DIB_DATAN

DIB_DATAP

SR2CLK (P_PGP05)

A15

GND

A14

A13

A12

A11

VDD_CORE

A10

PLLGND

PLLVDD

VDD

GND

HD5 (PC5)

VDD

HD6 (PC6)

HD7 (PC7)

PARIF

HA0 (PD0)

HA1 (PD1)

HA2 (PD2)

STPMODE# (PD3)

GND

HCS# (PD4)

HWT# (PD5)

HRD# (PD6)

RESERVED (PE0)

VDD

VOICE# (PE1)

RESERVED (PE2)

NVMDATA (PE3)

HS_LCS (PE4)

VDD_CORE

RESERVED (PE5)

RESERVED (PE6)

LINE_SEL (PE7)

RESERVED (PA0)

GND

RESERVED (PA1)

RESERVED (PA2)

RESERVED (PA3)

RESERVED (PA4)

GND

RESERVED (PA5)

RESERVED (PA6)

NVMCLK (PA7)

RESET#

SR3OUT

SR3IN (P_PX01)

M_CLK (P_PB00)

SA2CLK (P_PX05)

CX81801

Parallel Interface

(PARIF Pin = High)

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-6 Conexant 102247B

Table 3-1. CX81801 Modem 128-Pin LQFP Pin Signals for Parallel Interface (PARIF = High)

Pin Signal Label I/O I/O Type Interface Pin Signal Label I/O I/O Type Interface

1 HD5 (PC5) I/O Ith/Ot8 HB: HD5 65 D3 I/O Ith/Ot2 EB: D3

2 VDD P PWR +3.3V 66 D4 I/O Ith/Ot2 EB: D4

3 HD6 (PC6) I/O Ith/Ot8 HB: HD6 67 D5 I/O Ith/Ot2 EB: D5

4 HD7 (PC7) I/O Ith/Ot8 HB: HD7 68 GND G GND GND

5 PARIF I Itpu NC (parallel interface) 69 D6 I/O Ith/Ot2 EB: D6

6 HA0 (PD0) I Ithpd/Ot2 HB: HA0 70 D7 I/O Ith/Ot2 EB: D7

7 HA1 (PD1) I Ithpd/Ot2 HB: HA1 71 A0 O It/Ot8 EB: A0

8 HA2 (PD2) I Ithpd/Ot2 HB: HA2 72 A1 O It/Ot8 EB: A1

9 STPMODE# (PD3) I Ith/Ot2 NC 73 A2 O It/Ot8 EB: A2

10 GND G GND GND 74 A3 O It/Ot8 EB: A3

11 HCS# (PD4) I It HB: CS# 75 A4 O It/Ot8 EB: A4

12 HWT# (PD5) I Ithpu HB: WT# 76 A5 O It/Ot8 EB: A5

13 HRD# (PD6) I Ithpu HB: RD# 77 A6 O It/Ot8 EB: A6

14 RESERVED (PE0) O It/Ot8 NC 78 VDD P PWR +3.3V

15 VDD P PWR +3.3V 79 A7 O It/Ot8 EB: A7

16 VOICE# (PE1) O It/Ot2 DAA: VOICE# 80 A8 O It/Ot8 EB: A8

17 RESERVED (PE2) O It/Ot2 RESERVED 81 A9 O It/Ot8 EB: A9

18 NVMDATA (PE3) I/O It/Ot2 NVRAM: SDA 82 PLLVDD P PWR +3.3V and to GND

through 0.1 µF

19 HS_LCS (PE4) I It/Ot2 GND through 47 KΩ 83 PLLGND G GND GND

20 VDD_CORE P PWR Internal core voltage 84 A10 O It/Ot8 EB: A10

21 CELDATA (PE5) I/O It/Ot2 +3.3V through 47 KΩ 85 VDD_CORE P PWR Internal core voltage

22 SSD_RING# (PE6) O It/Ot2 NC 86 A11 O It/Ot8 EB: A11

23 LINE_SEL (PE7) I It/Ot8 +3.3V through 47 KΩ 87 A12 O It/Ot8 EB: A12

24 RESERVED (PA0) O It/Ot2 NC 88 A13 O It/Ot8 EB: A13

25 GND G GND GND 89 A14 O It/Ot8 EB: A14

26 SSD_INT (PA1) O It/Ot2 NC 90 GND G GND GND

27 PA2 I/O It/Ot2 NC 91 A15 O It/Ot8 EB: A15

28 RESERVED (PA3) I Itpu/Ot2 RESERVED 92 SR2CLK (P_PGP05) I Itpu/Ot2 VC: M_SCK

29 RESERVED (PA4) I Itpu/Ot2 RESERVED 93 DIB_DATAP I/O Idd/Odd DIB: Data Pos.

Channel

30 GND G GND GND 94 DIB_DATAN I/O Idd/Odd DIB: Data Neg.

Channel

31 RESERVED (PA5) I It/Ot2 +3.3V through 47 KΩ 95 GND G GND GND

32 PA6 I/O It/Ot2 NC 96 PWRCLKP O Odpc DIB: Transformer

primary winding non-

dotted terminal

33 NVMCLK (PA7) O It/Ot2 NVRAM: SCL 97 PWRCLKN O Odpc DIB: Transformer

primary winding dotted

terminal

34 RESET# I It HB: RESET# 98 DSPKOUT O It/Ot2 Speaker Circuit

35 SR3OUT O Ot2 VC: M_TXSIN 99 A16 (PB0) O It/Ot2 EB: A16

36 SR3IN (P_PX01) I Itk/Ot2 VC: M_RXOUT 100 VDD P PWR +3.3V

37 M_CLK (P_PB00) O It/Ot2 VC: M_CLKIN 101 RESERVED (PB1) O It/Ot2 NC

38 SA2CLK (P_PX05) I Itpu/Ot2 VC: M_STROBE 102 ROMSEL# (PB2) O Ot2 EB: ROM CE#

39 SR2IO (P_PX06) O It/Ot2 VC: M_CNTRLSIN 103 GND G GND GND

40 VDD P PWR +3.3V 104 RAMSEL# (PB3) O It/Ot2 EB: RAM CS#

41 P_PX00 I/O It/Ot8 NC 105 A17 (PB4) O It/Ot2 EB: A17

42 P_PX02 I/O Itpu/Ot2 NC 106 A18 (PB5) O It/Ot2 EB: A18

43 P_PX03 I/O Itpu/Ot2 NC 107 EXT_RES# (PB6) O It/Ot2 NC

44 GND G GND GND 108 VDD P PWR +3.3V

45 SR4IN I Itk NC 109 HINT (PB7) O It/Ot8 HB: HINT

46 PD7 I/O It/Ot2 NC 110 TESTP I Itpu NC

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-7

Table 3-1. CX81801 Modem 128-Pin LQFP Pin Signals for Parallel Interface (PARIF = High) (Continued)

Pin Signal Label I/O I/O Type Interface Pin Signal Label I/O I/O Type Interface

47 NOXYCK I Itpu GND 111 DV1TP I Itpu Clock Select

48 GND G GND GND 112 GND G GND GND

49 XCLK O It/Ot2 NC 113 CLKIN I It GND

50 IASLEEP (P_PF05) O Ot2 VC: SLEEP 114 XTLI I Ix Crystal Circuit

51 RESERVED

(P_PB01)

I/O Itpu/Ot2 NC 115 XTLO O Ox Crystal Circuit

52 RESERVED (GP00) I/O It/Ot2 NC 116 VDD P PWR +3.3V

53 VDD_CORE P PWR Internal core voltage 117 NMI# I Ithpu +3.3V

54 RESERVED

(P_PA04)

I/O Itpu/Ot2 NC 118 WRITE# O It/Ot2 EB: WRITE#

55 RESERVED

(P_PA00)

I/O Itpu/Ot2 NC 119 READ# O It/Ot2 EB: READ#

56 RESERVED

(P_PA05)

I/O Itk/Ot2 NC 120 GND G GND GND

57 LPO I Itpu/Ot2

+3.3V through 240 KΩ 121 PHS2 O Ot2 NC

58 VDD P PWR +3.3V 122 HD0 (PC0) I/O Ith/Ot8 HB: HD0

59 RESERVED

(BD2CLK)

O Itpu/Ot2 NC 123 HD1 (PC1) I/O Ith/Ot8 HB: HD1

60 VGG P PWRG +3.3V or +5V 124 VDD P PWR +3.3V

61 CLKOUT O It/Ot2 NC 125 HD2 (PC2) I/O Ith/Ot8 HB: HD2

62 D0 I/O Ith/Ot2 EB: D0 126 HD3 (PC3) I/O Ith/Ot8 HB: HD3

63 D1 I/O IthOt2 EB: D1 127 HD4 (PC4) I/O Ith/Ot8 HB: HD4

64 D2 I/O Ith/Ot2 EB: D2 128 GND G GND GND

Notes:

1. I/O Types: See Table 3-5.

2. Interface Legend:

DIB Digital Isolation Barrier

EB Expansion Bus

HB Host Bus

NC No internal pin connection

VC Voice Codec

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-8 Conexant 102247B

Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High)

Label Pin I/O I/O Type Signal Name/Description

System

XTLI,

XTLO

114,

115

Ix,

Crystal In and Crystal Out. If an external 28.224 MHz crystal

circuit is used instead of an external clock circuit, connect XTLI

and XTLO to the external crystal circuit and connect CLKIN to

digital ground (GND).

CLKIN 113 I It Clock In. If an external 28.224 MHz clock circuit is used instead of

an external crystal circuit, connect CLKIN to the clock output and

leave XTLI and XTLO open.

CLKOUT 61 O It/Ot2 Clock Out. 28.224 MHz output clock. Leave open.

DV1TP 111 I Itpu Clock Input Select. This input is used to choose the clock input.

Connect to +3.3V or leave open to select XTLI as the clock input.

Connect to GND to select CLKIN as the clock input.

PARIF 5 I Itpu Parallel/Serial Interface Select. PARIF input high (open) selects

parallel host interface operation (see this table); PARIF low (GND)

selects serial DTE interface operation (see Table 3-4).

LINE_SEL (PE7) 23 I It/Ot8 Line Interface Select. Selects telephone line interface. Connect to

+3.3V though 47 KΩ.

STPMODE# (PD3) 9 I Ith/Ot2 Stop Mode. Not used. Leave open.

NMI# 117 I Ithpu Non-Maskable Interrupt. Not used. Connect to +3.3V.

RESET# 34 I It Reset. The active low RESET# input resets the Smart Modem

logic, and restores the saved configuration from serial EEPROM or

returns the modem to the factory default values if NVRAM is not

present.

RESET# low holds the modem in the reset state; RESET# going

high releases the modem from the reset state. After application of

VDD, RESET# must be held low for at least 15 ms after the VDD

power reaches operating range. The modem device set is ready to

use 25 ms after the low-to-high transition of RESET#.

For parallel Interface, connect RESET# input to the host bus

RESET line through an inverter.

VGG 60 P PWRG I/O Signaling Voltage Source. Connect to +3.3V for +3.3V inputs,

or to +5V for +5V inputs.

VDD 2, 15, 40, 58,

78, 100, 108,

116, 124

P PWR Digital Supply Voltage. Connect to VCC (+3.3V, filtered).

VDD_CORE 20, 53, 85 P PWR Core Voltage. Internal core voltage.

GND 10, 25, 30, 44,

48, 68, 90, 95,

103, 112, 120,

128

G GND Digital Ground. Connect to digital ground (GND).

LPO 57 I I/O

Low Power Oscillator. Connect to +3.3V through 240 KΩ.

NOXYCK 47 I Itpu Disable XCLK Output. When low, disables XCLK output (reduces

internal power consumption). When high, enables XCLK output.

Connect to GND.

PLLVDD 82 P PWR PLL Circuit Digital Supply Voltage. Connect to +3.3V and to

GND through 0.1 µF.

PLLGND 83 G GND PLL Circuit Digital Ground. Connect to GND.

Serial EEPROM (NVRAM) Interface

NVMCLK (PA7) 33 O It/Ot2 NVRAM Clock. NVMCLK output high enables the EEPROM.

Connect to EEPROM SCL pin.

NVMDATA (PE3) 18 I/O It/Ot2 NVRAM Data. The NVMDATA pin supplies a serial data interface

to the EEPROM. Connect to EEPROM SDA pin and to +3.3V

through 10 KΩ.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-9

Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) (Continued)

Label Pin I/O I/O Type Signal Name/Description

Speaker Interface

DSPKOUT 98 O It/Ot2 Modem Speaker Digital Output. The DSPKOUT digital output

reflects the received analog input signal digitized to TTL high or low

level by an internal comparator.

DIB Interface

PWRCLKP 96 O Odpc Clock and Power Positive. Provides clock and power to the LSD.

Connect to DIB transformer primary winding non-dotted terminal.

PWRCLKN 97 O Odpc Clock and Power Negative. Provides clock and power to the LSD.

Connect to DIB transformer primary winding dotted terminal.

DIB_DATAP 93 I/O Idd/Odd Data Positive. Transfers data, control, and status information

between the Smart Modem and the LSD. Connect to LSD through

DIB data positive channel components.

DIB_DATAN 94 I/0 Idd/Odd Data Negative. Transfers data, control, and status information

between the Smart Modem and the LSD. Connect to LSD through

DIB data negative channel components.

External Bus Interface

A0-A9,

A10-A15,

A16 (PB0),

A17 (PB4),

A18 (PB5)

71-77, 79-81,

84, 86-89, 91,

99,

105,

106

It/Ot8,

It/Ot2,

It/Ot2

Address Lines 0-18. A0-A18 are the address output lines used to

access external memory; up to 4 Mb (512 KB) ROM/flash ROM

using A0-A18 and up to 1 Mb (128 KB) RAM using A0-A16.

The 256 KB base modem ROM code is located in the 0-256 KB

address range.

D0-D7 62-67, 69-70 I/O Ith/Ot2 Data Line 0-7. D0-D7 are the bidirectional external memory bus

data lines.

READ# 119 O It/Ot2 Read Enable. READ# output low enables data transfer from the

selected device to the D0-D7 lines.

WRITE# 118 O It/Ot2 Write Enable. WRITE# output low enables data transfer from the

D0-D7 lines to the selected device.

ROMSEL# (PB2) 102 O Ot2 ROM Select. ROMSEL# (PB2, ES3) output low selects the external

ROM/flash ROM.

RAMSEL# (PB3) 104 O It/Ot2 RAM Select. RAMSEL# (PB3, ES2) output low selects the external

RAM.

RESERVED (PB1) 101 O It/Ot2 Reserved. PB1 (ES4) is used internally. Leave open.

EXT_RES# (PB6) 107 O It/Ot2 External Device Reset. Active low reset for external devices.

Leave open if not used.

CX20442 VC Interface

IASLEEP (P_PF05) 50 O Ot2 Modem Sleep. Connect to VC SLEEP pin.

M_CLK (P_PB00) 37 O It/Ot2 Master Clock Output. Connect to VC M_CLKIN pin.

SR2CLK (P_PGP05) 92 I Itpu/Ot2 Voice Serial Clock input. Connect to VC M_SCK pin.

SA2CLK (P_PX05) 38 I Itpu/Ot2 Voice Serial Frame Sync Input. Connect to VC M_STROBE pin.

SR3OUT 35 O Ot2 Voice Serial Transmit Data Output. Connect to VC M_TXSIN pin.

SR3IN (P_PX01) 36 I Itk/Ot2 Voice Serial Receive Data Input. Connect to VC M_RXOUT pin.

SR2IO (P_PX06) 39 O It/Ot2 Voice Control Output. Connect to VC M_CNTRLSIN pin.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-10 Conexant 102247B

Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) (Continued)

Label Pin I/O I/O Type Signal Name/Description

Parallel Host Interface

HCS# (PD4) 11 I It Host Bus Chip Select. HCS# input low enables the MCU host

bus interface.

HWT# (PD5) 12 I Ithpu Host Bus Write. HWT# is an active low, write control input. When

HCS# is low, HWT# low allows the host to write data or control

words into a selected MCU register.

HRD# (PD6) 13 I Ithpu Host Bus Read. HRD# is an active low, read control input. When

HCS# is low, HRD# low allows the host to read status information

or data from a selected MCU register.

HINT (PB7) 109 O It/Ot8 Host Bus Interrupt. HINT output is set high when the receiver

error flag, received data available, transmitter holding register

empty, or modem status interrupt is asserted. HINT is reset low

upon the appropriate interrupt service or master reset operation.

HA0-HA2

(PD0-PD2)

6-8 I Ithpd/Ot2 Host Bus Address Lines 0-2. During a host read or write

operation with HCS# low, HA0-HA2 select an internal MCU

16550A-compatible register.

HD0-HD7

(PC0-PC7)

122-123, 125-

127, 1, 3-4

I/O Ith/Ot8 Host Bus Data Lines 0-7. HD0-HD7 are three-state input/output

lines providing bidirectional communication between the host and

the MCU. Data, control words, and status information are

transferred over HD0-HD7.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-11

Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) (Continued)

Label Pin I/O I/O Type Signal Name/Description

DAA Interface

VOICE# (PE1) 16 O It/Ot2 Voice Relay Control. This output (typically active low) used to

control the normally open voice relay.

HS_LCS (PE4) 19 I It/Ot2 Handset Line Current Sense. LCS is an active high input that

indicates a handset off-hook status. Not required for

data/fax/voice/speakerphone operation. If not used, connect to

GND through 47 KΩ.

Not Used

TESTP 110 I Itpu Test. Used for factory test only. Leave open.

XCLK 49 O It/Ot2 Not Used. Leave open.

PHS2 121 O Ot2 Not Used. Leave open.

SR4RIN 45 I Itk Not Used. Leave open.

PA2 27 I It/Ot2 Not Used. Leave open.

PA6 32 O It/Ot2 Not Used. Leave open.

PD7 46 I/O It/Ot2 Not Used. Leave open.

P_PX00 41 I/O It/Ot8 Not Used. Leave open.

P_PX02 42 I/O Itpu/Ot2 Not Used. Leave open.

P_PX03 43 I/O Itpu/Ot2 Not Used. Leave open.

RESERVED (PA0) 24 O It/Ot2 Not Used. Leave open.

RESERVED (PA1) 26 O It/Ot2 Not Used. Leave open.

RESERVED (PA3) 28 I Itpu/Ot2 Not Used. Leave open.

RESERVED (PA4) 29 I Itpu/Ot2 Not Used. Leave open.

RESERVED (PA5) 31 I It/Ot2 Reserved. Connect to +3.3V though 47 KΩ.

RESERVED (PE0) 14 O It/Ot8 Not Used. Leave open.

RESERVED (PE2) 17 O It/Ot2 Not Used. Leave open.

RESERVED (PE5) 21 I/O It/Ot2 Reserved. Connect to +3.3V though 47 KΩ.

RESERVED (PE6) 22 O It/Ot2 Not Used. Leave open.

RESERVED (GP00) 52 I/O It/Ot2 Not Used. Leave open.

RESERVED (P_PA00) 55 I/O Itpu/Ot2 Not Used. Leave open.

RESERVED (P_PA04) 54 I/O Itpu/Ot2 Not Used. Leave open.

RESERVED (P_PA05) 56 I/O Itk/Ot2 Not Used. Leave open.

RESERVED (P_PB01) 51 I/O Itpu/Ot2 Not Used. Leave open.

RESERVED

(P_BD2CLK)

59 I/O Itpu/Ot2 Not Used. Leave open.

Notes:

1. I/O Types: See Table 3-5.

2. Interface Legend:

DIB Digital Isolation Barrier

EB Expansion Bus

HB Host Bus

NC No internal pin connection

VC Voice Codec

RESERVED = No external connection allowed (may have internal connection).

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-12 Conexant 102247B

Figure 3-3. CX81801 Modem Hardware Signals for Serial Interface (PARIF = Low)

XTLI

XTLO

CLKIN

CLKOUT

XCLK

DV1TP

LPO

NOXYCK

PARIF

STPMODE# (PD3)

NMI#

RESET#

AAIND# (PC4)

TMIND# (PB7)

DTRIND# (PD0)

OHIND# (PE0)

TXD# (PA2)

RXD# (PA6)

CTS# (PC1)

DSR# (PC0)

RLSD# (PC2)

TM# (PC6)

RI# (PC5)

DTR# (PD4)

RTS# (PD6)

RXCLK# (P_PB01)

TXCLK# (P_PA05)

XTCLK # (P_GP00)

RESERVED (PA0)

RESERVED (PE6)

RESERVED (PA1)

TESTP

PHS2

SR4IN

PC3

PD1

PD2

PD7

RESERVED (PB1)

RESERVED (PC7)

RESERVED (PD5)

RESERVED (P_PA00)

RESERVED (P_PA05)

RESERVED (BD2CLK)

P_PX00

P_PX02

P_PX03

VGG

VDD

VDD_CORE

GND

114

115

113

111

117

127

109

123

122

125

110

121

126

101

100

108

116

124

103

112

120

128

SERIAL DTE

INTERFACE

LINE_SEL (PE7)

RESERVED (PA5)

RESERVED (PA4)

RESERVED (PE5)

RESERVED (PE2)

RESERVED (PA3)

VOICE# (PE1)

HS_LCS (PE4)

DSPKOUT

PWRCLKP

PWRCLKN

DIB_DATAP

DIB_DATAN

IASLEEP (P_PF05)

M_CLK (P_PB00)

SR2CLK (P_PGP05)

SA2CLK (P_PX05)

SR3OUT

SR3IN (P_PX01)

SR2IO (P_PX06)

NVMCLK (PA7)

NVMDATA (PE3)

A10

A11

A12

A13

A14

A15

A16 (PB0)

A17 (PB4)

A18 (PB5)

WRITE#

READ#

ROMSEL# (PB2)

RAMSEL# (PB3)

EXT_RES# (PB6)

PLLVDD

PLLGND

105

106

118

119

102

104

107

EEPROM (OPTIONAL)

102199_005

+3.3V

CX81801

Smart Modem

128-Pin LQFP

Serial Interface

(PARIF = Low)

+3.3V

DIGITAL ISOLATION

BARRIER (DIB)

0.1 uF

CRYSTAL

CIRCUIT

EXTERNAL MEMORY

LED

INTERFACE

RESET CIRCUIT

SPEAKER CIRCUIT

SLEEP

M_CLKIN

M_SCK

M_STROBE

M_TXSIN

M_RXOUT

M_CNTRLSIN

+3.3V

VOICE#

HS_LCS

CX20442

VOICE CODEC (VC)

(OPTIONAL)

SERIAL DTE

SYNCHRONOUS

CLOCKS

+3.3V

240K

+3.3V DAA

47K

+3.3V

47K

+3.3V

47K

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-13

Figure 3-4. CX81801 Modem 128-Pin LQFP Pin Signals for Serial Interface (PARIF = Low)

102199_006

102

101

100

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

GND

AAIND# (PC4)

PC3

RLSD# (PC2)

VDD

CTS# (PC1)

DSR# (PC0)

PHS2

GND

READ#

WRITE#

NMI#

VDD

XTLO

XTLI

CLKIN

GND

DV1TP

TESTP

TMIND# (PB7)

VDD

EXT_RES# (PB6)

A18 (PB5)

A17 (PB4)

RAMSEL# (PB3)

GND

SR2IO (P_PX06)

VDD

P_PX00

P_PX02

P_PX03

GND

SR4IN

PD7

NOXYCK

GND

XCLK

IASLEEP (P_PF05)

RXCLK# (P_PB01)

XTCLK# (GP00)

VDD_CORE

TXCLK# (P_PA04)

RESERVED (P_PA00)

RESERVED (P_PA05)

LPO

VDD

RESERVED (BD2CLK)

VGG

CLKOUT

ROMSEL# (PB2)

RESERVED (PB1)

VDD

A16 (PB0)

DSPKOUT

PWRCLKN

PWRCLKP

GND

DIB_DATAN

DIB_DATAP

SR2CLK (P_PGP05)

A15

GND

A14

A13

A12

A11

VDD_CORE

A10

PLLGND

PLLVDD

VDD

GND

RI# (PC5)

VDD

TM# (PC6)

RESERVED (PC7)

PARIF

DTRIND# (PD0)

PD1

PD2

STPMODE# (PD3)

GND

DTR# (PD4)

RESERVED (PD5)

RTS# (PD6)

OHIND# (PE0)

VDD

VOICE# (PE1)

RESERVED (PE2)

NVMDATA (PE3)

HS_LCS (PE4)

VDD_CORE

RESERVED (PE5)

RESERVED (PE6)

LINE_SEL (PE7)

RESERVED (PA0)

GND

RESERVED (PA1)

TXD# (PA2)

RESERVED (PA3)

RESERVED (PA4)

GND

RESERVED (PA5)

RXD# (PA6)

NVMCLK (PA7)

RESET#

SR3OUT

SR3IN (P_PX01)

M_CLK (P_PB00)

SA2CLK (P_PX05)

CX81801

Serial Interface

(PARIF Pin = Low)

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-14 Conexant 102247B

Table 3-3. CX81801 Modem 128-Pin LQFP Pin Signals for Serial Interface (PARIF = Low)

Pin Signal Label I/O I/O Type Interface Pin Signal Label I/O I/O Type Interface

1 RI# (PC5) O Ith/Ot8 DTE IF: RI# 65 D3 I/O Ith/Ot2 EB: D3

2 VDD P PWR +3.3V 66 D4 I/O Ith/Ot2 EB: D4

3 TM# (PC6) O Ith/Ot8 DTE IF: TM# 67 D5 I/O Ith/Ot2 EB: D5

4 RESERVED (PC7) I Ith/Ot8 +3.3V through 47 KΩ 68 GND G GND GND

5 PARIF I Itpu GND (serial interface) 69 D6 I/O Ith/Ot2 EB: D6

6 DTRIND# (PD0) O Ithpd/Ot2 LED: DTRIND# 70 D7 I/O Ith/Ot2 EB: D7

7 PD1 I/O Ithpd/Ot2 NC 71 A0 O It/Ot8 EB: A0

8 PD2 I/O Ithpd/Ot2 NC 72 A1 O It/Ot8 EB: A1

9 STPMODE# (PD3) I Ith/Ot2 NC 73 A2 O It/Ot8 EB: A2

10 GND G GND GND 74 A3 O It/Ot8 EB: A3

11 DTR# (PD4) I It DTE IF: DTR# 75 A4 O It/Ot8 EB: A4

12 RESERVED (PD5) I Ithpu NC 76 A5 O It/Ot8 EB: A5

13 RTS# (PD6) I Ithpu DTE IF: RTS# 77 A6 O It/Ot8 EB: A6

14 OHIND# (PE0) O It/Ot8 LED: OHIND# 78 VDD P PWR +3.3V

15 VDD P PWR +3.3V 79 A7 O It/Ot8 EB: A7

16 VOICE# (PE1) O It/Ot2 DAA: VOICE# 80 A8 O It/Ot8 EB: A8

17 RESERVED (PE2) O It/Ot2 NC 81 A9 O It/Ot8 EB: A9

18 NVMDATA (PE3) I/O It/Ot2 NVRAM: SDA 82 PLLVDD P PWR +3.3V and GND

through 0.1 µF

19 HS_LCS (PE4) I It/Ot2 GND through 47 KΩ 83 PLLGND G GND GND

20 VDD_CORE P PWR Internal core voltage 84 A10 O It/Ot8 EB: A10

21 RESERVED (PE5) I/O It/Ot2 +3.3V through 47 KΩ 85 VDD_CORE P PWR Internal core voltage

22 SSD_RING# (PE6) O It/Ot2 NC 86 A11 O It/Ot8 EB: A11

23 LINE_SEL (PE7) I It/Ot8 +3.3V through 47 KΩ 87 A12 O It/Ot8 EB: A12

24 RESERVED (PA0) O It/Ot2 NC 88 A13 O It/Ot8 EB: A13

25 GND G GND GND 89 A14 O It/Ot8 EB: A14

26 SSD_INT (PA1) O It/Ot2 NC 90 GND G GND GND

27 TXD# (PA2) I It/Ot2 DTE IF: TXD# 91 A15 O It/Ot8 EB: A15

28 RESERVED (PA3) I Itpu/Ot2 NC 92 SR2CLK (P_PGP05) I Itpu/Ot2 VC: M_SCK

29 RESERVED (PA4) I Itpu/Ot2 NC 93 DIB_DATAP I/O Idd/Odd DIB: Data Pos.

Channel

30 GND G GND GND 94 DIB_DATAN I/O Idd/Odd DIB: Data Neg.

Channel

31 RESERVED (PA5) I It/Ot2 +3.3V through 47 KΩ 95 GND G GND GND

32 RXD# (PA6) O It/Ot2 DTE IF: RXD# 96 PWRCLKP O Odpc DIB: Transformer

primary winding non-

dotted terminal

33 NVMCLK (PA7) O It/Ot2 NVRAM: SCL 97 PWRCLKN O Odpc DIB: Transformer

primary winding dotted

terminal

34 RESET# I It Reset Circuit 98 DSPKOUT O It/Ot2 Speaker Circuit

35 SR3OUT O Ot2 VC: M_TXSIN 99 A16 (PB0) O It/Ot2 EB: A16

36 SR3IN (P_PX01) I Itk/Ot2 VC: M_RXOUT 100 VDD P PWR +3.3V

37 M_CLK (P_PB00) O It/Ot2 VC: M_CLKIN 101 RESERVED (PB1) O It/Ot2 NC

38 SA2CLK (P_PX05) I Itpu/Ot2 VC: M_STROBE 102 ROMSEL# (PB2) O Ot2 EB: ROM CE#

39 SR2IO (P_PX06) O It/Ot2 VC: M_CNTRLSIN 103 GND G GND GND

40 VDD P PWR +3.3V 104 RAMSEL# (PB3) O It/Ot2 EB: RAM CS#

41 P_PX00 I/O It/Ot8 NC 105 A17 (PB4) O It/Ot2 EB: A17

42 P_PX02 I/O Itpu/Ot2 NC 106 A18 (PB5) O It/Ot2 EB: A18

43 P_PX03 I/O Itpu/Ot2 NC 107 EXT_RES# (PB6) O It/Ot2 NC

44 GND G GND GND 108 VDD P PWR +3.3V

45 SR4IN I Itk NC 109 TMIND# (PB7) O It/Ot8 LED: TMIND#

46 PD7 I/O It/Ot2 NC 110 TESTP I Itpu NC

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-15

Table 3-3. CX81801 Modem 128-Pin LQFP Pin Signals for Serial Interface (PARIF = Low) (Continued)

Pin Signal Label I/O I/O Type Interface Pin Signal Label I/O I/O Type Interface

47 NOXYCK I Itpu GND 111 DV1TP I Itpu Clock Select

48 GND G GND GND 112 GND G GND GND

49 XCLK O It/Ot2 NC 113 CLKIN I It GND

50 IASLEEP (P_PF05) O Ot2 VC: SLEEP 114 XTLI I Ix Crystal Circuit

51 RXCLK# (P_PB01) O Itpu/Ot2 DTE: RXCLK 115 XTLO O Ox Crystal Circuit

52 XTCLK# (GP00) I It/Ot2 DTE: XTCLK 116 VDD P PWR +3.3V

53 VDD_CORE P PWR Internal core voltage 117 NMI# I Ithpu +3.3V

54 TXCLK# (P_PA04) O Itpu/Ot2 DTE: TXCLK 118 WRITE# O It/Ot2 EB: WRITE#

55 RESERVED

(P_PA00)

I/O Itpu/Ot2 NC 119 READ# O It/Ot2 EB: READ#

56 RESERVED

(P_PA05)

I/O Itk/Ot2 NC 120 GND G GND GND

57 LPO I Itpu/Ot2 +3.3V through 240 KΩ 121 PHS2 O Ot2 NC

58 VDD P PWR +3.3V 122 DSR# (PC0) I/O Ith/Ot8 DTE IF: DSR#

59 RESERVED

(BD2CLK)

O Itpu/Ot2 NC 123 CTS# (PC1) I/O Ith/Ot8 DTE IF: CTS#

60 VGG P PWRG +3.3V or +5V 124 VDD P PWR +3.3V

61 CLKOUT O It/Ot2 NC 125 RLSD# (PC2) I/O Ith/Ot8 DTE IF: RLSD#

62 D0 I/O Ith/Ot2 EB: D0 126 PC3 I/O Ith/Ot8 NC

63 D1 I/O IthOt2 EB: D1 127 AAIND# (PC4) O Ith/Ot8 LED: AAIND#

64 D2 I/O Ith/Ot2 EB: D2 128 GND G GND GND

Notes:

1. I/O Types: See Table 3-5.

2. Interface Legend:

DIB Digital Isolation Barrier

EB Expansion Bus

HB Host Bus

NC No internal pin connection

VC Voice Codec

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-16 Conexant 102247B

Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low)

Label Pin I/O I/O Type Signal Name/Description

System

XTLI,

XTLO

114,

115

Ix,

Crystal In and Crystal Out. If an external 28.224 MHz crystal

circuit is used instead of an external clock circuit, connect XTLI

and XTLO to the external crystal circuit and connect CLKIN to

digital ground (GND).

CLKIN 113 I It Clock In. If an external 28.224 MHz clock circuit is used instead of

an external crystal circuit, connect CLKIN to the clock output and

leave XTLI and XTLO open.

CLKOUT 61 O It/Ot2 Clock Out. 28.224 MHz output clock. Leave open.

DV1TP 111 I Itpu Clock Input Select. This input is used to choose the clock input.

Connect to +3.3V or leave open to select XTLI as the clock input.

Connect to GND to select CLKIN as the clock input.

PARIF 5 I Itpu Parallel/Serial Interface Select. PARIF input high (open) selects

parallel host interface operation (see signal definitions in

Table 3-2); PARIF low (GND) selects serial DTE interface

operation (see signal definitions in this table).

LINE_SEL (PE7) 23 I It/Ot8 Line Interface Select. Selects telephone line interface. Connect to

+3.3V.

STPMODE# (PD3) 9 I Ith/Ot2 Stop Mode. Not used. Leave open.

NMI# 117 I Ithpu Non-Maskable Interrupt. Not used. Connect to +3.3V.

RESET# 34 I It Reset. The active low RESET# input resets the Smart Modem

logic, and restores the saved configuration from serial EEPROM or

returns the modem to the factory default values if NVRAM is not

present.

RESET# low holds the modem in the reset state; RESET# going

high releases the modem from the reset state. After application of

VDD, RESET# must be held low for at least 15 ms after the VDD

power reaches operating range. The modem device set is ready to

use 25 ms after the low-to-high transition of RESET#.

For serial Interface, the RESET# input is typically connected to a

reset switch circuit.

VGG 60 P PWRG I/O Signaling Voltage Source. Connect to +3.3V for +3.3V inputs,

or to +5V for +5V inputs.

VDD 2, 15, 40, 58,

78, 100, 108,

116, 124

P PWR Digital Supply Voltage. Connect to VCC (+3.3V, filtered).

VDD_CORE 20, 53, 85 P PWR Core Voltage. Internal core voltage.

GND 10, 25, 30, 44,

48, 68, 90, 95,

103, 112, 120,

128

G GND Digital Ground. Connect to digital ground (GND).

LPO 57 I I/O

Low Power Oscillator. Connect to +3.3V through 240 KΩ.

NOXYCK 47 I Itpu Disable XCLK Output. When low, disables XCLK output (reduces

internal power consumption). When high, enables XCLK output.

Connect to GND.

PLLVDD 82 P PWR PLL Circuit Digital Supply Voltage. Connect to +3.3V and to

GND through 0.1 µF.

PLLGND 83 G GND PLL Circuit Digital Ground. Connect to GND.

Serial EEPROM (NVRAM) Interface

NVMCLK (PA7) 33 O It/Ot2 NVRAM Clock. NVMCLK output high enables the EEPROM.

Connect to EEPROM SCL pin.

NVMDATA (PE3) 18 I/O It/Ot2 NVRAM Data. The NVMDATA pin supplies a serial data interface

to the EEPROM. Connect to EEPROM SDA pin and to +3.3V

through 10 KΩ.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-17

Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low) (Continued)

Label Pin I/O I/O Type Signal Name/Description

Speaker Interface

DSPKOUT 98 O It/Ot2 Modem Speaker Digital Output. The DSPKOUT digital output

reflects the received analog input signal digitized to TTL high or

low level by an internal comparator.

DIB Interface

PWRCLKP 96 O Odpc Clock and Power Positive. Provides clock and power to the LSD.

Connect to DIB transformer primary winding non-dotted terminal.

PWRCLKN 97 O Odpc Clock and Power Negative. Provides clock and power to the

LSD. Connect to DIB transformer primary winding dotted terminal.

DIB_DATAP 93 I/O Idd/Odd Data Positive. Transfers data, control, and status information

between the Smart Modem and the LSD. Connect to LSD through

DIB data positive channel components.

DIB_DATAN 94 I/0 Idd/Odd Data Negative. Transfers data, control, and status information

between the Smart Modem and the LSD. Connect to LSD through

DIB data negative channel components.

External Bus Interface

A0-A9,

A10-A15,

A16 (PB0),

A17 (PB4),

A18 (PB5)

71-77, 79-81,

84, 86-89, 91,

99,

105,

106

It/Ot8,

It/Ot2,

It/Ot2

Address Lines 0-18. A0-A18 are the address output lines used to

access external memory; up to 4 Mb (512 KB) ROM/flash ROM

using A0-A18 and up to 1 Mb (128 KB) RAM using A0-A16.

The 256 KB base modem ROM code is located in the 0-256 KB

address range.

D0-D7 62-67, 69-70 I/O Ith/Ot2 Data Line 0-7. D0-D7 are bidirectional external memory bus data

lines.

READ# 119 O It/Ot2 Read Enable. READ# output low enables data transfer from the

selected device to the D0-D7 lines.

WRITE# 118 O It/Ot2 Write Enable. WRITE# output low enables data transfer from the

D0-D7 lines to the selected device.

ROMSEL# (PB2) 102 O Ot2 ROM Select. ROMSEL# (PB2, ES3) output low selects the

external ROM.

RAMSEL# (PB3) 104 O It/Ot2 RAM Select. RAMSEL# (PB3, ES2) output low selects the

external RAM.

RESERVED (PB1) 101 O It/Ot2 Reserved. PB1 (ES4) is used internally. Leave open.

EXT_RES# (PB6) 107 O It/Ot2 External Device Reset. Active low reset for external devices.

Leave open if not used.

CX20442 VC Interface

IASLEEP (P_PF05) 50 O Ot2 Modem Sleep. Connect to VC SLEEP pin.

M_CLK (P_PB00) 37 O It/Ot2 Master Clock Output. Connect to VC M_CLKIN pin.

SR2CLK (P_PGP05) 92 I Itpu/Ot2 Voice Serial Clock input. Connect to VC M_SCK pin.

SA2CLK (P_PX05) 38 I Itpu/Ot2 Voice Serial Frame Sync Input. Connect to VC M_STROBE pin.

SR3OUT 35 O Ot2 Voice Serial Transmit Data Output. Connect to VC M_TXSIN

pin.

SR3IN (P_PX01) 36 I Itk/Ot2 Voice Serial Receive Data Input. Connect to VC M_RXOUT pin.

SR2IO (P_PX06) 39 O It/Ot2 Voice Control Output. Connect to VC M_CNTRLSIN pin.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-18 Conexant 102247B

Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low) (Continued)

Label Pin I/O I/O Type Signal Name/Description

V.24 (EIA/TIA-232-E) DTE Serial Interface

TXD# (PA2) 27 I It/Ot2 Transmitted Data (EIA BA/ITU-T CT103). The DTE uses the

TXD# line to send data to the modem for transmission over the

telephone line or to transmit commands to the modem.

RXD# (PA6) 32 O It/Ot2 Received Data (EIA BB/ITU-T CT104). The modem uses the

RXD# line to send data received from the telephone line to the

DTE and to send modem responses to the DTE. During command

mode, RXD# data represents the modem responses to the DTE.

CTS# (PC1) 123 O Ith/Ot8 Clear To Send (EIA CB/ITU-T CT106). CTS# output ON (low)

indicates that the modem is ready to accept data from the DTE. In

asynchronous operation, in error correction or normal mode, CTS#

is always ON (low) unless RTS/CTS flow control is selected by the

&Kn command.

In synchronous operation, the modem also holds CTS# ON during

asynchronous command state. The modem turns CTS# OFF

immediately upon going off-hook and holds CTS# OFF until both

DSR# and RLSD# are ON and the modem is ready to transmit and

receive synchronous data. The modem can also be commanded

by the &Rn command to turn CTS# ON in response to an RTS#

OFF-to-ON transition.

DSR# (PC0) 122 O Ith/Ot8 Data Set Ready (EIA CC/ITU-T CT107). DSR# indicates modem

status to the DTE. DSR# OFF (high) indicates that the DTE is to

disregard all signals appearing on the interchange circuits except

Ring Indicator (RI#). DSR# output is controlled by the AT&Sn

command.

RLSD# (PC2) 125 O Ith/Ot8 Received Line Signal Detector (EIA CF/ITU-T CT109). When

AT&C0 command is not in effect, RLSD# output is ON when a

carrier is detected on the telephone line or OFF when carrier is not

detected.

TM# (PC6) 3 O Ith/Ot8 Test Mode (EIA TM/ITU-T CT142). The TM# output indicates the

modem is in test mode (low) or in any other mode (high).

RI# (PC5) 1 O Ith/Ot8 Ring Indicator (EIA CE/ITU-T CT125). RI# output ON (low)

indicates the presence of an ON segment of a ring signal on the

telephone line.

DTR# (PD4) 11 I It Data Terminal Ready (EIA CD/ITU-T CT108). The DTR# input is

turned ON (low) by the DTE when the DTE is ready to transmit or

receive data. DTR# ON prepares the modem to be connected to

the telephone line, and maintains the connection established by

the DTE (manual answering) or internally (automatic answering).

DTR# OFF places the modem in the disconnect state under

control of the &Dn and &Qn commands.

RTS# (PD6) 13 I Ithpu Request To Send (EIA CA/ITU-T CT105). RTS# input ON (low)

indicates that the DTE is ready to send data to the modem. In the

command state, the modem ignores RTS#.

In asynchronous operation, the modem ignores RTS# unless

RTS/CTS flow control is selected by the &Kn command. In

synchronous on-line operation, the modem can be commanded by

the &Rn command to ignore RTS# or to respond to RTS# by

turning on CTS# after the delay specified by Register S26.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-19

Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low) (Continued)

Label Pin I/O I/O Type Signal Name/Description

V.24 (EIA/TIA-232-E) DTE Serial Interface (Continued)

RXCLK# (P_PB01) 51 O Itpu/Ot2 Receive Data Clock. A synchronous Receive Data Clock

(RXCLK) is output in synchronous modes. The RXCLK frequency

is the data rate (±0.01%) with a duty cycle of 50±1%. Leave open

if not used.

TXCLK# (P_PA04) 54 O Itpu/Ot2 Transmit Data Clock. A synchronous Transmit Data Clock

(TXCLK) is output in synchronous modes. The TXCLK frequency

is the data rate (±0.01%) with a duty cycle of 50±1%. Leave open

if not used.

XTCLK# (GP00) 52 I It/Ot2 External Data Clock. A synchronous External Transmit Data

Clock (XTCLK) is input in synchronous modes.

LED Indicator Interface

AAIND# (PC4) 127 O Ith/Ot8 Auto Answer Indicator. AAIND# output ON (low) corresponds to

the indicator on. AAIND# output is active when the modem is

configured to answer the ring automatically (ATS0 command ≠ 0).

TMIND# (PB7) 109 O It/Ot8 Test Mode Indicator. TMIND# output ON (low) corresponds to the

indicator on. TMIND# output pulses (indicator flashes) when the

modem is in test mode and if an error is detected.

DTRIND# (PD0) 6 O Ithpd/Ot2 DTR Indicator. DTRIND# output ON (low) corresponds to the

indicator on. The DTRIND# state reflects the DTR# output state

except when the &D0 command is active, in which case DTRIND#

is low.

OHIND# (PE0) 14 O It/Ot8 Off-Hook Indicator. OHIND# (PE0) indicates the status of the off-

hook relay.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-20 Conexant 102247B

Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low) (Continued)

Label Pin I/O I/O Type Signal Name/Description

DAA Interface

VOICE# (PE1) 16 O It/Ot2 Voice Relay Control. This output (typically active low) used to

control the normally open voice relay.

HS_LCS (PE4) 19 I It/Ot2 Handset Line Current Sense. LCS is an active high input that

indicates a handset off-hook status. Not required for

data/fax/voice/speakerphone operation. If not used, connect to

GND through 47 KΩ.

Not Used

TESTP 110 I Itpu Test. Used for factory test only. Leave open.

XCLK 49 O It/Ot2 Not Used. Leave open.

S4RIN 45 I Itk Not Used. Leave open.

PHS2 121 O Ot2 Not Used. Leave open.

PC3 126 I/O Ith/Ot8 Not Used. Leave open.

PD1 7 I/O Ithpd/Ot2 Not Used. Leave open.

PD2 8 I/O Ithpd/Ot2 Not Used. Leave open.

PD7 46 I/O It/Ot2 Not Used. Leave open.

P_PX00 41 I/O It/Ot8 Not Used. Leave open.

P_PX02 42 I/O Itpu/Ot2 Not Used. Leave open.

P_PX03 43 I/O Itpu/Ot2 Not Used. Leave open.

RESERVED (PA0) 24 O It/Ot2 Not Used. Leave open.

RESERVED (PA1) 26 O It/Ot2 Not Used. Leave open.

RESERVED (PA3) 28 I Itpu/Ot2 Not Used. Leave open.

RESERVED (PA4) 29 I Itpu/Ot2 Not Used. Leave open.

RESERVED (PA5) 31 I It/Ot2 Reserved. Connect to +3.3V though 47 KΩ.

RESERVED (PC7) 4 I Ith/Ot8 Reserved. Connect to +3.3V through 47 KΩ.

RESERVED (PD5) 12 I Ithpu Reserved. Leave open.

RESERVED (PE2) 17 O It/Ot2 Not Used. Leave open.

RESERVED (PE5) 21 I/O It/Ot2 Reserved. Connect to +3.3V though 47 KΩ.

RESERVED (PE6) 22 O It/Ot2 Not Used. Leave open.

RESERVED (P_PA00) 55 I/O Itpu/Ot2 Not Used. Leave open.

RESERVED (P_PA05) 56 I/O Itk/Ot2 Not Used. Leave open.

RESERVED

(P_BD2CLK)

59 I/O Itpu/Ot2 Not Used. Leave open.

Notes:

1. I/O Types: See Table 3-5.

2. Interface Legend:

DIB Digital Isolation Barrier

EB Expansion Bus

HB Host Bus

NC No internal pin connection

VC Voice Codec

RESERVED = No external connection allowed (may have internal connection).

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-21

Table 3-5. CX81801 Modem I/O Type Definitions

I/O Type Description

Idd/Odd Digital input/output, DIB data transceiver

Ix/Ox I/O, wire

It/Ot2 Digital input, +5V tolerant/ Digital output, 2 mA, ZINT = 120 Ω

Itk/Ot2 Digital input, +5V tolerant, keeper/ Digital output, 2 mA, ZINT = 120 Ω

Itpu/Ot2 Digital input, +5V tolerant, 75k Ω pull up/ Digital output, 2 mA, ZINT = 120 Ω

It/Ot8 Digital input, +5V tolerant,/ Digital output, 8 mA, ZINT = 50 Ω

Ithpd/Ot2 Digital input, +5V tolerant, hysteresis, 75k Ω pull down/ Digital output, 2 mA, ZINT = 120 Ω

Ith/Ot2 Digital input, +5V tolerant, hysteresis/Digital output, 2 mA, ZINT = 120 Ω

Ith/Ot8 Digital input, +5V tolerant, hysteresis/Digital output, 8 mA, ZINT = 50 Ω

It Digital input, +5V tolerant

Itk Digital input, +5V tolerant, keeper

Itkpu Digital input, +5V tolerant, keeper, 75k Ω pull up

Itpu Digital input, +5V tolerant, 75k Ω pull up

Ithpu Digital input, +5V tolerant, hysteresis, 75k Ω pull up

Odpc Digital output with adjustable drive, DIB clock and power

Ot2 Digital output, three-state, 2 mA, ZINT = 120 Ω

PWR VCC Power

PWRG VGG Power

GND Ground

NOTES:

1. See DC characteristics in Table 3-6.

2. I/O Type corresponds to the device Pad Type. The I/O column in signal interface tables refers to signal I/O direction used in

the application.

Table 3-6. CX81801 Modem DC Electrical Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions

Input Voltage Low VIL

+5V tolerant 0 – 0.8 V

+5V tolerant hysteresis 0 – 0.3 * VGG V

Input Voltage High VIH – V

+5V tolerant 2 – 5.25 V

+5V tolerant hysteresis 0.7 * VDD – 5.25 V

Input Hysteresis VH – V

+3V hysteresis 0.5 – V

+5V tolerant, hysteresis 0.3 – V

Output Voltage Low VOL

INT = 120 Ω 0 – 0.4 V IOL = 2 mA

INT = 50 Ω 0 – 0.4 V IOL = 8 mA

Output Voltage High VOH – V

INT = 120 Ω 2.4 – VDD V IOL = -2 mA

INT = 50 Ω 2.4 – VDD V IOL = -8 mA

Pull-Up Resistance Rpu 50 – 200 kΩ

Pull-Down Resistance Rpd 50 – 200 kΩ

Test Conditions unless otherwise stated: VDD = +3.3 ± 0.3 VDC; TA = 0°C to 70°C; external load = 50 pF.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-22 Conexant 102247B

3.2 CX20493 LSD Hardware Pins and Signals

3.2.1 CX20493 LSD Signal Summary

3.2.1.1 CX81801 Interface (Through DIB)

The DIB interface, power, and ground signals are:

• Clock (CLK, pin 29); input

• Digital Power (PWR+, pin 8); unregulated input power

• Regulated Digital Voltage Supply (DVdd, pin 28)

• Digital Ground (DGnd, pin 26 and pin 27); digital ground

• Regulated Analog Voltage Supply (AVdd, pin 2 and pin 3)

• Analog Ground (AGnd, pin 7); analog ground

• Data Positive (DIB_P, pin 30); input/output

• Data Negative (DIB_N, pin 31); input/output

3.2.1.2 Telephone Line Interface

The telephone line interface signals are:

• RING 1 AC Coupled (RAC1, pin 24); input

• TIP 1 AC Coupled (TAC1, pin 23); input

• RING 2 AC Coupled (RAC2, pin 22); input

• TIP 2 AC Coupled (TAC2, pin 21); input

• TIP and RING DC Measurement (TRDC, pin 13); input

• Electronic Inductor Capacitor (EIC, pin 12)

• Electronic Inductor Output (EIO, pin 20)

• Electronic Inductor Feedback (EIF, pin 19)

• Receive Analog Input (RXI, pin 10); input

• Transmit Output (TXO, pin 15); output

• Transmit Feedback (TXF, pin 14); input

• Virtual Impedance 0 (VZ, pin 11); input

• Electronic Inductor Ground (DC_GND, pins 1, 9, 16, 18, and 25)

3.2.1.3 Voltage References

There are three reference voltage pins:

• Output Middle (Center) Reference Voltage (Vc, pin 4); output for decoupling

• Output Reference Voltage (VRef, pin 5); output for decoupling

• Bias Resistor (RBias, pin 6); input

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-23

3.2.1.4 General Purpose Input/Output

There is one unassigned general purpose input/output pin:

• General Purpose Input/Output 1 (GPIO1, pin 32); input/output

3.2.1.5 No Connects

There is one No Connect pin:

• No Connect (NC, pin 17); no internal connection

3.2.2 CX20493 LSD Pin Assignments and Signal Definitions

CX20493 LSD hardware interface signals are shown by major interface in Figure 3-5, are

shown by pin number in Figure 3-6, and are listed by pin number in Table 3-7.

CX20493 LSD hardware interface signals are defined in Table 3-8.

CX20493 LSD GPIO DC electrical characteristics are specified in Table 3-9.

CX20493 LSD AVdd DC electrical characteristics are listed in Table 3-10.

Figure 3-5. CX20493 LSD Hardware Interface Signals

RAC2

TAC2

RAC1

TAC1

EIC

TRDC

EIO

EIF

RXI

TXO

TXF

RBias

VRef

GPIO1

102247_007

CX20493

SmartDAA 3

Line Side

Device

(LSD)

32-Pin LQFP

Electronic

Inductor,

Off-Hook,

Pulse Dial,

and TIP and

RING VI

Control

AGND_LSD

Safety

and EMI

Protection

Ring

Filter

AGND_LSD

C944

Receive

Coupling

Impedance

Matching

and

Transmitter

R954

AGND_LSD

DVdd

CLK

PWR+

AVdd

AGnd

DIB_P

DIB_N

DC_GND

DGnd

2, 3

1, 9, 16, 18, 25

26, 27

C930 C928

AGND_LSD

DIGITAL

ISOLATION

BARRIER

(DIB)

PWRCLKN

PWRCLKP

DIB_DATAP

DIB_DATAN

DATA

CHANNEL

POWER AND

CLOCK

CHANNEL

R922

C922

C924

Telephone

Line

Connector

TIP

RING

C926

R932

Vdd

C952

C950

NOTE:

Consult applicable reference design for exact component

placement and values, and for layout guidelines.

C962

C974 C976

R990

C970

C978

DGND_LSD

Vdd

AGND_LSD DGND_LSD

GND_TIE

U908

C940

FB906

On-hook

Monitor

(Optional)

R950

R952

BR908

BR908 CC

BR908 AC1

PCLK2 CLK2

R924

R926

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-24 Conexant 102247B

Figure 3-6. CX20493 LSD 32-Pin LQFP Pin Signals

102247_008

DC_GND

AVdd

VRef

RBias

AGnd

PWR+

RAC1

TAC1

RAC2

TAC2

EIO

EIF

DC_GND

RXI

EIC

TRDC

TXF

TXO

DC_GND

GPIO1

DIB_N

DIB_P

CLK

DVdd

DGnd

DC_GND

CX20493

Table 3-7. CX20493 LSD 32-Pin LQFP Pin Signals

Pin Signal Label Pin Signal Label

1 DC_GND 17 NC

2 AVdd 18 DC_GND

3 AVdd 19 EIF

4 Vc 20 EIO

5 VRef 21 TAC2

6 RBias 22 RAC2

7 AGnd 23 TAC1

8 PWR+ 24 RAC1

9 DC_GND 25 DC_GND

10 RXI 26 DGnd

11 VZ 27 DGnd

12 EIC 28 DVdd

13 TRDC 29 CLK

14 TXF 30 DIB_P

15 TXO 31 DIB_N

16 DC_GND 32 GPIO1

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-25

Table 3-8. CX20493 LSD Pin Signal Definitions

Label Pin I/O I/O Type Signal Name/Description

System Signals

AVdd 2, 3 PWR PWR Regulated Power Output. Provides external power for LSD digital

circuits and a connection point for external decoupling. (AVdd is routed

internally to LSD analog circuits.) See PWR+ pin description. Connect to

LSD DVdd pin and connect to AGND_LSD through C928 and C930 in

parallel. C928 and C930 must be placed close to pin 3 (AVdd) and pin 7

(AGnd). C930 must have ESR < 2 Ω.

AGnd 7 AGND_LSD AGND_LSD

Analog Ground. Connect to minus (-) terminal of full wave rectifier

(FWR). Connect FWR BR980 terminal to DIB transformer secondary

winding undotted terminal through R922.

VRef 5 REF REF Output Reference Voltage. Connect to AGND_LSD through C940 and

C976, which must be placed close to pin 5 (VRef). Ensure a very close

proximity between C940 and pin 5. C940 must have a maximum ESR of

2 Ω.

Vc 4 REF REF Output Middle Reference Voltage. Connect to AGND_LSD through

C944 and C974, which must be placed close to pin 4 (Vc). Ensure a very

close proximity between C944 and pin 4. Use a short path and a wide

trace to AGND_LSD pin.

PWR+ 8 PWR PWR Unregulated Power Input. Provides unregulated input power to the

LSD. PWR+ pin is an input which takes unregulated +3.2V to +4.5V from

the DIB power supply made up of the transformer, full-wave rectifier, and

filter capacitors. The PWR+ input is regulated by an internal linear

regulator to +3.3V ± 5% which is routed to the AVdd pin. If PWR+ is less

than +3.4V, then AVdd is equal to the unregulated PWR+ input value

minus 150 mV (Table 3-10).

Connect to plus (+) terminal of FWR. Connect terminal BR908 AC1 to

DIB transformer secondary winding dotted terminal through R990.

Connect transformer side of FB906 to AGND_LSD though C970. Place

FB906 and C970 close to pin 8 (PWR+) and pin 7 (AGnd).

DVdd 28 PWR PWR Digital Power Input. Input power for LSD digital circuits. Connect to LSD

AVdd pin and connect to DGND_LSD through C978. Place C978 near

pin 27 (DVdd).

DGnd 26, 27 DGND_LSD DGND_LSD

LSD Digital Ground. Connect to DGND_LSD, and to AGND_LSD at the

DGND_LSD/AGND_LSD tie point (U908).

DIB Interface Signals

CLK 29 I I Clock. Provides input clock, AC coupled to the LSD. Connect to DIB

transformer secondary winding undotted terminal through C926 (closest

to the CX20493), R932, then R922 in series. Connect the R932 and

R922 node to LSD AGND pin through full-wave rectifier BR908. Place

C926 near pin 29 (CLK) and place R932 near C926.

DIB_P 30 I/O I/O

Data and Control Positive. Connect to DIBDAT_P through R924 in

series with C922. DIB_P and DIB_N signals are differential and half-

duplex bidirectional.

DIB_N 31 I/O I/O

Data and Control Negative. Connect to DIBDAT_N through R926 in

series with C924. DIB_P and DIB_N signals are differential and half-

duplex bidirectional.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-26 Conexant 102247B

Table 3-8. CX20493 LSD Pin Signal Definitions (Continued)

Label Pin I/O I/O Type Signal Name/Description

TIP and RING Interface

RAC1

TAC1

RING1 AC Coupled and TIP1 AC Coupled. AC-coupled voltage from

telephone line used to detect ring.

Connect RAC1 to the diode bridge AC node (RING) through R902

(connects to pin 24) and C902 in series.

Connect TAC1 to the diode bridge AC node (TIP) through R904

(connects to pin 23) and C904 in series.

RAC2

TAC2

RING2 AC Coupled and TIP2 AC Coupled. AC-coupled voltage from

telephone line used to optionally detect signal while on-hook.

Connect RAC2 to the diode bridge AC node (RING) through R948

(connects to pin 22) and C948. Leave open if not used.

Connect TAC2 to the diode bridge AC node (TIP) through R946

(connects to pin 21) and C946. Leave open if not used.

EIC 12 O Oa Electronic Inductor Capacitor Switch. Internally switched to TRDC

when pulse dialing. Connect to AGND_LSD through C958.

TRDC 13 I Ia TIP and RING DC Measurement. Input on-hook voltage (from a resistive

divider). Used internally to extract TIP and RING DC voltage and Line

Polarity Reversal (LPR) information. R906 and C918 must be placed

very close to pin 13 (TRDC).

EIO 20 O Oa Electronic Inductor Output. Calculated voltage is applied to this output

to control off-hook and DC VI mask operation. Connect to base of Q902.

DC_GND 1, 9,

16, 18,

GND AGND_LSD

LSD Electronic Inductor Ground. Connect to AGND_LSD and to the

GND_LSD/AGND_LSD tie point (U908).

EIF 19 I Ia Electronic Inductor Feedback. Connect to emitter of Q904 through

R968.

RXI 10 I Ia Receive Analog Input. Receiver operational amplifier inverting input.

AC coupled to the Bridge CC node through R910 (connects to pin 10)

and C912 in series. R910 and C912 must be placed very close to pin 10.

The length of the PCB trace connecting R910 to the RXI pin must be

kept at an absolute minimum.

RBias 6 I Ia Receiver Bias. Connect to AGND_LSD through R954, which must be

placed close to pin 6.

VZ 11 I Ia Virtual Impedance. Input signal used to provide line complex

impedance matching for worldwide countries. AC coupled to Bridge CC

node through R908 (connects to pin 11) and C910 in series. R908 and

C910 must be placed very close to pin 11. The length of the PCB trace

connecting R908 to the VZ pin must be kept at an absolute minimum.

TXO 15 O Oa Transmit Output. Outputs transmit signal and impedance matching

signal; connect to base of transmitter transistor Q906.

TXF 14 I Ia Transmit Feedback. Connect to emitter of transmitter transistor Q906.

Not Used

GPIO1 32 I/O It/Ot12 General Purpose I/O 1. Leave open if not used.

NC 17 No Connect. No internal connection. Leave open.

Notes:

1. I/O types*:

Ia Analog input

It Digital input, TTL-compatible

Oa Analog output

Ot12 Digital output, TTL-compatible, 12 mA, ZINTERNAL = 32 Ω

AGND_LSD Isolated LSD Analog Ground

GND_LSD Isolated LSD Digital Ground

*See CX20493 LSD GPIO DC Electrical Characteristics (Table 3-9)

2. Refer to applicable reference design for exact component placement and values.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-27

Table 3-9. CX20493 LSD GPIO DC Electrical Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions

Input Voltage VIN -0.30 – 3.465 V DVdd = +3.465V

Input Voltage Low VIL – – 1.0 V

Input Voltage High VIH 1.6 – – V

Output Voltage Low VOL 0 – 0.33 V

Output Voltage High VOH 2.97 – – V

Input Leakage Current – -10 – 10 µA

Output Leakage Current (High Impedance) – -10 – 10 µA

GPIO Output Sink Current at 0.33 V maximum – 2.4 – - mA

GPIO Output Source Current at 2.97 V minimum – 2.4 – - mA

GPIO Rise Time/Fall Time 20 100 ns

Test Conditions unless otherwise stated: DVdd = +3.3V +5%; TA = 0°C to 70°C; external load = 50 pF

Table 3-10. CX20493 AVdd DC Electrical Characteristics

PWR+ Input AVdd Output

+3.4V < PWR+ < +4.5V +3.3V ± 5%

+3.2V < PWR+ < +3.39V 3.05V < AVdd < 3.24V

See PWR+, AVdd, and DVdd descriptions in Table 3-8.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-28 Conexant 102247B

3.3 CX20442 VC Hardware Pins and Signals (S Models)

3.3.1 CX20442 VC Signal Summary

Microphone and analog speaker interface signals, as well as telephone handset/headset

interface signals are provided to support functions such as speakerphone mode, telephone

emulation, microphone voice record, speaker voice playback, and call progress monitor.

3.3.1.1 Speakerphone Interface

The following signals are supported:

• Speaker Out (M_SPKR_OUT); analog output - Should be used in speakerphone

designs where sound quality is important

• Microphone (M_MIC_IN); analog input

3.3.1.2 Telephone Handset/Headset Interface

The following interface signals are supported:

• Telephone Input (M_LINE_IN), input (TELIN) - Optional connection to a telephone

handset interface circuit

• Telephone output (M_LINE_OUTP); output (TELOUT) - Optional connection to a

telephone handset interface circuit

• Center Voltage (VC); output reference voltage

3.3.1.3 CX81801 Modem Interface

The following interface signals are supported:

• Sleep (SLEEP); input

• Master Clock (M_CLKIN); input

• Serial Clock (M_SCK); output

• Control (M_CNTRLSIN); input

• Serial Frame Sync (M_STROBE); output

• Serial Transmit Data (M_TXSIN); input

• Serial Receive Data (M_RXOUT); output

3.3.1.4 Host Interface

The following interface signals are supported:

• Reset (POR); input

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-29

3.3.2 CX20442 VC Pin Assignments and Signal Definitions

VC hardware interface signals are shown by major interface in Figure 3-7, are shown by

pin number in Figure 3-8, and are listed by pin number in Table 3-11.

VC hardware interface signals are defined in Table 3-12.

VC pin signal DC electrical characteristics are defined in Table 3-13.

VC pin signal analog electrical characteristics are defined in Table 3-14.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-30 Conexant 102247B

Figure 3-7. CX20442 VC Hardware Interface Signals

102247_009

CX20442

Voice Codec

(VC)

32-Pin LQFP

AUDIO

CIRCUIT

SPKOUT

MIC

TELIN

TELOUT

CX81801

+3.3V

VAA (+3.3V)

IASLEEP

DRESET#

M_CLK

V_SCLK

V_STROBE

V_TXSIN

V_RXOUT

V_CTRL

SLEEP

POR

M_CLKIN

M_SCK

M_STROBE

M_TXSIN

M_RXOUT

M_CNTRLSIN

VDD

MAVDD

VSS

SET3V_BAR2

MAVSS

VSUB

M_DIG_SPEAKER

M_MIC_IN

M_SPKR_OUT

M_LINE_IN

M_LINE_OUTP

M_LINE_OUTM

VREF

M_MIC_BIAS

M_RELAYA

M_RELAYB

M_ACT90

M_1BIT_OUT

D_LPBK_BAR

AGND

0.1uF 10uF

HANDSET

INTERFACE

AGND

GND

AGND

0.1uF 10uF

Figure 3-8. CX20442 VC 32-Pin LQFP Pin Signals

102247_010

SLEEP

M_DIG_SPEAKER

M_SPKR_OUT

POR

MAVDD

MAVSS

M_RELAYA

M_STROBE

M_RXOUT

M_SCK

M_TXSIN

M_CLKIN

M_CNTRLSIN

VDD

M_LINE_OUTP

M_LINE_OUTM

VREF

M_MIC_IN

M_LINE_IN

M_MIC_BIAS

M_RELAYB

D_LPBK_BAR

M_1BIT_OUT

M_ACT90

VSS

VSUB

SET3V_BAR2

VDD

CX20442

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-31

Table 3-11. CX20442 VC 32-Pin LQFP Pin Signals

Pin Signal Label I/O Interface

1 SLEEP I CX81801: IASLEEP

2 M_DIG_SPEAKER O NC

3 M_SPKR_OUT O Speaker interface circuit

4 POR I Host: RESET# or reset circuit

5 MAVDD P VAA (+3.3V)

6 MAVSS G AGND

7 NC NC

8 NC NC

9 M_LINE_OUTP O Handset interface circuit: TELOUT

10 M_LINE_OUTM O NC

11 VREF AGND through capacitors

12 VC AGND through capacitors

13 M_MIC_IN I Microphone interface circuit

14 M_LINE_IN I Handset interface circuit: TELIN

15 M_MIC_BIAS NC

16 M_RELAYB NC

17 VDD P +3.3V

18 M_CNTRLSIN I CX81801: V_CTRL

19 M_CLKIN I CX81801: M_CLK

20 M_TXSIN I CX81801: V_TXSIN

21 M_SCK O CX81801: V_SCLK

22 M_RXOUT O CX81801: V_RXOUT

23 M_STROBE O CX81801: V_STROBE

24 M_RELAYA O NC

25 VDD P +3.3V

26 M_SET3V_BAR2 I GND

27 VSUB G AGND

28 VSS G GND

29 M_ACT90 I NC

30 M_1BIT_OUT O NC

31 D_LPBK_BAR I NC

32 NC NC

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-32 Conexant 102247B

Table 3-12. CX20442 VC Pin Signal Definitions

Label Pin I/O I/O Type Signal Name/Description

System Signals

VDD 17, 25 P PWR Digital Power Supply. Connect to +3.3V and digital circuits power

supply filter.

MAVDD 5 P PWR Analog Power Supply. Connect to +3.3V and analog circuits

power supply filter.

VSS 28 G GND Digital Ground. Connect to GND.

MAVSS 6 G AGND Analog Ground. Connect to AGND.

VSUB 27 G GND Analog Ground. Connect to AGND.

POR 4 I Itpu Power-On Reset. Active low reset input. Connect to Host

RESET# or reset circuit.

SET3V_BAR2 26 I Itpu Set +3.3V Analog Reference. Connect to GND.

CX81801 Interconnect

SLEEP 1 I Itpd IA Sleep. Active high sleep input. Connect to CX81801 IASLEEP

pin.

M_CLKIN 19 I Itpd Master Clock Input. Connect to CX81801 M_CLK pin.

M_SCK 21 O Ot2 Serial Clock Output. Connect to CX81801 V_SCLK pin.

M_CNTRL_SIN 18 I Itpd Control Input. Connect to CX81801 V_CTRL pin.

M_STROBE 23 O Ot2 Serial Frame Sync. Connect to CX81801 V_STROBE pin.

M_TXSIN 20 I Itpd Serial Transmit Data. Connect to CX81801 V_TXSIN pin.

M_RXOUT 22 O Ot2 Serial Receive Data. Connect to CX81801 V_RXOUT pin.

Microphone/Speaker Interface

M_MIC_IN 13 I I(DA) Microphone Input. Single-ended analog input from the

microphone circuit.

M_SPKR_OUT 3 O O(DF) Modem Speaker Analog Output. The M_SPKR_OUT analog

output reflects the received analog input signal. The

M_SPKR_OUT on/off and three levels of attenuation are controlled

by bits in DSP RAM. When the speaker is turned off, the

M_SPKR_OUT output is clamped to the voltage at the VC pin. The

M_SPKR_OUT output can drive an impedance as low as 300 Ω. In

a typical application, the M_SPKR_OUT output is an input to an

external LM386 audio power amplifier.

Handset/Headset Interface

M_LINE_OUTP 9 O O(DF) Telephone Handset Out (TELOUT). Single-ended analog data

output to the telephone handset circuit. The output can drive a

300 Ω load.

M_LINE_IN 14 I I(DA) Telephone Handset Out (TELIN). Single-ended analog data input

from the telephone handset circuit.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-33

Table 3-15. CX20442 VC Pin Signal Definitions (Continued)

Label Pin I/O I/O Type Signal Name/Description

Reference Voltage

VREF 11 R REF High Voltage Reference. Connect to analog ground through

10 µF (polarized, + terminal to VREF) and 0.1 µF (ceramic) in

parallel. Ensure a very close proximity between these capacitors

and VREF pin.

VC 12 R REF Low Voltage Reference. Connect to analog ground through

10 µF (polarized, + terminal to VC) and 0.1 µF (ceramic) in

parallel. Ensure a very close proximity between these capacitors

and VC pin.

For handset interface, also connect to handset interface circuit

(VC_HAND).

Not Used

M_DIG_SPEAKER 2 O Ot2 Not Used. Leave open.

M_LINE_OUTM 10 O Oa Not Used. Leave open.

M_RELAYA 24 O Ot Not Used. Leave open.

M_RELAYB 16 O Ot Not Used. Leave open.

M_MIC_BIAS 15 O Oa Not Used. Leave open.

M_ACT90 29 I Itpu Not Used. Leave open.

M_1BIT_OUT 30 O Ot2 Not Used. Leave open.

D_LPBK_BAR 31 I It Not Used. Leave open.

NC 7, 8, 32 Internal No Connect. Leave open.

Notes:

1. I/O types*:

Ia Analog input

It Digital input, TTL-compatible

Itpd Digital input, TTL-compatible, internal 75k ± 25k Ω pull-down

Itpu Digital input, TTL-compatible, internal 75k ± 25k Ω pull-up

Oa Analog output

Ot2 Digital output, TTL-compatible, 2 mA, ZINTERNAL = 120 Ω

Ot2od Digital output, TTL-compatible, 2 mA, open drain, ZINTERNAL = 120 Ω

AGND Analog Ground

GND Digital Ground

Table 3-13. CX20442 VC DC Electrical Characteristics

Parameter Symbol Min. Typ. Max. Units Test Conditions

Input Voltage VIN -0.30 – VDD+0.3 V

Input Voltage Low VIL -0.30 – 0.2 *VDD V

Input Voltage High VIH 0.4*VDD – VDD+0.3 V

Output Voltage Low VOL 0 – 0.4 V

Output Voltage High VOH 0.8*VDD – VDD V

Input Leakage Current – -10 – 10 µA

Output Leakage Current (High

Impedance)

– -10 – 10 µA

Test Conditions unless otherwise stated: VDD = +3.3 ± 0.3 VDC; TA = 0°C to 70°C; external load = 50 pF

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-34 Conexant 102247B

Table 3-14. CX20442 VC Analog Electrical Characteristics

Signal Name Type Characteristic Value

M_LINE_IN, I (DA) Input Impedance > 70K Ω

M_MIC_IN AC Input Voltage Range 1.1 VP-P

Reference Voltage +1.35 VDC

M_LINE_OUTP O (DD) Minimum Load 300 Ω

Maximum Capacitive Load 0 µF

Output Impedance

10 Ω

AC Output Voltage Range 1.4 VP-P (with reference to ground and a

600 Ω load)

Reference Voltage +1.35 VDC

DC Offset Voltage ± 200 mV

M_SPKR_OUT O (DF) Minimum Load 300 Ω

Maximum Capacitive Load 0.01 µF

Output Impedance

10 Ω

AC Output Voltage Range 1.4 VP-P

Reference Voltage +1.35 VDC

DC Offset Voltage ± 20 mV

Test Conditions unless otherwise stated: VDD = +3.3 ± 0.3 VDC; MAVDD = +3.3 ± 0.3 VDC, TA = 0°C to 70°C

Parameter Min Typ Max Units

DAC to Line Driver output (600Ω load, 3dB in SCF and CTF) SNR/SDR at:

4Vp-p differential

2Vp-p differential

-10dBm differential

88/85

82/95

72/100

DAC to Speaker Driver output (150Ω load, 3dB in SCF and CTF, -6dB in

speaker driver) SNR/SDR at:

2Vp-p

1Vp-p

-10dBm

88/75

82/80

72/83

Line Input to ADC (6dB in AAF) SNR/SDR at –10 dBm 80/95 dB

Input Leakage Current (analog inputs) -10 10 µA

Output Leakage Current (analog outputs) -10 10 µA

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-35

3.4 Electrical and Environmental Specifications

3.4.1 Operating Conditions, Absolute Maximum Ratings, and Power Requirements

The operating conditions are specified in Table 3-15.

The absolute maximum ratings are listed in Table 3-16.

The current and power requirements are listed in Table 3-17.

Table 3-15. Operating Conditions

Parameter Symbol Limits Units

Supply Voltage VDD +3.0 to +3.6 VDC

Operating Ambient Temperature TA 0 to +70 °C

Table 3-16. Absolute Maximum Ratings

Parameter Symbol Limits Units

Supply Voltage VDD -0.5 to +4.0 VDC

Input Voltage VIN -0.5 to + (VGG + 0.5)* VDC

Storage Temperature Range TSTG -55 to +125 °C

Analog Inputs VIN -0.3 to (VAA + 0.5) VDC

Voltage Applied to Outputs in High

Impedance (Off) State

VHZ -0.5 to + (VGG + 0.5)* VDC

DC Input Clamp Current IIK ±20 mA

DC Output Clamp Current IOK ±20 mA

Static Discharge Voltage (25°C) VESD ±2500 VDC

Latch-up Current (25°C) ITRIG ±400 mA

* VGG = +3.3V ± 0.3V, or +5V ± 0.25V

Handling CMOS Devices

The device contains circuitry to protect the inputs against damage due to high static

voltages. However, it is advised that normal precautions be taken to avoid application of

any voltage higher than maximum rated voltage.

An unterminated input can acquire unpredictable voltages through coupling with stray

capacitance and internal cross talk. Both power dissipation and device noise immunity

degrades. Therefore, all inputs should be connected to an appropriate supply voltage.

Input signals should never exceed the voltage range from -0.5V to + (VGG + 0.5V). This

prevents forward biasing the input protection diodes and possibly entering a latch up

mode due to high current transients.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-36 Conexant 102247B

Table 3-17. Current and Power Requirements

Mode

Typical

Current

(Ityp)

(mA)

Maximum

Current

(Imax)

(mA)

Typical

Power

(Ptyp)

(mW)

Maximum

Power

(Pmax)

(mW)

Notes

CX81801 Modem and CX20493 LSD

Normal Mode: Off-hook, normal data connection 65 74 215 266 f = 28.224 MHz

Normal Mode: On-hook, idle, waiting for ring 63 72 208 259 f = 28.224 MHz

Sleep Mode 18 21 59 76 f = 0 MHz

CX20442 VC (Optional)

Normal Mode 1.5 2.0 5 7

Notes:

1. Operating voltage: VDD = +3.3V ± 0.3V.

2. Test conditions: VDD = +3.3V for typical values; VDD = +3.6V for maximum values.

3. Input Ripple ≤ 0.1 Vpeak-peak.

4. f = Internal frequency.

5. Maximum current computed from Ityp: Imax = Ityp * 1.1.

6. Typical power (Ptyp) computed from Ityp: Ptyp = Ityp * 3.3V; Maximum power (Pmax) computed from

Imax: Pmax = Imax * 3.6V.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-37

3.4.2 Interface and Timing Waveforms

3.4.2.1 External Memory Bus Timing

The external memory bus timing is listed in Table 3-18 and illustrated in Figure 3-9.

Table 3-18. Timing - External Memory Bus

Symbol Parameter Min Typ. Max Units

tFI Internal Operating Frequency 28.224 – – MHz

tCYC Internal Operating Clock Cycle 30 – – ns

Read

tAS READ# High to Address Valid – 6.5 9 ns

tES READ# High to ES Valid – 8 11 ns

tRW READ# Pulse Width 15 – 105 ns

tRDS Read Data Valid to READ# High 6.1 – – ns

tRDH READ# High to Read Data Hold 0 0 – ns

Write

tAS WRITE# High to Address Valid – 6.5 8 ns

tES WRITE# High to ES Valid – 8 11 ns

tWW WRITE# to WRITE# Pulse Width 15 – 105 ns

tWTD WRITE# Low to Write Data Valid – 5 8.2 ns

tWTH WRITE# High to Write Data Hold 5.0 – – ns

Notes:

1. ES = RAMSEL# or ROMSEL#.

2. Read pulse width and write pulse width:

RAM: tRW, tWW = 0.5 tCYC = 15 for Non-Extended Cycle Timing

ROM: tRW, tWW = 3.5 tCYC = 105 for Extended Cycle Timing

3. Memory speed determination:

RAM: tACCESS = tCYC - tES - tRDS = 330 - 8 - 6.1 = 15.9 ns (i.e., use 15 ns memory)

ROM: tACCESS = 4(tCYC) - tES - tRDS = 4(30) - 8 - 6.1 = 105.9 ns (i.e., use 90 ns memory).

4. Output Enable to Output Delay Timing:

RAM: tOE = tRW - tRDS = 0.5(tCYC) - tRDS = 15 - 6.1 = 8.9 ns

ROM: tOE = tRW - tRDS = 3.5(tCYC) - tRDS = 105 - 6.1 = 98.9 ns.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-38 Conexant 102247B

Figure 3-9. Waveforms - External Memory Bus

Write Timing

Read Timing

tCYC

tAS

RDH

C2*

A[18:0]

tRW

RDS

READ#

D[7:0]

ES#**

tES

* C2 = Internal Phase 2 clock.

** ES# = RAMSEL# or ROMSEL#.

100491 F3-09 WF EB

tCYC

tAS

tWW

ttWTH

WTD

C2*

A[18:0]

WRITE#

D[7:0]

ES#**

* C2 = Internal Phase 2 clock.

** ES# = RAMSEL# or ROMSEL#.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-39

3.4.2.2 Parallel Host Bus Timing

The parallel host bus timing is listed in Table 3-19 and illustrated in Figure 3-10.

Table 3-19. Timing - Parallel Host Bus

Symbol Parameter Min Max Units

READ (See Notes 1, 2, 3, 4, and 5)

tAS Address Setup 5 – ns

tAH Address Hold 10 – ns

tCS Chip Select Setup 0 – ns

tCH Chip Select Hold 10 – ns

tRD HRD# Strobe Width 45 – ns

tDD Read Data Delay – 25 ns

tDRH Read Data Hold 5 – ns

WRITE (See Notes 1, 2, 3, 4, and 5)

tAS Address Setup 5 – ns

tAH Address Hold 15 – ns

tCS Chip Select Setup 0 – ns

tCH Chip Select Hold 10 – ns

tWT HWT# Strobe Width 75 – ns

tDS Write Data Setup (see Note 4) – 20 ns

tDWH Write Data Hold (see Note 5) 5 – ns

Notes:

1. When the host executes consecutive Rx FIFO reads, a minimum delay of 2 times the internal CPU clock cycle

plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of HRD# to the falling edge of the next Host

Rx FIFO HRD# clock.

2. When the Host executes consecutive Tx FIFO writes, a minimum delay of 2 times the internal CPU clock cycle

plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of HWT# to the falling edge of the next Host

Tx FIFO HWT# clock.

3. tDS is measured from the point at which both HCS# and HWT# are active.

4. tDWH is measured from the point at which either HCS# and HWT# become inactive.

5. Clock frequency = 28.224 MHz clock.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-40 Conexant 102247B

Figure 3-10. Waveforms - Parallel Host Bus

tAS tAH

tCS tCH

tRD

tDD tDRH

HA[2-0]

HCS#

HRD#

HWT#

HD[7-0]

tAS tAH

tCS tCH

HA[2-0]

tWT

tDS tDWH

HCS#

HRD#

HWT#

HD[7-0]

100491 F3-10 WF-HB

a. Host Read

b. Host Write

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 3-41

3.4.2.3 Serial DTE Interface

The serial DTE interface waveforms for 4800 and 9600 bps are illustrated in Figure 3-11.

Figure 3-11. Waveforms - Serial DTE Interface

TXCLK

4800 BPS

TXD

4800 BPS

TXCLK

9600 BPS

TXD

9600 BPS

NOTE: THIS FIGURE IS VALID FOR SYNCHRONOUS MODE ONLY. THERE IS NO RELATIONSHIP BETWEEN

NOTE: TXD AND TXCLK IN ASYNCHRONOUS MODE.

RXCLK

4800 BPS

RXD

4800 BPS

RXCLK

9600 BPS

RXD

9600 BPS

NOTE: THIS FIGURE IS VALID FOR SYNCHRONOUS MODE ONLY. THERE IS NO RELATIONSHIP BETWEEN

NOTE: RXD AND RXCLK IN ASYNCHRONOUS MODE.

a. Transmit

b. Receive 1227F3-14 WF-Ser DTE

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

3-42 Conexant 102247B

3.5 Crystal Specifications

Crystal specifications are listed in Table 3-20.

Table 3-20. Crystal Specifications

Characteristic Value

Frequency 28.224 MHz nominal

Calibration Tolerance ±50 ppm at 25°C (CL = 16.5 and 19.5 pF)

Frequency Stability vs. Temperature ±35 ppm (0°C to 70°C)

Frequency Stability vs. Aging ±20 ppm/5 years

Oscillation Mode Fundamental

Calibration Mode Parallel resonant

Load Capacitance, CL 18 pF nom.

Shunt Capacitance, CO 7 pF max.

Series Resistance, R1 35-60 Ω max. @20 nW drive level

Drive Level 100µW correlation; 500µW max.

Operating Temperature 0°C to 70°C

Storage Temperature –40°C to 85°C

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 4-1

4. Package Dimensions

The 128-pin LQFP package dimensions are shown in Figure 4-1.

The 32-pin LQFP package dimensions are shown in Figure 4-2.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

4-2 Conexant 102247B

Figure 4-1. Package Dimensions - 128-Pin LQFP

DD1

E1 DETAIL A

DETAIL A

Millimeters

0.05

21.75

15.75

0.5

0.17

0.11

1.6 MAX

0.15

1.4 REF

22.25

20.0 REF

18.5 REF

16.25

14.0 REF

12.5 REF

0.75

1.0 REF

0.50 BSC

0.27

0.17

0.08 MAX

0.0020

0.8563

0.6201

0.0197

0.0067

0.0043

Coplanarity

Min. Max. Min. Max.

Inches*

Dim.

Ref: 128-PIN LQFP (GP00-D264)

* Metric values (millimeters) should be used for

PCB layout. English values (inches) are

converted from metric values and may include

round-off errors.

0.0630 MAX

0.0059

0.0551 REF

0.8760

0.7874 REF

0.7283 REF

0.6398

0.5512 REF

0.4921 REF

0.0295

0.0394 REF

0.0197 BSC

0.0106

0.0067

0.0031 MAX

PD-LQFP-128

PIN 1

REF

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 4-3

Figure 4-2. Package Dimensions - 32-Pin LQFP

DETAIL A

AA2

Millimeters

0.05

1.35

0.45

0.3

0.09

1.6 MAX

0.15

1.45

9.00 REF

7.00 REF

5.6

0.75

1.0 REF

0.80 BSC

0.45

0.20

0.10 MAX

0.0020

0.0531

0.018

0.012

0.004

Coplanarity

Min. Max. Min. Max.

Inches*

Dim.

* Metric values (millimeters) should be used for

PCB layout. English values (inches) are

converted from metric values and may include

round-off errors.

0.0630 MAX

0.0059

0.0571

0.354 REF

0.276 REF

0.22

0.03

0.0394 REF

0.031 BSC

0.018

0.008

0.004 MAX

PD-LQFP-32

DETAIL A

DD2

PIN 1

REF

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

4-4 Conexant 102247B

This page is intentionally blank.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 5-1

5. Parallel Host Interface

The modem supports a 16550A interface in parallel interface versions. The 16550A

interface can operate in FIFO mode or non-FIFO mode. Non-FIFO mode is the same as

16450 interface operation. FIFO mode unique operations are identified.

5.1 Overview

The parallel interface registers and the corresponding bit assignments are shown in

Table 5-1.

The modem emulates the 16450/16550A interface and includes both a 16-byte receiver

data first-in first-out buffer (RX FIFO) and a 16-byte transmit data first-in first-out buffer

(TX FIFO). When FIFO mode is selected in the FIFO Control Register (FCR0 = 1), both

FIFOs are operative. Furthermore, when FIFO mode is selected, DMA operation of the

FIFO can also be selected (FCR3 = 1). When FIFO mode is not selected, operation is

restricted to 16450 interface operation.

The received data is read by the host from the Receiver Buffer (RX Buffer). The RX

Buffer corresponds to the Receiver Buffer Register in a 16550A device. In FIFO mode,

the RX FIFO operates transparently behind the RX Buffer. Interface operation is

described with reference to the RX Buffer in both FIFO and non-FIFO modes.

The transmit data is loaded by the host into the Transmit Buffer (TX Buffer). The TX

Buffer corresponds to the Transmit Holding Register in a 16550A device. In FIFO mode,

the TX FIFO operates transparently behind the TX Buffer. Interface operation is

described with reference to the TX Buffer in both FIFO and non-FIFO modes.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

5-2 Conexant 102247B

Table 5-1. Parallel Interface Registers

No. Name 7 6 5 4 3 2 1 0

7 Scratch Register (SCR) Scratch Register

6 Modem Status Register (MSR) Data Carrier

Detect

(DCD)

Ring

Indicator (RI)

Data Set

Ready

(DSR)

Clear to

Send

(CTS)

Delta Data

Carrier

Detect

(DDCD)

Trailing

Edge of Ring

Indicator

(TERI)

Delta Data

Set Ready

(DDSR)

Delta Clear

to Send

(DCTS)

5 Line Status Register (LSR) RX FIFO

Error

Transmitter

Empty

(TEMT)

Transmitter

Buffer

Empty

(THRE)

Break

Interrupt (BI)

Framing

Error

(FE)

Parity

Error

(PE)

Overrun

Error

(OE)

Receiver

Data Ready

(DR)

4 Modem Control Register (MCR) 0 0 0 Local

Loopback

Out 2 Out 1 Request to

Send

(RTS)

Data

Terminal

Ready

(DTR)

3 Line Control Register (LCR) Divisor Latch

Access Bit

(DLAB)

Set Break Stick Parity Even Parity

Select (EPS)

Parity

Enable

(PEN)

Number of

Stop Bits

(STB)

Word Length

Select Bit 1

(WLS1)

Word Length

Select Bit 0

(WLS0)

2 Interrupt Identify Register (IIR)

(Read Only)

FIFOs

Enabled

FIFOs

Enabled

0 0 Pending

Interrupt ID

Bit 2

Pending

Interrupt ID

Bit 1

Pending

Interrupt ID

Bit 0

“0" if

Interrupt

Pending

2 FIFO Control Register (FCR)

(Write Only)

Receiver

Trigger MSB

Receiver

Trigger

LSB

Reserved Reserved DMA Mode

Select

TX FIFO

Reset

RX FIFO

Reset

FIFO Enable

(DLAB = 0)

Interrupt Enable Register (IER) 0 0 0 0 Enable

Modem

Status

Interrupt

(EDSSI)

Enable

Receiver

Line Status

Interrupt

(ELSI)

Enable

Transmitter

Holding

Empty

Interrupt

(ETBEI)

Enable

Received

Data

Available

Interrupt

(ERBFI)

(DLAB = 0)

Transmitter Buffer Register

(THR)

Transmitter FIFO Buffer Register (Write Only)

(DLAB = 0)

Receiver Buffer Register (RBR) Receiver FIFO Buffer Register (Read Only)

(DLAB = 1)

Divisor Latch MSB Register

(DLM)

Divisor Latch MSB

(DLAB = 1)

Divisor Latch LSB Register

(DLL)

Divisor Latch LSB

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 5-3

5.2 Register Signal Definitions

5.2.1 IER - Interrupt Enable Register (Addr = 1, DLAB = 0)

The IER enables five types of interrupts that can separately assert the HINT output signal

(Table 5-2). A selected interrupt can be enabled by setting the corresponding enable bit to

a 1, or disabled by setting the corresponding enable bit to a 0. Disabling an interrupt in

the IER prohibits setting the corresponding indication in the IIR and assertion of HINT.

Disabling all interrupts (resetting IER0 - IER3 to a 0) inhibits setting of any Interrupt

Identifier Register (IIR) bits and inhibits assertion of the HINT output. All other system

functions operate normally, including the setting of the Line Status Register (LSR) and

the Modem Status Register (MSR).

Bits 7-4 Not used.

Always 0.

Bit 3 Enable Modem Status Interrupt (EDSSI).

This bit, when a 1, enables assertion of the HINT output whenever the Delta CTS

(MSR0), Delta DSR (MSR1), Delta TER (MSR2), or Delta DCD (MSR3) bit in the

Modem Status Register (MSR) is a 1. This bit, when a 0, disables assertion of HINT

due to setting of any of these four MSR bits.

Bit 2 Enable Receiver Line Status Interrupt (ELSI).

This bit, when a 1, enables assertion of the HINT output whenever the Overrun Error

(LSR1), Parity Error (LSR2), Framing Error (LSR3), or Break Interrupt (LSR4)

receiver status bit in the Line Status Register (LSR) changes state. This bit, when a 0,

disables assertion of HINT due to change of the receiver LSR bits 1-4.

Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETBEI).

This bit, when a 1, enables assertion of the HINT output when the Transmitter Empty

bit in the Line Status Register (LSR5) is a 1. This bit, when a 0, disables assertion of

HINT due to LSR5.

Bit 0 Enable Receiver Data Available Interrupt (ERBFI) and Character

Timeout in FIFO Mode.

This bit, when a 1, enables assertion of the HINT output when the Receiver Data Ready

bit in the Line Status Register (LSR0) is a1 or character timeout occurs in the FIFO

mode. This bit, when a 0, disables assertion of HINT due to the LSR0 or character

timeout.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

5-4 Conexant 102247B

5.2.2 FCR - FIFO Control Register (Addr = 2, Write Only)

The FCR is a write-only register used to enable FIFO mode, clear the RX FIFO and TX

FIFO, enable DMA mode, and set the RX FIFO trigger level.

Bits 7-6 RX FIFO Trigger Level.

FCR7 and FCR6 set the trigger level for the RX FIFO (Receiver Data Available)

interrupt.

FCR7 FCR6 RX FIFO Trigger Level (Bytes)

0 0 01

0 1 04

1 0 08

1 1 14

Bits 5-4 Not used.

Bit 3 DMA Mode Select.

When FIFO mode is selected (FCR0 = 1), FCR3 selects non-DMA operation (FCR3 =

0) or DMA operation (FCR3 = 1). When FIFO mode is not selected (FCR0 = 0), this

bit is not used (the modem operates in non-DMA mode in 16450 operation).

DMA operation in FIFO mode.

RXRDY will be asserted when the number of characters in the RX FIFO is equal to or

greater than the value in the RX FIFO Trigger Level (IIR0-IIR3 = 4h) or the received

character timeout (IIR0-IIR3 = Ch) has occurred. RXRDY will go inactive when there

are no more characters in the RX FIFO.

TXRDY will be asserted when there are one or more empty (unfilled) locations in the

TX FIFO. TXRDY will go inactive when the TX FIFO is completely full.

Non-DMA operation in FIFO mode.

RXRDY will be asserted when there are one or more characters in the RX FIFO.

RXRDY will go inactive when there are no more characters in the RX FIFO.

TXRDY will be asserted when there are no characters in the TX FIFO. TXRDY will go

inactive when the first character is loaded into the TX FIFO Buffer.

Bit 2 TX FIFO Reset.

When FCR2 is a 1, all bytes in the TX FIFO are cleared. This bit is cleared

automatically by the modem.

Bit 1 RX FIFO Reset.

When FCR1 is a 1, all bytes in the RX FIFO are cleared. This bit is cleared

automatically by the modem.

Bit 0 FIFO Enable.

When FCR0 is a 0, 16450 mode is selected and all bits are cleared in both FIFOs.

When FCR0 is a 1, FIFO mode (16550A mode) is selected and both FIFOs are

enabled. FCR0 must be a 1 when other bits in the FCR are written or they will not be

acted upon.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 5-5

5.2.3 IIR - Interrupt Identifier Register (Addr = 2)

The Interrupt Identifier Register (IIR) identifies the existence and type of up to five

prioritized pending interrupts. Four priority levels are set to assist interrupt processing in

the host. The four levels, in order of decreasing priority, are: Highest: Receiver Line

Status, 2: Receiver Data Available or Receiver Character Timeout, 3: TX Buffer Empty,

and 4: Modem Status.

When the IIR is accessed, the modem freezes all interrupts and indicates the highest

priority interrupt pending to the host. Any change occurring in interrupt conditions are

not indicated until this access is complete.

Bits 7-6 FIFO Mode.

These two bits copy FCR0.

Bits 5-4 Not Used.

Always 0.

Bits 3-1 Highest Priority Pending Interrupt.

These three bits identify the highest priority pending interrupt (Table 5-2). Bit 3 is

applicable only when FIFO mode is selected, otherwise bit 3 is a 0.

Bit 0 Interrupt Pending.

When this bit is a 0, an interrupt is pending; IIR bits 1-3 can be used to determine the

source of the interrupt. When this bit is a1, an interrupt is not pending.

Table 5-2. Interrupt Sources and Reset Control

Interrupt Identification Register Interrupt Set and Reset Functions

Bit

Bit 2 Bit 1 Bit 0 Priority

Level

Interrupt Type Interrupt Source Interrupt Reset Control

0 0 0 1 — None None —

0 1 1 0 Highest Receiver Line

Status

Overrun Error OE (LSR1),

Parity Error (PE) (LSR2),

Framing Error (FE) (LSR3),

or Break Interrupt (BI) (LSR4)

Reading the LSR

0 1 0 0 2 Received Data

Available

Received Data Available (LSR0) or

RX FIFO Trigger Level (FCR6-

FCR7) Reached1

Reading the RX Buffer or the RX

FIFO drops below the Trigger

Level

1 1 0 0 2 Character Time-out

Indication 1

The RX FIFO contains at least 1

character and no characters have

been removed from or input to the

RX FIFO during the last 4 character

times.

Reading the RX Buffer

0 0 1 0 3 TX Buffer Empty TX Buffer Empty Reading the IIR or writing to the

TX Buffer

0 0 0 0 4 Modem Status Delta CTS (DCTS) (MSR0),

Delta DSR (DDSR) (MSR1),

Trailing Edge Ring Indicator (TERI)

(MSR3), or Delta DCD (DCD)

(MSR4)

Reading the MSR

Notes:

1. FIFO Mode only.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

5-6 Conexant 102247B

5.2.4 LCR - Line Control Register (Addr = 3)

The Line Control Register (LCR) specifies the format of the asynchronous data

communications exchange.

Bit 7 Divisor Latch Access Bit (DLAB).

This bit must be set to a 1 to access the Divisor latch registers during a read or write

operation. It must be reset to a 0 to access the Receiver Buffer, the Transmitter Buffer,

or the Interrupt Enable Register.

Bit 6 Set Break.

When bit 6 is a 1, the transmit data is forced to the break condition, i.e., space (0) is

sent. When bit 6 is a 0, break is not sent. The Set Break bit acts only on the transmit

data and has no effect on the serial in logic.

Bit 5 Stick Parity.

When parity is enabled (LCR3 = 1) and stick parity is selected (LCR5 = 1), the parity

bit is transmitted and checked by the receiver as a 0 if even parity is selected (LCR4 =

1) or as a 1 if odd parity is selected (LCR4 = 0). When stick parity is not selected

(LCR3 = 0), parity is transmit and checked as determined by the LCR3 and LCR4 bits.

Bit 4 Even Parity Select (EPS).

When parity is enabled (LCR3 = 1) and stick parity is not selected (LCR5 = 0), the

number of 1s transmitted or checked by the receiver in the data word bits and parity bit

is either even (LCR4 = 1) or odd (LCR4 = 0).

Bit 3 Enable Parity (PEN).

When bit 3 is a 1, a parity bit is generated in the serial out (transmit) data stream and

checked in the serial in (receive) data stream as determined by the LCR 4 and LCR5

bits. The parity bit is located between the last data bit and the first stop bit.

Bit 2 Number of Stop Bits (STB).

This bit specifies the number of stop bits in each serial out character. If bit 2 is a 0, one

stop bit is generated regardless of word length. If bit 2 is a 1 and 5-bit word length is

selected, one and one-half stop bits are generated. If bit 2 is a 1 and a 6-, 7-, or 8-bit

word length is selected, two stop bits are generated. The serial in logic checks the first

stop bit only, regardless of the number of stop bits selected.

Bits 1-0 Word Length Select (WLS0 and WLS1).

These two bits specify the number of bits in each serial in or serial out character. The

encoding of bits 0 and 1 is:

Bit 1 Bit 0 Word Length

0 0 5 Bits (Not supported)

0 1 6 Bits (Not supported)

1 0 7 Bits

1 1 8 Bits

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 5-7

5.2.5 MCR - Modem Control Register (Addr = 4)

The Modem Control Register (MCR) controls the interface with the modem or data set.

Bit 7-5 Not used.

Always 0.

Bit 4 Local Loopback.

When this bit is set to a 1, the diagnostic mode is selected and the following occurs:

Data written to the Transmit Buffer is looped back to the Receiver Buffer.

The DTS (MCR0), RTS (MCR1), Out1 (MCR2), and Out2 (MCR3) modem control

DCD (MSR7) modem status register bits, respectively.

Bit 3 Output 2.

When this bit is a 1, HINT is enabled. When this bit is a 0, HINT is in the high

impedance state.

Bit 2 Output 1.

This bit is used in local loopback (see MCR4).

Bit 1 Request to Send (RTS).

This bit controls the Request to Send (RTS) function. When this bit is a 1, RTS is on.

When this bit is a 0, RTS is off.

Bit 0 Data Terminal Ready (DTR).

This bit controls the Data Terminal Ready (DTR) function. When this bit is a 1, DTR is

on. When this bit is a 0, DTR is off.

5.2.6 LSR - Line Status Register (Addr = 5)

This 8-bit register provides status information to the host concerning data transfer.

Bit 7 RX FIFO Error.

In the 16450 mode, this bit is not used and is always 0.

In the FIFO mode, this bit is set if there are one or more characters in the RX FIFO

with a parity error, framing error, or break indication detected. This bit is reset to a 0

when the host reads the LSR and none of the above conditions exist in the RX FIFO.

Bit 6 Transmitter Empty (TEMT).

This bit is set to a 1 whenever the TX Buffer (THR) and equivalent of the Transmitter

Shift Register (TSR) are both empty. It is reset to a 0 whenever either the THR or the

equivalent of the TSR contains a character.

In the FIFO mode, this bit is set to a 1 when ever the TX FIFO and the equivalent of

the TSR are both empty.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

5-8 Conexant 102247B

Bit 5 Transmitter Holding Register Empty (THRE) [TX Buffer Empty].

This bit, when set, indicates that the TX Buffer is empty and the modem can accept a

new character for transmission. In addition, this bit causes the modem to issue an

interrupt to the host when the Transmit Holding Register Empty Interrupt Enable bit

(IIR1) is set to 1. The THRE bit is set to a 1 when a character is transferred from the

TX Buffer. The bit is reset to 0 when a byte is written into the TX Buffer by the host.

In the FIFO mode, this bit is set when the TX FIFO is empty; it is cleared when at least

one byte is in the TX FIFO.

Bit 4 Break Interrupt (BI).

This bit is set to a 1 whenever the received data input is a space (logic 0) for longer

than two full word lengths plus 3 bits. The BI bit is reset when the host reads the LSR.

Bit 3 Framing Error (FE).

This bit indicates that the received character did not have a valid stop bit. The FE bit is

set to a 1 whenever the stop bit following the last data bit or parity bit is detected as a

logic o (space). The FE bit is reset to a 0 when the host reads the LSR.

In the FIFO mode, the error indication is associated with the particular character in the

FIFO it applies to; the FE bit is set to a 1 when this character is loaded into the RX

Buffer.

Bit 2 Parity Error (PE).

This bit indicates that the received data character in the RX Buffer does not have the

correct even or odd parity, as selected by the Even Parity Select bit (LCR4) and the

Stick Parity bit (LCR5). The PE bit is reset to a 0 when the host reads the LSR.

In the FIFO mode, the error indication is associated with the particular character in the

it applies to; the PE bit is set to a 1 when this character is loaded into the RX Buffer.

Bit 1 Overrun Error (OE).

This bit is set to a 1 whenever received data is loaded into the RX Buffer before the

host has read the previous data from the RX Buffer. The OE bit is reset to a 0 when the

host reads the LSR.

In the FIFO mode, if data continues to fill beyond the trigger level, an overrun

condition will occur only if the RX FIFO is full and the next character has been

completely received.

Bit 0 Receiver Data Ready (DR).

This bit is set to a 1 whenever a complete incoming character has been received and

has been transferred into the RX Buffer. The DR bit is reset to a 0 when the host reads

the RX Buffer.

In the FIFO mode, the DR bit is set when the number of received data bytes in the RX

FIFO equals or exceeds the trigger level specified in FCR0-FCR1.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 5-9

5.2.7 MSR - Modem Status Register (Addr = 6)

The Modem Status Register (MSR) reports current state and change information of the

modem. Bits 4-7 supply current state and bits 0-3 supply change information. The change

bits are set to a 1 whenever a control input from the modem changes state from the last

MSR read by the host. Bits 0-3 are reset to 0 when the host reads the MSR or upon reset.

Whenever bits 0, 1, 2, or 3 are set to a 1, a Modem Status Interrupt (IIR0-IIR3 = 0) is

generated.

Bit 7 Data Carrier Detect (DCD).

This bit indicates the logic state of the DCD# (RLSD#) output. If Loopback is selected

(MCR4 = 1), this bit reflects the state of the Out2 bit in the MCR (MCR3).

Bit 6 Ring Indicator (RI).

This bit indicates the logic state of the RI# output. If Loopback is selected (MCR4 = 1),

this bit reflects the state of the Out1 bit in the MCR (MCR2).

Bit 5 Data Set Ready (DSR).

This bit indicates the logic state of the DSR# output. If Loopback is selected (MCR4 =

1), this bit reflects the state of the DTR bit in the MCR (MCR0).

Bit 4 Clear to Send (CTS).

This bit indicates the logic state of the CTS# output. If Loopback is selected (MCR4 =

1), this bit reflects the state of the RTS bit in the MCR (MCR1).

Bit 3 Delta Data Carrier Detect (DDCD).

This bit is set to a 1 when the DCD bit changes state since the MSR was last read by

the host.

Bit 2 Trailing Edge of Ring Indicator (TERI).

This bit is set to a 1 when the RI bit changes from a 1 to a 0 state since the MSR was

last read by the host.

Bit 1 Delta Data Set Ready (DDSR).

This bit is set to a 1 when the DSR bit has changed since the MSR was last read by the

host.

Bit 0 Delta Clear to Send (DCTS).

This bit is set to a 1 when the CTS bit has changed since the MSR was last read by the

host.

5.2.8 RBR - RX Buffer (Receiver Buffer Register) (Addr = 0, DLAB = 0)

The RX Buffer (RBR) is a read-only register at location 0 (with DLAB = 0). Bit 0 is the

least significant bit of the data, and is the first bit received.

5.2.9 THR - TX Buffer (Transmitter Holding Register) (Addr = 0, DLAB = 0)

The TX Buffer (THR) is a write-only register at address 0 when DLAB = 0. Bit 0 is the

least significant bit and the first bit sent.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

5-10 Conexant 102247B

5.2.10 Divisor Registers (Addr = 0 and 1, DLAB = 1)

The Divisor Latch LS (least significant byte) and Divisor Latch MS (most significant

byte) are two read-write registers at locations 0 and 1 when DLAB = 1, respectively.

The baud rate is selected by loading each divisor latch with the appropriate hex value.

Programmable values corresponding to the desired baud rate are listed in Table 5-3.

1. SCR - Scratch Register (Addr = 7)

The Scratchpad Register is a read-write register at location 7. This register is not used by

the modem and can be used by the host for temporary storage.

Table 5-3. Programmable Baud Rates

Divisor Latch (Hex)

MS LS Divisor (Decimal) Baud Rate

06 00 1536 75

04 17 1047 110

03 00 768 150

01 80 384 300

00 C0 192 600

00 60 96 1200

00 30 48 2400

00 18 24 4800

00 0C 12 9600

00 06 6 19200

00 04 4 28800

00 03 3 38400

00 02 2 57600

00 01 1 115200

00 00 NA 230400

5.3 Receiver FIFO Interrupt Operation

5.3.1 Receiver Data Available Interrupt

When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (RX Data Available)

is enabled (IER0 = 1), receiver interrupt operation is as follows:

The Receiver Data Available Flag (LSR0) is set as soon as a received data character is

available in the RX FIFO. LSR0 is cleared when the RX FIFO is empty.

The Receiver Data Available interrupt code (IIR0-IIR4 = 4h) is set whenever the number

of received data bytes in the RX FIFO reaches the trigger level specified by FCR6-FCR7

bits; it is cleared whenever the number of received data bytes in the RX FIFO drops

below the trigger level specified by FCR6-FCR7 bits.

The HINT interrupt is asserted whenever the number of received data bytes in the RX

FIFO reaches the trigger level specified by FCR6-FCR7 bits. HINT interrupt is de-

asserted when the number of received data bytes in the RX FIFO drops below the trigger

level specified by FCR6-FCR7 bits.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

102247B Conexant 5-11

5.3.2 Receiver Character Timeout Interrupts

When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (Receiver Data

Available) is enabled (IER0 = 1), receiver character timeout interrupt operation is as

follows:

1. A Receiver character timeout interrupt code (IIR0-IIR3 = Ch) is set if at least one

received character is in the RX FIFO, the most recent received serial character was

longer than four continuous character times ago (if 2 stop bits are specified, the

second stop bit is included in this time period), and the most recent host read of the

RX FIFO was longer than four continuous character times ago.

5.4 Transmitter FIFO Interrupt Operation

5.4.1 Transmitter Empty Interrupt

When the FIFO mode is enabled (FCR0 = 1) and transmitter interrupt (TX Buffer Empty)

is enabled (IER0 = 1), transmitter interrupt operation is as follows:

The TX Buffer Empty interrupt code (IIR0-IIR3 = 2h) will occur when the TX Buffer is

empty; it is cleared when the TX Buffer is written to (1 to 16 characters) or the IIR is

read.

The TX Buffer Empty indications will be delayed 1 character time minus the last stop bit

time whenever the following occur: THRE = 1 and there have not been at least two bytes

at the same time in the TX FIFO Buffer since the last setting of THRE was set. The first

transmitter interrupt after setting FCR0 will be immediate.

CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet

5-12 Conexant 102247B

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NOTES

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