REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add B, S, Q, and V test limits. Change to one part-one part number format. Add ground bounce and latch-up immunity tests. Add 10.1 substitution statement. Editorial changes throughout. 92-07-10 Monica L. Poelking B Changes in accordance with NOR 5962-R041-93. 92-12-29 Monica L. Poelking C Changes in accordance with NOR 5962-R095-98. 98-04-24 Monica L. Poelking D Incorporate NOR 5962-R041-93 and NOR 5962-R095-98. Add V device class level. Add vendor CAGE code F8859. Add device type 03. Add case outlines X and Z. Add radiation features for device type 01. Update boilerplate to MIL-PRF-38535 requirements. - LTG 02-07-12 Thomas M. Hess E Add radiation features for device type 03 in section 1.5. Update the boilerplate to include radiation hardness assured requirements for device type 03. Editorial changes throughout. - jak 04-09-09 Thomas M. Hess F Change ICCL and ICCH maximum limits I for device type 03 in table I. Correct the test circuit in figure 5. - jak 05-08-31 Thomas M. Hess G Add appendix A, microcircuit die. Update the boilerplate to MIL-PRF-38535 requirements and to include radiation hardness assurance requirements. - jak 07-03-07 Thomas M. Hess REV SHEET REV G G G G G G G G G G G G G G G SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 REV STATUS REV G G G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeffery Tunstall STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http://www.dscc.dla.mil CHECKED BY Ray Monnin APPROVED BY Michael A. Frye DRAWING APPROVAL DATE MICROCIRCUIT, DIGITAL, ADVANCED CMOS, QUAD TWO-INPUT NAND GATE, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON 88-09-30 AMSC N/A REVISION LEVEL G SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 1 OF 5962-87699 29 5962-E240-07 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes M, B, and Q) and space application (device classes S and V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following examples. 5962 F Federal stock class designator \ 87699 RHA designator (see 1.2.1) 01 V X A Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 RHA designator. Device classes B, S, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 03 Generic number Circuit function 54ACT00 54ACT11000 54ACT00 Quad 2-input NAND gate, TTL compatible inputs Quad 2-input NAND gate, TTL compatible inputs Quad 2-input NAND gate, TTL compatible inputs 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class M B, S, Q, or V Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. Certification and qualification to MIL-PRF-38535. 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter C D X E Z 2 Descriptive designator GDIP1-T14 or CDIP2-T14 GDFP1-F14 or CDFP2-F14 CDFP3-F14 GDIP1-T16 or CDIP2-T16 GDFP1-G14 CQCC1-N20 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 Terminals 14 14 14 16 14 20 Package style Dual-in-line Flat pack Flat pack Dual-in-line Flat pack with gullwing leads Square leadless chip carrier SIZE 5962-87699 A REVISION LEVEL E SHEET 2 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes B, S, Q, and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC).................................................................................. DC input voltage range (VIN)................................................................................ DC output voltage range (VOUT) ........................................................................... Clamp diode current (IIK, IOK) ............................................................................... DC output current (IOUT)....................................................................................... DC VCC or GND current (ICC, IGND) ....................................................................... Storage temperature range (TSTG) ....................................................................... Maximum power dissipation (PD) ......................................................................... Lead temperature (soldering, 10 seconds): Case outline X.................................................................................................. All other case outlines except case X .............................................................. Thermal resistance, junction-to-case (JC)........................................................... Junction temperature (TJ) .................................................................................... Case operating temperature (TC)......................................................................... -0.5 V dc to +6.0 V dc -0.5 V dc to VCC +0.5 V dc -0.5 V dc to VCC +0.5 V dc 20 mA 50 mA 100 mA 3/ -65C to +150C 500 mW +260C +300C See MIL-STD-1835 +175C -55C to +125C 1.4 Recommended operating conditions. 2/ 4/ Supply voltage range (VCC) ................................................................................. Input voltage range (VIN)...................................................................................... Output voltage range (VOUT) ................................................................................ Maximum low level input voltage (VIL) ................................................................. +4.5 V dc to +5.5 V dc +0.0 V dc to VCC +0.0 V dc to VCC 0.8 V dc at VCC = 4.5 V dc 0.8 V dc at VCC = 5.5 V dc Minimum high level input voltage (VIH)................................................................. 2.0 V dc at VCC = 4.5 V dc 2.0 V dc at VCC = 5.5 V dc Case operating temperature range (TC)............................................................... -55C to +125C Input rise and fall rate (tr, tf) maximum: VCC = 4.5 V....................................................................................................... 10 ns/V VCC = 5.5 V....................................................................................................... 8.0 ns/V Maximum high level output current (IOH) .............................................................. -24 mA Maximum low level output current (IOL)................................................................ 24 mA 1.5 Radiation features. Device type 01: Maximum total dose available (dose rate = 50 - 300 rads (Si)/s) .................... Single Event Latch-up (SEL) ........................................................................... Device type 03: Maximum total dose available (dose rate = 50 - 300 rads (Si)/s) .................... Single Event Latchup (SEL)............................................................................. 1/ 2/ 3/ 4/ 5/ 100 krads (Si) 120 MeV-cm2/mg 5/ 300 krads (Si) 93 MeV-cm2/mg 5/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. The maximum junction temperature may be exceeded for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Unless otherwise specified, all voltages are referenced to GND. For packages with multiple VCC and GND pins, this value represents the maximum total current flowing into or out of all VCC or GND pins. Unless otherwise specified, the values listed above shall apply over the full VCC and TC recommended operating range. Limits are based on characterization, but not production tested unless specified by the customer through the purchase order or contract. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 3 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ELECTRONIC INDUSTRIES ALLIANCE (EIA) JEDEC Standard No. 20 - Standard for Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed CMOS Devices. JESD 78 - IC Latch-Up Test (Copies of this document is available online at www.eia.org/ or from the Electronics Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of semiconductor Devices. (Copies of these documents are available online at http://www.astm.org or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA, 19428-2959). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes B, S, Q, and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 4 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes B, S, Q, and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Ground bounce waveforms and test circuit. The ground bounce waveforms and test circuit shall be as specified on figure 4. 3.2.6 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 5. 3.2.7 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes B, S, Q, and V shall be a "QML" or "Q" as required in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes B, S, Q, and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturer's product meets, for device classes B, S, Q, and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes B, S, Q, and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 36 (see MIL-PRF-38535, appendix A). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 5 TABLE IA. Electrical performance characteristics. Test and MIL-STD-883 test method 1/ High level output voltage 3006 Symbol VOH1 6/ VOH2 7/ 8/ Conditions -55C TC +125C 2/ 3/ 4.5 V VCC 5.5 V unless otherwise specified Device type 4/ and device class For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -50 A For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -50 A VCC Group A subgroups 4.5 V 1, 2, 3 Min 4.4 5.5 V 1, 2, 3 5.4 1 5.4 M 01 B, S, Q, V V V 5.4 P, L, R 5.4 5.5 V 1, 2, 3 5.4 1 3.7 V All All M D 01 B, S, Q, V 3.7 P, L, R VOH4 6/ Max All All For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -24 mA Unit All All D VOH3 7/ 8/ Limits 5/ 3.7 5.5 V For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -24 mA 1, 2, 3 4.7 V All All See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 6 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ High level output voltage 3006 Symbol VOH5 7/ 8/ 9/ Conditions -55C TC +125C 2/ 3/ 4.5 V VCC 5.5 V unless otherwise specified VCC 5.5 V For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOH = -50 mA Device type 4/ and device class Group A subgroups 1, 2, 3 Min 3.85 1 3.85 M 01 B, S, Q, V VOL2 7/ 8/ For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 50 A For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 50 A 3.85 4.5 V 1, 2, 3 0.1 V 5.5 V 1, 2, 3 0.1 V 1 0.1 All All All All M D 01 B, S, Q, V 0.1 P, L, R VOL3 7/ 8/ For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V 0.1 All B, S, Q, V 4.5 V All M For all other inputs VIN = VCC or GND IOL = 24 mA V 3.85 P, L, R VOL1 6/ Max All All D Low level output voltage 3007 Unit Limits 5/ M D 01 B, S, Q, V 1, 3 0.4 2 0.5 1 0.4 2, 3 0.5 1 0.4 V 0.4 P, L, R 0.4 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 7 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Conditions -55C TC +125C 2/ 3/ 4.5 V VCC 5.5 V unless otherwise specified Device type 4/ and device class VCC For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 24 mA All B, S, Q, V 5.5 V Group A subgroups Min Low level output voltage 3007 VOL4 6/ VOL5 7/ 8/ 9/ All M 5.5 V For all inputs affecting output under test, VIN = VIH or VIL VIH = 2.0 V VIL = 0.8 V For all other inputs VIN = VCC or GND IOL = 50 mA 1, 3 Max 0.4 2 0.5 1 0.4 2, 3 0.5 1, 2, 3 1.65 1 1.65 M 01 B, S, Q, V 1.65 P, L, R VIC+ 7/ 8/ For input under test IIN = 1 mA 1.65 All B, S, Q, V M D GND 01 B, S, Q, V 1 0.4 1.5 1 0.4 1.5 0.4 1.5 0.4 1.5 1 -0.4 -1.5 1 -0.4 -1.5 -0.4 -1.5 -0.4 -1.5 P, L, R Negative input clamp voltage 3022 VIC7/ 8/ V All All D Positive input clamp voltage 3022 Unit Limits 5/ For input under test IIN = -1 mA All B, S, Q, V M D Open 01 B, S, Q, V P, L, R V V See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 8 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Conditions -55C TC +125C 2/ 3/ 4.5 V VCC 5.5 V unless otherwise specified Device type 4/ and device class VCC For input under test, VIN = VCC For all other inputs, VIN = VCC or GND All B, S, Q, V 5.5 V Group A subgroups Min Input current high 3010 IIH 7/ 8/ All M M D 1 Max 0.1 2 1.0 1 0.1 2, 3 1.0 1 0.1 01 B, S, Q, V IIL 7/ 8/ For input under test, VIN = GND For all other inputs, VIN = VCC or GND 0.1 All B, S, Q, V 5.5 V All M M D 1 -0.1 2 -1.0 1 -0.1 2, 3 -1.0 1 -0.1 01 B, S, Q, V Quiescent supply current delta, TTL input levels 3005 CIN -0.1 CPD 10/ ICC 7/ 8/ 11/ All All 01, 03 All 02 All 01, 02 B, S, Q, V See 4.4.1c TC = +25 See 4.4.1c TC = +25 For input under test, VIN = VCC - 2.1 V For all other inputs, VIN = VCC or GND M D A -0.1 P, L, R Input capacitance 3012 Power dissipation capacitance A 0.1 P, L, R Input current low 3009 Unit Limits 5/ 03 B, S, Q, V All M 01 B, S, Q, V GND 4 10 pF 5.0 V 4 50 pF 65 5.5 V 3 1.6 1, 2 1.0 1, 2, 3 1.6 1, 2, 3 1.6 1 1.0 mA 1.0 3.0 P, L, R See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 9 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Conditions -55C TC +125C 2/ 3/ 4.5 V VCC 5.5 V unless otherwise specified Device type 4/ and device class VCC 01, 02 B, S, Q, V 5.5 V 03 All 5.5 V Group A subgroups Limits 5/ Min Quiescent supply current output high 3005 ICCH 7/ 8/ For all inputs, VIN = GND 01, 02 M M D P, L, R M, D, P, L, R, F 12/ Quiescent supply current output low 3005 ICCL 7/ 8/ For all inputs, VIN = VCC 01 B, S, Q, V M, D, P, L, R, F 12/ 1 Max 1.0 2 20.0 1 2.0 2, 3 40.0 1 4.0 2, 3 1 80.0 75.0 300.0 1.0 mA A 03 Q, V 5.5 V 1 50.0 A 01, 02 B, S, Q, V 5.5 V 1 1.0 A 2 20.0 03 All 5.5 V 01, 02 M M D P, L, R Unit 01 B, S, Q, V 1 2.0 2, 3 40.0 1 4.0 2, 3 1 80.0 75.0 300.0 1.0 mA 03 Q, V 5.5 V 1 50.0 A Low level ground bounce noise VGBL 13/ VLD = 2.5 V IOL = +24 mA See figure 4 All B, S, Q, V 4.5 V 4 1200 mV High level ground bounce noise VGBH 13/ VLD = 2.5 V IOH = -24 mA See figure 4 All B, S, Q, V 4.5 V 4 1500 mV Latch-up input/ output over-voltage ICC (O/V1) 14/ All B, S, Q, V 5.5 V 2 200 mA Latch-up input/ output positive over-current ICC (O/I1+) 14/ tw 100 s tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Vover = 10.5 V, See 4.4.1b tw 100 s tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Itrigger = +120 mA, See 4.4.1b All B, S, Q, V 5.5 V 2 200 mA See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 10 TABLE IA. Electrical performance characteristics - Continued. Test and MIL-STD-883 test method 1/ Symbol Conditions -55C TC +125C 2/ 3/ 4.5 V VCC 5.5 V unless otherwise specified Device type 4/ and device class VCC Group A subgroups Limits 5/ Min Unit Latch-up input/ output negative over-current ICC (O/I1-) 14/ tw 100 s tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Itrigger = -120 mA, See 4.4.1b All B, S, Q, V 5.5 V 2 Max 200 mA Latch-up supply over-voltage ICC (O/V2) 14/ tw 100 s tcool tw 5 s tr 5 ms 5 s tf 5 ms Vtest = 6.0 V VCCQ = 5.5 V Vover = 9.0 V, See 4.4.1b All B, S, Q, V 5.5 V 2 100 mA Truth table test output voltage 3014 7/ 8/ 15/ VIL = 0.4 V VIH = 2.4 V Verify output VO See 4.4.1e All All 4.5 V 7, 8 L H 7 L H L H M D 01 B, S, Q, V P, L, R Propagation delay time, data to output, nA, nB to nY 3003 tPHL, tPLH 7/ 8/ 16/ 17/ VIL = 0.40 V VIH = 2.40 V Verify output VO, See 4.4.1e CL = 50 pF minimum RL = 500 See figure 5 L H All M 5.5 V 7, 8 L H 01, 03 B, S, Q, V 4.5 V 9, 11 1.0 9.0 10 1.0 9.5 02 B, S, Q, V 9, 11 1.0 10.9 10 1.0 13.3 01, 03 M 9 1.0 9.0 10, 11 1.0 9.5 9 1.0 10.9 10, 11 1.0 13.3 9 1.0 9.0 02 M M D 01 B, S, Q, V P, L, R 1.0 9.0 1.0 9.0 ns See footnotes on next sheet. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 11 TABLE IA. Electrical performance characteristics - Continued. 1/ For tests not listed in the referenced MIL-STD-883 (e.g. ICC), utilize the general test procedure under the conditions listed herein. All inputs and outputs shall be tested, as applicable, to the tests in table IA herein. 2/ Each input/output, as applicable, shall be tested at the specified temperature for the specified limits. Output terminals not designated shall be high level logic, low level logic, or open, except as follows: 3/ a. VIC (pos) tests, the GND terminal can be open. TC = +25C. b. VIC (neg) tests, the VCC terminal shall be open. TC = +25C. c. All ICC and ICC tests, the output terminal shall be open. When performing these tests, the current meter shall be placed in the circuit such that all current flows through the meter. RHA parts for device type 01 supplied to this drawing have been characterized through all levels M, D, P, L, and R of irradiation. However, this device is only tested at the 'R' level. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25C. RHA parts for device type 03 supplied to this drawing have been characterized through all levels M, D, P, L, R, and F of irradiation. However, this device is only tested at the 'F' level. Pre and Post irradiation values are identical unless otherwise specified in Table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25C. 4/ The word "All" in the device type and device class column, means limits for all device types and classes. 5/ For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, respectively; and the absolute value of the magnitude, not the sign, is relative to the minimum and maximum limits, as applicable, listed herein. 6/ For device classes B, S, Q, and V, this test is guaranteed, if not tested, to the limits specified in table IA. 7/ RHA samples do not have to be tested at -55C and +125C postirradiation. 8/ When performing postirradiation electrical measurements for RHA level, TA = +25C. Limits shown are guaranteed at TA = +25C 5C. 9/ Transmission driving tests are performed at VCC = 5.5 V dc with a 2 ms duration maximum. This test may be performed using VIN = VCC or GND. When VIN = VCC or GND is used, the test is guaranteed for VIN = 2.0 V or 0.8 V. 10/ Power dissipation capacitance (CPD) determines the no load dynamic power consumption, PD = (CPD + CL) (VCC x VCC)f + (ICC x VCC) + (n x d x ICC x VCC). The dynamic current consumption, IS = (CPD + CL) VCCf + ICC + n x d x ICC. For both PD and IS, n is the number of device inputs at TTL levels, f is the frequency of the input signal, and d is the duty cycle of the input signal. 11/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at VIN = VCC - 2.1 V (alternate method). Classes B, S, Q, and V shall use the preferred method. When the test is performed using the alternate test method, the maximum limits is equal to the number of inputs at a high TTL input level times ICC maximum limits, and the preferred method and limits are guaranteed. 12/ The maximum limit for this parameter at 100 krads (Si) is 2 A. 13/ This test is for qualification only. Ground bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of induced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture with all outputs fully dc loaded (IOL maximum and IOH maximum = 24 mA, for example) and 50 pF of load capacitance (see figure 4). The loads must be located as close as possible to the device output. Inputs are then conditioned with 1 MHz pulse (tr = tf = 3.5 1.5 ns) switching simultaneously and in phase such that one output is forced low and all others (possible) are switched. The low level ground bounce noise is measured at the quiet output using a F.E.T. oscilloscope probe with at least 1 M impedance. Measurement is taken from the peak of the largest positive pulse with respect to the nominal low level output voltage (see figure 4). The device inputs are then conditioned such that the output under test is at a high nominal VOH level. The high level ground bounce measurement is then measured from nominal VOH level to the largest negative peak. This procedure is repeated such that all outputs are tested at a high and low level with a maximum number of outputs switching. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 12 TABLE IA. Electrical performance characteristics - Continued. 14/ See EIA/JEDEC STD. No. 78 for electrically induced latch-up test methods and procedures. The values listed for Itrigger and Vover are to be accurate within 5 percent. 15/ Tests shall be performed in sequence, attributes data only. Functional tests shall include the truth table and other logic patterns used for fault detection. Functional tests shall be performed in sequence as approved by the qualifying activity on qualified devices. H 2.5 V, L < 2.5 V; high inputs = 2.4 V and low inputs = 0.4 V. The input voltage levels have the allowable tolerances in accordance with MIL-STD-883, already incorporated. Functional tests at VCC = 4.5 V are worst case for RHA specified devices. 16/ Device classes B, S, Q, and V are tested at VCC = 4.5 V at TC = +125C for sample testing and at VCC = 4.5 V at TC = +25C for screening. Other voltages of VCC and temperatures are guaranteed, if not tested, see 4.4.1d. 17/ AC limits at VCC = 5.5 V are equal to the limits at VCC = 4.5 V and guaranteed by testing at VCC = 4.5 V. Minimum ac limits for VCC = 5.5 V are 1.0 ns and guaranteed by guardbanding the VCC = 4.5 V minimum limits to 1.5 ns. For propagation delay tests, all paths must be tested. TABLE IB. SEP test limits. 1/ 2/ Device type SEP TC = temperature 10C VCC Effective LET 01 SEL +25C 5.5 V 120 MeV-cm2/mg 03 SEL +25C 5.5 V 93 MeV-cm2/mg 1/ For SEP test conditions, see 4.4.5.2 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity. Device types Case outlines Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 01 and 03 C, D, X, and Z 2 E Terminal symbol 1A NC 1A 1B 1A 1Y 1Y 1B 2Y 2A 1Y GND 2B NC GND 2Y 2A 3Y GND NC 4Y 3Y 2B 4B 3A 2Y 4A 3B GND 3B 4Y NC 3A 4A 3Y VCC 4B 3A VCC VCC 3B 2B NC 2A --4Y 1B --NC ----4A ----4B ----VCC ----- 02 2 NC VCC 2B 2A 1B NC 1A 1Y 2Y GND NC GND 3Y 4Y 4B NC 4A 3B 3A VCC NC = No connection FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 13 All device types Inputs nB L L H H nA L H L H Output nY H H H L H = High voltage level L = Low voltage level FIGURE 2. Truth table. FIGURE 3. Logic diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 14 NOTE: Resistor and capacitor tolerances = 10% FIGURE 4. Ground bounce waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 15 NOTES: 1. CL = pF minimum or equivalent (includes test jig and probe capacitance). 2. RL = 500 or equivalent. 3. RT = 50 or equivalent. 4. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR 10 MHz; tr 3 ns; tf 3 ns; duty cycle = 50 percent. 5. Timing parameters shall be tested at a minimum input frequency of 1 MHz. 6. The outputs are measured one at a time with one transition per measurement. FIGURE 5. Switching waveforms and test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 16 4. VERIFICATION 4.1 Sampling and inspection. For device classes B, S, Q, and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes B, S, Q, and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device classes M, B, and S. a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. (3) Delete the sequence specified in 3.1.10 through 3.1.14 of method 5004 and substitute the first 7 test requirements of table IIA herein. (4) For device class M, unless otherwise specified, the requirements for device class B in method 1015 of MIL-STD-883 shall be followed. (5) Static burn-in, device classes B and S, test condition A, method 1015 of MIL-STD-883 (unless otherwise specified in the QM plan). Test duration for each static test shall be 24 hours minimum for class S devices and in accordance with table IA of method 1015 for class B devices. (a) (6) For static burn-in I, all inputs shall be connected to GND. Outputs may be open or connected to VCC/2 0.5 V. Resistors R1 are optional on both inputs and open outputs, and required on outputs connected to VCC/2 0.5 V. R1 = 220 to 47 k. (b) For static burn-in II, all inputs shall be connected through the R1 resistors to VCC. Outputs may be open or connected to VCC/2 0.5 V. Resistors R1 are optional on open outputs, and required on outputs connected to VCC/2 0.5 V. R1 = 220 to 47 k. (c) VCC = 5.5 V +0.5 V, -0.00 V. Dynamic burn-in, device classes B and S, test condition D, method 1015 of MIL-STD-883 (unless otherwise specified in the QM plan). (a) Input resistors = 220 to 2 k 20 percent. (b) Output resistors = 220 20 percent. (c) VCC = 5.5 V +0.5 V, -0.00 V. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 17 (d) All inputs shall be connected through the resistors in parallel to a common clock pulse (CP). Outputs shall be connected through the resistors to VCC/2 0.5 V. (e) CP = 25 kHz to 1 MHz square wave; duty cycle = 50 percent 15 percent; VIH = 4.5 V to VCC, VIL = 0 V 0.5 V; tr, tf 100 ns. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. For class S devices, post dynamic burn-in, or class B devices, post static burn-in, electrical parameter measurements may, at the manufacturer's option, be performed separately or included in the final electrical parameter requirements. 4.2.2 Additional criteria for device classes B, S, Q, and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table IIA herein. c. Additional screening for device class S or V beyond the requirements of device class B or Q shall be as specified in MIL-PRF-38535, appendix B. 4.2.3 Percent Defective Allowable (PDA). a. The PDA for class S or V devices shall be 5 percent for static burn-in and 5 percent for dynamic burn-in, based on the exact number of devices submitted to each separate burn-in. b. Static burn-in I and II failures shall be cumulative for determining the PDA. c. The PDA for class B or Q devices shall be in accordance with MIL-PRF-38535 for static burn-in. Dynamic burn-in is not required. d. The PDA for class M devices shall be in accordance with MIL-PRF-38535, appendix A for static burn-in and dynamic burn-in. e. Those devices whose measured characteristics, after burn-in, exceed the specified delta limits or electrical parameter limits specified in table IA, subgroup 1, are defective and shall be removed from the lot. The verified number of failed devices times 100 divided by the total number of devices in the lot initially submitted to burn-in shall be used to determine the percent defective for the lot and the lot shall be accepted or rejected based on the specified PDA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 18 4.3 Qualification inspection for device classes B, S, Q, and V. Qualification inspection for device classes B, S, Q, and V shall be in accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5). 4.4 Conformance inspection. Technology conformance inspection for classes B, S, Q, and V shall be in accordance with MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.5). TABLE IIA. Electrical test requirements. Test requirements Interim electrical parameters, method 5004 Static burn-in I, method 1015 (see 4.2.1a) Interim electrical parameters, method 5004 (see 4.2.1b) Static burn-in II, method 1015 (see 4.2.1a) Interim electrical parameters, method 5004 (see 4.2.1b) Dynamic burn-in I, method 1015 (see 4.2.1a) Interim electrical parameters, method 5004 (see 4.2.1b) Final electrical parameters, method 5004 Group A test requirements method 5005 (see 4.4.1) Group B end-point electrical parameters, method 5005 (see 4.4.2) Group C end-point electrical parameters, method 5005 (see 4.4.3) Group D end-point electrical parameters, method 5005 (see 4.4.4) Group E end-point electrical parameters, method 5005 (see 4.4.5) Subgroups 1/ (in accordance with MIL-STD-883, method 5005, table I) Device class M Subgroups 1/ (in accordance with MIL-PRF-38535, table III) Device 2/ class B 1 Device 2/ class S 1 Device class Q 1 Device class V 1 3/ Not required Required 4/ 1 5/ Not required Required 4/ 1 5/ 3/ Required 6/ 1 2/ 5/ Required 4/ 1 2/ 5/ Required 6/ 1 2/ 5/ Required 4/ 1 2/ 5/ 3/ Not required Required 4/ 1 5/ Not required Required 4/ 1 5/ 2/ 6/ 1, 2, 7, 9 1, 2, 3, 4, 7, 8, 9, 10, 11 2/ 1, 2, 7, 9 2/ 6/ 1, 2, 3, 7, 8, 9,10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 2/ 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 5/ 1, 2, 3 5/ 1, 2, 3, 7, 8, 9, 10, 11 2/ 1, 2, 3, 7, 8, 9 1, 2, 3, 4, 7, 8, 9, 10, 11 1, 2, 3, 4, 7, 8, 9, 10, 11 5/ 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3 5/ 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9 See footnotes on next sheet. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 19 TABLE IIA. Electrical test requirements - Continued. 1/ Blank spaces indicate tests are not applicable. 2/ PDA applies to subgroup 1 (see 4.2.3). For device classes S and V, PDA applies to subgroups 1 and 7 (see 4.2.3). 3/ The burn-in shall meet the requirements of 4.2.1a herein. 4/ On all class S lots, the device manufacturer shall maintain read-and-record data (as a minimum on disk) for burn-in electrical parameters (group A, subgroup 1), in accordance with test method 5004 of MIL-STD-883. For preburn-in and interim electrical parameters, the read-and-record requirements are for delta measurements only. 5/ Delta limits, as specified in table IIB, shall be required only on table IA, subgroup 1. The delta values shall be computed with reference to the previous interim electrical parameters. 6/ The device manufacturer may at his option either complete subgroup 1 electrical parameter measurements, including delta measurements, within 96 hours after burn-in completion (removal of bias; or may complete subgroup 1 electrical measurements without delta measurements within 24 hours after burn-in completion (removal of bias). When the manufacturer elects to perform the subgroup 1 electrical parameter measurements without delta measurements, there is no requirement to perform the pre-burn-in electrical tests (first interim electrical parameters test in table IIA). TABLE IIB. Burn-in and operating life test, delta parameters (+25C). Parameter 1/ Supply current Supply current delta Input current low level Input current high level Output voltage low level VCC = 5.5 V, IOL = 24 mA Output voltage high level VCC = 5.5 V, IOH = -24 mA Symbol ICCH, ICCL ICC IIL IIH VOL Device type 01 03 03 03 03 03 Delta limits 100 nA 2/ 150 nA 0.4 mA 20 nA 20 nA 0.04 V VOH 03 0.20 V 1/ These parameters shall be recorded before and after the required burn-in and life test to determine delta limits. 2/ Guaranteed, if not tested. 4.4.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Latch-up and ground bounce tests are required for device classes B, S, Q, and V. These tests shall be performed only for initial qualification and after process or design changes which may affect the performance of the device. Latch-up tests shall be considered destructive. For latch-up and ground bounce tests, test all applicable pins on five devices with zero failures. c. CIN and CPD shall be measured only for initial qualification and after process or design changes which may affect capacitance. CIN shall be measured between the designated terminal and GND at a frequency of 1 MHz. CPD shall be tested in accordance with the latest revision of JEDEC Standard No. 20 and table IA herein. For CIN and CPD, test all applicable pins on five devices with zero failures. d. For device classes B, S, Q, and V, subgroups 9 and 11 tests shall be measured only for initial qualification and after process or design changes which may affect dynamic performance. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 20 e. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth table on figure 2 herein. The test vectors used to verify the truth table shall test all possible input to output logic patterns. For device classes B, S, Q, and V, subgroups 7 and 8 shall include verifying the functionality of the device. 4.4.2 Group B inspection. When applicable, the group B inspection end-point electrical parameters shall be as specified in table IIA herein. For device class S steady-state life tests, the test circuit shall be maintained by the manufacturer and shall be made available to the acquiring or preparing activity upon request. 4.4.3 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.3.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883: a. Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. b. TA = +125C, minimum. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.3.2 Additional criteria for device classes B, S, Q, and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. 4.4.4 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein. 4.4.5 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured (see 3.5 herein). a. End-point electrical parameters shall be as specified in table IIA herein. b. For device classes B, S, Q, and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25C 5C, after exposure, to the subgroups specified in table IIA herein. c. RHA tests for device classes M, B, S, Q, and V for levels M, D, P, L, R, and F shall be performed through each level to determine at what levels the devices meet the RHA requirements. These RHA tests shall be performed for initial qualification and after design or process changes which may affect the RHA performance of the device. d. Prior to irradiation, each selected sample shall be assembled in its qualified package. It shall pass the specified group A electrical parameters in table IA for subgroups specified in table IIA herein. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 21 4.4.5.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883 method 1019, condition A and as specified herein. Prior to and during total dose irradiation characterization and testing, the devices for characterization shall be biased so that 50 percent are at inputs high and 50 percent are at inputs low, and the devices for testing shall be biased to the worst case condition established during characterization. Devices shall be biased as follows: a. Device type 01: (1) Inputs tested high, VCC = 5.5 V dc +5%, RCC = 10 +20%, VIN = 5.0 V dc +5%, RIN = 1 k +20%, and all outputs are open. (2) Inputs tested low, VCC = 5.5 V dc +5%, RCC = 10 +20%, VIN = 0.0 V dc, RIN = 1 k +20%, and all outputs are open. b. Device type 03: (1) Inputs tested high, VCC = 5.5 V dc 5%, VIN = 5.0 V dc +10%, RIN = 1 k 20%, and all outputs are open. (2) Inputs tested low, VCC = 5.5 V dc 5%, VIN = 0.0 V dc, RIN = 1 k 20%, and all outputs are open. 4.4.5.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limit at 25C 5C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.4.5.2 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be required on class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or latchup characteristics. Test four devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP testing. The test conditions for SEP are as follows: a. The ion beam angle of incidence shall be between normal to the die surface and 60 to the normal, inclusive (i.e. 0 angle 60). No shadowing of the ion beam due to fixturing or package related effects is allowed. b. The fluence shall be 100 errors or 106 ions/cm2. c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by measuring the cross-section at two flux rates which differ by at least an order of magnitude. d. The particle range shall be 20 microns in silicon. e. The upset test temperature shall be +25C and the latchup test temperature is maximum rated operating temperature 10C. f. Bias conditions shall be defined by the manufacturer for latchup measurements. g. For SEP test limits, see table IB herein. 4.5 Methods of inspection. Methods of inspection shall be specified as follows: 4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal. Currents given are conventional current and positive when flowing into the referenced terminal. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes B, S, Q, and V or MIL-PRF-38535, appendix A for device class M. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 22 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.1.2 Substitutability. Device classes B and Q devices will replace device class M devices. 6.1.2.1 Substitution data New PIN 5962-8769901MCA 5962-8769901MDA 5962-8769901M2A 5962-8769902MEA 5962-8769902M2A Old PIN 5962-8769901CA 5962-8769901DA 5962-87699012A 5962-8769902EA 5962-87699022A 6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.4 Comments. Comments on this drawing should be directed to DSCC-VA, P.O. Box 3990, Columbus, Ohio 43218-3990 or telephone (614) 692-0547. 6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. 6.6 Sources of supply. 6.6.1 Sources of supply for device classes B, S, Q, and V. Sources of supply for device classes B, S, Q, and V are listed in QML-38535. The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to this drawing. 6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103. The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. 6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be supplied. a. RHA upset levels. b. Test conditions (SEP). c. Number of upsets (SEP). d. Number of transients (SEP). e. Occurrence of latch-up (SEP). STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 23 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87699 A.1 SCOPE A.1.1 Scope. This appendix establishes minimum requirements for microcircuit die to be supplied under the Qualified Manufacturers List (QML) Program. QML microcircuit die meeting the requirements of MIL-PRF-38535 and the manufacturers approved QM plan for use in monolithic microcircuits, multi-chip modules (MCMs), hybrids, electronic modules, or devices using chip and wire designs in accordance with MIL-PRF-38534 are specified herein. Two product assurance classes consisting of military high reliability (device class Q) and space application (device class V) are reflected in the Part or Identification Number (PIN). When available, a choice of Radiation Hardiness Assurance (RHA) levels are reflected in the PIN. A.1.2 PIN. The PIN is as shown in the following example: 5962 F Federal stock class designator \ RHA designator (see A.1.2.1) 87699 03 Device type (see A.1.2.2) / V Device class designator (see A.1.2.3) 9 A Die code Die details (see A.1.2.4) \/ Drawing number A.1.2.1 RHA designator. Device classes Q and V RHA identified die meet the MIL-PRF-38535 specified RHA levels. A dash (-) indicates a non-RHA die. A.1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 03 Generic number Circuit function 54ACT00 Quad 2-input NAND gate, TTL compatible inputs A.1.2.3 Device class designator. Device class Q designator will not be included in the PIN and will not be marked on the device since the device class designator has been added after the original issuance of this drawing. Device class Q or V Device requirements documentation Certification and qualification to the die requirements of MIL-PRF-38535 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 24 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87699 A.1.2.4 Die details. The die details designation is a unique letter which designates the die's physical dimensions, bonding pad location(s) and related electrical function(s), interface materials, and other assembly related information, for each product and variant supplied to this appendix. A.1.2.4.1 Die physical dimensions. Die type Figure number 03 A-1 A.1.2.4.2 Die bonding pad locations and electrical functions. Die type Figure number 03 A-1 A.1.2.4.3 Interface materials. Die type Figure number 03 A-1 A.1.2.4.4 Assembly related information. Die type Figure number 03 A-1 A.1.3 Absolute maximum ratings. See paragraph 1.3 herein for details. A.1.4 Recommended operating conditions. See paragraph 1.4 herein for details. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 25 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87699 A.2. APPLICABLE DOCUMENTS A.2.1 Government specification, standards, and handbooks. The following specification, standard, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARD MIL-STD-883 - Test Method Standard Microcircuits. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) A.2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. A.3 REQUIREMENTS A.3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. A.3.2 Design, construction and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein and the manufacturer's QM plan for device classes Q and V. A.3.2.1 Die physical dimensions. The die physical dimensions shall be as specified in A.1.2.4.1 and on figure A-1. A.3.2.2 Die bonding pad locations and electrical functions. The die bonding pad locations and electrical functions shall be as specified in A.1.2.4.2 and on figure A-1. A.3.2.3 Interface materials. The interface materials for the die shall be as specified in A.1.2.4.3 and on figure A-1. A.3.2.4 Assembly related information. The assembly related information shall be as specified in A.1.2.4.4 and on figure A-1. A.3.2.5 Truth table. The truth table shall be as defined in paragraph 3.2.3 herein. A.3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as defined in paragraph 3.2.6 herein. A.3.3 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post-irradiation parameter limits are as specified in table IA of the body of this document. A.3.4 Electrical test requirements. The wafer probe test requirements shall include functional and parametric testing sufficient to make the packaged die capable of meeting the electrical performance requirements in table IA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 26 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87699 A.3.5 Marking. As a minimum, each unique lot of die, loaded in single or multiple stack of carriers, for shipment to a customer, shall be identified with the wafer lot number, the certification mark, the manufacturer's identification and the PIN listed in A.1.2 herein. The certification mark shall be a "QML" or "Q" as required by MIL-PRF-38535. A.3.6 Certification of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see A.6.4 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this appendix shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and the requirements herein. A.3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuit die delivered to this drawing. A.4 VERIFICATION A.4.1 Sampling and inspection. For device classes Q and V, die sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modifications in the QM plan shall not affect the form, fit, or function as described herein. A.4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and as defined in the manufacturer's QM plan. As a minimum, it shall consist of: a. Wafer lot acceptance for class V product using the criteria defined in MIL-STD-883, method 5007. b. 100% wafer probe (see paragraph A.3.4 herein). c. 100% internal visual inspection to the applicable class Q or V criteria defined in MIL-STD-883, method 2010 or the alternate procedures allowed in MIL-STD-883, method 5004. A.4.3 Conformance inspection. A.4.3.1 Group E inspection. Group E inspection is required only for parts intended to be identified as radiation assured (see A.3.5 herein). RHA levels for device classes Q and V shall be as specified in MIL-PRF-38535. End point electrical testing of packaged die shall be as specified in table IIA herein. Group E tests and conditions are as specified in paragraphs 4.4.4 herein. A.5 DIE CARRIER A.5.1 Die carrier requirements. The requirements for the die carrier shall be accordance with the manufacturer's QM plan or as specified in the purchase order by the acquiring activity. The die carrier shall provide adequate physical, mechanical and electrostatic protection. A.6 NOTES A.6.1 Intended use. Microcircuit die conforming to this drawing are intended for use in microcircuits built in accordance with MIL-PRF-38535 or MIL-PRF-38534 for government microcircuit applications (original equipment), design applications, and logistics purposes. A.6.2 Comments. Comments on this appendix should be directed to DSCC-VA, P.O. Box 3990, Columbus, Ohio 43218-3990 or telephone (614) 692-0547. A.6.3 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in MIL-PRF-38535 and MIL-HDBK-1331. A.6.4 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535. The vendors listed within QML-38535 have submitted a certificate of compliance (see A.3.6 herein) to DSCC-VA and have agreed to this drawing. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 27 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87699 Die physical dimensions. Die size: Die thickness: 1991 x 1281 m 285 25 m Die bonding pad locations and electrical functions. Optional manufacturer's logo Pad size: Pad numbers 1 to 6 and 8 to 13: 100 x 100 m Pad numbers 7 (GND) and 14 (VCC): 100 x 280 m NOTE: Pad numbers reflect terminal numbers when placed in case outline X (see figure 1). FIGURE A-1 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 28 APPENDIX A APPENDIX A FORMS A PART OF SMD 5962-87699 Interface materials. Top metallization: Al Si Cu Backside metallization: None 0.85 m Glassivation. Type: Thickness: Substrate: P. Vapox + Nitride 5000A - 7000A Silicon Assembly related information. Substrate potential: Floating or tied to GND Special assembly instructions: Bond pad #14 (VCC) first FIGURE A-1 - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-87699 A REVISION LEVEL G SHEET 29 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 07-03-07 Approved sources of supply for SMD 5962-87699 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ 5962-8769901MCA 5962-8769901MDA 5962-8769901M2A 5962-8769901BCA 5962-8769901BDA 5962-8769901B2A 5962-8769901SCA 5962-8769901SDA 5962-8769901S2A 5962R8769901B2A 5962R8769901BCA 5962R8769901BDA 5962R8769901S2A 5962R8769901SCA 5962R8769901SDA 5962R8769901SZA 5962-8769902MEA 5962-8769902M2A 5962-8769903VXA 5962-8769903QXA 5962-8769903VXC 5962-8769903QXC 5962F8769903VXA 5962F8769903QXA 5962F8769903VXC 5962F8769903QXC 5962F8769903VCA 5962F8769903VCC 5962F8769903QCA 5962F8769903QCC 5962F8769903V9A Vendor CAGE number 27014 01295 0C7V7 27014 01295 0C7V7 27014 01295 0C7V7 27014 0C7V7 27014 0C7V7 27014 0C7V7 Vendor similar PIN 2/ 54ACT00DMQB SNJ54ACT00J 54ACT00DMQB 54ACT00FMQB SNJ54ACT00W 54ACT00FMQB 54ACT00LMQB SNJ54ACT00FK 54ACT00LMQB JM54ACT00BCA 3/ 3/ 3/ 3/ 3/ 3/ 27014 27014 27014 27014 3V146 3V146 3/ 3/ 3/ 3/ F8859 F8859 F8859 F8859 F8859 F8859 F8859 F8859 F8859 JM54ACT00SCA-RH JM54ACT00SDA-RH JM54ACT00S2A-RH JM54ACT00B2A-RH JM54ACT00BCA-RH JM54ACT00BDA-RH JM54ACT00S2A-RH JM54ACT00SCA-RH JM54ACT00SDA-RH JM54ACT00SZA-RH 54ACT11000/BEA 54ACT11000/B2A 54ACT00K02V 54ACT00K02Q 54ACT00K01V 54ACT00K01Q RHFACT00K02V RHFACT00K02Q RHFACT00K01V RHFACT00K01Q RHFACT00D04V RHFACT00D03V RHFACT00D04Q RHFACT00D03Q ACT00DIE2V See footnotes on next sheet. Sheet 1 of 2 JM54ACT00BDA JM54ACT00B2A STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued. 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source of supply. Vendor CAGE number Vendor name and address 27014 National Semiconductor 2900 Semiconductor Drive P. O. Box 58090 Santa Clara, CA 95052-8090 01295 Texas Instruments Incorporated Semiconductor Group 8505 Forest Ln. P. O. Box 660199 Dallas, TX 75243 Point of contact: U.S. Highway 75 South P. O. Box 84, M/S 853 Sherman, TX 75090-9493 F8859 STMicroelectronics 3 rue de Suisse CS 60816 35208 RENNES cedex2-FRANCE 3V146 Rochester Electronics 16 Malcolm Hoyt Drive Newburyport, MA 01950 0C7V7 QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. Sheet 2 of 2